GPR_T0 - Linux

arch/mips/kernel/pm-cps.c

202

UASM_i_LA(pp, GPR_T0, (long)CKSEG0);

arch/mips/kernel/pm-cps.c

206

uasm_i_addiu(pp, GPR_T1, GPR_T0, cache_size);

arch/mips/kernel/pm-cps.c

216

uasm_i_cache(pp, op, 0, GPR_T0);

arch/mips/kernel/pm-cps.c

217

uasm_i_addiu(pp, GPR_T0, GPR_T0, cache->linesz);

arch/mips/kernel/pm-cps.c

219

uasm_i_cache(pp, op, i * cache->linesz, GPR_T0);

arch/mips/kernel/pm-cps.c

225

uasm_i_addiu(pp, GPR_T0, GPR_T0, unroll_lines * cache->linesz);

arch/mips/kernel/pm-cps.c

228

uasm_il_bne(pp, pr, GPR_T0, GPR_T1, lbl);

arch/mips/kernel/pm-cps.c

278

uasm_i_addiu(pp, GPR_T0, GPR_ZERO, (perf_event << 5) | 0xf);

arch/mips/kernel/pm-cps.c

279

uasm_i_mtc0(pp, GPR_T0, 25, (perf_counter * 2) + 0); /* PerfCtlN */

arch/mips/kernel/pm-cps.c

285

UASM_i_LA(pp, GPR_T0, (long)CKSEG0);

arch/mips/kernel/pm-cps.c

292

uasm_i_lw(pp, GPR_ZERO, i * line_size * line_stride, GPR_T0);

arch/mips/kernel/pm-cps.c

300

i * line_size * line_stride, GPR_T0);

arch/mips/kernel/pm-cps.c

302

i * line_size * line_stride, GPR_T0);

arch/mips/kernel/pm-cps.c

329

uasm_i_lui(pp, GPR_T0, uasm_rel_hi(0x80000000));

arch/mips/kernel/pm-cps.c

332

uasm_i_or(pp, GPR_T1, GPR_T1, GPR_T0);

arch/mips/kernel/pm-cps.c

382

UASM_i_LA(&p, GPR_T0, (long)mips_cps_pm_save);

arch/mips/kernel/pm-cps.c

383

uasm_i_jalr(&p, GPR_V0, GPR_T0);

arch/mips/kernel/pm-cps.c

423

uasm_i_lw(&p, GPR_T0, 0, r_nc_count);

arch/mips/kernel/pm-cps.c

424

uasm_il_bltz(&p, &r, GPR_T0, lbl_secondary_cont);

arch/mips/kernel/pm-cps.c

437

uasm_i_addiu(&p, GPR_T0, GPR_ZERO, TCHALT_H);

arch/mips/kernel/pm-cps.c

438

uasm_i_mtc0(&p, GPR_T0, 2, 4);

arch/mips/kernel/pm-cps.c

444

uasm_i_addiu(&p, GPR_T0, GPR_ZERO, 1 << vpe_id);

arch/mips/kernel/pm-cps.c

446

uasm_i_sw(&p, GPR_T0, 0, GPR_T1);

arch/mips/kernel/pm-cps.c

481

uasm_i_addiu(&p, GPR_T0, GPR_ZERO, 1 << cpu_core(&cpu_data[cpu]));

arch/mips/kernel/pm-cps.c

482

uasm_i_sw(&p, GPR_T0, 0, r_pcohctl);

arch/mips/kernel/pm-cps.c

483

uasm_i_lw(&p, GPR_T0, 0, r_pcohctl);

arch/mips/kernel/pm-cps.c

492

uasm_i_lw(&p, GPR_T0, 0, r_pcohctl);

arch/mips/kernel/pm-cps.c

514

UASM_i_LA(&p, GPR_T0, (long)addr_cpc_cl_cmd());

arch/mips/kernel/pm-cps.c

516

uasm_i_sw(&p, GPR_T1, 0, GPR_T0);

arch/mips/kernel/pm-cps.c

563

uasm_i_addiu(&p, GPR_T0, GPR_ZERO, mips_cm_revision() < CM_REV_CM3

arch/mips/kernel/pm-cps.c

567

uasm_i_sw(&p, GPR_T0, 0, r_pcohctl);

arch/mips/kernel/pm-cps.c

568

uasm_i_lw(&p, GPR_T0, 0, r_pcohctl);

arch/mips/kvm/entry.c

246

UASM_i_LW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, pc), GPR_K1);

arch/mips/kvm/entry.c

247

UASM_i_MTC0(&p, GPR_T0, C0_EPC);

arch/mips/kvm/entry.c

288

uasm_i_mfc0(&p, GPR_T0, C0_GUESTCTL1);

arch/mips/kvm/entry.c

290

uasm_i_ext(&p, GPR_T1, GPR_T0, MIPS_GCTL1_ID_SHIFT,

arch/mips/kvm/entry.c

292

uasm_i_ins(&p, GPR_T0, GPR_T1, MIPS_GCTL1_RID_SHIFT,

arch/mips/kvm/entry.c

294

uasm_i_mtc0(&p, GPR_T0, C0_GUESTCTL1);

arch/mips/kvm/entry.c

542

uasm_i_mfhi(&p, GPR_T0);

arch/mips/kvm/entry.c

543

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, hi), GPR_K1);

arch/mips/kvm/entry.c

545

uasm_i_mflo(&p, GPR_T0);

arch/mips/kvm/entry.c

546

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, lo), GPR_K1);

arch/mips/kvm/entry.c

551

UASM_i_MFC0(&p, GPR_T0, scratch_tmp[0], scratch_tmp[1]);

arch/mips/kvm/entry.c

552

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K1]), GPR_K1);

arch/mips/kvm/entry.c

610

uasm_i_cfc1(&p, GPR_T0, 31);

arch/mips/kvm/entry.c

611

uasm_i_sw(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31),

arch/mips/kvm/entry.c

622

uasm_i_mfc0(&p, GPR_T0, C0_CONFIG5);

arch/mips/kvm/entry.c

623

uasm_i_ext(&p, GPR_T0, GPR_T0, 27, 1); /* MIPS_CONF5_MSAEN */

arch/mips/kvm/entry.c

624

uasm_il_beqz(&p, &r, GPR_T0, label_msa_1);

arch/mips/kvm/entry.c

626

uasm_i_cfcmsa(&p, GPR_T0, MSA_CSR);

arch/mips/kvm/entry.c

627

uasm_i_sw(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr),

arch/mips/kvm/entry.c

670

uasm_i_mfc0(&p, GPR_T0, C0_GUESTCTL1);

arch/mips/kvm/entry.c

672

uasm_i_ins(&p, GPR_T0, GPR_ZERO, MIPS_GCTL1_RID_SHIFT,

arch/mips/kvm/entry.c

674

uasm_i_mtc0(&p, GPR_T0, C0_GUESTCTL1);

arch/mips/kvm/entry.c

765

uasm_i_andi(&p, GPR_T0, GPR_V0, RESUME_HOST);

arch/mips/kvm/entry.c

766

uasm_il_bnez(&p, &r, GPR_T0, label_return_to_host);

arch/mips/kvm/entry.c

796

UASM_i_LW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, guest_ebase), GPR_K1);

arch/mips/kvm/entry.c

804

build_set_exc_base(&p, GPR_T0);