arch/mips/kernel/smp-cps.c

107

uasm_i_mfc0(&p, GPR_K0, C0_STATUS);

arch/mips/kernel/smp-cps.c

109

uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9);

arch/mips/kernel/smp-cps.c

111

uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi);

arch/mips/kernel/smp-cps.c

113

UASM_i_LA(&p, GPR_K0, (long)&nmi_handler);

arch/mips/kernel/smp-cps.c

118

uasm_i_lui(&p, GPR_K0, val >> 16);

arch/mips/kernel/smp-cps.c

119

uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);

arch/mips/kernel/smp-cps.c

120

uasm_i_mtc0(&p, GPR_K0, C0_CAUSE);

arch/mips/kernel/smp-cps.c

122

uasm_i_lui(&p, GPR_K0, val >> 16);

arch/mips/kernel/smp-cps.c

123

uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);

arch/mips/kernel/smp-cps.c

124

uasm_i_mtc0(&p, GPR_K0, C0_STATUS);

arch/mips/kernel/traps.c

2050

UASM_i_LA(&buf, GPR_K0, handler);

arch/mips/kernel/traps.c

2051

uasm_i_jr(&buf, GPR_K0);

arch/mips/kvm/entry.c

199

UASM_i_LA(&p, GPR_K0, ST0_EXL | KSU_USER | ST0_BEV | ST0_KX_IF_64);

arch/mips/kvm/entry.c

200

uasm_i_mtc0(&p, GPR_K0, C0_STATUS);

arch/mips/kvm/entry.c

204

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, guest_ebase), GPR_K1);

arch/mips/kvm/entry.c

205

build_set_exc_base(&p, GPR_K0);

arch/mips/kvm/entry.c

212

uasm_i_addiu(&p, GPR_K0, GPR_ZERO, ST0_EXL | KSU_USER | ST0_IE | ST0_KX_IF_64);

arch/mips/kvm/entry.c

214

uasm_i_or(&p, GPR_K0, GPR_K0, GPR_V0);

arch/mips/kvm/entry.c

215

uasm_i_mtc0(&p, GPR_K0, C0_STATUS);

arch/mips/kvm/entry.c

251

UASM_i_MFC0(&p, GPR_K0, C0_PWBASE);

arch/mips/kvm/entry.c

253

UASM_i_MFC0(&p, GPR_K0, c0_kscratch(), pgd_reg);

arch/mips/kvm/entry.c

254

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_pgd), GPR_K1);

arch/mips/kvm/entry.c

277

uasm_i_mfc0(&p, GPR_K0, C0_GUESTCTL0);

arch/mips/kvm/entry.c

278

uasm_i_ins(&p, GPR_K0, GPR_V1, MIPS_GCTL0_GM_SHIFT, 1);

arch/mips/kvm/entry.c

279

uasm_i_mtc0(&p, GPR_K0, C0_GUESTCTL0);

arch/mips/kvm/entry.c

303

UASM_i_MFC0(&p, GPR_K0, C0_ENTRYHI);

arch/mips/kvm/entry.c

304

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_entryhi),

arch/mips/kvm/entry.c

317

UASM_i_LW(&p, GPR_K0, 0, GPR_T3);

arch/mips/kvm/entry.c

329

uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T2);

arch/mips/kvm/entry.c

331

uasm_i_andi(&p, GPR_K0, GPR_K0, MIPS_ENTRYHI_ASID);

arch/mips/kvm/entry.c

335

uasm_i_mtc0(&p, GPR_K0, C0_ENTRYHI);

arch/mips/kvm/entry.c

345

if (i == GPR_K0 || i == GPR_K1)

arch/mips/kvm/entry.c

352

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, hi), GPR_K1);

arch/mips/kvm/entry.c

353

uasm_i_mthi(&p, GPR_K0);

arch/mips/kvm/entry.c

355

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, lo), GPR_K1);

arch/mips/kvm/entry.c

356

uasm_i_mtlo(&p, GPR_K0);

arch/mips/kvm/entry.c

360

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

400

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu, arch.gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

410

uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */

arch/mips/kvm/entry.c

412

uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */

arch/mips/kvm/entry.c

430

build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */

arch/mips/kvm/entry.c

432

build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */

arch/mips/kvm/entry.c

437

build_get_ptep(&p, GPR_K0, GPR_K1);

arch/mips/kvm/entry.c

438

build_update_entries(&p, GPR_K0, GPR_K1);

arch/mips/kvm/entry.c

448

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu, arch.gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

487

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

535

if (i == GPR_K0 || i == GPR_K1)

arch/mips/kvm/entry.c

563

UASM_i_MFC0(&p, GPR_K0, C0_EPC);

arch/mips/kvm/entry.c

564

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, pc), GPR_K1);

arch/mips/kvm/entry.c

566

UASM_i_MFC0(&p, GPR_K0, C0_BADVADDR);

arch/mips/kvm/entry.c

567

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr),

arch/mips/kvm/entry.c

570

uasm_i_mfc0(&p, GPR_K0, C0_CAUSE);

arch/mips/kvm/entry.c

571

uasm_i_sw(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), GPR_K1);

arch/mips/kvm/entry.c

574

uasm_i_mfc0(&p, GPR_K0, C0_BADINSTR);

arch/mips/kvm/entry.c

575

uasm_i_sw(&p, GPR_K0, offsetof(struct kvm_vcpu_arch,

arch/mips/kvm/entry.c

580

uasm_i_mfc0(&p, GPR_K0, C0_BADINSTRP);

arch/mips/kvm/entry.c

581

uasm_i_sw(&p, GPR_K0, offsetof(struct kvm_vcpu_arch,

arch/mips/kvm/entry.c

592

uasm_i_or(&p, GPR_K0, GPR_V0, GPR_AT);

arch/mips/kvm/entry.c

594

uasm_i_mtc0(&p, GPR_K0, C0_STATUS);

arch/mips/kvm/entry.c

597

UASM_i_LA_mostly(&p, GPR_K0, (long)&ebase);

arch/mips/kvm/entry.c

598

UASM_i_LW(&p, GPR_K0, uasm_rel_lo((long)&ebase), GPR_K0);

arch/mips/kvm/entry.c

599

build_set_exc_base(&p, GPR_K0);

arch/mips/kvm/entry.c

635

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_entryhi),

arch/mips/kvm/entry.c

637

UASM_i_MTC0(&p, GPR_K0, C0_ENTRYHI);

arch/mips/kvm/entry.c

657

uasm_i_mfc0(&p, GPR_K0, C0_GUESTCTL0);

arch/mips/kvm/entry.c

658

uasm_i_ins(&p, GPR_K0, GPR_ZERO, MIPS_GCTL0_GM_SHIFT, 1);

arch/mips/kvm/entry.c

659

uasm_i_mtc0(&p, GPR_K0, C0_GUESTCTL0);

arch/mips/kvm/entry.c

662

uasm_i_sw(&p, GPR_K0,

arch/mips/kvm/entry.c

703

kvm_mips_build_restore_scratch(&p, GPR_K0, GPR_SP);

arch/mips/kvm/entry.c

706

UASM_i_LA_mostly(&p, GPR_K0, (long)&hwrena);

arch/mips/kvm/entry.c

707

uasm_i_lw(&p, GPR_K0, uasm_rel_lo((long)&hwrena), GPR_K0);

arch/mips/kvm/entry.c

708

uasm_i_mtc0(&p, GPR_K0, C0_HWRENA);

arch/mips/kvm/entry.c

801

uasm_i_or(&p, GPR_K0, GPR_V1, GPR_AT);

arch/mips/kvm/entry.c

802

uasm_i_mtc0(&p, GPR_K0, C0_STATUS);

arch/mips/kvm/entry.c

841

uasm_i_sra(&p, GPR_K0, GPR_V0, 2);

arch/mips/kvm/entry.c

842

uasm_i_move(&p, GPR_V0, GPR_K0);

arch/mips/kvm/entry.c

852

UASM_i_LA_mostly(&p, GPR_K0, (long)&hwrena);

arch/mips/kvm/entry.c

853

uasm_i_lw(&p, GPR_K0, uasm_rel_lo((long)&hwrena), GPR_K0);

arch/mips/kvm/entry.c

854

uasm_i_mtc0(&p, GPR_K0, C0_HWRENA);

arch/mips/mm/tlbex.c

1260

htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, GPR_K0, GPR_K1,

arch/mips/mm/tlbex.c

1264

htlb_info.huge_pte = GPR_K0;

arch/mips/mm/tlbex.c

1274

uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);

arch/mips/mm/tlbex.c

1276

uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1277

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);

arch/mips/mm/tlbex.c

1278

uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1);

arch/mips/mm/tlbex.c

1279

uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits);

arch/mips/mm/tlbex.c

1280

uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1281

uasm_il_bnez(&p, &r, GPR_K0, label_leave);

arch/mips/mm/tlbex.c

1286

build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */

arch/mips/mm/tlbex.c

1288

build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */

arch/mips/mm/tlbex.c

1292

build_is_huge_pte(&p, &r, GPR_K0, GPR_K1, label_tlb_huge_update);

arch/mips/mm/tlbex.c

1295

build_get_ptep(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1296

build_update_entries(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1306

build_huge_tlb_write_entry(&p, &l, &r, GPR_K0, tlb_random,

arch/mips/mm/tlbex.c

1311

build_get_pgd_vmalloc64(&p, &l, &r, GPR_K0, GPR_K1, vmalloc_mode);

arch/mips/mm/tlbex.c

1484

uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);

arch/mips/mm/tlbex.c

1485

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0,

arch/mips/mm/tlbex.c

1490

uasm_il_bgez(&p, &r, GPR_K0, label_large_segbits_fault);

arch/mips/mm/tlbex.c

1497

uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */

arch/mips/mm/tlbex.c

1499

uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */

arch/mips/mm/tlbex.c

1507

uasm_i_lui(&p, GPR_K0, PM_DEFAULT_MASK >> 16);

arch/mips/mm/tlbex.c

1508

uasm_i_ori(&p, GPR_K0, GPR_K0, PM_DEFAULT_MASK & 0xffff);

arch/mips/mm/tlbex.c

1509

uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK);

arch/mips/mm/tlbex.c

1511

uasm_i_ori(&p, GPR_K0, 0, PM_DEFAULT_MASK);

arch/mips/mm/tlbex.c

1512

uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK);

arch/mips/mm/tlbex.c

1888

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1889

build_pte_present(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbl);

arch/mips/mm/tlbex.c

1891

build_make_valid(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1892

build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1918

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1919

build_pte_writable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbs);

arch/mips/mm/tlbex.c

1921

build_make_write(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1922

build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1948

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1949

build_pte_modifiable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbm);

arch/mips/mm/tlbex.c

1951

build_make_write(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1952

build_r3000_pte_reload_tlbwi(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

2068

uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);

arch/mips/mm/tlbex.c

2070

uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

2071

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);

arch/mips/mm/tlbex.c

2072

uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1);

arch/mips/mm/tlbex.c

2073

uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits);

arch/mips/mm/tlbex.c

2074

uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

2075

uasm_il_bnez(&p, &r, GPR_K0, label_leave);

arch/mips/mm/tlbex.c

2218

uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_0));

arch/mips/mm/tlbex.c

2219

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_0));

arch/mips/mm/tlbex.c

2220

uasm_i_jr(&p, GPR_K0);

arch/mips/mm/tlbex.c

2274

uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

2275

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

2276

uasm_i_jr(&p, GPR_K0);

arch/mips/mm/tlbex.c

2331

uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

2332

uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));

arch/mips/mm/tlbex.c

2333

uasm_i_jr(&p, GPR_K0);

arch/mips/mm/tlbex.c

340

r.r1 = GPR_K0;

arch/mips/mm/tlbex.c

348

UASM_i_CPUID_MFC0(p, GPR_K0, SMP_CPUID_REG);

arch/mips/mm/tlbex.c

349

UASM_i_SRL_SAFE(p, GPR_K0, GPR_K0, SMP_CPUID_REGSHIFT);

arch/mips/mm/tlbex.c

352

UASM_i_SLL(p, GPR_K0, GPR_K0, ilog2(sizeof(struct tlb_reg_save)));

arch/mips/mm/tlbex.c

355

UASM_i_ADDU(p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

357

UASM_i_LA(p, GPR_K0, (long)&handler_reg_save);

arch/mips/mm/tlbex.c

360

UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0);

arch/mips/mm/tlbex.c

361

UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0);

arch/mips/mm/tlbex.c

377

UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0);

arch/mips/mm/tlbex.c

378

UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0);

arch/mips/mm/tlbex.c

397

uasm_i_mfc0(&p, GPR_K0, C0_BADVADDR);

arch/mips/mm/tlbex.c

400

uasm_i_srl(&p, GPR_K0, GPR_K0, 22); /* load delay */

arch/mips/mm/tlbex.c

401

uasm_i_sll(&p, GPR_K0, GPR_K0, 2);

arch/mips/mm/tlbex.c

402

uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);

arch/mips/mm/tlbex.c

403

uasm_i_mfc0(&p, GPR_K0, C0_CONTEXT);

arch/mips/mm/tlbex.c

405

uasm_i_andi(&p, GPR_K0, GPR_K0, 0xffc); /* load delay */

arch/mips/mm/tlbex.c

406

uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);

arch/mips/mm/tlbex.c

407

uasm_i_lw(&p, GPR_K0, 0, GPR_K1);

arch/mips/mm/tlbex.c

409

uasm_i_mtc0(&p, GPR_K0, C0_ENTRYLO0);