GPIO_D5_SPI_CCLK
GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
#define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
#define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
#define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
tmp &= ~GPIO_D5_SPI_CCLK;
tmp |= GPIO_D5_SPI_CCLK;
#define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\