Symbol: GPIO_BASE
drivers/leds/leds-ss4200.c
373
status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
drivers/mfd/lpc_sch.c
148
ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio",
drivers/pinctrl/pinctrl-xway.c
43
#define GPIO_OUT(p) GPIO_BASE(p)
drivers/pinctrl/pinctrl-xway.c
44
#define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
drivers/pinctrl/pinctrl-xway.c
45
#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
drivers/pinctrl/pinctrl-xway.c
46
#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
drivers/pinctrl/pinctrl-xway.c
47
#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
drivers/pinctrl/pinctrl-xway.c
48
#define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
drivers/pinctrl/pinctrl-xway.c
49
#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
drivers/pinctrl/pinctrl-xway.c
50
#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
drivers/pinctrl/pinctrl-xway.c
53
#define GPIO3_OD (GPIO_BASE(0) + 0x24)
drivers/pinctrl/pinctrl-xway.c
54
#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
drivers/pinctrl/pinctrl-xway.c
55
#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
drivers/pinctrl/pinctrl-xway.c
56
#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h
19
OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h
20
ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h
29
OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/gpio_private.h
30
return ia_css_device_load_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data));
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl.c
62
OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/timed_ctrl.c
65
GPIO_BASE[GPIO_ID] + offset, value);
drivers/staging/media/atomisp/pci/system_local.c
93
const hrt_address GPIO_BASE[N_GPIO_ID] = {
drivers/staging/media/atomisp/pci/system_local.h
62
extern const hrt_address GPIO_BASE[N_GPIO_ID];