GPDR
(GPDR(i) & GPIO_bit(i))) {
saved_gpdr[i] = GPDR(i * 32);
GPDR(i) |= GPIO_bit(i);
GPDR(i) &= ~GPIO_bit(i);
GPDR(i * 32) = saved_gpdr[i];
gpdr_lpm[i] = GPDR(i * 32);
GPDR(gpio) |= mask;
GPDR(gpio) &= ~mask;
GPDR &= ~SDA;
GPDR |= SDA;
unsigned gpdr = GPDR;
GPDR = (GPDR | SCK | MOD) & ~SDA;
GPDR |= SDA;
GPDR = gpdr;
GPDR |= GPIO_GPIO16;
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPDR |= GPIO_GPIO27;
GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
GPDR |= 0x3fc; /* restore correct pin direction */
GPDR |= GPIO_32_768kHz;
GPDR &= ~GPIO_32_768kHz;
GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
GPDR = 0; /* Configure all GPIOs as input */
GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */
SAVE(GPDR);
RESTORE(GPDR);
gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR));
writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR));
GPDR |= mask;