GPC_PGC_CTRL
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),