drivers/gpu/drm/gma500/intel_gmbus.c

123

GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);

drivers/gpu/drm/gma500/intel_gmbus.c

124

GMBUS_REG_WRITE(gpio->reg, reserved);

drivers/gpu/drm/gma500/intel_gmbus.c

133

GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);

drivers/gpu/drm/gma500/intel_gmbus.c

134

GMBUS_REG_WRITE(gpio->reg, reserved);

drivers/gpu/drm/gma500/intel_gmbus.c

151

GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);

drivers/gpu/drm/gma500/intel_gmbus.c

168

GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);

drivers/gpu/drm/gma500/intel_gmbus.c

264

GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);

drivers/gpu/drm/gma500/intel_gmbus.c

271

GMBUS_REG_WRITE(GMBUS1 + reg_offset,

drivers/gpu/drm/gma500/intel_gmbus.c

301

GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);

drivers/gpu/drm/gma500/intel_gmbus.c

302

GMBUS_REG_WRITE(GMBUS1 + reg_offset,

drivers/gpu/drm/gma500/intel_gmbus.c

322

GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);

drivers/gpu/drm/gma500/intel_gmbus.c

340

GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);

drivers/gpu/drm/gma500/intel_gmbus.c

341

GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);

drivers/gpu/drm/gma500/intel_gmbus.c

347

GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);

drivers/gpu/drm/gma500/intel_gmbus.c

353

GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);

drivers/gpu/drm/gma500/intel_gmbus.c

81

GMBUS_REG_WRITE(GMBUS0, 0);