drivers/gpu/drm/gma500/intel_gmbus.c

111

reserved = GMBUS_REG_READ(gpio->reg) &

drivers/gpu/drm/gma500/intel_gmbus.c

125

return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;

drivers/gpu/drm/gma500/intel_gmbus.c

135

return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;

drivers/gpu/drm/gma500/intel_gmbus.c

152

GMBUS_REG_READ(gpio->reg); /* Posting */

drivers/gpu/drm/gma500/intel_gmbus.c

169

GMBUS_REG_READ(gpio->reg);

drivers/gpu/drm/gma500/intel_gmbus.c

277

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

281

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

284

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

drivers/gpu/drm/gma500/intel_gmbus.c

287

val = GMBUS_REG_READ(GMBUS3 + reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

307

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

310

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

313

if (GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

323

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

327

if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))

drivers/gpu/drm/gma500/intel_gmbus.c

329

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)