drivers/gpu/drm/gma500/intel_gmbus.c

277

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

281

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

284

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

drivers/gpu/drm/gma500/intel_gmbus.c

307

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

310

if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

313

if (GMBUS_REG_READ(GMBUS2 + reg_offset) &

drivers/gpu/drm/gma500/intel_gmbus.c

323

GMBUS_REG_READ(GMBUS2+reg_offset);

drivers/gpu/drm/gma500/intel_gmbus.c

327

if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))

drivers/gpu/drm/gma500/intel_gmbus.c

329

if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

drivers/gpu/drm/i915/display/intel_gmbus.c

418

ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

drivers/gpu/drm/i915/display/intel_gmbus.c

422

ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),

drivers/gpu/drm/i915/display/intel_gmbus.c

450

ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);