AMDGPU_MAX_MES_PIPES
for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++)
for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES];
uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
void *resource_1_addr[AMDGPU_MAX_MES_PIPES];
struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES];
uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES];
void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES];
(AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES)
(xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id)
uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
(AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE;
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {