drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

228

unsigned int phy_inst = GET_INST(GC, xcc_inst);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

299

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

300

hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

338

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

342

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

344

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

346

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

351

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

355

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

48

SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

493

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

498

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

127

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

128

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

174

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), gfx_index_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

175

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regSQ_CMD), sq_cmd);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

184

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

350

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

354

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

67

WREG32_SOC15(GC, GET_INST(GC, inst), regCPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

82

uint32_t dev_inst = GET_INST(SDMA0, engine_id);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1072

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1111

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1113

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1119

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1121

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1201

WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1211

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1212

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

171

WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

238

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

241

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

277

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

281

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

283

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

290

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

294

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

372

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

373

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

54

soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

540

WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

557

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

59

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

635

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

636

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

645

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

909

*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

94

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

95

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

964

soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

499

inst_id = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

46

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

49

JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

73

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

75

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

78

JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

87

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

89

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

439

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

568

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

147

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

150

VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

200

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

203

VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

134

i = GET_INST(GC, (ffs(inst_mask) - 1));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1123

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1126

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1129

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1142

data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1145

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1146

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1354

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1362

gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1366

gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1382

gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1387

gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1450

soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1452

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1453

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1456

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1458

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1461

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1463

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1465

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1483

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1486

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1501

soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1503

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1510

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1513

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1545

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1556

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1564

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1566

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1568

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1577

u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1580

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1595

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1598

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1617

rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1631

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1642

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1662

tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1665

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1680

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1684

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1688

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1707

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1712

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1717

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1724

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1729

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1734

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1737

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1740

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1791

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1794

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1836

soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1837

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1840

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1843

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1846

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1851

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1858

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1881

soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1882

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1885

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1888

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1900

cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1901

bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1942

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1963

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2054

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2058

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2060

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2063

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2067

soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2069

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2073

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2078

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2080

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2084

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2087

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2089

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2093

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2106

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2108

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2112

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2136

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2139

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2141

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2148

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2149

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2152

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2156

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2308

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2311

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2314

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2316

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2320

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2324

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2328

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2329

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2331

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2335

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2337

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2339

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2341

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2346

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2348

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2352

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2356

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2358

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2362

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2366

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2368

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2372

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2374

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2377

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2381

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2383

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2387

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2389

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2393

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2397

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2420

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2422

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2429

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2432

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2452

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2454

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2648

gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2685

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2687

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2689

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

269

scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2691

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2700

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2703

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2709

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2710

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2718

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2721

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2729

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2732

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2894

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2896

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2940

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3015

rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3028

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3032

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3042

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3063

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3073

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3075

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3081

uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3145

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3159

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3163

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3178

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3182

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3190

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3192

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3197

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3200

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3209

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3224

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3231

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3235

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3242

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3255

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3265

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3276

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3284

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3295

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3303

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3363

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3380

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3538

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3617

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3622

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3627

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3632

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3760

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3783

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3859

GET_INST(GC, i), regRLC_RLCS_FED_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

4053

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

4061

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

4062

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

534

reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

537

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

539

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

542

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

544

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

546

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

548

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

550

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

552

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

635

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

638

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

646

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

652

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

718

soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

731

reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

742

if (xcc == GET_INST(GC, logic_xcc))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1238

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1240

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1241

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1244

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1246

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1248

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1256

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1257

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1258

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1259

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1274

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1275

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1276

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1277

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1292

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1307

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1314

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1316

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1323

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1331

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1335

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1352

RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1378

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1393

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1395

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1403

rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1417

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1421

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1433

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1443

reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1444

reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1445

reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1446

reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1447

reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1448

reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1449

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1450

reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1476

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1500

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1513

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1519

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1524

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1541

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1544

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1560

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1583

rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1590

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1594

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1617

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1624

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1626

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1646

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1675

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1686

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1688

WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1735

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1737

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1776

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1778

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1780

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1784

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1786

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1807

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1810

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1853

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1860

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1893

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1903

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1930

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1935

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1940

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1946

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1969

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1971

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1973

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1977

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1981

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1985

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1986

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1988

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1992

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1994

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1996

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1998

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2003

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2005

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2009

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2013

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2015

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2019

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2023

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2025

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2029

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2031

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2037

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2043

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2050

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2054

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2056

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2060

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2062

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2066

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2070

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2082

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2084

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2087

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2096

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2099

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2103

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2104

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2105

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2106

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2107

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2108

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2109

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2110

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2138

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2140

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2149

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2152

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2181

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2183

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2210

ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2212

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2330

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2342

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2345

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2500

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2504

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2532

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2551

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2564

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2567

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2568

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2573

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2574

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2592

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2597

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2602

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2607

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2650

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2659

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2672

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2681

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2694

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2702

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2708

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2711

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2715

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2718

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2723

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2731

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2734

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2737

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2741

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2744

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2758

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2767

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2770

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2779

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2782

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2786

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2788

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2793

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2881

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2886

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2895

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2900

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

304

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

305

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3056

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

308

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3131

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3150

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3153

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3156

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3159

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3201

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3203

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3205

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3207

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3226

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3266

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3305

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3494

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3497

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3500

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3503

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3525

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

353

dev_inst = GET_INST(GC, i);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3548

soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3550

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3558

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3588

reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3621

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3622

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

426

scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4480

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4489

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4510

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4546

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4551

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4568

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4587

data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4603

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4729

GET_INST(GC, xcc_id)));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4748

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4756

RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4764

GET_INST(GC, xcc_id)));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4954

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4961

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4962

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

5029

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

5032

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

514

WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

516

((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

713

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

718

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

723

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

730

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

738

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

784

soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

792

xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

817

WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

111

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

114

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

118

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

121

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

125

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

128

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

132

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

135

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

158

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

160

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

162

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

165

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

167

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

169

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

171

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

174

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

176

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

179

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

182

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

184

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

188

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

190

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

192

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

195

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

198

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

201

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

206

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

210

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

214

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

218

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

226

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

229

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

234

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

237

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

247

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

260

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

282

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

295

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

311

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

314

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

319

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

332

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

347

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

352

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL5, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

363

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

375

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

386

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

389

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

393

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

396

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

400

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

403

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

424

tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

43

base = RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

451

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regGCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

453

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

456

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

459

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

463

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

483

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

486

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

49

RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

503

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

506

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

509

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

512

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

552

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

557

tmp = RREG32_SOC15(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

56

return (u64)(RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

563

WREG32_SOC15_RLC(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

568

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

570

WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

571

WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

591

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

639

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

642

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

647

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

70

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

75

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

765

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

768

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

771

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

774

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

777

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

780

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

784

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

787

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

101

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

104

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

108

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

111

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

115

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

118

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

135

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

136

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

137

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

141

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

154

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

159

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

165

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

167

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

171

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

173

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

176

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

179

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

186

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

187

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

188

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

189

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

190

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

191

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

204

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

218

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

230

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

239

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

244

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

256

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

267

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

278

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

286

WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

297

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

300

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

304

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

307

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

311

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

313

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

346

tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

380

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

382

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

385

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

388

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

392

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

410

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

412

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

456

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

460

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

466

WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

470

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

472

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

473

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

494

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

52

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

523

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

551

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

554

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

557

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

559

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

561

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

563

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

565

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

568

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

57

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

599

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

601

RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

94

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

97

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

261

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

249

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

326

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

825

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

827

tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

838

WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

840

WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

853

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

855

tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

868

WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

870

WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

100

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

109

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_D_RAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

112

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

116

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

93

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_I_RAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

96

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1018

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1036

ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1162

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1262

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1344

NULL, 0, GET_INST(VCN, jpeg_inst),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1369

GET_INST(VCN, jpeg_inst));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

173

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

276

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

392

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

397

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

412

VCN, GET_INST(VCN, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

498

jpeg_inst = GET_INST(JPEG, inst_idx);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

523

jpeg_inst = GET_INST(JPEG, inst_idx);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

545

int jpeg_inst = GET_INST(JPEG, inst);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

575

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

637

int jpeg_inst = GET_INST(JPEG, inst);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

680

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

698

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

724

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

742

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

783

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

170

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

271

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

275

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

285

WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

368

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

389

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

405

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

474

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

613

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

631

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

650

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

667

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

687

ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

821

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

927

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

156

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

226

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

230

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

246

WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

324

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

345

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

361

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

456

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

474

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

493

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

510

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

530

ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

649

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c

745

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1065

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1068

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1073

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1076

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1079

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1083

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1089

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1098

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1106

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1121

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1125

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1127

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1130

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1160

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1162

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1165

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1167

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1171

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1174

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1176

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1180

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1184

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1187

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1190

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1192

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1195

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1364

soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1367

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1369

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1372

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1375

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1378

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1379

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1382

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1384

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1387

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1388

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1391

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1393

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1397

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1400

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1402

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1406

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1410

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1413

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1415

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1695

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1698

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1699

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1701

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1706

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1711

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1713

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1715

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1716

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1717

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1719

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1731

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1734

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1736

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

2086

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

2091

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

2128

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

2135

tmp = RREG32_SOC15(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

578

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

586

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

597

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

607

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

611

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

755

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

758

adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

760

adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

762

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

774

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

781

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

783

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

790

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

792

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

799

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

801

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

808

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

810

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

817

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

820

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

828

uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

841

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

118

base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

124

RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

132

return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

146

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

151

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

185

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

188

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

192

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

195

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

199

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

202

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

206

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

209

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

235

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

237

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

239

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

242

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

244

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

246

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

248

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

251

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

253

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

256

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

259

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

261

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

265

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

267

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

269

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

272

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

275

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

278

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

283

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

287

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

291

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

295

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

303

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

306

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

311

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

314

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

318

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

324

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

337

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

350

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

369

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

383

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

385

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

390

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

402

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

417

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

422

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL5, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

433

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

444

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

461

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

464

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

468

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

471

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

475

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

478

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

494

tmp = RREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

522

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

524

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

526

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

528

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

531

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

550

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

553

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

595

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

600

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

606

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

610

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

612

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

613

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

639

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

668

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

763

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

766

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

769

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

772

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

775

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

778

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

782

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

785

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

805

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_BANK_SELECT_RESERVED_CID2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

808

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXTS_DISABLE);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

832

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

833

def1 = data1 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

834

def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

853

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

855

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2, data1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

858

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2, data2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

867

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

87

xgmi_lfb_cntl = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

875

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

90

RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMMMC_VM_XGMI_LFB_SIZE),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

902

data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

81

dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

118

u32 dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1752

return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2049

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2054

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2196

dev_inst = GET_INST(SDMA0, i);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2444

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2482

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

120

u32 dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1321

if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id))

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1326

xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1334

GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1544

GET_INST(GC, xcc_id) * adev->sdma.num_inst_per_xcc;

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1546

if (inst == GET_INST(SDMA0, instances))

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1697

dev_inst = GET_INST(SDMA0, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1046

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1219

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1386

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1429

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1565

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1585

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1652

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1693

VCN, GET_INST(VCN, inst),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1734

vcn_inst = GET_INST(VCN, ring->me);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1748

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1820

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1839

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1859

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1886

if (RREG32_SOC15(VCN, GET_INST(VCN, i),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2068

NULL, 0, GET_INST(VCN, vcn_inst),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2093

GET_INST(VCN, vcn_inst));

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

216

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

316

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

362

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

479

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

670

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

817

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

872

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1140

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1178

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1299

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1339

VCN, GET_INST(VCN, inst),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1380

vcn_inst = GET_INST(VCN, ring->me);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1464

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1482

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1500

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1528

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

177

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

278

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

316

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

430

vcn_inst = GET_INST(VCN, inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

627

vcn_inst = GET_INST(VCN, vinst->inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

678

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

817

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

992

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

1038

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

1056

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

1074

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

1102

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

116

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

206

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x200)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

209

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

327

vcn_inst = GET_INST(VCN, inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

524

vcn_inst = GET_INST(VCN, vinst->inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

574

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

696

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

839

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

872

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

947

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

967

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

988

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdkfd/kfd_device.c

724

mapped_xcc = GET_INST(GC, xcc);

drivers/gpu/drm/amd/amdkfd/kfd_device.c

733

mapped_xcc = GET_INST(GC, xcc);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

410

xcc_id = GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

802

inst = GET_INST(VCN, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

826

inst = GET_INST(GC, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

904

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

912

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

935

gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

972

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

986

inst = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1294

xcc_id = GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2708

inst = GET_INST(VCN, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2736

inst = GET_INST(GC, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2829

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2837

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2864

version) >> GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2930

inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2938

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2945

inst = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1638

inst = GET_INST(VCN, k);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1655

inst = GET_INST(GC, k);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1740

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1755

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1771

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1811

inst = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

387

xcc_id = GET_INST(GC, 0);