GENMASK_U32
#define PERF_BURST_SCALE_MASK GENMASK_U32(3, 2)
#define PERF_MRRS_MASK GENMASK_U32(6, 4)
#define PERF_INTERVAL_MASK GENMASK_U32(10, 8)
#define PERF_BURST_SIZE_MASK GENMASK_U32(14, 12)
#define PERF_ARB_WEIGHT_MASK GENMASK_U32(31, 24)
#define SE_BUF_BASE_MASK GENMASK_U32(10, 2)
#define SE_BUF_LEN_MASK GENMASK_U32(20, 12)
#define SE_THRESH_MASK GENMASK_U32(31, 23)
#define RXPSIZESETR_SIZE_MASK GENMASK_U32(6, 3)
#define RXPHDR_VC_MASK GENMASK_U32(23, 22)
#define RXPHDR_DT_MASK GENMASK_U32(21, 16)
#define RXPHDR_DATA1_MASK GENMASK_U32(15, 8)
#define RXPHDR_DATA0_MASK GENMASK_U32(7, 0)
#define AKEPR_VC_MASK GENMASK_U32(23, 22)
#define AKEPR_DT_MASK GENMASK_U32(21, 16)
#define AKEPR_ERRRPT_MASK GENMASK_U32(15, 0)
#define TXVMSETR_PIXWDTH_MASK GENMASK_U32(10, 8)
#define TXSETR_LANECNT_MASK GENMASK_U32(1, 0)
#define TXVMVPRMSET0R_BPP_MASK GENMASK_U32(2, 0)
#define TXVMVPRMSET1R_VACTIVE_MASK GENMASK_U32(30, 16)
#define TXVMVPRMSET1R_VSA_MASK GENMASK_U32(11, 0)
#define TXVMVPRMSET2R_VFP_MASK GENMASK_U32(28, 16)
#define TXVMVPRMSET2R_VBP_MASK GENMASK_U32(12, 0)
#define TXVMVPRMSET3R_HACTIVE_MASK GENMASK_U32(30, 16)
#define TXVMVPRMSET3R_HSA_MASK GENMASK_U32(11, 0)
#define TXVMVPRMSET4R_HFP_MASK GENMASK_U32(28, 16)
#define TXVMVPRMSET4R_HBP_MASK GENMASK_U32(12, 0)
#define PPISETR_DLEN_MASK GENMASK_U32(3, 0)
#define PPIDLSR_STPST GENMASK_U32(3, 0)
#define LPCLKSET_LPCLKDIV_MASK GENMASK_U32(5, 0)
#define CFGCLKSET_CFGCLKDIV_MASK GENMASK_U32(5, 0)
#define DOTCLKDIV_DOTCLKDIV_MASK GENMASK_U32(5, 0)
#define VCLKSET_DIV_V3U_MASK GENMASK_U32(5, 4)
#define VCLKSET_DIV_V4H_MASK GENMASK_U32(6, 4)
#define VCLKSET_BPP_MASK GENMASK_U32(3, 2)
#define VCLKSET_LANE_MASK GENMASK_U32(1, 0)
#define PHYSETUP_HSFREQRANGE_MASK GENMASK_U32(22, 16)
#define PHYSETUP_CFGCLKFREQRANGE_MASK GENMASK_U32(13, 8)
#define CLOCKSET1_CLKINSEL_MASK GENMASK_U32(3, 2)
#define CLOCKSET2_M_MASK GENMASK_U32(27, 16)
#define CLOCKSET2_VCO_CNTRL_MASK GENMASK_U32(13, 8)
#define CLOCKSET2_N_MASK GENMASK_U32(3, 0)
#define CLOCKSET3_PROP_CNTRL_MASK GENMASK_U32(29, 24)
#define CLOCKSET3_INT_CNTRL_MASK GENMASK_U32(21, 16)
#define CLOCKSET3_CPBIAS_CNTRL_MASK GENMASK_U32(14, 8)
#define CLOCKSET3_GMP_CNTRL_MASK GENMASK_U32(1, 0)
#define PHTW_TESTDIN_DATA_MASK GENMASK_U32(23, 16)
#define PHTW_TESTDIN_CODE_MASK GENMASK_U32(7, 0)
#define PHTR_TESTDOUT GENMASK_U32(23, 16)
#define TXCMPHDR_VC_MASK GENMASK_U32(23, 22)
#define TXCMPHDR_DT_MASK GENMASK_U32(21, 16)
#define TXCMPHDR_DATA1_MASK GENMASK_U32(15, 8)
#define TXCMPHDR_DATA0_MASK GENMASK_U32(7, 0)
#define RXSETR_CRCEN_MASK GENMASK_U32(27, 24)
#define RXSETR_ECCEN_MASK GENMASK_U32(19, 16)
#define GLB_CTRL_CUR_VERSION(r) FIELD_GET(GENMASK_U32(19, 16), r)
return FIELD_GET(GENMASK_U32(15, 0), val);
ack = FIELD_GET(GENMASK_U32(31, 16), val);
val &= ~GENMASK_U32(31, 16);
val |= FIELD_PREP(GENMASK_U32(31, 16), ack);
return FIELD_GET(GENMASK_U32(31, 16), val);
req = FIELD_GET(GENMASK_U32(15, 0), val);
val &= ~GENMASK_U32(15, 0);
val |= FIELD_PREP(GENMASK_U32(15, 0), req);
hw->mbx.fw_req = FIELD_GET(GENMASK_U32(15, 0), val);
hw->mbx.fw_ack = FIELD_GET(GENMASK_U32(31, 16), val);
mbx_ctrl_wr32(mbx, MUCSE_MBX_FWPF_MASK(mbx), GENMASK_U32(31, 16));
.version = cpu_to_le32(GENMASK_U32(31, 0)),
#define DWMAC_SNPSVER GENMASK_U32(7, 0)
#define DWMAC_USERVER GENMASK_U32(15, 8)
mac->mii.addr_mask = GENMASK_U32(15, 11);
mac->mii.reg_mask = GENMASK_U32(10, 6);
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
mac->mii.reg_mask = GENMASK_U32(8, 4);
mac->mii.addr_mask = GENMASK_U32(16, 12);
mac->mii.clk_csr_mask = GENMASK_U32(22, 20);
mac->mii.addr_mask = GENMASK_U32(15, 11);
mac->mii.reg_mask = GENMASK_U32(10, 6);
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
mac->mii.addr_mask = GENMASK_U32(15, 11);
mac->mii.reg_mask = GENMASK_U32(10, 6);
mac->mii.clk_csr_mask = GENMASK_U32(5, 2);
mac->mii.addr_mask = GENMASK_U32(25, 21);
mac->mii.reg_mask = GENMASK_U32(20, 16);
mac->mii.clk_csr_mask = GENMASK_U32(11, 8);
mac->mii.addr_mask = GENMASK_U32(20, 16);
mac->mii.reg_mask = GENMASK_U32(15, 0);
mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
mac->mii.addr_mask = GENMASK_U32(20, 16);
mac->mii.reg_mask = GENMASK_U32(15, 0);
mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
#define PCIE_INT_ALL_MASK GENMASK_U32(31, 0)
.reset_vector_mask = GENMASK_U32(31, 16),
.reset_vector_mask = GENMASK_U32(31, 16),
.reset_vector_mask = GENMASK_U32(31, 16),
.reset_vector_mask = GENMASK_U32(31, 16),
res->max_value = GENMASK_U32(param->width - 1, 0);
#define REG_GENMASK(high, low) GENMASK_U32(high, low)
u32 bytes_mask = GENMASK_U32(31, 22);
static_assert(assert_type(u32, GENMASK_U32(31, 0)) == U32_MAX);
KUNIT_EXPECT_EQ(test, 0x10000, GENMASK_U32(16, 16));
GENMASK_U32(0, 31);
GENMASK_U32(32, 0);
~GENMASK_U32(min(channels, slots) - 1, 0));