arch/arm/mach-tegra/irq.c

51

writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);

arch/arm64/kvm/vgic/vgic-mmio-v2.c

284

case GIC_CPU_CTRL:

arch/arm64/kvm/vgic/vgic-mmio-v2.c

331

case GIC_CPU_CTRL:

arch/arm64/kvm/vgic/vgic-mmio-v2.c

477

REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,

drivers/irqchip/irq-gic.c

457

bypass = readl(cpu_base + GIC_CPU_CTRL);

drivers/irqchip/irq-gic.c

460

writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);

drivers/irqchip/irq-gic.c

536

val = readl(cpu_base + GIC_CPU_CTRL);

drivers/irqchip/irq-gic.c

538

writel_relaxed(val, cpu_base + GIC_CPU_CTRL);

drivers/irqchip/irq-hip04.c

293

writel_relaxed(1, base + GIC_CPU_CTRL);

tools/testing/selftests/kvm/arm64/vgic_init.c

388

KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0));

tools/testing/selftests/kvm/arm64/vgic_init.c

393

KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val);

tools/testing/selftests/kvm/arm64/vgic_init.c

398

KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val);