Symbol: GEN8_RING_CS_GPR
drivers/gpu/drm/i915/gt/intel_lrc.c
1267
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/intel_lrc.c
1275
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/intel_lrc.c
1281
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/intel_lrc.c
1295
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/intel_lrc.c
1311
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/intel_lrc.c
1319
*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
drivers/gpu/drm/i915/gt/selftest_lrc.c
355
i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),
drivers/gpu/drm/i915/gt/selftest_rps.c
68
#define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)
drivers/gpu/drm/i915/gt/selftest_timeline.c
778
const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
drivers/gpu/drm/i915/gvt/handlers.c
2813
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
drivers/gpu/drm/i915/gvt/handlers.c
2815
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
drivers/gpu/drm/i915/gvt/handlers.c
2817
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
drivers/gpu/drm/i915/gvt/handlers.c
2819
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
drivers/gpu/drm/i915/i915_cmd_parser.c
652
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
drivers/gpu/drm/i915/i915_cmd_parser.c
653
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
drivers/gpu/drm/i915/i915_cmd_parser.c
654
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
drivers/gpu/drm/i915/i915_cmd_parser.c
655
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
drivers/gpu/drm/i915/i915_cmd_parser.c
656
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
drivers/gpu/drm/i915/i915_cmd_parser.c
657
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
drivers/gpu/drm/i915/i915_cmd_parser.c
658
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
drivers/gpu/drm/i915/i915_cmd_parser.c
659
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
drivers/gpu/drm/i915/i915_cmd_parser.c
660
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
drivers/gpu/drm/i915/i915_cmd_parser.c
661
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
drivers/gpu/drm/i915/i915_cmd_parser.c
662
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
drivers/gpu/drm/i915/i915_cmd_parser.c
663
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
drivers/gpu/drm/i915/i915_cmd_parser.c
664
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
drivers/gpu/drm/i915/i915_cmd_parser.c
665
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
drivers/gpu/drm/i915/i915_cmd_parser.c
666
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
drivers/gpu/drm/i915/i915_cmd_parser.c
667
REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
drivers/gpu/drm/i915/i915_cmd_parser.c
690
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
drivers/gpu/drm/i915/i915_cmd_parser.c
691
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
drivers/gpu/drm/i915/i915_cmd_parser.c
692
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
drivers/gpu/drm/i915/i915_cmd_parser.c
693
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
drivers/gpu/drm/i915/i915_cmd_parser.c
694
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
drivers/gpu/drm/i915/i915_cmd_parser.c
695
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
drivers/gpu/drm/i915/i915_cmd_parser.c
696
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
drivers/gpu/drm/i915/i915_cmd_parser.c
697
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
drivers/gpu/drm/i915/i915_cmd_parser.c
698
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
drivers/gpu/drm/i915/i915_cmd_parser.c
699
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
drivers/gpu/drm/i915/i915_cmd_parser.c
700
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
drivers/gpu/drm/i915/i915_cmd_parser.c
701
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
drivers/gpu/drm/i915/i915_cmd_parser.c
702
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
drivers/gpu/drm/i915/i915_cmd_parser.c
703
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
drivers/gpu/drm/i915/i915_cmd_parser.c
704
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
drivers/gpu/drm/i915/i915_cmd_parser.c
705
REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
drivers/gpu/drm/i915/i915_perf.c
1946
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1266
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1267
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1268
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40);
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
1269
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);
drivers/gpu/drm/i915/selftests/i915_perf.c
307
gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));