arch/arm64/kvm/vgic/vgic-mmio-v3.c

269

return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS;

arch/arm64/kvm/vgic/vgic-mmio-v3.c

295

if (!(val & GICR_CTLR_ENABLE_LPIS)) {

arch/arm64/kvm/vgic/vgic-mmio-v3.c

301

GICR_CTLR_ENABLE_LPIS,

arch/arm64/kvm/vgic/vgic-mmio-v3.c

303

if (ctlr != GICR_CTLR_ENABLE_LPIS)

arch/arm64/kvm/vgic/vgic-mmio-v3.c

311

GICR_CTLR_ENABLE_LPIS);

drivers/irqchip/irq-gic-v3-its.c

3083

if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {

drivers/irqchip/irq-gic-v3-its.c

3165

(val & GICR_CTLR_ENABLE_LPIS)) {

drivers/irqchip/irq-gic-v3-its.c

3239

val |= GICR_CTLR_ENABLE_LPIS;

drivers/irqchip/irq-gic-v3-its.c

5366

if (!(val & GICR_CTLR_ENABLE_LPIS))

drivers/irqchip/irq-gic-v3-its.c

5388

val &= ~GICR_CTLR_ENABLE_LPIS;

drivers/irqchip/irq-gic-v3-its.c

5414

if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

447

ctlr |= GICR_CTLR_ENABLE_LPIS;