GICD_ISPENDR
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
case GICD_ISPENDR:
reg = val ? GICD_ISPENDR : GICD_ICPENDR;
*val = gic_peek_irq(d, GICD_ISPENDR);
#define GICR_ISPENDR0 GICD_ISPENDR
#define GICR_ISPENDR0 GICD_ISPENDR
gicv3_write_reg(intid, GICD_ISPENDR, 32, 1, 1);
return gicv3_read_reg(intid, GICD_ISPENDR, 32, 1);
vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISPENDR);