arch/arm64/kvm/vgic/vgic-mmio-v3.c

128

case GICD_CTLR: {

arch/arm64/kvm/vgic/vgic-mmio-v3.c

206

case GICD_CTLR:

arch/arm64/kvm/vgic/vgic-mmio-v3.c

627

REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,

arch/arm64/kvm/vgic/vgic-mmio-v3.c

88

case GICD_CTLR:

drivers/irqchip/irq-gic-v3.c

162

return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;

drivers/irqchip/irq-gic-v3.c

179

val = readl_relaxed(gic_data.dist_base + GICD_CTLR);

drivers/irqchip/irq-gic-v3.c

181

writel_relaxed(val, gic_data.dist_base + GICD_CTLR);

drivers/irqchip/irq-gic-v3.c

349

ret = readl_relaxed_poll_timeout_atomic(base + GICD_CTLR, val, !(val & bit),

drivers/irqchip/irq-gic-v3.c

931

writel_relaxed(0, base + GICD_CTLR);

drivers/irqchip/irq-gic-v3.c

969

writel_relaxed(val, base + GICD_CTLR);

include/linux/irqchip/arm-gic-v3.h

114

#define GICR_CTLR GICD_CTLR

tools/testing/selftests/kvm/include/arm64/gic_v3.h

114

#define GICR_CTLR GICD_CTLR

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

361

writel(0, GICD_BASE_GVA + GICD_CTLR);

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

384

GICD_CTLR_ENABLE_G1, GICD_BASE_GVA + GICD_CTLR);

tools/testing/selftests/kvm/lib/arm64/gic_v3.c

47

while (readl(GICD_BASE_GVA + GICD_CTLR) & GICD_CTLR_RWP) {