GIC
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
#define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP
MAX_FEAT(ID_AA64PFR0_EL1, GIC, IMP),
val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
aa64pfr0 |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
pfr1 |= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3);
return kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP);
ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0);
ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME);
ravb_modify(ndev, GIC, GIC_PTME, 0);
gis &= ravb_read(ndev, GIC);
ravb_write(ndev, 0, GIC);
REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),