drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

228

unsigned int phy_inst = GET_INST(GC, xcc_inst);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

299

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

300

hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

309

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

338

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

340

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

342

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

344

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

346

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

351

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

355

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

48

SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

493

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

498

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

127

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

128

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

174

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), gfx_index_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

175

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regSQ_CMD), sq_cmd);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

184

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

350

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

354

WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

67

WREG32_SOC15(GC, GET_INST(GC, inst), regCPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

82

uint32_t dev_inst = GET_INST(SDMA0, engine_id);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1072

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1111

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1113

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1119

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1121

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1201

WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1211

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1212

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

171

WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

238

hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

241

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

277

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

281

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

283

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

290

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

294

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

372

for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

373

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

54

soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

540

WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

557

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

59

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

635

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

636

WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

645

WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

909

*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

94

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

95

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

964

soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

965

reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

1065

amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

934

ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

499

inst_id = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

46

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

49

JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

73

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

75

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

78

JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

87

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

89

WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

147

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

150

VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

200

WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

203

VCN, GET_INST(VCN, inst_idx), \

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

134

i = GET_INST(GC, (ffs(inst_mask) - 1));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1109

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1112

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1115

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1128

data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1131

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1132

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1321

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1329

gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1333

gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1349

gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1354

gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1417

soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1419

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1420

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1423

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1425

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1428

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1430

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1432

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1455

soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1457

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1464

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1467

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1497

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1508

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1516

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1518

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1520

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1529

u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1532

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1547

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1550

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1569

rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1583

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1594

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1614

tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1617

WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1632

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1636

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1640

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1659

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1664

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1669

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1676

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1681

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1686

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1689

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1692

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1743

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1746

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1788

soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1789

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1792

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1795

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1798

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1803

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1810

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1833

soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1834

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1837

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1840

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1852

cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1853

bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1894

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1915

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2006

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2010

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2012

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2015

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2019

soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2021

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2025

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2030

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2032

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2036

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2039

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2041

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2045

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2058

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2060

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2064

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2088

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2091

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2093

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2100

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2101

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2104

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2108

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2255

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2258

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2261

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2263

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2267

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2271

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2275

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2276

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2278

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2282

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2284

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2286

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2288

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2293

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2295

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2299

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2303

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2305

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2309

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2313

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2315

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2319

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2321

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2324

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2328

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2330

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2334

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2336

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2340

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2344

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2367

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2369

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2376

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2379

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2399

soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2401

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2586

gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2623

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2625

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2627

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2629

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2638

val = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2646

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2656

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2659

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2665

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2666

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2674

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2677

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2685

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2688

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

270

scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2789

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2791

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2834

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2909

rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2922

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2926

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2936

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2957

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2967

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2969

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2975

uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3039

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3053

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3057

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3072

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3076

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3084

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3086

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3091

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3094

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3103

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3118

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3125

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3129

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3136

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3149

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3159

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3170

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3178

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3189

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3197

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3257

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3274

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3438

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3519

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3524

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3529

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3534

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3673

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3696

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3937

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3945

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3946

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

529

reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

532

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

534

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

537

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

539

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

541

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

543

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

545

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

547

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

630

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

633

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

641

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

647

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

713

soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

728

if (xcc == GET_INST(GC, logic_xcc))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1238

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1240

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1241

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1244

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1246

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1248

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1256

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1257

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1258

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1259

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1274

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1275

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1276

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1277

WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1292

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1307

soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1314

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1316

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1323

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1331

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1335

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1352

RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1378

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1393

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1395

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1403

rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1417

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1421

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1433

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1443

reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1444

reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1445

reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1446

reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1447

reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1448

reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1449

reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1450

reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1476

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1500

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1513

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1519

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1524

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1541

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1544

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1560

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1583

rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1590

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1594

WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1617

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1624

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1626

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1646

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1675

reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1686

WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1688

WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1735

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1737

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1776

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1778

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1780

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1784

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1786

SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1807

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1810

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1853

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1860

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1893

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1903

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1930

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1935

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1940

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1946

mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1965

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1967

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1969

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1973

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1977

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1981

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1982

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1984

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1988

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1990

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1992

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1994

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1999

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2001

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2005

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2009

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2011

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2015

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2019

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2021

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2025

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2027

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2033

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2039

GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2046

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2050

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2052

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2056

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2058

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2062

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2066

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2078

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2080

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2083

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2092

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2095

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2099

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2100

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2101

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2102

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2103

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2104

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2105

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2106

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2134

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2136

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2145

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2148

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2177

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2179

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2206

ring->queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2208

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2326

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2338

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2341

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2407

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2434

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2453

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2466

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2469

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2470

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2475

WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2476

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2494

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2499

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2504

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2509

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2563

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2572

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2585

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2594

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2607

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2615

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2621

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2624

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2628

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2631

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2636

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2644

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2647

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2650

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2654

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2657

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2671

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2680

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2683

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2692

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2695

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2699

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2701

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2706

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2794

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2799

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2808

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2813

data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2972

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

304

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3047

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

305

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3066

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3069

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3072

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3075

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

308

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3117

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3119

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3121

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3123

return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3142

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3182

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3221

WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3410

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3413

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3416

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3419

wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3441

SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3464

soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3466

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3474

soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3504

reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

353

dev_inst = GET_INST(GC, i);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3537

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3538

WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

426

scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4396

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4405

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4426

GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4462

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4467

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4484

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4503

data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4519

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4645

GET_INST(GC, xcc_id)));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4664

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4672

RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4680

GET_INST(GC, xcc_id)));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4870

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4877

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4878

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4945

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4948

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

514

WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

516

((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

713

WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

718

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

723

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

730

WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

738

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

784

soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

792

xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

817

WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

111

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

114

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

118

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

121

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

125

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

128

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

132

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

135

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

151

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

153

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

155

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

158

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

161

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

164

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

170

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

173

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

176

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

179

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

185

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

188

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

193

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

196

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

200

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

206

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

214

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

216

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

218

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

221

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

223

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

225

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

227

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

229

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

231

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

234

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

237

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

239

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

253

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

275

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

288

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

304

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

307

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

312

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

325

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

332

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

337

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL5, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

348

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

360

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

371

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

374

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

378

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

381

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

385

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

388

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

409

tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

43

base = RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

436

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regGCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

438

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

441

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

444

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

448

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

468

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

471

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

488

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

49

RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

491

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

494

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

497

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

537

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

542

tmp = RREG32_SOC15(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

548

WREG32_SOC15_RLC(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

553

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

555

WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

556

WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

56

return (u64)(RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

576

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

625

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

628

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

634

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

70

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

75

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

752

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

755

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

758

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

761

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

764

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

767

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

771

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

774

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

818

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

820

seg_size = REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

101

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

104

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

108

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

111

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

115

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

118

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

135

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

136

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

137

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

141

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

154

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

159

WREG32_SOC15_RLC(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

165

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

167

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

171

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

173

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

176

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

179

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

186

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

187

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

188

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

189

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

190

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

191

WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

204

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

218

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

230

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

239

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

244

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

256

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

267

WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

278

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

286

WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

297

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

300

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

304

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

307

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

311

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

313

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

346

tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

380

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

382

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

385

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

388

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

392

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

410

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

412

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

456

WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

460

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

466

WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

470

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

472

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

473

WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

494

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

52

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

525

WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

553

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

556

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

559

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

561

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

563

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

565

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

567

SOC15_REG_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

57

WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

570

SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

601

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

603

RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

94

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

97

WREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

261

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

249

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

326

1 << vmid, GET_INST(GC, 0));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

860

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

862

tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

873

WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

875

WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

888

tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

890

tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

903

WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

905

WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

100

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

109

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_D_RAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

112

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

116

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

93

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_I_RAM_ADDR, 0);

drivers/gpu/drm/amd/amdgpu/imu_v12_1.c

96

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1122

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1221

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1303

NULL, 0, GET_INST(VCN, jpeg_inst),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1328

GET_INST(VCN, jpeg_inst));

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

173

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

276

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

392

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

397

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

412

VCN, GET_INST(VCN, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

498

jpeg_inst = GET_INST(JPEG, inst_idx);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

523

jpeg_inst = GET_INST(JPEG, inst_idx);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

545

int jpeg_inst = GET_INST(JPEG, inst);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

575

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

637

int jpeg_inst = GET_INST(JPEG, inst);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

680

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

698

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

724

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

978

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

996

ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

170

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

271

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

275

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

285

WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

368

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

389

int jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

405

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

474

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

613

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

631

return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

650

WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

667

ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

687

ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

821

int jpeg_inst = GET_INST(JPEG, ring->me);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

926

jpeg_inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1010

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1013

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1018

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1021

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1024

WREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1028

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1034

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1043

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1051

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1066

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1070

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1072

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1075

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1105

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1107

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1110

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1112

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1116

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1119

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1121

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1125

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1129

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1132

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1135

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1137

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1140

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1312

soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1315

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1317

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1320

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1323

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1326

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1327

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1330

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1332

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1335

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1336

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1339

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1341

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1345

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1348

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1350

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1354

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1358

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1361

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1363

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1428

soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1431

adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1433

adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1435

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1653

GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1656

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1657

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1659

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1664

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1669

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1671

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1673

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1674

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1675

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1677

soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1689

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1692

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1694

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

540

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

552

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

567

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

582

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

585

GET_INST(GC, input->xcc_id),

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

747

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

754

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

756

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

763

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

765

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

772

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

774

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

781

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

783

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

790

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

793

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

801

uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

814

WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

107

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

112

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

146

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

149

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

153

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

156

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

160

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

163

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

167

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

170

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

194

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

196

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

198

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

201

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

204

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

207

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

212

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

216

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

220

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

224

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

231

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

234

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

239

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

242

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

246

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

252

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

260

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

262

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

264

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

266

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

268

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

270

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

272

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

274

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

276

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

279

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

282

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

284

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

297

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

310

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

329

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

343

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

345

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

350

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

362

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

377

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL4, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

382

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL5, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

393

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

404

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

421

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

424

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

428

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

431

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

435

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

438

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

454

tmp = RREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

482

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

484

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

486

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

488

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

491

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

510

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

513

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

555

WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

560

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

566

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

570

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

572

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

573

WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL3, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

599

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

628

WREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

731

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

734

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

737

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

740

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

743

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

746

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

750

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

753

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

773

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_BANK_SELECT_RESERVED_CID2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

776

SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXTS_DISABLE);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

79

base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

796

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

797

def1 = data1 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

798

def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

817

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

819

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2, data1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

822

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2, data2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

831

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

839

WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

85

RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

866

data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

93

return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

81

dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

119

u32 dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1743

return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2040

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2045

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2187

dev_inst = GET_INST(SDMA0, i);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2463

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2501

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

121

u32 dev_inst = GET_INST(SDMA0, instance);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1294

if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id))

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1299

xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1307

GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1511

GET_INST(GC, xcc_id) * adev->sdma.num_inst_per_xcc;

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1513

if (inst == GET_INST(SDMA0, instances))

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1664

dev_inst = GET_INST(SDMA0, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1029

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1202

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1369

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1412

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1548

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1568

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1635

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1676

VCN, GET_INST(VCN, inst),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1717

vcn_inst = GET_INST(VCN, ring->me);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1731

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1802

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1821

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1841

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1868

if (RREG32_SOC15(VCN, GET_INST(VCN, i),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

199

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2050

NULL, 0, GET_INST(VCN, vcn_inst),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2075

GET_INST(VCN, vcn_inst));

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

299

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

345

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

462

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

653

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

800

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

855

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1140

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1178

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1299

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1339

VCN, GET_INST(VCN, inst),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1380

vcn_inst = GET_INST(VCN, ring->me);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1463

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1481

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1499

ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1527

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

177

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

278

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

316

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

430

vcn_inst = GET_INST(VCN, inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

627

vcn_inst = GET_INST(VCN, vinst->inst);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

678

vcn_inst = GET_INST(VCN, inst_idx);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

817

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

992

vcn_inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/amdkfd/kfd_device.c

711

mapped_xcc = GET_INST(GC, xcc);

drivers/gpu/drm/amd/amdkfd/kfd_device.c

720

mapped_xcc = GET_INST(GC, xcc);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

402

xcc_id = GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

789

inst = GET_INST(VCN, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

813

inst = GET_INST(GC, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

866

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

874

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

897

gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

934

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

948

inst = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1275

xcc_id = GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2614

inst = GET_INST(VCN, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2642

inst = GET_INST(GC, k);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2735

xcc_id = GET_INST(GC, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2743

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2770

version) >> GET_INST(GC, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2836

inst = GET_INST(JPEG, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2844

inst = GET_INST(VCN, i);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2851

inst = GET_INST(GC, i);