drivers/edac/i10nm_base.c

1058

return !!GET_BITFIELD(mcmtr, 2, 2);

drivers/edac/i10nm_base.c

1067

return (mcmtr == ~0 || GET_BITFIELD(mcmtr, 18, 18));

drivers/edac/i10nm_base.c

57

#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)

drivers/edac/i10nm_base.c

58

#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)

drivers/edac/i10nm_base.c

59

#define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \

drivers/edac/i10nm_base.c

60

GET_BITFIELD(reg, 0, 10) + 1) << 12)

drivers/edac/i10nm_base.c

619

res->column = GET_BITFIELD(m->misc, 9, 18) << 2;

drivers/edac/i10nm_base.c

62

((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)

drivers/edac/i10nm_base.c

620

res->row = GET_BITFIELD(m->misc, 19, 39);

drivers/edac/i10nm_base.c

621

res->bank_group = GET_BITFIELD(m->misc, 40, 41);

drivers/edac/i10nm_base.c

622

res->bank_address = GET_BITFIELD(m->misc, 42, 43);

drivers/edac/i10nm_base.c

623

res->bank_group |= GET_BITFIELD(m->misc, 44, 44) << 2;

drivers/edac/i10nm_base.c

624

res->rank = GET_BITFIELD(m->misc, 56, 58);

drivers/edac/i10nm_base.c

632

res->column = GET_BITFIELD(m->misc, 9, 18) << 2;

drivers/edac/i10nm_base.c

633

res->row = GET_BITFIELD(m->misc, 19, 36);

drivers/edac/i10nm_base.c

634

res->bank_group = GET_BITFIELD(m->misc, 37, 38);

drivers/edac/i10nm_base.c

635

res->bank_address = GET_BITFIELD(m->misc, 39, 40);

drivers/edac/i10nm_base.c

636

res->bank_group |= GET_BITFIELD(m->misc, 41, 41) << 2;

drivers/edac/i10nm_base.c

637

res->rank = GET_BITFIELD(m->misc, 57, 57);

drivers/edac/i10nm_base.c

638

res->dimm = GET_BITFIELD(m->misc, 58, 58);

drivers/edac/i10nm_base.c

68

#define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24)

drivers/edac/i10nm_base.c

69

#define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)

drivers/edac/i10nm_base.c

70

#define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)

drivers/edac/i10nm_base.c

73

#define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)

drivers/edac/i10nm_base.c

74

#define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)

drivers/edac/igen6_edac.c

100

#define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)

drivers/edac/igen6_edac.c

104

#define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)

drivers/edac/igen6_edac.c

105

#define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8)

drivers/edac/igen6_edac.c

106

#define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29)

drivers/edac/igen6_edac.c

107

#define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25)

drivers/edac/igen6_edac.c

111

#define MAC_MC_HASH_LSB(v) GET_BITFIELD(v, 1, 3)

drivers/edac/igen6_edac.c

117

#define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)

drivers/edac/igen6_edac.c

118

#define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)

drivers/edac/igen6_edac.c

119

#define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28)

drivers/edac/igen6_edac.c

122

#define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)

drivers/edac/igen6_edac.c

123

#define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)

drivers/edac/igen6_edac.c

409

return !GET_BITFIELD(val, 6, 6);

drivers/edac/igen6_edac.c

453

maddr = GET_BITFIELD(eaddr, intlv_bit, 63) << (intlv_bit + 1) |

drivers/edac/igen6_edac.c

454

GET_BITFIELD(eaddr, 0, intlv_bit - 1);

drivers/edac/igen6_edac.c

492

imc_addr = GET_BITFIELD(eaddr, intlv_bit + 1, 63) << intlv_bit |

drivers/edac/igen6_edac.c

493

GET_BITFIELD(eaddr, 0, intlv_bit - 1);

drivers/edac/igen6_edac.c

764

channel_addr = GET_BITFIELD(addr, intlv_bit + 1, 63) << intlv_bit;

drivers/edac/igen6_edac.c

765

channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);

drivers/edac/igen6_edac.c

786

*idx = GET_BITFIELD(addr, 6, 6);

drivers/edac/igen6_edac.c

83

#define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)

drivers/edac/igen6_edac.c

93

#define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)

drivers/edac/igen6_edac.c

94

#define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)

drivers/edac/igen6_edac.c

95

#define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)

drivers/edac/igen6_edac.c

96

#define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)

drivers/edac/imh_base.c

24

#define MMIO_BASE_H(reg) (((u64)GET_BITFIELD(reg, 0, 29)) << 23)

drivers/edac/imh_base.c

25

#define SOCKET_ID(reg) GET_BITFIELD(reg, 0, 3)

drivers/edac/imh_base.c

28

#define DDR_IMC_BITMAP(reg) GET_BITFIELD(reg, 23, 30)

drivers/edac/imh_base.c

31

#define ECC_ENABLED(reg) GET_BITFIELD(reg, 2, 2)

drivers/edac/imh_base.c

32

#define DIMM_POPULATED(reg) GET_BITFIELD(reg, 15, 15)

drivers/edac/imh_base.c

35

#define TOLM(reg) (((u64)GET_BITFIELD(reg, 16, 31)) << 16)

drivers/edac/imh_base.c

36

#define TOHM(reg) (((u64)GET_BITFIELD(reg, 16, 51)) << 16)

drivers/edac/imh_base.c

39

#define NMCACHING(reg) GET_BITFIELD(reg, 8, 8)

drivers/edac/pnd2_edac.c

1131

u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);

drivers/edac/pnd2_edac.c

1132

u32 mscod = GET_BITFIELD(m->status, 16, 31);

drivers/edac/pnd2_edac.c

1133

u32 errcode = GET_BITFIELD(m->status, 0, 15);

drivers/edac/pnd2_edac.c

1134

u32 optypenum = GET_BITFIELD(m->status, 4, 6);

drivers/edac/sb_edac.c

1007

return GET_BITFIELD(reg, 0, 2);

drivers/edac/sb_edac.c

1049

return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;

drivers/edac/sb_edac.c

1058

rc = GET_BITFIELD(reg, 26, 31);

drivers/edac/sb_edac.c

1070

return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;

drivers/edac/sb_edac.c

1087

return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;

drivers/edac/sb_edac.c

1184

if (!GET_BITFIELD(reg_limit_lo, 0, 0))

drivers/edac/sb_edac.c

1187

way_id = GET_BITFIELD(reg_limit_lo, 3, 5);

drivers/edac/sb_edac.c

1203

*offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |

drivers/edac/sb_edac.c

1204

((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);

drivers/edac/sb_edac.c

1205

*limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |

drivers/edac/sb_edac.c

1206

((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);

drivers/edac/sb_edac.c

1237

return GET_BITFIELD(reg, entry*3, (entry*3)+2);

drivers/edac/sb_edac.c

1263

mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);

drivers/edac/sb_edac.c

1264

chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);

drivers/edac/sb_edac.c

1305

#define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)

drivers/edac/sb_edac.c

1308

#define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)

drivers/edac/sb_edac.c

1311

#define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)

drivers/edac/sb_edac.c

1314

#define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)

drivers/edac/sb_edac.c

1317

#define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)

drivers/edac/sb_edac.c

148

return GET_BITFIELD(reg, table[interleave].start,

drivers/edac/sb_edac.c

163

#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)

drivers/edac/sb_edac.c

164

#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)

drivers/edac/sb_edac.c

1676

GET_BITFIELD(pvt->info.mcmtr, 9, 9);

drivers/edac/sb_edac.c

1677

pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0);

drivers/edac/sb_edac.c

170

#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)

drivers/edac/sb_edac.c

172

#define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)

drivers/edac/sb_edac.c

1721

pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);

drivers/edac/sb_edac.c

1722

if (GET_BITFIELD(reg, 28, 28)) {

drivers/edac/sb_edac.c

185

#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)

drivers/edac/sb_edac.c

186

#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)

drivers/edac/sb_edac.c

187

#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)

drivers/edac/sb_edac.c

188

#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)

drivers/edac/sb_edac.c

189

#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)

drivers/edac/sb_edac.c

190

#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)

drivers/edac/sb_edac.c

191

#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)

drivers/edac/sb_edac.c

1970

int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);

drivers/edac/sb_edac.c

1973

ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);

drivers/edac/sb_edac.c

198

#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)

drivers/edac/sb_edac.c

199

#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)

drivers/edac/sb_edac.c

200

#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)

drivers/edac/sb_edac.c

205

#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)

drivers/edac/sb_edac.c

2146

bits = GET_BITFIELD(addr, 7, 8) << 1;

drivers/edac/sb_edac.c

2147

bits |= GET_BITFIELD(addr, 9, 9);

drivers/edac/sb_edac.c

2149

bits = GET_BITFIELD(addr, 6, 8);

drivers/edac/sb_edac.c

215

#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)

drivers/edac/sb_edac.c

2153

idx = GET_BITFIELD(addr, 16, 18);

drivers/edac/sb_edac.c

216

#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)

drivers/edac/sb_edac.c

2165

shiftup = GET_BITFIELD(reg, 22, 22);

drivers/edac/sb_edac.c

217

#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)

drivers/edac/sb_edac.c

218

#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)

drivers/edac/sb_edac.c

219

#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)

drivers/edac/sb_edac.c

226

#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)

drivers/edac/sb_edac.c

227

#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)

drivers/edac/sb_edac.c

234

#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)

drivers/edac/sb_edac.c

235

#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)

drivers/edac/sb_edac.c

2374

u32 reg, channel = GET_BITFIELD(m->status, 0, 3);

drivers/edac/sb_edac.c

248

GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))

drivers/edac/sb_edac.c

251

GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))

drivers/edac/sb_edac.c

259

#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)

drivers/edac/sb_edac.c

260

#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)

drivers/edac/sb_edac.c

261

#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)

drivers/edac/sb_edac.c

262

#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)

drivers/edac/sb_edac.c

274

#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)

drivers/edac/sb_edac.c

275

#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)

drivers/edac/sb_edac.c

3083

bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);

drivers/edac/sb_edac.c

3084

bool overflow = GET_BITFIELD(m->status, 62, 62);

drivers/edac/sb_edac.c

3085

bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);

drivers/edac/sb_edac.c

3087

u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);

drivers/edac/sb_edac.c

3088

u32 mscod = GET_BITFIELD(m->status, 16, 31);

drivers/edac/sb_edac.c

3089

u32 errcode = GET_BITFIELD(m->status, 0, 15);

drivers/edac/sb_edac.c

3090

u32 channel = GET_BITFIELD(m->status, 0, 3);

drivers/edac/sb_edac.c

3091

u32 optypenum = GET_BITFIELD(m->status, 4, 6);

drivers/edac/sb_edac.c

3097

u32 lsb = GET_BITFIELD(m->misc, 0, 5);

drivers/edac/sb_edac.c

3106

recoverable = GET_BITFIELD(m->status, 56, 56);

drivers/edac/sb_edac.c

3275

if (!GET_BITFIELD(mce->status, 58, 58))

drivers/edac/sb_edac.c

3279

if (!GET_BITFIELD(mce->status, 59, 59))

drivers/edac/sb_edac.c

3283

if (GET_BITFIELD(mce->misc, 6, 8) != 2)

drivers/edac/sb_edac.c

77

#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)

drivers/edac/sb_edac.c

78

#define A7MODE(reg) GET_BITFIELD(reg, 26, 26)

drivers/edac/sb_edac.c

838

return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;

drivers/edac/sb_edac.c

843

return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;

drivers/edac/sb_edac.c

848

return GET_BITFIELD(reg, 1, 1);

drivers/edac/sb_edac.c

853

return GET_BITFIELD(reg, 2, 3);

drivers/edac/sb_edac.c

858

return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;

drivers/edac/sb_edac.c

863

return GET_BITFIELD(reg, 1, 2);

drivers/edac/sb_edac.c

880

return GET_BITFIELD(reg, 3, 4);

drivers/edac/sb_edac.c

892

if (GET_BITFIELD(reg, 11, 11))

drivers/edac/sb_edac.c

915

if (GET_BITFIELD(reg, 16, 16))

drivers/edac/sb_edac.c

919

if (GET_BITFIELD(reg, 14, 14)) {

drivers/edac/sb_edac.c

972

return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));

drivers/edac/sb_edac.c

978

return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));

drivers/edac/sb_edac.c

991

return GET_BITFIELD(reg, 0, 2);

drivers/edac/sb_edac.c

999

return GET_BITFIELD(reg, 0, 3);

drivers/edac/skx_base.c

177

return !!GET_BITFIELD(mcmtr, 2, 2);

drivers/edac/skx_base.c

224

#define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)

drivers/edac/skx_base.c

225

#define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)

drivers/edac/skx_base.c

226

#define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)

drivers/edac/skx_base.c

227

#define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)

drivers/edac/skx_base.c

228

#define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)

drivers/edac/skx_base.c

229

#define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)

drivers/edac/skx_base.c

230

#define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)

drivers/edac/skx_base.c

303

idx = GET_BITFIELD(addr, 6, 8);

drivers/edac/skx_base.c

306

idx = GET_BITFIELD(addr, 8, 10);

drivers/edac/skx_base.c

309

idx = GET_BITFIELD(addr, 12, 14);

drivers/edac/skx_base.c

312

idx = GET_BITFIELD(addr, 30, 32);

drivers/edac/skx_base.c

316

tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);

drivers/edac/skx_base.c

370

res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);

drivers/edac/skx_base.c

371

res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);

drivers/edac/skx_base.c

387

#define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)

drivers/edac/skx_base.c

388

#define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)

drivers/edac/skx_base.c

389

#define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)

drivers/edac/skx_base.c

390

#define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)

drivers/edac/skx_base.c

391

#define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)

drivers/edac/skx_base.c

392

#define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))

drivers/edac/skx_base.c

393

#define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)

drivers/edac/skx_base.c

462

#define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)

drivers/edac/skx_base.c

463

#define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)

drivers/edac/skx_base.c

464

#define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))

drivers/edac/skx_base.c

465

#define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)

drivers/edac/skx_base.c

466

#define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))

drivers/edac/skx_base.c

546

int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);

drivers/edac/skx_base.c

549

ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);

drivers/edac/skx_common.c

313

*id = GET_BITFIELD(reg, 12, 14);

drivers/edac/skx_common.c

320

switch (GET_BITFIELD(mtr, 8, 9)) {

drivers/edac/skx_common.c

362

d->bus[0] = GET_BITFIELD(reg, 0, 7);

drivers/edac/skx_common.c

363

d->bus[1] = GET_BITFIELD(reg, 8, 15);

drivers/edac/skx_common.c

366

d->bus[2] = GET_BITFIELD(reg, 16, 23);

drivers/edac/skx_common.c

367

d->bus[3] = GET_BITFIELD(reg, 24, 31);

drivers/edac/skx_common.c

369

d->seg = GET_BITFIELD(reg, 16, 23);

drivers/edac/skx_common.c

444

u32 val = GET_BITFIELD(reg, lobit, hibit);

drivers/edac/skx_common.c

490

imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);

drivers/edac/skx_common.c

491

imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);

drivers/edac/skx_common.c

492

imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);

drivers/edac/skx_common.c

656

bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);

drivers/edac/skx_common.c

657

bool overflow = GET_BITFIELD(m->status, 62, 62);

drivers/edac/skx_common.c

658

bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);

drivers/edac/skx_common.c

662

u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);

drivers/edac/skx_common.c

663

u32 mscod = GET_BITFIELD(m->status, 16, 31);

drivers/edac/skx_common.c

664

u32 errcode = GET_BITFIELD(m->status, 0, 15);

drivers/edac/skx_common.c

665

u32 optypenum = GET_BITFIELD(m->status, 4, 6);

drivers/edac/skx_common.c

667

recoverable = GET_BITFIELD(m->status, 56, 56);

drivers/edac/skx_common.c

731

u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;

drivers/edac/skx_common.h

47

#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)

drivers/edac/skx_common.h

48

#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)