arch/arc/kernel/jump_label.c

49

u32 pcl = pc & GENMASK(31, 2);

arch/arc/kernel/jump_label.c

70

s = (u_offset >> 1) & GENMASK(9, 0);

arch/arc/kernel/jump_label.c

71

S = (u_offset >> 11) & GENMASK(9, 0);

arch/arc/kernel/jump_label.c

72

t = (u_offset >> 21) & GENMASK(3, 0);

arch/arc/kernel/jump_label.c

79

return (instruction_r << 16) | (instruction_l & GENMASK(15, 0));

arch/arm/kernel/cacheinfo.c

26

#define CTR_FORMAT_MASK GENMASK(31, 29)

arch/arm/kernel/cacheinfo.c

29

#define CTR_CWG_MASK GENMASK(27, 24)

arch/arm/kernel/cacheinfo.c

30

#define CTR_DSIZE_LEN_MASK GENMASK(13, 12)

arch/arm/kernel/cacheinfo.c

31

#define CTR_ISIZE_LEN_MASK GENMASK(1, 0)

arch/arm/kernel/smp_scu.c

21

#define SCU_CPU_STATUS_MASK GENMASK(1, 0)

arch/arm/mm/cache-uniphier.c

373

data->way_mask = GENMASK(cache_size / data->nsets / data->line_size - 1,

arch/arm/mm/pmsa-v7.c

113

u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0);

arch/arm/mm/pmsa-v7.c

121

u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16);

arch/arm64/include/asm/apple_m1_pmu.h

23

#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0)

arch/arm64/include/asm/apple_m1_pmu.h

24

#define PMCR0_IMODE GENMASK(10, 8)

arch/arm64/include/asm/apple_m1_pmu.h

31

#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12)

arch/arm64/include/asm/apple_m1_pmu.h

36

#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32)

arch/arm64/include/asm/apple_m1_pmu.h

37

#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44)

arch/arm64/include/asm/apple_m1_pmu.h

41

#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8)

arch/arm64/include/asm/apple_m1_pmu.h

42

#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16)

arch/arm64/include/asm/apple_m1_pmu.h

43

#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40)

arch/arm64/include/asm/apple_m1_pmu.h

44

#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48)

arch/arm64/include/asm/apple_m1_pmu.h

51

#define PMESR0_EVT_CNT_2 GENMASK(7, 0)

arch/arm64/include/asm/apple_m1_pmu.h

52

#define PMESR0_EVT_CNT_3 GENMASK(15, 8)

arch/arm64/include/asm/apple_m1_pmu.h

53

#define PMESR0_EVT_CNT_4 GENMASK(23, 16)

arch/arm64/include/asm/apple_m1_pmu.h

54

#define PMESR0_EVT_CNT_5 GENMASK(31, 24)

arch/arm64/include/asm/apple_m1_pmu.h

57

#define PMESR1_EVT_CNT_6 GENMASK(7, 0)

arch/arm64/include/asm/apple_m1_pmu.h

58

#define PMESR1_EVT_CNT_7 GENMASK(15, 8)

arch/arm64/include/asm/apple_m1_pmu.h

59

#define PMESR1_EVT_CNT_8 GENMASK(23, 16)

arch/arm64/include/asm/apple_m1_pmu.h

60

#define PMESR1_EVT_CNT_9 GENMASK(31, 24)

arch/arm64/include/asm/apple_m1_pmu.h

63

#define PMSR_OVERFLOW GENMASK(9, 0)

arch/arm64/include/asm/asm-extable.h

17

#define EX_DATA_REG_ERR GENMASK(4, 0)

arch/arm64/include/asm/asm-extable.h

19

#define EX_DATA_REG_ZERO GENMASK(9, 5)

arch/arm64/include/asm/asm-extable.h

23

#define EX_DATA_REG_DATA GENMASK(4, 0)

arch/arm64/include/asm/asm-extable.h

25

#define EX_DATA_REG_ADDR GENMASK(9, 5)

arch/arm64/include/asm/brk-imm.h

37

#define CFI_BRK_IMM_TARGET GENMASK(4, 0)

arch/arm64/include/asm/brk-imm.h

38

#define CFI_BRK_IMM_TYPE GENMASK(9, 5)

arch/arm64/include/asm/cpufeature.h

553

return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);

arch/arm64/include/asm/esr.h

392

#define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0)

arch/arm64/include/asm/esr.h

412

#define ESR_ELx_ExType_MASK GENMASK(23, 20)

arch/arm64/include/asm/esr.h

414

#define ESR_ELx_Raddr_MASK GENMASK(14, 10)

arch/arm64/include/asm/esr.h

416

#define ESR_ELx_Rn_MASK GENMASK(9, 5)

arch/arm64/include/asm/esr.h

418

#define ESR_ELx_Rvalue_MASK GENMASK(9, 5)

arch/arm64/include/asm/esr.h

420

#define ESR_ELx_IT_MASK GENMASK(4, 0)

arch/arm64/include/asm/esr.h

80

#define ESR_ELx_ISS_MASK (GENMASK(24, 0))

arch/arm64/include/asm/kvm_arm.h

278

#define CPTR_NVHE_EL2_RES1 (BIT(13) | BIT(9) | GENMASK(7, 0))

arch/arm64/include/asm/kvm_arm.h

279

#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \

arch/arm64/include/asm/kvm_arm.h

280

GENMASK(29, 21) | \

arch/arm64/include/asm/kvm_arm.h

281

GENMASK(19, 14) | \

arch/arm64/include/asm/kvm_arm.h

284

#define CPTR_VHE_EL2_RES0 (GENMASK(63, 32) | \

arch/arm64/include/asm/kvm_arm.h

285

GENMASK(27, 26) | \

arch/arm64/include/asm/kvm_arm.h

286

GENMASK(23, 22) | \

arch/arm64/include/asm/kvm_arm.h

287

GENMASK(19, 18) | \

arch/arm64/include/asm/kvm_arm.h

288

GENMASK(15, 0))

arch/arm64/include/asm/kvm_host.h

1031

#define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))

arch/arm64/include/asm/kvm_nested.h

276

tg = FIELD_GET(GENMASK(47, 46), val);

arch/arm64/include/asm/kvm_nested.h

291

base = (val & GENMASK(36, 0)) << shift;

arch/arm64/include/asm/kvm_nested.h

296

scale = FIELD_GET(GENMASK(45, 44), val);

arch/arm64/include/asm/kvm_nested.h

297

num = FIELD_GET(GENMASK(43, 39), val);

arch/arm64/include/asm/kvm_pgtable.h

102

#define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2)

arch/arm64/include/asm/kvm_pgtable.h

138

pa &= GENMASK(51, 50);

arch/arm64/include/asm/kvm_pgtable.h

143

pa &= GENMASK(51, 48);

arch/arm64/include/asm/kvm_pgtable.h

55

#define KVM_PTE_ADDR_MASK GENMASK(47, PAGE_SHIFT)

arch/arm64/include/asm/kvm_pgtable.h

56

#define KVM_PTE_ADDR_51_48 GENMASK(15, 12)

arch/arm64/include/asm/kvm_pgtable.h

57

#define KVM_PTE_ADDR_MASK_LPA2 GENMASK(49, PAGE_SHIFT)

arch/arm64/include/asm/kvm_pgtable.h

58

#define KVM_PTE_ADDR_51_50_LPA2 GENMASK(9, 8)

arch/arm64/include/asm/kvm_pgtable.h

67

#define KVM_PTE_LEAF_ATTR_LO GENMASK(11, 2)

arch/arm64/include/asm/kvm_pgtable.h

69

#define KVM_PTE_LEAF_ATTR_LO_S1_ATTRIDX GENMASK(4, 2)

arch/arm64/include/asm/kvm_pgtable.h

70

#define KVM_PTE_LEAF_ATTR_LO_S1_AP GENMASK(7, 6)

arch/arm64/include/asm/kvm_pgtable.h

75

#define KVM_PTE_LEAF_ATTR_LO_S1_SH GENMASK(9, 8)

arch/arm64/include/asm/kvm_pgtable.h

79

#define KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR GENMASK(5, 2)

arch/arm64/include/asm/kvm_pgtable.h

82

#define KVM_PTE_LEAF_ATTR_LO_S2_SH GENMASK(9, 8)

arch/arm64/include/asm/kvm_pgtable.h

86

#define KVM_PTE_LEAF_ATTR_HI GENMASK(63, 50)

arch/arm64/include/asm/kvm_pgtable.h

88

#define KVM_PTE_LEAF_ATTR_HI_SW GENMASK(58, 55)

arch/arm64/include/asm/kvm_pgtable.h

94

#define KVM_PTE_LEAF_ATTR_HI_S2_XN GENMASK(54, 53)

arch/arm64/include/asm/mte-def.h

13

#define MTE_TAG_MASK GENMASK((MTE_TAG_SHIFT + (MTE_TAG_SIZE - 1)), MTE_TAG_SHIFT)

arch/arm64/include/asm/pgtable-hwdef.h

177

#define PTE_SWBITS_MASK _AT(pteval_t, (BIT(63) | GENMASK(58, 55)))

arch/arm64/include/asm/pkeys.h

75

u8 all_pkeys_mask = GENMASK(arch_max_pkey() - 1, 0);

arch/arm64/include/asm/sysreg.h

1027

#define GCS_CAP_ADDR_MASK GENMASK(63, 12)

arch/arm64/include/asm/sysreg.h

1032

#define GCS_CAP_TOKEN_MASK GENMASK(11, 0)

arch/arm64/include/asm/sysreg.h

327

#define SYS_PAR_EL1_FST GENMASK(6, 1)

arch/arm64/include/asm/sysreg.h

357

#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)

arch/arm64/include/asm/sysreg.h

946

#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)

arch/arm64/kernel/pi/idreg-override.c

118

id_aa64zfr0_override.mask = GENMASK(63, 0);

arch/arm64/kernel/pi/idreg-override.c

144

id_aa64smfr0_override.mask = GENMASK(63, 0);

arch/arm64/kvm/at.c

1624

ipa &= GENMASK(51, ctxt->wi->pgshift);

arch/arm64/kvm/at.c

309

if ((!va55 && va > GENMASK(ia_bits - 1, 0)) ||

arch/arm64/kvm/at.c

310

(va55 && va < GENMASK(63, ia_bits)))

arch/arm64/kvm/at.c

510

if (check_output_size(baddr & GENMASK(52, va_bottom), wi))

arch/arm64/kvm/at.c

539

wr->pa = baddr & GENMASK(52, va_bottom);

arch/arm64/kvm/at.c

649

#define MEMATTR_IS_DEVICE(m) (((m) & GENMASK(7, 4)) == 0)

arch/arm64/kvm/at.c

701

s1 = MEMATTR_Wt | (s1 & GENMASK(1,0));

arch/arm64/kvm/at.c

705

s1 = MEMATTR_Wb | (s1 & GENMASK(1,0));

arch/arm64/kvm/at.c

712

if ((s1 & GENMASK(3, 2)) == MEMATTR_NC ||

arch/arm64/kvm/at.c

713

(s2 & GENMASK(3, 2)) == MEMATTR_NC)

arch/arm64/kvm/at.c

715

else if ((s1 & GENMASK(3, 2)) == MEMATTR_Wt ||

arch/arm64/kvm/at.c

716

(s2 & GENMASK(3, 2)) == MEMATTR_Wt)

arch/arm64/kvm/at.c

724

switch (s1 & GENMASK(3, 2)) {

arch/arm64/kvm/at.c

734

final |= s1 & GENMASK(1, 0);

arch/arm64/kvm/at.c

801

s2_memattr = FIELD_GET(GENMASK(5, 2), tr->desc);

arch/arm64/kvm/at.c

864

par |= tr->output & GENMASK(47, 12);

arch/arm64/kvm/config.c

1336

u64 regfld = (regval >> map->shift) & GENMASK(map->width - 1, 0);

arch/arm64/kvm/guest.c

389

GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \

arch/arm64/kvm/guest.c

392

GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)

arch/arm64/kvm/hyp/vgic-v3-sr.c

680

return pri & (GENMASK(7, 0) << bpr);

arch/arm64/kvm/hyp/vhe/switch.c

92

va |= __vcpu_sys_reg(vcpu, VNCR_EL2) & GENMASK(PAGE_SHIFT - 1, 0);

arch/arm64/kvm/hypercalls.c

13

GENMASK(KVM_REG_ARM_STD_BMAP_BIT_COUNT - 1, 0)

arch/arm64/kvm/hypercalls.c

15

GENMASK(KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT - 1, 0)

arch/arm64/kvm/hypercalls.c

17

GENMASK(KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT - 1, 0)

arch/arm64/kvm/hypercalls.c

19

GENMASK(KVM_REG_ARM_VENDOR_HYP_BMAP_2_BIT_COUNT - 1, 0)

arch/arm64/kvm/hypercalls.c

432

#define KVM_REG_FEATURE_LEVEL_MASK GENMASK(3, 0)

arch/arm64/kvm/inject_fault.c

216

far &= GENMASK(31, 0);

arch/arm64/kvm/inject_fault.c

221

far &= GENMASK(63, 32);

arch/arm64/kvm/mmio.c

205

if (FIELD_GET(GENMASK(12, 11), esr)) {

arch/arm64/kvm/nested.c

1719

resx.res0 |= GENMASK(63, 56);

arch/arm64/kvm/nested.c

1729

resx.res0 = GENMASK(63, 40) | GENMASK(30, 24);

arch/arm64/kvm/nested.c

1800

resx.res0 = GENMASK(63, 20);

arch/arm64/kvm/nested.c

1811

resx.res0 |= GENMASK(11, 8);

arch/arm64/kvm/nested.c

884

asid &= GENMASK(7, 0);

arch/arm64/kvm/pauth.c

108

mask = GENMASK(54, bottom_pac);

arch/arm64/kvm/pauth.c

110

mask |= GENMASK(63, 56);

arch/arm64/kvm/pauth.c

132

mask = GENMASK(54, 53);

arch/arm64/kvm/pauth.c

135

mask = GENMASK(62, 61);

arch/arm64/kvm/pmu-emul.c

177

val = __vcpu_sys_reg(vcpu, reg) & GENMASK(63, 32);

arch/arm64/kvm/pmu-emul.c

300

return GENMASK(n - 1, hpmn);

arch/arm64/kvm/pmu-emul.c

325

return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);

arch/arm64/kvm/pmu-emul.c

47

return GENMASK(9, 0);

arch/arm64/kvm/pmu-emul.c

52

return GENMASK(15, 0);

arch/arm64/kvm/pmu-emul.c

527

val = (-counter) & GENMASK(63, 0);

arch/arm64/kvm/pmu-emul.c

529

val = (-counter) & GENMASK(31, 0);

arch/arm64/kvm/sys_regs.c

2630

.val = GENMASK(31, 0), \

arch/arm64/kvm/sys_regs.c

3161

.val = GENMASK(31, 0) },

arch/arm64/kvm/sys_regs.c

936

mask |= GENMASK(n - 1, 0);

arch/arm64/kvm/sys_regs.c

947

__vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0));

arch/arm64/kvm/va_layout.c

155

tag_val & GENMASK(11, 0),

arch/arm64/kvm/va_layout.c

162

tag_val & GENMASK(23, 12),

arch/arm64/kvm/vgic/vgic-its.c

1514

#define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))

arch/arm64/kvm/vgic/vgic-mmio-v2.c

185

u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

258

irq->mpidr = val & GENMASK(23, 0);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

353

value = (u64)(mpidr & GENMASK(23, 0)) << 32;

arch/arm64/kvm/vgic/vgic-mmio.c

705

irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);

arch/arm64/kvm/vmid.c

28

#define VMID_MASK (~GENMASK(kvm_arm_vmid_bits - 1, 0))

arch/arm64/lib/insn.c

1363

mask = GENMASK(esz - 1, 0);

arch/arm64/lib/insn.c

1539

insn &= ~GENMASK(11, 8);

arch/arm64/lib/insn.c

1554

insn &= ~GENMASK(11, 8);

arch/arm64/lib/insn.c

1565

insn &= ~GENMASK(19, 0);

arch/arm64/lib/insn.c

173

return (insn >> shift) & GENMASK(4, 0);

arch/arm64/lib/insn.c

212

insn &= ~(GENMASK(4, 0) << shift);

arch/arm64/lib/insn.c

236

insn &= ~GENMASK(31, 30);

arch/arm64/lib/insn.c

637

insn &= ~GENMASK(23, 22);

arch/arm64/lib/insn.c

845

mask = GENMASK(4, 0);

arch/arm64/lib/insn.c

849

mask = GENMASK(5, 0);

arch/arm64/mm/context.c

34

#define ASID_MASK (~GENMASK(asid_bits - 1, 0))

arch/arm64/mm/trans_pgd.c

246

int max_msb = (dst_addr & GENMASK(52, 48)) ? 51 : 47;

arch/arm64/net/bpf_jit_comp.c

1083

#define BPF_FIXUP_OFFSET_MASK GENMASK(15, 0)

arch/arm64/net/bpf_jit_comp.c

1084

#define BPF_FIXUP_ARENA_REG_MASK GENMASK(20, 16)

arch/arm64/net/bpf_jit_comp.c

1086

#define BPF_FIXUP_REG_MASK GENMASK(31, 27)

arch/csky/mm/asid.c

18

#define ASID_MASK(info) (~GENMASK((info)->bits - 1, 0))

arch/loongarch/include/asm/asm-extable.h

44

#define EX_DATA_REG_ERR GENMASK(4, 0)

arch/loongarch/include/asm/asm-extable.h

46

#define EX_DATA_REG_ZERO GENMASK(9, 5)

arch/loongarch/include/asm/cmpxchg.h

149

mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);

arch/loongarch/include/asm/cmpxchg.h

50

mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);

arch/loongarch/include/asm/irq.h

55

#define AVEC_IRQ_MASK GENMASK(AVEC_IRQ_BIT - 1, 0)

arch/loongarch/include/asm/irq.h

58

#define AVEC_CPU_MASK GENMASK(AVEC_CPU_BIT - 1, 0)

arch/loongarch/include/asm/loongarch.h

113

#define CPUCFG3_SPW_LVL GENMASK(10, 8)

arch/loongarch/include/asm/loongarch.h

116

#define CPUCFG3_RVAMAX GENMASK(16, 13)

arch/loongarch/include/asm/loongarch.h

126

#define CPUCFG4_CCFREQ GENMASK(31, 0)

arch/loongarch/include/asm/loongarch.h

129

#define CPUCFG5_CCMUL GENMASK(15, 0)

arch/loongarch/include/asm/loongarch.h

130

#define CPUCFG5_CCDIV GENMASK(31, 16)

arch/loongarch/include/asm/loongarch.h

134

#define CPUCFG6_PAMVER GENMASK(3, 1)

arch/loongarch/include/asm/loongarch.h

135

#define CPUCFG6_PMNUM GENMASK(7, 4)

arch/loongarch/include/asm/loongarch.h

137

#define CPUCFG6_PMBITS GENMASK(13, 8)

arch/loongarch/include/asm/loongarch.h

164

#define CPUCFG_CACHE_WAYS_M GENMASK(15, 0)

arch/loongarch/include/asm/loongarch.h

165

#define CPUCFG_CACHE_SETS_M GENMASK(23, 16)

arch/loongarch/include/asm/loongarch.h

166

#define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24)

arch/loongarch/include/asm/loongarch.h

60

#define CPUCFG0_PRID GENMASK(31, 0)

arch/loongarch/include/asm/loongarch.h

65

#define CPUCFG1_ISA GENMASK(1, 0)

arch/loongarch/include/asm/loongarch.h

68

#define CPUCFG1_PABITS GENMASK(11, 4)

arch/loongarch/include/asm/loongarch.h

69

#define CPUCFG1_VABITS GENMASK(19, 12)

arch/loongarch/include/asm/loongarch.h

82

#define CPUCFG2_FPVERS GENMASK(5, 3)

arch/loongarch/include/asm/loongarch.h

88

#define CPUCFG2_LVZVER GENMASK(13, 11)

arch/loongarch/include/asm/loongarch.h

90

#define CPUCFG2_LLFTPREV GENMASK(17, 15)

arch/loongarch/kernel/cpu-probe.c

241

asid_mask = GENMASK(config - 1, 0);

arch/loongarch/kernel/cpu-probe.c

246

c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);

arch/loongarch/kvm/main.c

396

vpid_mask = GENMASK(vpid_mask - 1, 0);

arch/loongarch/kvm/vcpu.c

691

*v = GENMASK(31, 0);

arch/loongarch/kvm/vcpu.c

694

*v = GENMASK(26, 0);

arch/loongarch/kvm/vcpu.c

723

*v = GENMASK(23, 0);

arch/loongarch/kvm/vcpu.c

732

*v = GENMASK(31, 0);

arch/loongarch/kvm/vcpu.c

736

*v = GENMASK(14, 0);

arch/loongarch/kvm/vcpu.c

741

*v = GENMASK(16, 0);

arch/loongarch/kvm/vcpu.c

744

*v = GENMASK(30, 0);

arch/loongarch/net/bpf_jit.c

460

#define BPF_FIXUP_REG_MASK GENMASK(31, 27)

arch/loongarch/net/bpf_jit.c

461

#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0)

arch/mips/generic/board-ocelot.c

12

#define CHIP_ID_PART_ID GENMASK(27, 12)

arch/mips/include/asm/kvm_host.h

265

#define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

106

#define LOONGSON_CFG3_LCAMREV GENMASK(3, 1)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

107

#define LOONGSON_CFG3_LCAMNUM GENMASK(11, 4)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

108

#define LOONGSON_CFG3_LCAMKW GENMASK(19, 12)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

109

#define LOONGSON_CFG3_LCAMVW GENMASK(27, 20)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

122

#define LOONGSON_CFG4_CCFREQ GENMASK(31, 0)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

125

#define LOONGSON_CFG5_CFM GENMASK(15, 0)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

126

#define LOONGSON_CFG5_CFD GENMASK(31, 16)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

39

#define LOONGSON_CFG0_PRID GENMASK(31, 0)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

43

#define LOONGSON_CFG1_FPREV GENMASK(3, 1)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

84

#define LOONGSON_CFG2_LPMREV GENMASK(11, 9)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

89

#define LOONGSON_CFG2_LVZREV GENMASK(18, 16)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

91

#define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20)

arch/mips/include/asm/mach-loongson64/loongson_regs.h

93

#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24)

arch/mips/include/asm/mips-cm.h

168

#define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)

arch/mips/include/asm/mips-cm.h

169

#define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)

arch/mips/include/asm/mips-cm.h

170

#define CM_GCR_CONFIG_PCORES GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

175

#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)

arch/mips/include/asm/mips-cm.h

183

#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

187

#define CM_GCR_REV_MAJOR GENMASK(15, 8)

arch/mips/include/asm/mips-cm.h

188

#define CM_GCR_REV_MINOR GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

209

#define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)

arch/mips/include/asm/mips-cm.h

211

#define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)

arch/mips/include/asm/mips-cm.h

218

#define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)

arch/mips/include/asm/mips-cm.h

222

#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)

arch/mips/include/asm/mips-cm.h

227

#define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)

arch/mips/include/asm/mips-cm.h

232

#define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)

arch/mips/include/asm/mips-cm.h

240

#define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)

arch/mips/include/asm/mips-cm.h

247

#define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)

arch/mips/include/asm/mips-cm.h

248

#define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)

arch/mips/include/asm/mips-cm.h

251

#define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)

arch/mips/include/asm/mips-cm.h

267

#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

272

#define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)

arch/mips/include/asm/mips-cm.h

273

#define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)

arch/mips/include/asm/mips-cm.h

274

#define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

278

#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)

arch/mips/include/asm/mips-cm.h

288

#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)

arch/mips/include/asm/mips-cm.h

290

#define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

295

#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

312

#define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)

arch/mips/include/asm/mips-cm.h

319

#define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)

arch/mips/include/asm/mips-cm.h

327

#define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)

arch/mips/include/asm/mips-cm.h

344

#define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

349

#define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)

arch/mips/include/asm/mips-cm.h

350

#define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)

arch/mips/include/asm/mips-cm.h

354

#define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */

arch/mips/include/asm/mips-cm.h

357

#define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */

arch/mips/include/asm/mips-cm.h

362

#define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */

arch/mips/include/asm/mips-cm.h

363

#define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */

arch/mips/include/asm/mips-cm.h

365

#define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */

arch/mips/include/asm/mips-cm.h

370

#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)

arch/mips/include/asm/mips-cm.h

376

#define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)

arch/mips/include/asm/mips-cm.h

377

#define CM_GCR_Cx_ID_CORE GENMASK(7, 0)

arch/mips/include/asm/mips-cm.h

383

#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)

arch/mips/include/asm/mips-cm.h

384

#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)

arch/mips/include/asm/mips-cpc.h

110

#define CPC_Cx_CMD GENMASK(3, 0)

arch/mips/include/asm/mips-cpc.h

119

#define CPC_Cx_STAT_CONF_SEQSTATE GENMASK(22, 19)

arch/mips/include/asm/mips-cpc.h

137

#define CPC_Cx_OTHER_CORENUM GENMASK(23, 16)

arch/mips/include/asm/mips-gic.h

184

#define GIC_CONFIG_COUNTBITS GENMASK(27, 24)

arch/mips/include/asm/mips-gic.h

185

#define GIC_CONFIG_NUMINTERRUPTS GENMASK(23, 16)

arch/mips/include/asm/mips-gic.h

186

#define GIC_CONFIG_PVPS GENMASK(6, 0)

arch/mips/include/asm/mips-gic.h

213

#define GIC_WEDGE_INTR GENMASK(7, 0)

arch/mips/include/asm/mips-gic.h

231

#define GIC_MAP_PIN_MAP GENMASK(5, 0)

arch/mips/include/asm/mips-gic.h

282

#define GIC_VX_OTHER_VPNUM GENMASK(5, 0)

arch/mips/include/asm/mips-gic.h

286

#define GIC_VX_IDENT_VPNUM GENMASK(5, 0)

arch/mips/include/asm/mipsregs.h

1200

#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)

arch/mips/kernel/cmpxchg.c

20

mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);

arch/mips/kernel/cmpxchg.c

61

mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);

arch/mips/kernel/cpu-probe.c

712

if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {

arch/mips/kernel/cpu-probe.c

715

asid_mask = GENMASK(max_mmid_width - 1, 0);

arch/mips/kernel/module.c

173

unsigned long mask = GENMASK(bits - 1, 0);

arch/mips/kernel/process.c

210

((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op &&

arch/mips/lantiq/xway/dma.c

34

#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */

arch/mips/mm/tlb-r4k.c

593

vpn_mask = GENMASK(current_cpu_data.vmbits - 1, VPN2_SHIFT);

arch/riscv/include/asm/asm-extable.h

47

#define EX_DATA_REG_ERR GENMASK(4, 0)

arch/riscv/include/asm/asm-extable.h

49

#define EX_DATA_REG_ZERO GENMASK(9, 5)

arch/riscv/include/asm/asm-extable.h

52

#define EX_DATA_REG_DATA GENMASK(4, 0)

arch/riscv/include/asm/asm-extable.h

54

#define EX_DATA_REG_ADDR GENMASK(9, 5)

arch/riscv/include/asm/cmpxchg.h

152

ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \

arch/riscv/include/asm/cmpxchg.h

34

ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \

arch/riscv/include/asm/csr.h

103

#define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)

arch/riscv/include/asm/csr.h

164

#define HGATP32_VMID GENMASK(28, 22)

arch/riscv/include/asm/csr.h

165

#define HGATP32_PPN GENMASK(21, 0)

arch/riscv/include/asm/csr.h

169

#define HGATP64_VMID GENMASK(57, 44)

arch/riscv/include/asm/csr.h

170

#define HGATP64_PPN GENMASK(43, 0)

arch/riscv/include/asm/csr.h

195

#define TOPI_IID_MASK GENMASK(11, 0)

arch/riscv/include/asm/csr.h

196

#define TOPI_IPRIO_MASK GENMASK(7, 0)

arch/riscv/include/asm/csr.h

200

#define TOPEI_ID_MASK GENMASK(10, 0)

arch/riscv/include/asm/csr.h

201

#define TOPEI_PRIO_MASK GENMASK(10, 0)

arch/riscv/include/asm/csr.h

205

#define ISELECT_MASK GENMASK(8, 0)

arch/riscv/include/asm/csr.h

208

#define HVICTL_IID GENMASK(27, 16)

arch/riscv/include/asm/csr.h

212

#define HVICTL_IPRIO GENMASK(7, 0)

arch/riscv/include/asm/insn.h

106

#define RVC_B_IMM_4_3_MASK GENMASK(1, 0)

arch/riscv/include/asm/insn.h

107

#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)

arch/riscv/include/asm/insn.h

108

#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)

arch/riscv/include/asm/insn.h

109

#define RVC_B_IMM_5_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

11

#define RV_INSN_FUNCT3_MASK GENMASK(14, 12)

arch/riscv/include/asm/insn.h

111

#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)

arch/riscv/include/asm/insn.h

113

#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)

arch/riscv/include/asm/insn.h

115

#define RVC_INSN_J_RS1_MASK GENMASK(11, 7)

arch/riscv/include/asm/insn.h

116

#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)

arch/riscv/include/asm/insn.h

117

#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)

arch/riscv/include/asm/insn.h

13

#define RV_INSN_OPCODE_MASK GENMASK(6, 0)

arch/riscv/include/asm/insn.h

135

#define RVC_C2_RS1_MASK GENMASK(4, 0)

arch/riscv/include/asm/insn.h

145

#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)

arch/riscv/include/asm/insn.h

149

#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)

arch/riscv/include/asm/insn.h

25

#define RV_I_IMM_11_0_MASK GENMASK(11, 0)

arch/riscv/include/asm/insn.h

36

#define RV_J_IMM_10_1_MASK GENMASK(9, 0)

arch/riscv/include/asm/insn.h

37

#define RV_J_IMM_11_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

38

#define RV_J_IMM_19_12_MASK GENMASK(7, 0)

arch/riscv/include/asm/insn.h

47

#define RV_U_IMM_31_12_MASK GENMASK(31, 12)

arch/riscv/include/asm/insn.h

549

*insn &= ~GENMASK(31, 12);

arch/riscv/include/asm/insn.h

58

#define RV_B_IMM_10_5_MASK GENMASK(5, 0)

arch/riscv/include/asm/insn.h

59

#define RV_B_IMM_4_1_MASK GENMASK(3, 0)

arch/riscv/include/asm/insn.h

60

#define RV_B_IMM_11_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

66

#define RVG_RS1_MASK GENMASK(4, 0)

arch/riscv/include/asm/insn.h

67

#define RVG_RS2_MASK GENMASK(4, 0)

arch/riscv/include/asm/insn.h

68

#define RVG_RD_MASK GENMASK(4, 0)

arch/riscv/include/asm/insn.h

87

#define RVC_J_IMM_4_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

88

#define RVC_J_IMM_9_8_MASK GENMASK(1, 0)

arch/riscv/include/asm/insn.h

89

#define RVC_J_IMM_10_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

90

#define RVC_J_IMM_6_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

91

#define RVC_J_IMM_7_MASK GENMASK(0, 0)

arch/riscv/include/asm/insn.h

92

#define RVC_J_IMM_3_1_MASK GENMASK(2, 0)

arch/riscv/include/asm/insn.h

93

#define RVC_J_IMM_5_MASK GENMASK(0, 0)

arch/riscv/include/asm/pgtable-32.h

25

#define _PAGE_PFN_MASK GENMASK(31, 10)

arch/riscv/include/asm/pgtable-64.h

79

#define _PAGE_PFN_MASK GENMASK(53, 10)

arch/riscv/include/asm/pgtable.h

305

unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);

arch/riscv/kernel/jump_label.c

31

(((u32)offset & GENMASK(19, 12)) << (12 - 12)) |

arch/riscv/kernel/jump_label.c

32

(((u32)offset & GENMASK(11, 11)) << (20 - 11)) |

arch/riscv/kernel/jump_label.c

33

(((u32)offset & GENMASK(10, 1)) << (21 - 1)) |

arch/riscv/kernel/jump_label.c

34

(((u32)offset & GENMASK(20, 20)) << (31 - 20));

arch/riscv/kernel/traps_misaligned.c

159

insn &= GENMASK(15, 0);

arch/riscv/kernel/traps_misaligned.c

177

insn &= GENMASK(15, 0);

arch/riscv/kvm/vcpu_onereg.c

22

#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)

arch/riscv/kvm/vcpu_pmu.c

40

u64 counter_val_mask = GENMASK(pmc->cinfo.width, 0);

arch/riscv/net/bpf_jit_comp64.c

747

#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0)

arch/riscv/net/bpf_jit_comp64.c

748

#define BPF_FIXUP_REG_MASK GENMASK(31, 27)

arch/s390/include/asm/asm-extable.h

21

#define EX_DATA_REG_ERR GENMASK(3, 0)

arch/s390/include/asm/asm-extable.h

24

#define EX_DATA_REG_ADDR GENMASK(7, 4)

arch/s390/include/asm/asm-extable.h

27

#define EX_DATA_LEN GENMASK(11, 8)

arch/sparc/include/asm/hypervisor.h

1007

#define HV_CCB_ARG0_TYPE_NUCLEUS GENMASK(5, 4)

arch/sparc/include/asm/hypervisor.h

1013

#define HV_CCB_VA_NUCLEUS GENMASK(13, 12)

arch/x86/boot/startup/sev-shared.c

314

leaf->ebx = (leaf_hv.ebx & GENMASK(31, 24)) | (leaf->ebx & GENMASK(23, 0));

arch/x86/boot/startup/sev-shared.c

383

leaf->ebx = (leaf->ebx & GENMASK(31, 8)) | (leaf_hv.ebx & GENMASK(7, 0));

arch/x86/boot/startup/sev-shared.c

385

leaf->ecx = (leaf->ecx & GENMASK(31, 8)) | (leaf_hv.ecx & GENMASK(7, 0));

arch/x86/coco/tdx/tdx.c

32

#define VE_GET_IO_SIZE(e) (((e) & GENMASK(2, 0)) + 1)

arch/x86/coco/tdx/tdx.c

351

gpa_width = args.rcx & GENMASK(5, 0);

arch/x86/coco/tdx/tdx.c

696

u64 mask = GENMASK(BITS_PER_BYTE * size, 0);

arch/x86/coco/tdx/tdx.c

716

u64 mask = GENMASK(BITS_PER_BYTE * size, 0);

arch/x86/entry/syscall_32.c

165

regs->orig_ax = regs->ax & GENMASK(31, 0);

arch/x86/entry/syscall_32.c

229

regs->orig_ax = regs->ax & GENMASK(31, 0);

arch/x86/events/intel/uncore_snbep.c

4128

#define SKX_CHA_BIT_MASK GENMASK(27, 0)

arch/x86/include/asm/cpu_device_id.h

164

#define __X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins)

arch/x86/include/asm/cpu_device_id.h

24

#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT)

arch/x86/include/asm/cpu_device_id.h

25

#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT)

arch/x86/include/asm/cpu_device_id.h

26

#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT)

arch/x86/include/asm/msr-index.h

770

#define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0)

arch/x86/include/asm/msr-index.h

771

#define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8)

arch/x86/include/asm/msr-index.h

772

#define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16)

arch/x86/include/asm/msr-index.h

773

#define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24)

arch/x86/include/asm/msr-index.h

776

#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0)

arch/x86/include/asm/msr-index.h

777

#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8)

arch/x86/include/asm/msr-index.h

778

#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16)

arch/x86/include/asm/msr-index.h

779

#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24)

arch/x86/include/asm/mtrr.h

17

#define MTRR_CAP_VCNT GENMASK(7, 0)

arch/x86/include/asm/mtrr.h

21

#define MTRR_DEF_TYPE_TYPE GENMASK(7, 0)

arch/x86/include/asm/mtrr.h

28

#define MTRR_PHYSBASE_TYPE GENMASK(7, 0)

arch/x86/include/asm/mtrr.h

29

#define MTRR_PHYSBASE_RSVD GENMASK(11, 8)

arch/x86/include/asm/mtrr.h

31

#define MTRR_PHYSMASK_RSVD GENMASK(10, 0)

arch/x86/include/asm/sgx.h

28

#define SGX_CPUID_EPC_MASK GENMASK(3, 0)

arch/x86/include/asm/sgx.h

281

#define SGX_PAGE_TYPE_MASK GENMASK(7, 0)

arch/x86/kernel/cpu/mtrr/mtrr.c

552

phys_hi_rsvd = GENMASK(31, boot_cpu_data.x86_phys_bits - 32);

arch/x86/kernel/cpu/resctrl/monitor.c

458

r->mon.num_mbm_cntrs = (ebx & GENMASK(15, 0)) + 1;

arch/x86/kernel/cpu/sgx/encl.c

24

#define PCMD_FIRST_MASK GENMASK(4, 0)

arch/x86/kernel/process_64.c

817

mm->context.untag_mask = ~GENMASK(62, 57);

arch/x86/kvm/cpuid.c

1755

entry->ebx &= ~GENMASK(27, 16);

arch/x86/kvm/cpuid.c

1764

entry->edx &= ~GENMASK(17, 16);

arch/x86/kvm/cpuid.c

1815

entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));

arch/x86/kvm/cpuid.c

1835

entry->eax &= GENMASK(2, 0);

arch/x86/kvm/cpuid.c

1849

entry->ebx &= ~GENMASK(31, 12);

arch/x86/kvm/cpuid.c

1854

entry->ebx &= ~GENMASK(11, 6);

arch/x86/kvm/cpuid.c

1865

entry->ebx &= GENMASK(23, 16);

arch/x86/kvm/svm/avic.c

49

#define AVIC_VM_ID_MASK (GENMASK(31, AVIC_VM_ID_SHIFT) >> AVIC_VM_ID_SHIFT)

arch/x86/kvm/svm/nested.c

70

(cr3 & GENMASK(11, 5)) + index * 8, 8);

arch/x86/kvm/vmx/nested.c

3047

vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))

arch/x86/kvm/vmx/nested.c

3114

CC((vmcs12->tpr_threshold & GENMASK(3, 0)) > (vtpr & GENMASK(3, 0)))))

arch/x86/kvm/vmx/pmu_intel.c

34

#define INTEL_RDPMC_TYPE_MASK GENMASK(31, 16)

arch/x86/kvm/vmx/pmu_intel.c

35

#define INTEL_RDPMC_INDEX_MASK GENMASK(15, 0)

arch/x86/kvm/vmx/tdx.c

116

return (eax & GENMASK(23, 16)) >> 16;

arch/x86/kvm/vmx/tdx.c

121

return (eax & ~GENMASK(23, 16)) | (addr_bits & 0xff) << 16;

arch/x86/kvm/vmx/tdx.c

2579

#define TDX_MD_UNREADABLE_LEAF_MASK GENMASK(30, 7)

arch/x86/kvm/vmx/tdx.c

2580

#define TDX_MD_UNREADABLE_SUBLEAF_MASK GENMASK(31, 7)

arch/x86/kvm/vmx/tdx.h

109

#define VMCS_ENC_WIDTH_MASK GENMASK(14, 13)

arch/x86/kvm/vmx/tdx_arch.h

84

#define TDX_EXT_EXIT_QUAL_TYPE_MASK GENMASK(3, 0)

arch/x86/kvm/vmx/vmcs.h

200

#define VMCS_FIELD_INDEX_MASK GENMASK(9, 1)

arch/x86/kvm/x86.c

10079

(host_pat & GENMASK(2, 0)) != 6) {

arch/x86/kvm/x86.c

1079

cr3 & GENMASK(11, 5), sizeof(pdpte));

arch/x86/kvm/x86.h

743

#define CET_US_RESERVED_BITS GENMASK(9, 6)

arch/x86/kvm/x86.h

744

#define CET_US_SHSTK_MASK_BITS GENMASK(1, 0)

arch/x86/net/bpf_jit_comp.c

1473

#define FIXUP_INSN_LEN_MASK GENMASK(7, 0)

arch/x86/net/bpf_jit_comp.c

1474

#define FIXUP_REG_MASK GENMASK(15, 8)

arch/x86/net/bpf_jit_comp.c

1475

#define FIXUP_ARENA_REG_MASK GENMASK(23, 16)

arch/x86/net/bpf_jit_comp.c

1477

#define DATA_ARENA_OFFSET_MASK GENMASK(31, 16)

arch/x86/pci/fixup.c

717

#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8)

arch/x86/pci/fixup.c

720

#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8)

arch/x86/pci/fixup.c

723

#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0)

arch/x86/pci/fixup.c

725

#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16)

arch/x86/pci/pcbios.c

38

#define PCIBIOS_RETURN_CODE GENMASK(15, 8)

arch/x86/virt/svm/sev.c

626

segment_shift_min = eax & GENMASK(5, 0);

arch/x86/virt/svm/sev.c

627

segment_shift_max = (eax & GENMASK(11, 6)) >> 6;

arch/x86/virt/svm/sev.c

640

rst_max_index = ebx & GENMASK(9, 0);

drivers/accel/amdxdna/aie2_message.c

366

*bitmap |= GENMASK(hwctx->start_col + hwctx->num_col - 1, hwctx->start_col);

drivers/accel/amdxdna/aie2_msg_priv.h

318

#define AIE2_MSG_CFG_CU_PDI_ADDR GENMASK(16, 0)

drivers/accel/amdxdna/aie2_msg_priv.h

319

#define AIE2_MSG_CFG_CU_FUNC GENMASK(24, 17)

drivers/accel/amdxdna/aie2_msg_priv.h

423

#define AIE2_MSG_SYNC_BO_SRC_TYPE GENMASK(3, 0)

drivers/accel/amdxdna/aie2_msg_priv.h

424

#define AIE2_MSG_SYNC_BO_DST_TYPE GENMASK(7, 4)

drivers/accel/amdxdna/amdxdna_ctx.h

76

#define AMDXDNA_CMD_STATE GENMASK(3, 0)

drivers/accel/amdxdna/amdxdna_ctx.h

77

#define AMDXDNA_CMD_EXTRA_CU_MASK GENMASK(11, 10)

drivers/accel/amdxdna/amdxdna_ctx.h

78

#define AMDXDNA_CMD_COUNT GENMASK(22, 12)

drivers/accel/amdxdna/amdxdna_ctx.h

79

#define AMDXDNA_CMD_OPCODE GENMASK(27, 23)

drivers/accel/amdxdna/amdxdna_mailbox.c

71

#define MSG_BODY_SZ GENMASK(10, 0)

drivers/accel/amdxdna/amdxdna_mailbox.c

72

#define MSG_PROTO_VER GENMASK(23, 16)

drivers/accel/ethosu/ethosu_device.h

46

#define ID_ARCH_MAJOR_MASK GENMASK(31, 28)

drivers/accel/ethosu/ethosu_device.h

47

#define ID_ARCH_MINOR_MASK GENMASK(27, 20)

drivers/accel/ethosu/ethosu_device.h

48

#define ID_ARCH_PATCH_MASK GENMASK(19, 16)

drivers/accel/ethosu/ethosu_device.h

49

#define ID_VER_MAJOR_MASK GENMASK(11, 8)

drivers/accel/ethosu/ethosu_device.h

50

#define ID_VER_MINOR_MASK GENMASK(7, 4)

drivers/accel/ethosu/ethosu_device.h

52

#define CONFIG_MACS_PER_CC_MASK GENMASK(3, 0)

drivers/accel/ethosu/ethosu_device.h

53

#define CONFIG_CMD_STREAM_VER_MASK GENMASK(7, 4)

drivers/accel/habanalabs/common/pci/pci.c

20

#define IATU_REGION_CTRL_BAR_NUM_MASK GENMASK(10, 8)

drivers/accel/habanalabs/common/security.h

16

#define HL_GLBL_ERR_ADDRESS_MASK GENMASK(11, 0)

drivers/accel/habanalabs/gaudi/gaudiP.h

181

#define HW_CAP_NIC_MASK GENMASK(23, 14)

drivers/accel/habanalabs/gaudi/gaudiP.h

192

#define HW_CAP_TPC_MASK GENMASK(31, 24)

drivers/accel/habanalabs/gaudi2/gaudi2.c

126

#define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)

drivers/accel/habanalabs/gaudi2/gaudi2.c

127

#define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)

drivers/accel/habanalabs/gaudi2/gaudi2.c

9725

le16_to_cpu(row_cmd[i]) & (u16)GENMASK(13, 0),

drivers/accel/habanalabs/gaudi2/gaudi2.c

9726

le32_to_cpu(col_cmd[i]) & (u32)GENMASK(17, 0));

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2504

event_mask |= GENMASK(input->event_types_num - 1, 0);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2612

full_mask = GENMASK(unit_count - 1, 0);

drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

116

#define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0)

drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

125

#define SM_CQ_L2H_LOW_MASK GENMASK(31, 20)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

145

#define CFG_RST_L_IF_MASK GENMASK(24, 21)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

154

#define CFG_RST_L_TPC_MASK GENMASK(31, 25)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

162

#define CFG_RST_H_MME_MASK GENMASK(4, 1)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

168

#define CFG_RST_H_HBM_MASK GENMASK(8, 5)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

175

#define CFG_RST_H_NIC_MASK GENMASK(13, 9)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

181

#define CFG_RST_H_SM_MASK GENMASK(17, 14)

drivers/accel/habanalabs/include/gaudi/gaudi_masks.h

185

#define CFG_RST_H_DMA_MASK GENMASK(19, 18)

drivers/accel/ivpu/ivpu_drv.h

52

#define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_drv.h

53

#define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

115

#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

116

#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

119

#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

120

#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

129

#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

130

#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

161

#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTVEC_MASK GENMASK(31, 4)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

28

#define VPU_37XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

29

#define VPU_37XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

30

#define VPU_37XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

33

#define VPU_37XX_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

90

#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_READ_POINTER_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

91

#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_WRITE_POINTER_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

92

#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_37xx_reg.h

93

#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_RSVD0_MASK GENMASK(31, 24)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

102

#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

117

#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

118

#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

119

#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

122

#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

136

#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

137

#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

140

#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

141

#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

150

#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

151

#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

37

#define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

38

#define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

39

#define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_40xx_reg.h

44

#define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

106

#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

107

#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

110

#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

48

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

49

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

50

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

51

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK GENMASK(31, 24)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

54

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

55

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

56

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

57

#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

60

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

61

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

64

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

65

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

68

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

69

#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

75

#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

78

#define VPU_HW_BTRS_LNL_CDYN_CDYN_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

82

#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)

drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h

92

#define VPU_HW_BTRS_LNL_VPU_STATUS_PLATFORM_MASK GENMASK(31, 29)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

19

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

20

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

23

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

24

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

27

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

33

#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

36

#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

41

#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

42

#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

45

#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

49

#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

77

#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

78

#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12)

drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

79

#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20)

drivers/accel/ivpu/ivpu_mmu.c

102

#define IVPU_MMU_CMD_CFGI_0_SSID GENMASK(31, 12)

drivers/accel/ivpu/ivpu_mmu.c

103

#define IVPU_MMU_CMD_CFGI_0_SID GENMASK(63, 32)

drivers/accel/ivpu/ivpu_mmu.c

104

#define IVPU_MMU_CMD_CFGI_1_RANGE GENMASK(4, 0)

drivers/accel/ivpu/ivpu_mmu.c

106

#define IVPU_MMU_CMD_TLBI_0_ASID GENMASK(63, 48)

drivers/accel/ivpu/ivpu_mmu.c

107

#define IVPU_MMU_CMD_TLBI_0_VMID GENMASK(47, 32)

drivers/accel/ivpu/ivpu_mmu.c

150

#define IVPU_MMU_CR1_TABLE_SH GENMASK(11, 10)

drivers/accel/ivpu/ivpu_mmu.c

151

#define IVPU_MMU_CR1_TABLE_OC GENMASK(9, 8)

drivers/accel/ivpu/ivpu_mmu.c

152

#define IVPU_MMU_CR1_TABLE_IC GENMASK(7, 6)

drivers/accel/ivpu/ivpu_mmu.c

153

#define IVPU_MMU_CR1_QUEUE_SH GENMASK(5, 4)

drivers/accel/ivpu/ivpu_mmu.c

154

#define IVPU_MMU_CR1_QUEUE_OC GENMASK(3, 2)

drivers/accel/ivpu/ivpu_mmu.c

155

#define IVPU_MMU_CR1_QUEUE_IC GENMASK(1, 0)

drivers/accel/ivpu/ivpu_mmu.c

22

#define IVPU_MMU_REG_CR0ACK_VAL_MASK GENMASK(31, 0)

drivers/accel/ivpu/ivpu_mmu.c

33

#define IVPU_MMU_REG_IRQ_CTRLACK_VAL_MASK GENMASK(31, 0)

drivers/accel/ivpu/ivpu_mmu.c

51

#define IVPU_MMU_REG_CMDQ_CONS_VAL_MASK GENMASK(23, 0)

drivers/accel/ivpu/ivpu_mmu.c

52

#define IVPU_MMU_REG_CMDQ_CONS_ERR_MASK GENMASK(30, 24)

drivers/accel/ivpu/ivpu_mmu.c

81

#define IVPU_MMU_Q_WRAP_MASK GENMASK(IVPU_MMU_Q_COUNT_LOG2, 0)

drivers/accel/ivpu/ivpu_mmu.c

92

#define IVPU_MMU_CMD_OPCODE GENMASK(7, 0)

drivers/accel/ivpu/ivpu_mmu.c

94

#define IVPU_MMU_CMD_SYNC_0_CS GENMASK(13, 12)

drivers/accel/ivpu/ivpu_mmu.c

95

#define IVPU_MMU_CMD_SYNC_0_MSH GENMASK(23, 22)

drivers/accel/ivpu/ivpu_mmu.c

96

#define IVPU_MMU_CMD_SYNC_0_MSI_ATTR GENMASK(27, 24)

drivers/accel/ivpu/ivpu_mmu.c

97

#define IVPU_MMU_CMD_SYNC_0_MSI_ATTR GENMASK(27, 24)

drivers/accel/ivpu/ivpu_mmu.c

98

#define IVPU_MMU_CMD_SYNC_0_MSI_DATA GENMASK(63, 32)

drivers/accel/ivpu/ivpu_mmu_context.c

18

#define IVPU_MMU_VPU_ADDRESS_MASK GENMASK(47, 12)

drivers/accel/ivpu/ivpu_mmu_context.c

19

#define IVPU_MMU_PGD_INDEX_MASK GENMASK(47, 39)

drivers/accel/ivpu/ivpu_mmu_context.c

20

#define IVPU_MMU_PUD_INDEX_MASK GENMASK(38, 30)

drivers/accel/ivpu/ivpu_mmu_context.c

21

#define IVPU_MMU_PMD_INDEX_MASK GENMASK(29, 21)

drivers/accel/ivpu/ivpu_mmu_context.c

22

#define IVPU_MMU_PTE_INDEX_MASK GENMASK(20, 12)

drivers/accel/ivpu/ivpu_mmu_context.c

23

#define IVPU_MMU_ENTRY_FLAGS_MASK (BIT(52) | GENMASK(11, 0))

drivers/accel/qaic/qaic_data.c

1192

last_req->cmd = GENMASK(7, 2) & reqs[first_n].cmd;

drivers/accel/qaic/qaic_data.c

46

FIELD_PREP(GENMASK(11, 0), (val)) | \

drivers/accel/qaic/qaic_data.c

47

FIELD_PREP(GENMASK(20, 16), (index)) | \

drivers/accel/qaic/qaic_data.c

49

FIELD_PREP(GENMASK(26, 24), (cmd)) | \

drivers/accel/qaic/qaic_data.c

50

FIELD_PREP(GENMASK(30, 29), (flags)) | \

drivers/acpi/apei/einj-core.c

866

tval = type & GENMASK(30, 0);

drivers/acpi/arm64/mpam.c

22

#define ACPI_MPAM_MSC_IRQ_TYPE_MASK GENMASK(2, 1)

drivers/acpi/cppc_acpi.c

193

GENMASK(((reg)->bit_width) - 1, 0))

drivers/acpi/cppc_acpi.c

195

((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \

drivers/acpi/cppc_acpi.c

196

((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \

drivers/acpi/osl.c

670

*value = GENMASK(width, 0);

drivers/acpi/pmic/intel_pmic_chtdc_ti.c

19

#define PMIC_REG_MASK GENMASK(9, 0)

drivers/acpi/pmic/intel_pmic_xpower.c

19

#define GPI1_LDO_MASK GENMASK(2, 0)

drivers/acpi/pmic/intel_pmic_xpower.c

23

#define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0)

drivers/acpi/riscv/cppc.c

22

#define FFH_CPPC_SBI_REG(r) ((r) & GENMASK(31, 0))

drivers/acpi/riscv/cppc.c

23

#define FFH_CPPC_CSR_NUM(r) ((r) & GENMASK(11, 0))

drivers/acpi/x86/lpss.c

906

#define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)

drivers/acpi/x86/lpss.c

911

#define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)

drivers/ata/ahci_dwc.c

103

#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0)

drivers/ata/ahci_dwc.c

107

#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0)

drivers/ata/ahci_dwc.c

32

#define AHCI_DWC_HOST_CWMIN_MASK GENMASK(30, 24)

drivers/ata/ahci_dwc.c

33

#define AHCI_DWC_HOST_CWMAX_MASK GENMASK(23, 16)

drivers/ata/ahci_dwc.c

34

#define AHCI_DWC_HOST_CIMIN_MASK GENMASK(15, 8)

drivers/ata/ahci_dwc.c

35

#define AHCI_DWC_HOST_CIMAX_MASK GENMASK(7, 0)

drivers/ata/ahci_dwc.c

41

#define AHCI_DWC_HOST_TIMV_MASK GENMASK(19, 0)

drivers/ata/ahci_dwc.c

46

#define AHCI_DWC_HOST_PHY_DATA_MASK GENMASK(29, 28)

drivers/ata/ahci_dwc.c

48

#define AHCI_DWC_HOST_PHY_CTRL_MASK GENMASK(26, 21)

drivers/ata/ahci_dwc.c

49

#define AHCI_DWC_HOST_PHY_STAT_MASK GENMASK(20, 15)

drivers/ata/ahci_dwc.c

51

#define AHCI_DWC_HOST_PHY_TYPE_MASK GENMASK(13, 11)

drivers/ata/ahci_dwc.c

53

#define AHCI_DWC_HOST_AHB_ENDIAN_MASK GENMASK(9, 8)

drivers/ata/ahci_dwc.c

56

#define AHCI_DWC_HOST_S_HDATA_MASK GENMASK(5, 3)

drivers/ata/ahci_dwc.c

57

#define AHCI_DWC_HOST_M_HDATA_MASK GENMASK(2, 0)

drivers/ata/ahci_dwc.c

61

#define AHCI_DWC_HOST_FBS_PMPN_MASK GENMASK(17, 16)

drivers/ata/ahci_dwc.c

70

#define AHCI_DWC_HOST_RXOOB_CLK_MASK GENMASK(8, 0)

drivers/ata/ahci_dwc.c

77

#define AHCI_DWC_HOST_TXFIFO_DEPTH GENMASK(7, 4)

drivers/ata/ahci_dwc.c

78

#define AHCI_DWC_HOST_RXFIFO_DEPTH GENMASK(3, 0)

drivers/ata/ahci_dwc.c

81

#define AHCI_DWC_HOST_PSEL_MASK GENMASK(18, 16)

drivers/ata/ahci_dwc.c

88

#define AHCI_DWC_PORT_RXABL_MASK GENMASK(15, 12)

drivers/ata/ahci_dwc.c

89

#define AHCI_DWC_PORT_TXABL_MASK GENMASK(11, 8)

drivers/ata/ahci_dwc.c

90

#define AHCI_DWC_PORT_RXTS_MASK GENMASK(7, 4)

drivers/ata/ahci_dwc.c

91

#define AHCI_DWC_PORT_TXTS_MASK GENMASK(3, 0)

drivers/ata/ahci_dwc.c

97

#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23)

drivers/ata/ahci_dwc.c

98

#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20)

drivers/ata/ahci_imx.c

50

IMX8QM_SATA_AHCI_PTC_RXWM_MASK = GENMASK(6, 0),

drivers/ata/ahci_mtk.c

24

#define SYS_CFG_SATA_MSK GENMASK(31, 30)

drivers/ata/ahci_tegra.c

462

.nvoob_comma_cnt_mask = GENMASK(30, 28),

drivers/ata/ahci_tegra.c

482

.nvoob_comma_cnt_mask = GENMASK(23, 16),

drivers/ata/libahci_platform.c

823

writel(GENMASK(host->n_ports, 0), mmio + HOST_IRQ_STAT);

drivers/ata/pata_ixp4xx_cf.c

38

#define IXP4XX_EXP_T1_T5_MASK GENMASK(29, 16)

drivers/base/regmap/regmap-irq.c

354

memset32(data->status_buf, GENMASK(31, 0), chip->num_regs);

drivers/base/regmap/regmap-kunit.c

1081

val_mask = GENMASK(config.val_bits - 1, 0);

drivers/base/regmap/regmap-mdio.c

11

#define REGNUM_C45_MASK GENMASK(20, 0)

drivers/base/regmap/regmap-mdio.c

8

#define REGVAL_MASK GENMASK(15, 0)

drivers/base/regmap/regmap-mdio.c

9

#define REGNUM_C22_MASK GENMASK(4, 0)

drivers/base/regmap/regmap.c

1222

rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb);

drivers/bluetooth/btmtksdio.c

100

#define RX_PKT_LEN GENMASK(31, 16)

drivers/bluetooth/btmtksdio.c

99

#define INT_MASK GENMASK(15, 0)

drivers/bluetooth/hci_bcm4377.c

103

#define BCM4377_MSGID_GENERATION GENMASK(15, 8)

drivers/bluetooth/hci_bcm4377.c

104

#define BCM4377_MSGID_ID GENMASK(7, 0)

drivers/bluetooth/hci_bcm4377.c

70

#define BCM4377_BAR0_DOORBELL_VALUE GENMASK(31, 16)

drivers/bluetooth/hci_bcm4377.c

71

#define BCM4377_BAR0_DOORBELL_IDX GENMASK(15, 8)

drivers/bus/brcmstb_gisb.c

38

#define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)

drivers/bus/bt1-axi.c

32

#define BT1_AXI_WERRH_ADDR_MASK GENMASK(31, BT1_AXI_WERRH_ADDR_FLD)

drivers/bus/fsl-mc/fsl-mc-uapi.c

430

module_id = (cmdid & GENMASK(9, 4)) >> 4;

drivers/bus/intel-ixp4xx-eb.c

36

#define IXP4XX_EXP_T1_MASK GENMASK(29, 28)

drivers/bus/intel-ixp4xx-eb.c

38

#define IXP4XX_EXP_T2_MASK GENMASK(27, 26)

drivers/bus/intel-ixp4xx-eb.c

40

#define IXP4XX_EXP_T3_MASK GENMASK(25, 22)

drivers/bus/intel-ixp4xx-eb.c

42

#define IXP4XX_EXP_T4_MASK GENMASK(21, 20)

drivers/bus/intel-ixp4xx-eb.c

44

#define IXP4XX_EXP_T5_MASK GENMASK(19, 16)

drivers/bus/intel-ixp4xx-eb.c

46

#define IXP4XX_EXP_CYC_TYPE_MASK GENMASK(15, 14)

drivers/bus/intel-ixp4xx-eb.c

48

#define IXP4XX_EXP_SIZE_MASK GENMASK(13, 10)

drivers/bus/intel-ixp4xx-eb.c

71

#define IXP43x_EXP_FUSE_SPEED_MASK GENMASK(23, 22)

drivers/bus/mhi/common.h

100

#define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)

drivers/bus/mhi/common.h

107

#define MHICFG_NHWER_MASK GENMASK(31, 24)

drivers/bus/mhi/common.h

108

#define MHICFG_NER_MASK GENMASK(23, 16)

drivers/bus/mhi/common.h

109

#define MHICFG_NHWCH_MASK GENMASK(15, 8)

drivers/bus/mhi/common.h

110

#define MHICFG_NCH_MASK GENMASK(7, 0)

drivers/bus/mhi/common.h

111

#define MHICTRL_MHISTATE_MASK GENMASK(15, 8)

drivers/bus/mhi/common.h

113

#define MHISTATUS_MHISTATE_MASK GENMASK(15, 8)

drivers/bus/mhi/common.h

121

#define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))

drivers/bus/mhi/common.h

126

#define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

drivers/bus/mhi/common.h

127

FIELD_PREP(GENMASK(23, 16), \

drivers/bus/mhi/common.h

133

#define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

drivers/bus/mhi/common.h

134

FIELD_PREP(GENMASK(23, 16), \

drivers/bus/mhi/common.h

140

#define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

drivers/bus/mhi/common.h

141

FIELD_PREP(GENMASK(23, 16), \

drivers/bus/mhi/common.h

145

#define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))

drivers/bus/mhi/common.h

146

#define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))

drivers/bus/mhi/common.h

150

#define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \

drivers/bus/mhi/common.h

151

FIELD_PREP(GENMASK(15, 0), len))

drivers/bus/mhi/common.h

152

#define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

drivers/bus/mhi/common.h

153

FIELD_PREP(GENMASK(23, 16), type))

drivers/bus/mhi/common.h

155

#define MHI_TRE_GET_EV_CODE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

156

#define MHI_TRE_GET_EV_LEN(tre) FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

157

#define MHI_TRE_GET_EV_CHID(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))

drivers/bus/mhi/common.h

158

#define MHI_TRE_GET_EV_TYPE(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))

drivers/bus/mhi/common.h

159

#define MHI_TRE_GET_EV_STATE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

160

#define MHI_TRE_GET_EV_EXECENV(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

164

#define MHI_TRE_GET_EV_VEID(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

165

#define MHI_TRE_GET_EV_LINKSPEED(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))

drivers/bus/mhi/common.h

166

#define MHI_TRE_GET_EV_LINKWIDTH(tre) FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))

drivers/bus/mhi/common.h

170

#define MHI_SC_EV_DWORD0(state) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), state))

drivers/bus/mhi/common.h

171

#define MHI_SC_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))

drivers/bus/mhi/common.h

175

#define MHI_EE_EV_DWORD0(ee) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), ee))

drivers/bus/mhi/common.h

176

#define MHI_EE_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))

drivers/bus/mhi/common.h

181

#define MHI_CC_EV_DWORD0(code) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code))

drivers/bus/mhi/common.h

182

#define MHI_CC_EV_DWORD1(type) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), type))

drivers/bus/mhi/common.h

186

#define MHI_TRE_DATA_DWORD0(len) cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))

drivers/bus/mhi/common.h

188

#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \

drivers/bus/mhi/common.h

195

#define MHI_TRE_DATA_GET_LEN(tre) FIELD_GET(GENMASK(15, 0), MHI_TRE_GET_DWORD(tre, 0))

drivers/bus/mhi/common.h

202

#define MHI_RSCTRE_DATA_PTR(ptr, len) cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)

drivers/bus/mhi/common.h

204

#define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \

drivers/bus/mhi/common.h

255

#define EV_CTX_RESERVED_MASK GENMASK(7, 0)

drivers/bus/mhi/common.h

256

#define EV_CTX_INTMODC_MASK GENMASK(15, 8)

drivers/bus/mhi/common.h

257

#define EV_CTX_INTMODT_MASK GENMASK(31, 16)

drivers/bus/mhi/common.h

269

#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)

drivers/bus/mhi/common.h

270

#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)

drivers/bus/mhi/common.h

271

#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)

drivers/bus/mhi/common.h

272

#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)

drivers/bus/mhi/common.h

66

#define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)

drivers/bus/mhi/common.h

68

#define BHI_STATUS_MASK GENMASK(31, 30)

drivers/bus/mhi/common.h

87

#define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)

drivers/bus/mhi/common.h

89

#define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)

drivers/bus/mhi/common.h

91

#define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)

drivers/bus/mhi/common.h

96

#define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)

drivers/bus/mhi/common.h

98

#define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)

drivers/bus/mhi/ep/internal.h

69

#define MHI_CHDB_INT_CLEAR_n_CLEAR_ALL GENMASK(31, 0)

drivers/bus/mhi/ep/internal.h

71

#define MHI_ERDB_INT_CLEAR_n_CLEAR_ALL GENMASK(31, 0)

drivers/bus/mhi/ep/internal.h

78

#define MHI_CTRL_INT_MASK_MASK GENMASK(1, 0)

drivers/bus/mhi/ep/internal.h

83

#define MHI_CHDB_INT_MASK_n_EN_ALL GENMASK(31, 0)

drivers/bus/mhi/ep/internal.h

85

#define MHI_ERDB_INT_MASK_n_EN_ALL GENMASK(31, 0)

drivers/bus/qcom-ebi2.c

34

#define EBI2_CSN_MASK GENMASK(9, 0)

drivers/bus/stm32_etzpc.c

30

#define ETZPC_HWCFGR_NUM_TZMA GENMASK(7, 0)

drivers/bus/stm32_etzpc.c

31

#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8)

drivers/bus/stm32_etzpc.c

32

#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16)

drivers/bus/stm32_etzpc.c

33

#define ETZPC_HWCFGR_CHUNKS1N4 GENMASK(31, 24)

drivers/bus/stm32_etzpc.c

38

#define ETZPC_PROT_MASK GENMASK(1, 0)

drivers/bus/stm32_rifsc.c

41

#define HWCFGR2_CONF1_MASK GENMASK(15, 0)

drivers/bus/stm32_rifsc.c

42

#define HWCFGR2_CONF2_MASK GENMASK(23, 16)

drivers/bus/stm32_rifsc.c

43

#define HWCFGR2_CONF3_MASK GENMASK(31, 24)

drivers/bus/stm32_rifsc.c

50

#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)

drivers/bus/stm32_rifsc.c

52

#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)

drivers/bus/stm32_rifsc.c

53

#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24)

drivers/bus/stm32_rifsc.c

85

#define RIFSC_RIMC_MCID_MASK GENMASK(6, 4)

drivers/bus/stm32_rifsc.c

89

#define RIFSC_RISC_SRCID_MASK GENMASK(6, 4)

drivers/bus/stm32_rifsc.c

94

#define RIFSC_RISC_SRLENGTH_MASK GENMASK(27, 16)

drivers/bus/stm32_rifsc.c

95

#define RIFSC_RISC_SRSTART_MASK GENMASK(10, 0)

drivers/bus/sunxi-rsb.c

371

*buf = readl(rsb->regs + RSB_DATA) & GENMASK(len * 8 - 1, 0);

drivers/bus/sunxi-rsb.c

78

#define RSB_INTS_TRANS_ERR_DATA GENMASK(11, 8)

drivers/cache/hisi_soc_hha.c

33

#define HISI_HHA_CTRL_TYPE GENMASK(3, 2)

drivers/cache/starfive_starlink_cache.c

22

#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0)

drivers/cache/starfive_starlink_cache.c

23

#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1)

drivers/char/hw_random/airoha-trng.c

16

#define CNT_TRANS GENMASK(15, 8)

drivers/char/hw_random/cctrng.c

24

#define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))

drivers/char/hw_random/histb-rng.c

16

#define RNG_SOURCE GENMASK(1, 0)

drivers/char/hw_random/histb-rng.c

19

#define POST_PROCESS_DEPTH GENMASK(15, 8)

drivers/char/hw_random/histb-rng.c

22

#define DATA_COUNT GENMASK(2, 0) /* max 4 */

drivers/char/hw_random/imx-rngc.c

32

#define RNG_TYPE GENMASK(31, 28)

drivers/char/hw_random/imx-rngc.c

50

#define RNGC_STATUS_FIFO_LEVEL_MASK GENMASK(11, 8)

drivers/char/hw_random/npcm-rng.c

22

#define NPCM_RNG_CLK_SET_25MHZ GENMASK(4, 3) /* 20-25 MHz */

drivers/char/hw_random/rockchip-rng.c

51

#define TRNG_RNG_CTL_MASK GENMASK(15, 0)

drivers/char/hw_random/stm32-rng.c

24

#define RNG_CR_CONFIG1 GENMASK(11, 8)

drivers/char/hw_random/stm32-rng.c

26

#define RNG_CR_CONFIG2 GENMASK(15, 13)

drivers/char/hw_random/stm32-rng.c

28

#define RNG_CR_CLKDIV GENMASK(19, 16)

drivers/char/hw_random/stm32-rng.c

29

#define RNG_CR_CONFIG3 GENMASK(25, 20)

drivers/char/hw_random/stm32-rng.c

45

#define RNG_NSCR_MASK GENMASK(17, 0)

drivers/char/ipmi/kcs_bmc_aspeed.c

101

#define LPC_LSADR12_LSADR2_MASK GENMASK(31, 16)

drivers/char/ipmi/kcs_bmc_aspeed.c

103

#define LPC_LSADR12_LSADR1_MASK GENMASK(15, 0)

drivers/char/ipmi/kcs_bmc_aspeed.c

63

#define LPC_HICR5_ID3IRQX_MASK GENMASK(23, 20)

drivers/char/ipmi/kcs_bmc_aspeed.c

65

#define LPC_HICR5_ID2IRQX_MASK GENMASK(19, 16)

drivers/char/ipmi/kcs_bmc_aspeed.c

90

#define LPC_HICRC_ID4IRQX_MASK GENMASK(7, 4)

drivers/char/ipmi/kcs_bmc_aspeed.c

92

#define LPC_HICRC_TY4IRQX_MASK GENMASK(3, 2)

drivers/char/ipmi/kcs_bmc_cdev_ipmi.c

102

#define KCS_STATUS_STATE_MASK GENMASK(7, 6)

drivers/char/tpm/tpm2-cmd.c

682

~(GENMASK(2, 0) << TPM2_CC_ATTR_CHANDLES);

drivers/char/tpm/tpm2-cmd.c

788

cc_mask = 1 << TPM2_CC_ATTR_VENDOR | GENMASK(15, 0);

drivers/char/tpm/tpm2-sessions.c

615

handles = (attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0);

drivers/char/tpm/tpm2-space.c

258

nr_handles = (attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0);

drivers/char/tpm/tpm2-space.c

295

4 * ((attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0));

drivers/char/tpm/tpm_crb_ffa.c

38

#define CRB_FFA_MAJOR_VERSION_MASK GENMASK(30, 16)

drivers/char/tpm/tpm_crb_ffa.c

39

#define CRB_FFA_MINOR_VERSION_MASK GENMASK(15, 0)

drivers/clk/actions/owl-divider.c

63

reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);

drivers/clk/actions/owl-mux.c

42

reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);

drivers/clk/aspeed/clk-ast2600.c

25

#define CHIP_REVISION_ID GENMASK(23, 16)

drivers/clk/aspeed/clk-ast2600.c

45

#define APLL_DIV_SELECTION GENMASK(30, 28)

drivers/clk/aspeed/clk-ast2600.c

649

regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));

drivers/clk/aspeed/clk-ast2700.c

22

#define GET_USB_REFCLK_DIV(x) ((GENMASK(23, 20) & (x)) >> 20)

drivers/clk/aspeed/clk-ast2700.c

35

#define REVISION_ID GENMASK(23, 16)

drivers/clk/aspeed/clk-ast2700.c

40

#define SCU1_CLK_I3C_DIV_MASK GENMASK(25, 23)

drivers/clk/aspeed/clk-ast2700.c

42

#define UXCLK_MASK GENMASK(1, 0)

drivers/clk/aspeed/clk-ast2700.c

43

#define HUXCLK_MASK GENMASK(4, 3)

drivers/clk/aspeed/clk-ast2700.c

636

r = val & GENMASK(15, 0);

drivers/clk/aspeed/clk-ast2700.c

637

n = (val >> 16) & GENMASK(15, 0);

drivers/clk/aspeed/clk-ast2700.c

653

switch ((val & GENMASK(4, 2)) >> 2) {

drivers/clk/aspeed/clk-ast2700.c

669

} else if ((val & GENMASK(3, 2)) != 0) {

drivers/clk/aspeed/clk-ast2700.c

670

switch ((val & GENMASK(3, 2)) >> 2) {

drivers/clk/at91/at91sam9n12.c

75

.pid_mask = GENMASK(5, 0),

drivers/clk/at91/at91sam9n12.c

76

.div_mask = GENMASK(17, 16),

drivers/clk/at91/at91sam9x5.c

62

.pid_mask = GENMASK(5, 0),

drivers/clk/at91/at91sam9x5.c

63

.div_mask = GENMASK(17, 16),

drivers/clk/at91/clk-sam9x60-pll.c

18

#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)

drivers/clk/at91/clk-sam9x60-pll.c

19

#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)

drivers/clk/at91/clk-sam9x60-pll.c

20

#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)

drivers/clk/at91/clk-usb.c

21

#define SAM9X5_USBS_MASK GENMASK(0, 0)

drivers/clk/at91/clk-usb.c

22

#define SAM9X60_USBS_MASK GENMASK(1, 0)

drivers/clk/at91/dt-compat.c

112

.pid_mask = GENMASK(5, 0),

drivers/clk/at91/dt-compat.c

113

.div_mask = GENMASK(17, 16),

drivers/clk/at91/dt-compat.c

114

.gckcss_mask = GENMASK(10, 8),

drivers/clk/at91/sam9x60.c

56

.mul_mask = GENMASK(31, 24),

drivers/clk/at91/sam9x60.c

57

.frac_mask = GENMASK(21, 0),

drivers/clk/at91/sam9x60.c

63

.div_mask = GENMASK(7, 0),

drivers/clk/at91/sam9x60.c

80

.gckcss_mask = GENMASK(12, 8),

drivers/clk/at91/sam9x60.c

81

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sam9x7.c

148

.mul_mask = GENMASK(31, 24),

drivers/clk/at91/sam9x7.c

149

.frac_mask = GENMASK(21, 0),

drivers/clk/at91/sam9x7.c

157

.mul_mask = GENMASK(31, 24),

drivers/clk/at91/sam9x7.c

158

.frac_mask = GENMASK(21, 0),

drivers/clk/at91/sam9x7.c

165

.div_mask = GENMASK(7, 0),

drivers/clk/at91/sam9x7.c

173

.div_mask = GENMASK(7, 0),

drivers/clk/at91/sam9x7.c

182

.div_mask = GENMASK(19, 12),

drivers/clk/at91/sam9x7.c

338

.gckcss_mask = GENMASK(12, 8),

drivers/clk/at91/sam9x7.c

339

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sama5d2.c

36

.gckcss_mask = GENMASK(10, 8),

drivers/clk/at91/sama5d2.c

37

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sama5d3.c

36

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sama5d3.c

37

.div_mask = GENMASK(17, 16),

drivers/clk/at91/sama5d4.c

36

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sama7d65.c

1093

.gckcss_mask = GENMASK(12, 8),

drivers/clk/at91/sama7d65.c

1094

.pid_mask = GENMASK(6, 0),

drivers/clk/at91/sama7d65.c

74

.mul_mask = GENMASK(31, 24),

drivers/clk/at91/sama7d65.c

75

.frac_mask = GENMASK(21, 0),

drivers/clk/at91/sama7d65.c

82

.div_mask = GENMASK(7, 0),

drivers/clk/at91/sama7d65.c

90

.div_mask = GENMASK(19, 12),

drivers/clk/at91/sama7g5.c

69

.mul_mask = GENMASK(31, 24),

drivers/clk/at91/sama7g5.c

70

.frac_mask = GENMASK(21, 0),

drivers/clk/at91/sama7g5.c

77

.div_mask = GENMASK(7, 0),

drivers/clk/at91/sama7g5.c

85

.div_mask = GENMASK(19, 12),

drivers/clk/at91/sama7g5.c

971

.gckcss_mask = GENMASK(12, 8),

drivers/clk/at91/sama7g5.c

972

.pid_mask = GENMASK(6, 0),

drivers/clk/baikal-t1/ccu-div.c

35

GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)

drivers/clk/baikal-t1/ccu-pll.c

35

#define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)

drivers/clk/baikal-t1/ccu-pll.c

37

#define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)

drivers/clk/baikal-t1/ccu-pll.c

39

#define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)

drivers/clk/baikal-t1/ccu-pll.c

44

#define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)

drivers/clk/bcm/clk-bcm2835.c

223

#define A2W_PLL_KA_MASK GENMASK(9, 7)

drivers/clk/bcm/clk-bcm2835.c

225

#define A2W_PLL_KI_MASK GENMASK(21, 19)

drivers/clk/bcm/clk-bcm2835.c

227

#define A2W_PLL_KP_MASK GENMASK(18, 15)

drivers/clk/bcm/clk-bcm2835.c

230

#define A2W_PLLH_KA_MASK GENMASK(21, 19)

drivers/clk/bcm/clk-bcm2835.c

232

#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)

drivers/clk/bcm/clk-bcm2835.c

234

#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)

drivers/clk/bcm/clk-bcm2835.c

236

#define A2W_PLLH_KP_MASK GENMASK(4, 1)

drivers/clk/bcm/clk-bcm2835.c

45

# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)

drivers/clk/bcm/clk-bcm2835.c

948

GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;

drivers/clk/bcm/clk-bcm2835.c

966

maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,

drivers/clk/clk-apple-nco.c

26

#define DIV_FINE GENMASK(1, 0)

drivers/clk/clk-apple-nco.c

27

#define DIV_COARSE GENMASK(12, 2)

drivers/clk/clk-axi-clkgen.c

35

#define ADI_CLKGEN_INFO_FPGA_VOLTAGE(val) ((val) & GENMASK(15, 0))

drivers/clk/clk-en7523.c

39

#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)

drivers/clk/clk-en7523.c

40

#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)

drivers/clk/clk-ep93xx.c

292

pdiv = (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0);

drivers/clk/clk-ep93xx.c

293

div = val & GENMASK(6, 0);

drivers/clk/clk-ep93xx.c

332

val &= ~(GENMASK(9, 0) & ~BIT(7));

drivers/clk/clk-ep93xx.c

467

clk->mask = GENMASK(shift + width - 1, shift);

drivers/clk/clk-ep93xx.c

56

#define EP93XX_SYSCON_CLKDIV_MASK GENMASK(14, 13)

drivers/clk/clk-ep93xx.c

582

rate *= ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */

drivers/clk/clk-ep93xx.c

583

rate *= ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */

drivers/clk/clk-ep93xx.c

584

do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */

drivers/clk/clk-ep93xx.c

585

rate >>= (config_word >> 16) & GENMASK(1, 0); /* PS */

drivers/clk/clk-ep93xx.c

618

clk_f_div = fclk_divisors[(value >> 25) & GENMASK(2, 0)];

drivers/clk/clk-ep93xx.c

619

clk_h_div = hclk_divisors[(value >> 20) & GENMASK(2, 0)];

drivers/clk/clk-ep93xx.c

620

clk_p_div = pclk_divisors[(value >> 18) & GENMASK(1, 0)];

drivers/clk/clk-ep93xx.c

690

clk_usb_div = (value >> 28 & GENMASK(3, 0)) + 1;

drivers/clk/clk-eyeq.c

56

#define PCSR0_POST_DIV1 GENMASK(6, 4)

drivers/clk/clk-eyeq.c

57

#define PCSR0_POST_DIV2 GENMASK(9, 7)

drivers/clk/clk-eyeq.c

58

#define PCSR0_REF_DIV GENMASK(15, 10)

drivers/clk/clk-eyeq.c

59

#define PCSR0_INTIN GENMASK(27, 16)

drivers/clk/clk-eyeq.c

65

#define PCSR1_SSGC_DIV GENMASK(4, 1)

drivers/clk/clk-eyeq.c

67

#define PCSR1_SPREAD GENMASK(9, 5)

drivers/clk/clk-eyeq.c

71

#define PCSR1_FRAC_IN GENMASK(31, 12)

drivers/clk/clk-fractional-divider.c

146

max_m = GENMASK(fd->mwidth - 1, 0);

drivers/clk/clk-fractional-divider.c

147

max_n = GENMASK(fd->nwidth - 1, 0);

drivers/clk/clk-fractional-divider.c

195

max_m = GENMASK(fd->mwidth - 1, 0);

drivers/clk/clk-fractional-divider.c

196

max_n = GENMASK(fd->nwidth - 1, 0);

drivers/clk/clk-fractional-divider.c

205

mmask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;

drivers/clk/clk-fractional-divider.c

206

nmask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;

drivers/clk/clk-fractional-divider.c

89

mmask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;

drivers/clk/clk-fractional-divider.c

90

nmask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;

drivers/clk/clk-hsdk-pll.c

28

#define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)

drivers/clk/clk-hsdk-pll.c

29

#define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)

drivers/clk/clk-hsdk-pll.c

30

#define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)

drivers/clk/clk-k210.c

255

#define K210_PLL_CLKR GENMASK(3, 0)

drivers/clk/clk-k210.c

256

#define K210_PLL_CLKF GENMASK(9, 4)

drivers/clk/clk-k210.c

257

#define K210_PLL_CLKOD GENMASK(13, 10)

drivers/clk/clk-k210.c

258

#define K210_PLL_BWADJ GENMASK(19, 14)

drivers/clk/clk-k210.c

265

#define K210_PLL_SEL GENMASK(27, 26) /* PLL2 only */

drivers/clk/clk-k210.c

278

#define K210_ACLK_DIV GENMASK(2, 1)

drivers/clk/clk-k210.c

365

u32 reg, mask = GENMASK(pll->lock_shift + pll->lock_width - 1,

drivers/clk/clk-k210.c

406

reg &= ~GENMASK(19, 0);

drivers/clk/clk-k210.c

760

div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0);

drivers/clk/clk-lan966x.c

20

#define GCK_SRC_SEL GENMASK(9, 8)

drivers/clk/clk-lan966x.c

21

#define GCK_PRESCALER GENMASK(23, 16)

drivers/clk/clk-lmk04832.c

117

#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)

drivers/clk/clk-lmk04832.c

129

#define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3)

drivers/clk/clk-lmk04832.c

131

#define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0)

drivers/clk/clk-lmk04832.c

138

#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)

drivers/clk/clk-lmk04832.c

140

#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)

drivers/clk/clk-lmk04832.c

145

#define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0)

drivers/clk/clk-lmk04832.c

148

#define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5)

drivers/clk/clk-lmk04832.c

151

#define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0)

drivers/clk/clk-lmk04832.c

155

#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)

drivers/clk/clk-lmk04832.c

161

#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)

drivers/clk/clk-lmk04832.c

163

#define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0)

drivers/clk/clk-lmk04832.c

36

#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)

drivers/clk/clk-lmk04832.c

38

#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)

drivers/clk/clk-lmk04832.c

42

#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)

drivers/clk/clk-lmk04832.c

43

#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)

drivers/clk/clk-lmk04832.c

52

#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)

drivers/clk/clk-lmk04832.c

55

#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)

drivers/clk/clk-lmk04832.c

77

#define LMK04832_BIT_VCO_MUX GENMASK(6, 5)

drivers/clk/clk-lmk04832.c

83

#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)

drivers/clk/clk-lmk04832.c

89

#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)

drivers/clk/clk-lmk04832.c

92

#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)

drivers/clk/clk-loongson1.c

57

return (val & GENMASK(shift + width, shift)) >> shift;

drivers/clk/clk-loongson2.c

278

return (val & GENMASK(shift + width - 1, shift)) >> shift;

drivers/clk/clk-multiplier.c

141

val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);

drivers/clk/clk-multiplier.c

48

val &= GENMASK(mult->width - 1, 0);

drivers/clk/clk-npcm7xx.c

299

{0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,

drivers/clk/clk-npcm7xx.c

303

{4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,

drivers/clk/clk-npcm7xx.c

307

{6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,

drivers/clk/clk-npcm7xx.c

310

{8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,

drivers/clk/clk-npcm7xx.c

313

{10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,

drivers/clk/clk-npcm7xx.c

316

{12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,

drivers/clk/clk-npcm7xx.c

319

{14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,

drivers/clk/clk-npcm7xx.c

32

#define PLLCON_FBDV GENMASK(27, 16)

drivers/clk/clk-npcm7xx.c

322

{16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,

drivers/clk/clk-npcm7xx.c

325

{18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,

drivers/clk/clk-npcm7xx.c

328

{21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,

drivers/clk/clk-npcm7xx.c

33

#define PLLCON_OTDV2 GENMASK(15, 13)

drivers/clk/clk-npcm7xx.c

331

{23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,

drivers/clk/clk-npcm7xx.c

35

#define PLLCON_OTDV1 GENMASK(10, 8)

drivers/clk/clk-npcm7xx.c

36

#define PLLCON_INDV GENMASK(5, 0)

drivers/clk/clk-npcm8xx.c

40

#define PLLCON_FBDV GENMASK(27, 16)

drivers/clk/clk-npcm8xx.c

41

#define PLLCON_OTDV2 GENMASK(15, 13)

drivers/clk/clk-npcm8xx.c

43

#define PLLCON_OTDV1 GENMASK(10, 8)

drivers/clk/clk-npcm8xx.c

44

#define PLLCON_INDV GENMASK(5, 0)

drivers/clk/clk-plldig.c

23

#define PLLDIG_MFD_MASK GENMASK(7, 0)

drivers/clk/clk-plldig.c

24

#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25)

drivers/clk/clk-plldig.c

29

#define PLLDIG_FRAC_MASK GENMASK(15, 0)

drivers/clk/clk-qoriq.c

1266

mult = (mult & GENMASK(8, 1)) >> 1;

drivers/clk/clk-qoriq.c

1268

mult = (mult & GENMASK(6, 1)) >> 1;

drivers/clk/clk-renesas-pcie.c

48

#define RS9_REG_VID_MASK GENMASK(3, 0)

drivers/clk/clk-rp1.c

223

#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */

drivers/clk/clk-rp1.c

224

#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */

drivers/clk/clk-rp1.c

225

#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */

drivers/clk/clk-rp1.c

231

#define PLL_PRIM_DIV1_MASK GENMASK(18, 16)

drivers/clk/clk-rp1.c

232

#define PLL_PRIM_DIV2_MASK GENMASK(14, 12)

drivers/clk/clk-rp1.c

234

#define PLL_SEC_DIV_MASK GENMASK(12, 8)

drivers/clk/clk-rp1.c

245

#define PLL_PWR_MASK GENMASK(5, 0)

drivers/clk/clk-rp1.c

261

#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5)

drivers/clk/clk-rpmi.c

29

#define RPMI_CLK_TYPE_MASK GENMASK(1, 0)

drivers/clk/clk-si521xx.c

27

#define SI521XX_REG_ID_PROG GENMASK(7, 4)

drivers/clk/clk-si521xx.c

28

#define SI521XX_REG_ID_VENDOR GENMASK(3, 0)

drivers/clk/clk-si521xx.c

32

#define SI521XX_REG_DA_AMP_MASK GENMASK(6, 4)

drivers/clk/clk-sp7021.c

34

#define MASK_SEL_FRA GENMASK(1, 1)

drivers/clk/clk-sp7021.c

35

#define MASK_SDM_MOD GENMASK(2, 2)

drivers/clk/clk-sp7021.c

36

#define MASK_PH_SEL GENMASK(4, 4)

drivers/clk/clk-sp7021.c

37

#define MASK_NFRA GENMASK(12, 6)

drivers/clk/clk-sp7021.c

38

#define MASK_DIVR GENMASK(8, 7)

drivers/clk/clk-sp7021.c

39

#define MASK_DIVN GENMASK(7, 0)

drivers/clk/clk-sp7021.c

40

#define MASK_DIVM GENMASK(14, 8)

drivers/clk/clk-sp7021.c

494

u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift);

drivers/clk/clk-sparx5.c

19

#define PLL_DIV GENMASK(7, 0)

drivers/clk/clk-sparx5.c

20

#define PLL_PRE_DIV GENMASK(10, 8)

drivers/clk/clk-sparx5.c

22

#define PLL_ROT_SEL GENMASK(13, 12)

drivers/clk/clk-stm32f4.c

44

#define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6)

drivers/clk/clk-stm32f4.c

48

#define STM32F4_RCC_SSCGR_RESERVED_MASK GENMASK(29, 28)

drivers/clk/clk-stm32f4.c

49

#define STM32F4_RCC_SSCGR_INCSTEP_MASK GENMASK(27, 13)

drivers/clk/clk-stm32f4.c

50

#define STM32F4_RCC_SSCGR_MODPER_MASK GENMASK(12, 0)

drivers/clk/clk-stm32h7.c

739

GENMASK(fd->fwidth - 1, 0);

drivers/clk/clk-stm32h7.c

752

mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;

drivers/clk/clk-stm32h7.c

756

mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;

drivers/clk/clk-versaclock3.c

23

#define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0))

drivers/clk/clk-versaclock3.c

37

#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))

drivers/clk/clk-versaclock3.c

375

div_int = (val & GENMASK(2, 0)) << 8;

drivers/clk/clk-versaclock3.c

53

#define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0))

drivers/clk/clk-versaclock5.c

107

#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)

drivers/clk/clk-versaclock5.c

112

#define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)

drivers/clk/clk-versaclock5.c

96

#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)

drivers/clk/clk-versaclock7.c

70

#define VC7_REG_XO_IB_H_DIV_MASK GENMASK(28, VC7_REG_XO_IB_H_DIV_SHIFT)

drivers/clk/clk-versaclock7.c

74

#define VC7_REG_APLL_FB_DIV_FRAC_MASK GENMASK(26, 0)

drivers/clk/clk-versaclock7.c

78

#define VC7_REG_APLL_FB_DIV_INT_MASK GENMASK(9, 0)

drivers/clk/clk-versaclock7.c

84

#define VC7_REG_OUTPUT_BANK_SRC_MASK GENMASK(2, 0)

drivers/clk/clk-versaclock7.c

88

#define VC7_REG_FOD_1ST_INT_MASK GENMASK(8, 0)

drivers/clk/clk-versaclock7.c

90

#define VC7_REG_FOD_2ND_INT_MASK GENMASK(25, VC7_REG_FOD_2ND_INT_SHIFT)

drivers/clk/clk-versaclock7.c

96

#define VC7_REG_IOD_INT_MASK GENMASK(24, 0)

drivers/clk/davinci/pll-da850.c

164

.pllm_mask = GENMASK(4, 0),

drivers/clk/davinci/pll-da850.c

195

.ocsrc_mask = GENMASK(4, 0),

drivers/clk/davinci/pll-da850.c

33

.pllm_mask = GENMASK(4, 0),

drivers/clk/davinci/pll-da850.c

86

.ocsrc_mask = GENMASK(4, 0),

drivers/clk/davinci/psc.c

50

#define MDSTAT_STATE_MASK GENMASK(5, 0)

drivers/clk/davinci/psc.c

52

#define PDSTAT_STATE_MASK GENMASK(4, 0)

drivers/clk/imx/clk-frac-pll.c

29

#define PLL_FRAC_DIV_MASK GENMASK(30, 7)

drivers/clk/imx/clk-frac-pll.c

30

#define PLL_INT_DIV_MASK GENMASK(6, 0)

drivers/clk/imx/clk-frac-pll.c

31

#define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)

drivers/clk/imx/clk-fracn-gppll.c

27

#define PLL_MFN_MASK GENMASK(31, 2)

drivers/clk/imx/clk-fracn-gppll.c

30

#define PLL_MFD_MASK GENMASK(29, 0)

drivers/clk/imx/clk-fracn-gppll.c

33

#define PLL_MFI_MASK GENMASK(24, 16)

drivers/clk/imx/clk-fracn-gppll.c

34

#define PLL_RDIV_MASK GENMASK(15, 13)

drivers/clk/imx/clk-fracn-gppll.c

35

#define PLL_ODIV_MASK GENMASK(7, 0)

drivers/clk/imx/clk-pll14xx.c

28

#define MDIV_MASK GENMASK(21, 12)

drivers/clk/imx/clk-pll14xx.c

29

#define PDIV_MASK GENMASK(9, 4)

drivers/clk/imx/clk-pll14xx.c

30

#define SDIV_MASK GENMASK(2, 0)

drivers/clk/imx/clk-pll14xx.c

31

#define KDIV_MASK GENMASK(15, 0)

drivers/clk/imx/clk-sscg-pll.c

26

#define PLL_DIVF1_MASK GENMASK(18, 13)

drivers/clk/imx/clk-sscg-pll.c

27

#define PLL_DIVF2_MASK GENMASK(12, 7)

drivers/clk/imx/clk-sscg-pll.c

28

#define PLL_DIVR1_MASK GENMASK(27, 25)

drivers/clk/imx/clk-sscg-pll.c

29

#define PLL_DIVR2_MASK GENMASK(24, 19)

drivers/clk/imx/clk-sscg-pll.c

30

#define PLL_DIVQ_MASK GENMASK(6, 1)

drivers/clk/imx/clk-sscg-pll.c

31

#define PLL_REF_MASK GENMASK(2, 0)

drivers/clk/imx/clk-sscg-pll.c

67

#define SSCG_PLL_BYPASS_MASK GENMASK(5, 4)

drivers/clk/ingenic/cgu.c

102

od_enc &= GENMASK(pll_info->od_bits - 1, 0);

drivers/clk/ingenic/cgu.c

224

ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);

drivers/clk/ingenic/cgu.c

227

ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);

drivers/clk/ingenic/cgu.c

231

ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);

drivers/clk/ingenic/cgu.c

345

GENMASK(clk_info->mux.bits - 1, 0);

drivers/clk/ingenic/cgu.c

389

mask = GENMASK(clk_info->mux.bits - 1, 0);

drivers/clk/ingenic/cgu.c

423

GENMASK(clk_info->div.bits - 1, 0);

drivers/clk/ingenic/cgu.c

553

mask = GENMASK(clk_info->div.bits - 1, 0);

drivers/clk/ingenic/cgu.c

95

m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);

drivers/clk/ingenic/cgu.c

97

n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);

drivers/clk/ingenic/x1000-cgu.c

178

const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0);

drivers/clk/ingenic/x1000-cgu.c

179

const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0);

drivers/clk/mediatek/clk-mt6795-apmixedsys.c

82

.dds_mask = GENMASK(21, 0), \

drivers/clk/mediatek/clk-mt6795-apmixedsys.c

94

.msk_frddsx_dys = GENMASK(23, 20), \

drivers/clk/mediatek/clk-mt6795-apmixedsys.c

95

.msk_frddsx_dts = GENMASK(19, 16), \

drivers/clk/mediatek/clk-mt8173-apmixedsys.c

103

.dds_mask = GENMASK(21, 0), \

drivers/clk/mediatek/clk-mt8173-apmixedsys.c

115

.msk_frddsx_dys = GENMASK(23, 20), \

drivers/clk/mediatek/clk-mt8173-apmixedsys.c

116

.msk_frddsx_dts = GENMASK(19, 16), \

drivers/clk/mediatek/clk-mt8186-apmixedsys.c

104

.dds_mask = GENMASK(21, 0), \

drivers/clk/mediatek/clk-mt8186-apmixedsys.c

116

.msk_frddsx_dys = GENMASK(23, 20), \

drivers/clk/mediatek/clk-mt8186-apmixedsys.c

117

.msk_frddsx_dts = GENMASK(19, 16), \

drivers/clk/mediatek/clk-mt8192-apmixedsys.c

120

.dds_mask = GENMASK(21, 0), \

drivers/clk/mediatek/clk-mt8192-apmixedsys.c

132

.msk_frddsx_dys = GENMASK(23, 20), \

drivers/clk/mediatek/clk-mt8192-apmixedsys.c

133

.msk_frddsx_dts = GENMASK(19, 16), \

drivers/clk/mediatek/clk-mt8195-apmixedsys.c

135

.dds_mask = GENMASK(21, 0), \

drivers/clk/mediatek/clk-mt8195-apmixedsys.c

147

.msk_frddsx_dys = GENMASK(23, 20), \

drivers/clk/mediatek/clk-mt8195-apmixedsys.c

148

.msk_frddsx_dts = GENMASK(19, 16), \

drivers/clk/mediatek/clk-mux.c

163

u32 mask = GENMASK(mux->data->mux_width - 1, 0);

drivers/clk/mediatek/clk-mux.c

186

u32 mask = GENMASK(mux->data->mux_width - 1, 0);

drivers/clk/mediatek/clk-pll.c

121

val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,

drivers/clk/mediatek/clk-pll.c

206

pcw &= GENMASK(pll->data->pcwbits - 1, 0);

drivers/clk/mediatek/clk-pll.c

64

if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))

drivers/clk/mediatek/clk-pll.h

23

#define POSTDIV_MASK GENMASK(2, 0)

drivers/clk/meson/parm.h

13

#define PMASK(width) GENMASK(width - 1, 0)

drivers/clk/meson/parm.h

14

#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)

drivers/clk/mmp/clk-pxa1908-mpmu.c

53

.num_mask = GENMASK(12, 0),

drivers/clk/mmp/clk-pxa1908-mpmu.c

54

.den_mask = GENMASK(12, 0),

drivers/clk/nuvoton/clk-ma35d1-pll.c

37

#define SPLL0_CTL0_FBDIV GENMASK(7, 0)

drivers/clk/nuvoton/clk-ma35d1-pll.c

38

#define SPLL0_CTL0_INDIV GENMASK(11, 8)

drivers/clk/nuvoton/clk-ma35d1-pll.c

39

#define SPLL0_CTL0_OUTDIV GENMASK(13, 12)

drivers/clk/nuvoton/clk-ma35d1-pll.c

44

#define PLL_CTL0_FBDIV GENMASK(10, 0)

drivers/clk/nuvoton/clk-ma35d1-pll.c

45

#define PLL_CTL0_INDIV GENMASK(17, 12)

drivers/clk/nuvoton/clk-ma35d1-pll.c

46

#define PLL_CTL0_MODE GENMASK(19, 18)

drivers/clk/nuvoton/clk-ma35d1-pll.c

47

#define PLL_CTL0_SSRATE GENMASK(30, 20)

drivers/clk/nuvoton/clk-ma35d1-pll.c

50

#define PLL_CTL1_OUTDIV GENMASK(6, 4)

drivers/clk/nuvoton/clk-ma35d1-pll.c

51

#define PLL_CTL1_FRAC GENMASK(31, 24)

drivers/clk/nuvoton/clk-ma35d1-pll.c

52

#define PLL_CTL2_SLOPE GENMASK(23, 0)

drivers/clk/qcom/apcs-msm8996.c

19

#define APCS_AUX_DIV_MASK GENMASK(17, 16)

drivers/clk/qcom/apss-ipq-pll.c

77

.status_mask = GENMASK(10, 8),

drivers/clk/qcom/apss-ipq-pll.c

90

.status_mask = GENMASK(10, 8),

drivers/clk/qcom/camcc-qcs615.c

118

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/camcc-qcs615.c

174

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/camcc-qcs615.c

57

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/camcc-qcs615.c

89

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/clk-alpha-pll.c

2124

mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);

drivers/clk/qcom/clk-alpha-pll.c

369

#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)

drivers/clk/qcom/clk-alpha-pll.c

374

#define PONGO_PLL_OUT_MASK GENMASK(1, 0)

drivers/clk/qcom/clk-alpha-pll.c

375

#define PONGO_PLL_L_VAL_MASK GENMASK(11, 0)

drivers/clk/qcom/clk-alpha-pll.c

43

# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)

drivers/clk/qcom/clk-alpha-pll.c

742

a = low & GENMASK(alpha_width - 1, 0);

drivers/clk/qcom/clk-branch.h

64

#define CBCR_NOC_FSM_STATUS GENMASK(30, 28)

drivers/clk/qcom/clk-branch.h

69

#define CBCR_WAKEUP GENMASK(11, 8)

drivers/clk/qcom/clk-branch.h

70

#define CBCR_SLEEP GENMASK(7, 4)

drivers/clk/qcom/clk-cbf-8996.c

36

#define CBF_MUX_PARENT_MASK GENMASK(1, 0)

drivers/clk/qcom/clk-cbf-8996.c

37

#define CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)

drivers/clk/qcom/clk-cpu-8996.c

88

#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)

drivers/clk/qcom/clk-rcg2.c

1690

level &= GENMASK(4, 1);

drivers/clk/qcom/clk-rcg2.c

1789

GENMASK(rcg->mnd_width - 1, 0),

drivers/clk/qcom/clk-rcg2.c

1790

GENMASK(rcg->mnd_width - 1, 0), &den, &num);

drivers/clk/qcom/clk-rcg2.c

1837

GENMASK(rcg->mnd_width - 1, 0),

drivers/clk/qcom/clk-rcg2.c

1838

GENMASK(rcg->mnd_width - 1, 0), &den, &num);

drivers/clk/qcom/clk-regmap-mux.c

22

unsigned int mask = GENMASK(mux->width - 1, 0);

drivers/clk/qcom/clk-regmap-mux.c

40

unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);

drivers/clk/qcom/clk-regmap-phy-mux.c

14

#define PHY_MUX_MASK GENMASK(1, 0)

drivers/clk/qcom/clk-spmi-pmic-div.c

20

#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)

drivers/clk/qcom/dispcc-qcm2290.c

45

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/dispcc-qcs615.c

55

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/dispcc-sm6115.c

53

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-ipq5018.c

3371

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-ipq5018.c

3664

[GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) },

drivers/clk/qcom/gcc-ipq6018.c

4207

.post_div_mask = GENMASK(9, 8),

drivers/clk/qcom/gcc-ipq6018.c

4219

.pre_div_mask = GENMASK(14, 12),

drivers/clk/qcom/gcc-ipq6018.c

4221

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-ipq6018.c

4222

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-ipq8074.c

4309

.post_div_mask = GENMASK(9, 8),

drivers/clk/qcom/gcc-ipq8074.c

4319

.pre_div_mask = GENMASK(14, 12),

drivers/clk/qcom/gcc-ipq8074.c

4321

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-ipq8074.c

4322

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-ipq8074.c

4701

[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },

drivers/clk/qcom/gcc-ipq8074.c

4702

[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },

drivers/clk/qcom/gcc-ipq8074.c

4704

[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },

drivers/clk/qcom/gcc-ipq8074.c

4706

[GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },

drivers/clk/qcom/gcc-ipq8074.c

4708

[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },

drivers/clk/qcom/gcc-ipq8074.c

4709

[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },

drivers/clk/qcom/gcc-ipq8074.c

4710

[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },

drivers/clk/qcom/gcc-ipq8074.c

4711

[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },

drivers/clk/qcom/gcc-ipq8074.c

4712

[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },

drivers/clk/qcom/gcc-ipq8074.c

4713

[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },

drivers/clk/qcom/gcc-ipq8074.c

4714

[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },

drivers/clk/qcom/gcc-msm8917.c

117

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-msm8953.c

120

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-qcm2290.c

116

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-qcm2290.c

148

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-qcm2290.c

306

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-qcm2290.c

310

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-qcm2290.c

361

.post_div_mask = GENMASK(9, 8),

drivers/clk/qcom/gcc-sm6115.c

120

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-sm6115.c

174

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-sm6115.c

364

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gcc-sm6115.c

368

.post_div_mask = GENMASK(11, 8),

drivers/clk/qcom/gcc-sm6115.c

420

.post_div_mask = GENMASK(9, 8),

drivers/clk/qcom/gcc-sm6115.c

423

.test_ctl_mask = GENMASK(31, 0),

drivers/clk/qcom/gpucc-qcm2290.c

53

.test_ctl_val = GENMASK(28, 26),

drivers/clk/qcom/gpucc-qcs615.c

62

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gpucc-qcs615.c

94

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gpucc-sm6115.c

112

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/gpucc-sm6115.c

54

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/ipq-cmn-pll.c

57

#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)

drivers/clk/qcom/ipq-cmn-pll.c

67

#define CMN_PLL_REFCLK_DIV GENMASK(8, 4)

drivers/clk/qcom/ipq-cmn-pll.c

68

#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0)

drivers/clk/qcom/ipq-cmn-pll.c

74

#define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0)

drivers/clk/qcom/nsscc-ipq9574.c

3003

[PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) },

drivers/clk/qcom/nsscc-ipq9574.c

3004

[UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) },

drivers/clk/qcom/nsscc-ipq9574.c

3005

[UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },

drivers/clk/qcom/nsscc-ipq9574.c

3006

[UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },

drivers/clk/qcom/nsscc-ipq9574.c

3007

[UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) },

drivers/clk/qcom/nsscc-ipq9574.c

3008

[UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) },

drivers/clk/qcom/nsscc-ipq9574.c

3009

[UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) },

drivers/clk/qcom/nsscc-ipq9574.c

3010

[UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) },

drivers/clk/qcom/nsscc-ipq9574.c

3011

[UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },

drivers/clk/qcom/nsscc-ipq9574.c

3012

[UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },

drivers/clk/qcom/nsscc-ipq9574.c

3013

[NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) },

drivers/clk/qcom/nsscc-ipq9574.c

3014

[NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) },

drivers/clk/qcom/nsscc-ipq9574.c

3015

[NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) },

drivers/clk/qcom/nsscc-ipq9574.c

3016

[NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },

drivers/clk/qcom/nsscc-ipq9574.c

3017

[NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },

drivers/clk/qcom/nsscc-ipq9574.c

3018

[NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },

drivers/clk/qcom/nsscc-ipq9574.c

3019

[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },

drivers/clk/qcom/nsscc-ipq9574.c

72

.post_div_mask = GENMASK(9, 8),

drivers/clk/qcom/nsscc-qca8k.c

2004

[NSS_CC_GEPHY_FULL_ARES] = { .reg = 0x304, .bitmask = GENMASK(4, 0) },

drivers/clk/qcom/nsscc-qca8k.c

31

#define QCA8K_CLK_REG_MASK GENMASK(4, 0)

drivers/clk/qcom/nsscc-qca8k.c

32

#define QCA8K_CLK_PHY_ADDR_MASK GENMASK(7, 5)

drivers/clk/qcom/nsscc-qca8k.c

33

#define QCA8K_CLK_PAGE_MASK GENMASK(23, 8)

drivers/clk/qcom/videocc-kaanapali.c

23

#define ACCU_CFG_MASK GENMASK(25, 21)

drivers/clk/qcom/videocc-kaanapali.c

377

.mem_enable_ack_mask = GENMASK(11, 10),

drivers/clk/qcom/videocc-qcs615.c

50

.vco_mask = GENMASK(21, 20),

drivers/clk/qcom/videocc-sm8750.c

231

.mem_enable_ack_mask = GENMASK(11, 10),

drivers/clk/qcom/videocc-sm8750.c

405

regmap_update_bits(regmap, 0x8074, GENMASK(25, 21), GENMASK(25, 21));

drivers/clk/qcom/videocc-sm8750.c

406

regmap_update_bits(regmap, 0x8040, GENMASK(25, 21), GENMASK(25, 21));

drivers/clk/ralink/clk-mt7621.c

28

#define XTAL_MODE_SEL_MASK GENMASK(8, 6)

drivers/clk/ralink/clk-mt7621.c

29

#define CPU_CLK_SEL_MASK GENMASK(31, 30)

drivers/clk/ralink/clk-mt7621.c

30

#define CUR_CPU_FDIV_MASK GENMASK(12, 8)

drivers/clk/ralink/clk-mt7621.c

31

#define CUR_CPU_FFRAC_MASK GENMASK(4, 0)

drivers/clk/ralink/clk-mt7621.c

32

#define CPU_PLL_PREDIV_MASK GENMASK(13, 12)

drivers/clk/ralink/clk-mt7621.c

33

#define CPU_PLL_FBDIV_MASK GENMASK(10, 4)

drivers/clk/renesas/clk-div6.c

273

clock->src_mask = GENMASK(7, 6);

drivers/clk/renesas/clk-div6.c

277

clock->src_mask = GENMASK(14, 12);

drivers/clk/renesas/clk-vbattb.c

26

#define VBATTB_XOSCCR_XSEL GENMASK(1, 0)

drivers/clk/renesas/r9a07g043-cpg.c

225

0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),

drivers/clk/renesas/r9a07g043-cpg.c

227

0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),

drivers/clk/renesas/r9a07g044-cpg.c

315

0x568, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

317

0x568, 1, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

319

0x568, 2, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

321

0x568, 3, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

323

0x568, 4, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

325

0x568, 5, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),

drivers/clk/renesas/r9a07g044-cpg.c

327

0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),

drivers/clk/renesas/r9a07g044-cpg.c

329

0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),

drivers/clk/renesas/r9a08g045-cpg.c

305

MSTOP(BUS_MCPU3, GENMASK(8, 7))),

drivers/clk/renesas/r9a09g077-cpg.c

22

#define RZT2H_REG_OFFSET_MASK GENMASK(10, 0)

drivers/clk/renesas/r9a09g077-cpg.c

33

#define OFFSET_MASK GENMASK(31, 20)

drivers/clk/renesas/r9a09g077-cpg.c

34

#define SHIFT_MASK GENMASK(19, 12)

drivers/clk/renesas/r9a09g077-cpg.c

35

#define WIDTH_MASK GENMASK(11, 8)

drivers/clk/renesas/rcar-gen3-cpg.c

287

zclk->mask = GENMASK(offset + 4, offset);

drivers/clk/renesas/rcar-gen3-cpg.c

37

#define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */

drivers/clk/renesas/rcar-gen3-cpg.c

499

value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;

drivers/clk/renesas/rcar-gen4-cpg.c

400

zclk->mask = GENMASK(offset + 4, offset);

drivers/clk/renesas/rcar-gen4-cpg.c

48

#define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */

drivers/clk/renesas/rcar-gen4-cpg.c

52

#define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */

drivers/clk/renesas/rcar-gen4-cpg.c

53

#define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */

drivers/clk/renesas/rcar-gen4-cpg.c

56

#define CPG_PLLxCR0_NI8 GENMASK(27, 20) /* Integer mult. factor */

drivers/clk/renesas/rcar-gen4-cpg.c

57

#define CPG_PLLxCR1_NF25 GENMASK(24, 0) /* Fractional mult. factor */

drivers/clk/renesas/rcar-gen4-cpg.c

60

#define CPG_PLLxCR0_NI9 GENMASK(28, 20) /* Integer mult. factor */

drivers/clk/renesas/rcar-gen4-cpg.c

61

#define CPG_PLLxCR1_NF24 GENMASK(23, 0) /* Fractional mult. factor */

drivers/clk/renesas/rcar-gen4-cpg.c

63

#define CPG_PLLxCR_STC GENMASK(30, 24) /* R_Car V3U PLLxCR */

drivers/clk/renesas/rcar-gen4-cpg.c

69

#define CPG_SD0CKCR1_SDSRC_SEL GENMASK(30, 29) /* SDSRC clock freq. select */

drivers/clk/renesas/renesas-cpg-mssr.c

92

#define RZT2H_MSTPCR_OFFSET_MASK GENMASK(11, 0)

drivers/clk/renesas/rzg2l-cpg.c

204

u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf);

drivers/clk/renesas/rzg2l-cpg.c

276

val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);

drivers/clk/renesas/rzg2l-cpg.c

328

val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);

drivers/clk/renesas/rzg2l-cpg.c

50

#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), val))

drivers/clk/renesas/rzg2l-cpg.c

51

#define MDIV(val) FIELD_GET(GENMASK(15, 6), val)

drivers/clk/renesas/rzg2l-cpg.c

52

#define PDIV(val) FIELD_GET(GENMASK(5, 0), val)

drivers/clk/renesas/rzg2l-cpg.c

53

#define SDIV(val) FIELD_GET(GENMASK(2, 0), val)

drivers/clk/renesas/rzg2l-cpg.c

530

val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);

drivers/clk/renesas/rzg2l-cpg.c

55

#define RZG3S_DIV_P GENMASK(28, 26)

drivers/clk/renesas/rzg2l-cpg.c

56

#define RZG3S_DIV_M GENMASK(25, 22)

drivers/clk/renesas/rzg2l-cpg.c

57

#define RZG3S_DIV_NI GENMASK(21, 13)

drivers/clk/renesas/rzg2l-cpg.c

58

#define RZG3S_DIV_NF GENMASK(12, 1)

drivers/clk/renesas/rzg2l-cpg.c

75

#define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf))

drivers/clk/renesas/rzg2l-cpg.c

76

#define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf))

drivers/clk/renesas/rzv2h-cpg.c

60

#define CPG_PLL_CLK1_KDIV GENMASK(31, 16)

drivers/clk/renesas/rzv2h-cpg.c

61

#define CPG_PLL_CLK1_MDIV GENMASK(15, 6)

drivers/clk/renesas/rzv2h-cpg.c

62

#define CPG_PLL_CLK1_PDIV GENMASK(5, 0)

drivers/clk/renesas/rzv2h-cpg.c

64

#define CPG_PLL_CLK2_SDIV GENMASK(2, 0)

drivers/clk/renesas/rzv2h-cpg.h

159

#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)

drivers/clk/renesas/rzv2h-cpg.h

160

#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)

drivers/clk/renesas/rzv2h-cpg.h

163

#define BUS_MSTOP_NONE GENMASK(31, 0)

drivers/clk/rockchip/clk-ddr.c

79

val &= GENMASK(ddrclk->mux_width - 1, 0);

drivers/clk/rockchip/clk-muxgrf.c

24

unsigned int mask = GENMASK(mux->width - 1, 0);

drivers/clk/rockchip/clk-muxgrf.c

38

unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);

drivers/clk/samsung/clk-cpu.c

116

#define DIV_MASK GENMASK(2, 0)

drivers/clk/samsung/clk-cpu.c

117

#define DIV_MASK_ALL GENMASK(31, 0)

drivers/clk/samsung/clk-cpu.c

118

#define MUX_MASK GENMASK(2, 0)

drivers/clk/samsung/clk-cpu.c

179

#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)

drivers/clk/samsung/clk-cpu.c

180

#define E4210_DIV1_HPM_MASK GENMASK(6, 4)

drivers/clk/samsung/clk-cpu.c

181

#define E4210_DIV1_COPY_MASK GENMASK(2, 0)

drivers/clk/samsung/clk-cpu.c

408

#define E850_DIV_RATIO_MASK GENMASK(3, 0)

drivers/clk/samsung/clk.c

263

#define ACG_MSK GENMASK(6, 4)

drivers/clk/samsung/clk.c

264

#define CLK_IDLE GENMASK(5, 4)

drivers/clk/samsung/clk.c

492

#define DRCG_EN_MSK GENMASK(31, 0)

drivers/clk/socfpga/clk-gate-a10.c

31

val &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-gate-s10.c

31

val &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-gate-s10.c

44

val &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-gate.c

98

val &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-periph-a10.c

30

div &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-periph-s10.c

41

val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);

drivers/clk/socfpga/clk-periph.c

28

val &= GENMASK(socfpgaclk->width - 1, 0);

drivers/clk/socfpga/clk-pll-s10.c

30

#define SOCFPGA_N5X_PLLDIV_FDIV_MASK GENMASK(16, 8)

drivers/clk/socfpga/clk-pll-s10.c

32

#define SOCFPGA_N5X_PLLDIV_RDIV_MASK GENMASK(5, 0)

drivers/clk/socfpga/clk-pll-s10.c

33

#define SOCFPGA_N5X_PLLDIV_QDIV_MASK GENMASK(26, 24)

drivers/clk/sophgo/clk-cv1800.c

1211

val |= GENMASK(12, 9);

drivers/clk/sophgo/clk-cv18xx-common.h

61

GENMASK((_reg)->shift + (_reg)->width - 1, (_reg)->shift)

drivers/clk/sophgo/clk-cv18xx-common.h

63

(((_val) >> (_reg)->shift) & GENMASK((_reg)->width - 1, 0))

drivers/clk/sophgo/clk-cv18xx-common.h

66

(((_new) & GENMASK((_reg)->width - 1, 0)) << (_reg)->shift))

drivers/clk/sophgo/clk-cv18xx-pll.h

34

#define _PLL_PRE_DIV_SEL_FIELD GENMASK(6, 0)

drivers/clk/sophgo/clk-cv18xx-pll.h

35

#define _PLL_POST_DIV_SEL_FIELD GENMASK(14, 8)

drivers/clk/sophgo/clk-cv18xx-pll.h

36

#define _PLL_SEL_MODE_FIELD GENMASK(16, 15)

drivers/clk/sophgo/clk-cv18xx-pll.h

37

#define _PLL_DIV_SEL_FIELD GENMASK(23, 17)

drivers/clk/sophgo/clk-cv18xx-pll.h

38

#define _PLL_ICTRL_FIELD GENMASK(26, 24)

drivers/clk/sophgo/clk-sg2042-pll.c

84

#define PLLCTRL_FBDIV_MASK GENMASK(27, 16)

drivers/clk/sophgo/clk-sg2042-pll.c

85

#define PLLCTRL_POSTDIV2_MASK GENMASK(14, 12)

drivers/clk/sophgo/clk-sg2042-pll.c

86

#define PLLCTRL_POSTDIV1_MASK GENMASK(10, 8)

drivers/clk/sophgo/clk-sg2042-pll.c

87

#define PLLCTRL_REFDIV_MASK GENMASK(5, 0)

drivers/clk/sophgo/clk-sg2044-pll.c

25

#define PLL_VCOSEL_MASK GENMASK(17, 16)

drivers/clk/sophgo/clk-sg2044-pll.c

28

#define PLL_FBDIV_MASK GENMASK(11, 0)

drivers/clk/sophgo/clk-sg2044-pll.c

29

#define PLL_REFDIV_MASK GENMASK(17, 12)

drivers/clk/sophgo/clk-sg2044-pll.c

30

#define PLL_POSTDIV1_MASK GENMASK(20, 18)

drivers/clk/sophgo/clk-sg2044-pll.c

31

#define PLL_POSTDIV2_MASK GENMASK(23, 21)

drivers/clk/sophgo/clk-sg2044-pll.c

34

#define PLL_CALIBRATE_MASK GENMASK(29, 27)

drivers/clk/spacemit/ccu_ddn.h

34

.num_mask = GENMASK(_num_shift + _num_width - 1, _num_shift), \

drivers/clk/spacemit/ccu_ddn.h

36

.den_mask = GENMASK(_den_shift + _den_width - 1, _den_shift), \

drivers/clk/spacemit/ccu_mix.c

168

mask = GENMASK(div->width + div->shift - 1, div->shift);

drivers/clk/spacemit/ccu_mix.c

193

mask = GENMASK(mux->width + mux->shift - 1, mux->shift);

drivers/clk/spacemit/ccu_pll.c

18

#define PLL_SWCR3_MASK GENMASK(30, 0)

drivers/clk/spacemit/ccu_pll.c

21

#define PLLA_SWCR2_MASK GENMASK(15, 8)

drivers/clk/sprd/div.c

56

reg &= ~GENMASK(div->width + div->shift - 1, div->shift);

drivers/clk/sprd/mux.c

56

reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);

drivers/clk/sprd/pll.c

29

GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \

drivers/clk/starfive/clk-starfive-jh7110-pll.c

42

#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)

drivers/clk/starfive/clk-starfive-jh7110-pll.c

53

#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)

drivers/clk/starfive/clk-starfive-jh7110-pll.c

64

#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)

drivers/clk/starfive/clk-starfive-jh7110-pll.c

69

#define JH7110_PLL_FRAC_MASK GENMASK(23, 0)

drivers/clk/starfive/clk-starfive-jh7110-pll.c

71

#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)

drivers/clk/starfive/clk-starfive-jh7110-pll.c

73

#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)

drivers/clk/starfive/clk-starfive-jh71x0.h

13

#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)

drivers/clk/starfive/clk-starfive-jh71x0.h

15

#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)

drivers/clk/starfive/clk-starfive-jh71x0.h

16

#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)

drivers/clk/starfive/clk-starfive-jh71x0.h

18

#define JH71X0_CLK_INT_MASK GENMASK(7, 0)

drivers/clk/stm32/clk-stm32mp1.c

25

#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)

drivers/clk/stm32/clk-stm32mp13.c

16

#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)

drivers/clk/stm32/clk-stm32mp21.c

35

#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4)

drivers/clk/stm32/clk-stm32mp21.c

38

#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4)

drivers/clk/stm32/clk-stm32mp25.c

32

#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4)

drivers/clk/stm32/clk-stm32mp25.c

35

#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4)

drivers/clk/stm32/stm32mp13_rcc.h

1672

#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20)

drivers/clk/stm32/stm32mp13_rcc.h

1716

#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7)

drivers/clk/stm32/stm32mp13_rcc.h

1717

#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27)

drivers/clk/stm32/stm32mp13_rcc.h

1734

#define RCC_VERR_MINREV_MASK GENMASK(3, 0)

drivers/clk/stm32/stm32mp13_rcc.h

1735

#define RCC_VERR_MAJREV_MASK GENMASK(7, 4)

drivers/clk/stm32/stm32mp13_rcc.h

1740

#define RCC_IDR_ID_MASK GENMASK(31, 0)

drivers/clk/stm32/stm32mp13_rcc.h

1744

#define RCC_SIDR_SID_MASK GENMASK(31, 0)

drivers/clk/stm32/stm32mp13_rcc.h

245

#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

249

#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

253

#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)

drivers/clk/stm32/stm32mp13_rcc.h

343

#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)

drivers/clk/stm32/stm32mp13_rcc.h

346

#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)

drivers/clk/stm32/stm32mp13_rcc.h

355

#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16)

drivers/clk/stm32/stm32mp13_rcc.h

356

#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24)

drivers/clk/stm32/stm32mp13_rcc.h

357

#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27)

drivers/clk/stm32/stm32mp13_rcc.h

392

#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

393

#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

394

#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16)

drivers/clk/stm32/stm32mp13_rcc.h

400

#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)

drivers/clk/stm32/stm32mp13_rcc.h

401

#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)

drivers/clk/stm32/stm32mp13_rcc.h

406

#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

407

#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4)

drivers/clk/stm32/stm32mp13_rcc.h

413

#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

414

#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4)

drivers/clk/stm32/stm32mp13_rcc.h

420

#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

427

#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

432

#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

437

#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

450

#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0)

drivers/clk/stm32/stm32mp13_rcc.h

451

#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16)

drivers/clk/stm32/stm32mp13_rcc.h

456

#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0)

drivers/clk/stm32/stm32mp13_rcc.h

457

#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

458

#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16)

drivers/clk/stm32/stm32mp13_rcc.h

464

#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3)

drivers/clk/stm32/stm32mp13_rcc.h

469

#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0)

drivers/clk/stm32/stm32mp13_rcc.h

473

#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16)

drivers/clk/stm32/stm32mp13_rcc.h

486

#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0)

drivers/clk/stm32/stm32mp13_rcc.h

487

#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16)

drivers/clk/stm32/stm32mp13_rcc.h

492

#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0)

drivers/clk/stm32/stm32mp13_rcc.h

493

#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

494

#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16)

drivers/clk/stm32/stm32mp13_rcc.h

500

#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3)

drivers/clk/stm32/stm32mp13_rcc.h

505

#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0)

drivers/clk/stm32/stm32mp13_rcc.h

509

#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16)

drivers/clk/stm32/stm32mp13_rcc.h

522

#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0)

drivers/clk/stm32/stm32mp13_rcc.h

523

#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16)

drivers/clk/stm32/stm32mp13_rcc.h

524

#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24)

drivers/clk/stm32/stm32mp13_rcc.h

530

#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0)

drivers/clk/stm32/stm32mp13_rcc.h

531

#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

532

#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16)

drivers/clk/stm32/stm32mp13_rcc.h

538

#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3)

drivers/clk/stm32/stm32mp13_rcc.h

543

#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0)

drivers/clk/stm32/stm32mp13_rcc.h

547

#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16)

drivers/clk/stm32/stm32mp13_rcc.h

560

#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0)

drivers/clk/stm32/stm32mp13_rcc.h

561

#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16)

drivers/clk/stm32/stm32mp13_rcc.h

562

#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24)

drivers/clk/stm32/stm32mp13_rcc.h

568

#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0)

drivers/clk/stm32/stm32mp13_rcc.h

569

#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8)

drivers/clk/stm32/stm32mp13_rcc.h

570

#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16)

drivers/clk/stm32/stm32mp13_rcc.h

576

#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3)

drivers/clk/stm32/stm32mp13_rcc.h

581

#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0)

drivers/clk/stm32/stm32mp13_rcc.h

585

#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16)

drivers/clk/stm32/stm32mp13_rcc.h

590

#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

595

#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

600

#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

605

#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

609

#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0)

drivers/clk/stm32/stm32mp13_rcc.h

613

#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0)

drivers/clk/stm32/stm32mp13_rcc.h

618

#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

623

#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0)

drivers/clk/stm32/stm32mp13_rcc.h

628

#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

633

#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

638

#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

643

#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

648

#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

653

#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

679

#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11)

drivers/clk/stm32/stm32mp13_rcc.h

686

#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)

drivers/clk/stm32/stm32mp13_rcc.h

689

#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25)

drivers/clk/stm32/stm32mp13_rcc.h

690

#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28)

drivers/clk/stm32/stm32mp13_rcc.h

697

#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

701

#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

702

#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3)

drivers/clk/stm32/stm32mp13_rcc.h

703

#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6)

drivers/clk/stm32/stm32mp13_rcc.h

709

#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

713

#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

717

#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

718

#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3)

drivers/clk/stm32/stm32mp13_rcc.h

723

#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

724

#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3)

drivers/clk/stm32/stm32mp13_rcc.h

729

#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

733

#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

737

#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

741

#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

745

#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

749

#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

750

#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3)

drivers/clk/stm32/stm32mp13_rcc.h

755

#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

759

#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

763

#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

767

#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

771

#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

775

#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

776

#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2)

drivers/clk/stm32/stm32mp13_rcc.h

781

#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0)

drivers/clk/stm32/stm32mp13_rcc.h

782

#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3)

drivers/clk/stm32/stm32mp13_rcc.h

787

#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

788

#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4)

drivers/clk/stm32/stm32mp13_rcc.h

789

#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8)

drivers/clk/stm32/stm32mp13_rcc.h

790

#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12)

drivers/clk/stm32/stm32mp13_rcc.h

797

#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

802

#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

806

#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

810

#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

814

#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

818

#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0)

drivers/clk/stm32/stm32mp13_rcc.h

822

#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0)

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

1364

val &= ~GENMASK(1, 0);

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

1385

val &= ~GENMASK(9, 8);

drivers/clk/sunxi-ng/ccu-sun4i-a10.c

1451

val &= ~GENMASK(25, 16);

drivers/clk/sunxi-ng/ccu-sun4i-a10.c

1454

val &= ~GENMASK(29, 26);

drivers/clk/sunxi-ng/ccu-sun4i-a10.c

1467

val &= ~GENMASK(7, 6);

drivers/clk/sunxi-ng/ccu-sun50i-a100.c

1245

val &= ~GENMASK(25, 24);

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

957

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

1206

val &= ~(GENMASK(15, 8) | BIT(0));

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

1212

val &= ~GENMASK(3, 0);

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

1241

val &= ~GENMASK(25, 24);

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

1250

val &= ~(GENMASK(21, 16) | BIT(0));

drivers/clk/sunxi-ng/ccu-sun50i-h616.c

1203

val &= ~GENMASK(25, 24);

drivers/clk/sunxi-ng/ccu-sun50i-h616.c

1221

val &= ~GENMASK(1, 0);

drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c

440

val &= ~(GENMASK(22, 20) | GENMASK(18, 16));

drivers/clk/sunxi-ng/ccu-sun5i.c

1001

val &= ~GENMASK(29, 26);

drivers/clk/sunxi-ng/ccu-sun5i.c

1012

val &= ~GENMASK(7, 6);

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

1242

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

1253

val &= ~GENMASK(7, 6);

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

1256

val &= ~GENMASK(13, 12);

drivers/clk/sunxi-ng/ccu-sun6i-rtc.c

34

#define IOSC_32K_CLK_DIV GENMASK(4, 0)

drivers/clk/sunxi-ng/ccu-sun8i-a23.c

739

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun8i-a33.c

800

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

878

val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

1057

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

1322

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

1332

val &= ~GENMASK(25, 20);

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

755

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

764

val &= ~GENMASK(de_clk.mux.shift + de_clk.mux.width - 1,

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

769

val &= ~GENMASK(tcon_clk.mux.shift + tcon_clk.mux.width - 1,

drivers/clk/sunxi-ng/ccu-sun9i-a80.c

1204

val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1,

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c

547

val &= ~GENMASK(19, 16);

drivers/clk/sunxi-ng/ccu_div.c

107

reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);

drivers/clk/sunxi-ng/ccu_mp.c

239

reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);

drivers/clk/sunxi-ng/ccu_mp.c

240

reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);

drivers/clk/sunxi-ng/ccu_mult.c

135

reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);

drivers/clk/sunxi-ng/ccu_mux.c

214

reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);

drivers/clk/sunxi-ng/ccu_nk.c

138

reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);

drivers/clk/sunxi-ng/ccu_nk.c

139

reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);

drivers/clk/sunxi-ng/ccu_nkm.c

229

reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift);

drivers/clk/sunxi-ng/ccu_nkm.c

230

reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);

drivers/clk/sunxi-ng/ccu_nkm.c

231

reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);

drivers/clk/sunxi-ng/ccu_nkmp.c

194

n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,

drivers/clk/sunxi-ng/ccu_nkmp.c

197

k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1,

drivers/clk/sunxi-ng/ccu_nkmp.c

200

m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1,

drivers/clk/sunxi-ng/ccu_nkmp.c

203

p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1,

drivers/clk/sunxi-ng/ccu_nm.c

185

reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);

drivers/clk/sunxi-ng/ccu_nm.c

217

reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);

drivers/clk/sunxi-ng/ccu_nm.c

218

reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);

drivers/clk/sunxi-ng/ccu_phase.c

112

reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);

drivers/clk/sunxi/clk-a10-pll2.c

22

#define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)

drivers/clk/sunxi/clk-a10-pll2.c

26

#define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)

drivers/clk/sunxi/clk-a10-pll2.c

30

#define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)

drivers/clk/sunxi/clk-mod0.c

268

value &= ~GENMASK(phase->offset + 3, phase->offset);

drivers/clk/sunxi/clk-sun6i-ar100.c

64

.muxmask = GENMASK(1, 0),

drivers/clk/sunxi/clk-sun9i-cpus.c

25

#define SUN9I_CPUS_MUX_MASK GENMASK(17, 16)

drivers/clk/sunxi/clk-sun9i-cpus.c

30

#define SUN9I_CPUS_DIV_MASK GENMASK(5, 4)

drivers/clk/sunxi/clk-sun9i-cpus.c

36

#define SUN9I_CPUS_PLL4_DIV_MASK GENMASK(12, 8)

drivers/clk/tegra/clk-sdmmc-mux.c

20

#define DIV_MASK GENMASK(7, 0)

drivers/clk/tegra/clk-sdmmc-mux.c

22

#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)

drivers/clk/tegra/clk-tegra20-emc.c

23

#define CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK GENMASK(7, 0)

drivers/clk/tegra/clk-tegra20-emc.c

24

#define CLK_SOURCE_EMC_2X_CLK_SRC_MASK GENMASK(31, 30)

drivers/clk/tegra/clk-tegra210-emc.c

18

#define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29)

drivers/clk/tegra/clk-tegra210-emc.c

20

#define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0)

drivers/clk/tegra/clk-tegra210.c

2917

reg &= ~GENMASK(20, 0);

drivers/clk/tegra/clk-tegra210.c

3669

writel(GENMASK(26, 21) | BIT(7),

drivers/clk/tegra/clk-tegra210.c

3689

writel(GENMASK(26, 22) | BIT(7),

drivers/clk/tegra/clk-tegra210.c

692

writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),

drivers/clk/thead/clk-th1520-ap.c

112

.mask = GENMASK(_width - 1, 0), \

drivers/clk/thead/clk-th1520-ap.c

166

parent &= GENMASK(mux->width - 1, 0);

drivers/clk/thead/clk-th1520-ap.c

176

GENMASK(mux->width - 1, 0) << mux->shift,

drivers/clk/thead/clk-th1520-ap.c

21

#define TH1520_PLL_POSTDIV2 GENMASK(26, 24)

drivers/clk/thead/clk-th1520-ap.c

22

#define TH1520_PLL_POSTDIV1 GENMASK(22, 20)

drivers/clk/thead/clk-th1520-ap.c

221

val &= GENMASK(cd->div.width - 1, 0);

drivers/clk/thead/clk-th1520-ap.c

23

#define TH1520_PLL_FBDIV GENMASK(19, 8)

drivers/clk/thead/clk-th1520-ap.c

24

#define TH1520_PLL_REFDIV GENMASK(5, 0)

drivers/clk/thead/clk-th1520-ap.c

240

val &= GENMASK(cd->div.width - 1, 0);

drivers/clk/thead/clk-th1520-ap.c

258

curr_val &= GENMASK(cd->div.width - 1, 0);

drivers/clk/thead/clk-th1520-ap.c

267

reg_val &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);

drivers/clk/thead/clk-th1520-ap.c

29

#define TH1520_PLL_FRAC GENMASK(23, 0)

drivers/clk/ti/clock.h

80

#define CLKF_SOC_MASK GENMASK(11, 8)

drivers/clk/visconti/pll.c

40

#define PLL_INTIN_MASK GENMASK(11, 0)

drivers/clk/visconti/pll.c

41

#define PLL_FRACIN_MASK GENMASK(23, 0)

drivers/clk/visconti/pll.c

42

#define PLL_REFDIV_MASK GENMASK(5, 0)

drivers/clk/visconti/pll.c

43

#define PLL_POSTDIV_MASK GENMASK(2, 0)

drivers/clk/x86/clk-cgu.h

303

u32 mask = (GENMASK(width - 1, 0) << shift);

drivers/clk/x86/clk-cgu.h

311

u32 mask = (GENMASK(width - 1, 0) << shift);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

55

#define WZRD_CLKFBOUT_MULT_FRAC_MASK GENMASK(25, 16)

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

56

#define WZRD_CLKFBOUT_O_MASK GENMASK(7, 0)

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

59

#define WZRD_CLKFBOUT_L_MASK GENMASK(7, 0)

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

60

#define WZRD_CLKFBOUT_H_MASK GENMASK(15, 8)

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

63

#define WZRD_VERSAL_FRAC_MASK GENMASK(5, 0)

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

71

#define WZRD_CLKOUT0_FRAC_MASK GENMASK(17, 8)

drivers/clk/xilinx/xlnx_vcu.c

30

#define VCU_PLL_CTRL_FBDIV GENMASK(14, 8)

drivers/clk/xilinx/xlnx_vcu.c

31

#define VCU_PLL_CTRL_CLKOUTDIV GENMASK(18, 16)

drivers/clk/xilinx/xlnx_vcu.c

34

#define VCU_PLL_CFG_RES GENMASK(3, 0)

drivers/clk/xilinx/xlnx_vcu.c

35

#define VCU_PLL_CFG_CP GENMASK(8, 5)

drivers/clk/xilinx/xlnx_vcu.c

36

#define VCU_PLL_CFG_LFHF GENMASK(12, 10)

drivers/clk/xilinx/xlnx_vcu.c

37

#define VCU_PLL_CFG_LOCK_CNT GENMASK(22, 13)

drivers/clk/xilinx/xlnx_vcu.c

38

#define VCU_PLL_CFG_LOCK_DLY GENMASK(31, 25)

drivers/clk/zynqmp/clkc.c

105

#define CLK_ATTR_NODE_INDEX GENMASK(13, 0)

drivers/clk/zynqmp/clkc.c

106

#define CLK_ATTR_NODE_TYPE GENMASK(19, 14)

drivers/clk/zynqmp/clkc.c

107

#define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20)

drivers/clk/zynqmp/clkc.c

108

#define CLK_ATTR_NODE_CLASS GENMASK(31, 26)

drivers/clk/zynqmp/clkc.c

87

#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)

drivers/clk/zynqmp/clkc.c

88

#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)

drivers/clk/zynqmp/clkc.c

89

#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)

drivers/clk/zynqmp/clkc.c

90

#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)

drivers/clk/zynqmp/clkc.c

97

#define CLK_PARENTS_ID GENMASK(15, 0)

drivers/clk/zynqmp/clkc.c

98

#define CLK_PARENTS_FLAGS GENMASK(31, 16)

drivers/clocksource/arm_arch_timer.c

292

} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \

drivers/clocksource/arm_global_timer.c

35

#define GT_CONTROL_PRESCALER_MASK GENMASK(15, 8)

drivers/clocksource/ingenic-timer.c

297

tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,

drivers/clocksource/timer-atmel-pit.c

25

#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */

drivers/clocksource/timer-atmel-pit.c

32

#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */

drivers/clocksource/timer-atmel-pit.c

33

#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */

drivers/clocksource/timer-davinci.c

29

#define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)

drivers/clocksource/timer-davinci.c

30

#define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)

drivers/clocksource/timer-davinci.c

32

#define DAVINCI_TIMER_UNRESET GENMASK(1, 0)

drivers/clocksource/timer-davinci.c

34

#define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)

drivers/clocksource/timer-econet-en751221.c

21

#define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0)

drivers/clocksource/timer-imx-tpm.c

179

GENMASK(counter_width - 1,

drivers/clocksource/timer-imx-tpm.c

238

writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);

drivers/clocksource/timer-loongson1-pwm.c

226

0x1, GENMASK(CNTR_WIDTH - 1, 0));

drivers/clocksource/timer-mediatek-cpux.c

31

#define CPUX_CLK_DIV_MASK GENMASK(10, 8)

drivers/clocksource/timer-meson6.c

35

#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8)

drivers/clocksource/timer-meson6.c

41

#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6)

drivers/clocksource/timer-meson6.c

42

#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4)

drivers/clocksource/timer-meson6.c

43

#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2)

drivers/clocksource/timer-meson6.c

44

#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)

drivers/clocksource/timer-microchip-pit64b.c

27

#define MCHP_PIT64B_MR_PRES GENMASK(11, 8)

drivers/clocksource/timer-npcm7xx.c

35

#define NPCM7XX_Tx_OPER GENMASK(28, 27)

drivers/clocksource/timer-nxp-stm.c

30

#define STM_CR_CPS_MASK GENMASK(15, STM_CR_CPS_OFFSET)

drivers/clocksource/timer-rtl-otto.c

41

#define RTTM_MAX_DIVISOR GENMASK(15, 0)

drivers/clocksource/timer-sprd.c

32

#define TIMER_VALUE_LO_MASK GENMASK(31, 0)

drivers/clocksource/timer-sprd.c

33

#define TIMER_VALUE_HI_MASK GENMASK(31, 0)

drivers/clocksource/timer-tegra186.c

33

#define TMRSR_PCV GENMASK(28, 0)

drivers/clocksource/timer-tegra186.c

51

#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12)

drivers/comedi/drivers/plx9080.h

103

#define PLX_MARBR_PRIO_MASK GENMASK(20, 19)

drivers/comedi/drivers/plx9080.h

169

#define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0)

drivers/comedi/drivers/plx9080.h

172

#define PLX_LBRD_MSIWS_MASK GENMASK(5, 2)

drivers/comedi/drivers/plx9080.h

190

#define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)

drivers/comedi/drivers/plx9080.h

197

#define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16)

drivers/comedi/drivers/plx9080.h

200

#define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18)

drivers/comedi/drivers/plx9080.h

216

#define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28)

drivers/comedi/drivers/plx9080.h

249

(GENMASK(8, 5) & (v))) >> 5)

drivers/comedi/drivers/plx9080.h

250

#define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5))

drivers/comedi/drivers/plx9080.h

262

#define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14)

drivers/comedi/drivers/plx9080.h

264

#define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16)

drivers/comedi/drivers/plx9080.h

272

#define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0)

drivers/comedi/drivers/plx9080.h

275

#define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2)

drivers/comedi/drivers/plx9080.h

279

#define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8)

drivers/comedi/drivers/plx9080.h

283

#define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)

drivers/comedi/drivers/plx9080.h

287

#define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16)

drivers/comedi/drivers/plx9080.h

398

#define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0)

drivers/comedi/drivers/plx9080.h

403

#define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4)

drivers/comedi/drivers/plx9080.h

408

#define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8)

drivers/comedi/drivers/plx9080.h

413

#define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12)

drivers/comedi/drivers/plx9080.h

465

#define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0)

drivers/comedi/drivers/plx9080.h

468

#define PLX_DMAMODE_IWS_MASK GENMASK(5, 2)

drivers/comedi/drivers/plx9080.h

524

#define PLX_DMADPR_NEXT_MASK GENMASK(31, 4)

drivers/comedi/drivers/plx9080.h

555

#define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0)

drivers/comedi/drivers/plx9080.h

559

#define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4)

drivers/comedi/drivers/plx9080.h

563

#define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)

drivers/comedi/drivers/plx9080.h

567

#define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12)

drivers/comedi/drivers/plx9080.h

571

#define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16)

drivers/comedi/drivers/plx9080.h

575

#define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20)

drivers/comedi/drivers/plx9080.h

579

#define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24)

drivers/comedi/drivers/plx9080.h

583

#define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28)

drivers/comedi/drivers/plx9080.h

62

#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */

drivers/comedi/drivers/plx9080.h

65

#define PLX_LASRR_MEM_MASK GENMASK(31, 4)

drivers/comedi/drivers/plx9080.h

67

#define PLX_LASRR_IO_MASK GENMASK(31, 2)

drivers/comedi/drivers/plx9080.h

76

#define PLX_LASBA_MEM_MASK GENMASK(31, 4)

drivers/comedi/drivers/plx9080.h

78

#define PLX_LASBA_IO_MASK GENMASK(31, 2)

drivers/comedi/drivers/plx9080.h

87

#define PLX_MARBR_LT_MASK GENMASK(7, 0)

drivers/comedi/drivers/plx9080.h

91

#define PLX_MARBR_PT_MASK GENMASK(15, 8)

drivers/counter/104-quad-8.c

101

#define REGISTER_SELECTION GENMASK(6, 5)

drivers/counter/104-quad-8.c

115

#define RESETS GENMASK(2, 1)

drivers/counter/104-quad-8.c

116

#define LOADS GENMASK(4, 3)

drivers/counter/104-quad-8.c

1338

ret = regmap_write(priv->map, QUAD8_CABLE_STATUS, GENMASK(7, 0));

drivers/counter/104-quad-8.c

134

#define COUNT_MODE GENMASK(2, 1)

drivers/counter/104-quad-8.c

135

#define QUADRATURE_MODE GENMASK(4, 3)

drivers/counter/104-quad-8.c

160

#define FLG_PINS GENMASK(4, 3)

drivers/counter/104-quad-8.c

205

#define LS7267_CNTR_MAX GENMASK(23, 0)

drivers/counter/i8254.c

23

#define I8254_SC GENMASK(7, 6)

drivers/counter/i8254.c

24

#define I8254_RW GENMASK(5, 4)

drivers/counter/i8254.c

25

#define I8254_M GENMASK(3, 1)

drivers/counter/intel-qep.c

39

#define INTEL_QEPCON_INDX_GATING_MASK GENMASK(10, 9)

drivers/counter/intel-qep.c

46

#define INTEL_QEPCON_FIFO_THRE_MASK GENMASK(14, 12)

drivers/counter/intel-qep.c

61

#define INTEL_QEPINT_MASK_ALL GENMASK(5, 0)

drivers/counter/stm32-timer-cnt.c

621

u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */

drivers/counter/ti-ecap-capture.c

43

#define ECAP_EV_MODE_MASK GENMASK(7, 0)

drivers/counter/ti-ecap-capture.c

46

#define ECAP_STOPVALUE_MASK GENMASK(18, 17)

drivers/counter/ti-ecap-capture.c

48

#define ECAP_SYNCO_DIS_MASK GENMASK(23, 22)

drivers/counter/ti-ecap-capture.c

56

#define ECAP_EVT_EN_MASK GENMASK(ECAP_NB_EVT, ECAP_NB_CEVT)

drivers/counter/ti-ecap-capture.c

62

#define ECAP_EVT_CLR_MASK GENMASK(ECAP_NB_EVT, 0)

drivers/counter/ti-eqep.c

49

#define QDECCTL_QSRC GENMASK(15, 14)

drivers/counter/ti-eqep.c

60

#define QEPCTL_FREE_SOFT GENMASK(15, 14)

drivers/counter/ti-eqep.c

61

#define QEPCTL_PCRM GENMASK(13, 12)

drivers/counter/ti-eqep.c

62

#define QEPCTL_SEI GENMASK(11, 10)

drivers/counter/ti-eqep.c

63

#define QEPCTL_IEI GENMASK(9, 8)

drivers/counter/ti-eqep.c

66

#define QEPCTL_IEL GENMASK(5, 4)

drivers/cpufreq/apple-soc-cpufreq.c

28

#define APPLE_DVFS_CMD_PS1_S5L8960X GENMASK(24, 22)

drivers/cpufreq/apple-soc-cpufreq.c

30

#define APPLE_DVFS_CMD_PS2 GENMASK(15, 12)

drivers/cpufreq/apple-soc-cpufreq.c

31

#define APPLE_DVFS_CMD_PS1 GENMASK(4, 0)

drivers/cpufreq/apple-soc-cpufreq.c

41

#define APPLE_DVFS_STATUS_CUR_PS_S5L8960X GENMASK(5, 3)

drivers/cpufreq/apple-soc-cpufreq.c

43

#define APPLE_DVFS_STATUS_TGT_PS_S5L8960X GENMASK(2, 0)

drivers/cpufreq/apple-soc-cpufreq.c

44

#define APPLE_DVFS_STATUS_CUR_PS_T8103 GENMASK(7, 4)

drivers/cpufreq/apple-soc-cpufreq.c

46

#define APPLE_DVFS_STATUS_TGT_PS_T8103 GENMASK(3, 0)

drivers/cpufreq/apple-soc-cpufreq.c

47

#define APPLE_DVFS_STATUS_CUR_PS_T8112 GENMASK(9, 5)

drivers/cpufreq/apple-soc-cpufreq.c

49

#define APPLE_DVFS_STATUS_TGT_PS_T8112 GENMASK(4, 0)

drivers/cpufreq/apple-soc-cpufreq.c

58

#define APPLE_DVFS_PLL_FACTOR_MULT GENMASK(31, 16)

drivers/cpufreq/apple-soc-cpufreq.c

59

#define APPLE_DVFS_PLL_FACTOR_DIV GENMASK(15, 0)

drivers/cpufreq/intel_pstate.c

3698

#define POWERSAVE_MASK GENMASK(7, 0)

drivers/cpufreq/intel_pstate.c

3699

#define BALANCE_POWER_MASK GENMASK(15, 8)

drivers/cpufreq/intel_pstate.c

3700

#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)

drivers/cpufreq/intel_pstate.c

3701

#define PERFORMANCE_MASK GENMASK(31, 24)

drivers/cpufreq/mediatek-cpufreq-hw.c

20

#define LUT_FREQ GENMASK(11, 0)

drivers/cpufreq/qcom-cpufreq-hw.c

23

#define LUT_SRC GENMASK(31, 30)

drivers/cpufreq/qcom-cpufreq-hw.c

24

#define LUT_L_VAL GENMASK(7, 0)

drivers/cpufreq/qcom-cpufreq-hw.c

25

#define LUT_CORE_COUNT GENMASK(18, 16)

drivers/cpufreq/qcom-cpufreq-hw.c

26

#define LUT_VOLT GENMASK(11, 0)

drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c

419

wb &= GENMASK((nbw * 8) - 1, 0);

drivers/crypto/atmel-sha-regs.h

24

#define SHA_MR_ALGO_MASK GENMASK(10, 8)

drivers/crypto/axis/artpec6_crypto.c

108

#define A6_CRY_MD_OPER GENMASK(19, 16)

drivers/crypto/axis/artpec6_crypto.c

110

#define A6_CRY_MD_HASH_SEL_CTX GENMASK(21, 20)

drivers/crypto/axis/artpec6_crypto.c

113

#define A6_CRY_MD_CIPHER_LEN GENMASK(21, 20)

drivers/crypto/axis/artpec6_crypto.c

118

#define A7_CRY_MD_OPER GENMASK(11, 8)

drivers/crypto/axis/artpec6_crypto.c

120

#define A7_CRY_MD_HASH_SEL_CTX GENMASK(13, 12)

drivers/crypto/axis/artpec6_crypto.c

123

#define A7_CRY_MD_CIPHER_LEN GENMASK(13, 12)

drivers/crypto/axis/artpec6_crypto.c

66

#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)

drivers/crypto/axis/artpec6_crypto.c

67

#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)

drivers/crypto/axis/artpec6_crypto.c

73

#define PDMA_OUT_DESCRQ_PUSH_LEN GENMASK(5, 0)

drivers/crypto/axis/artpec6_crypto.c

74

#define PDMA_OUT_DESCRQ_PUSH_ADDR GENMASK(31, 6)

drivers/crypto/axis/artpec6_crypto.c

76

#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)

drivers/crypto/axis/artpec6_crypto.c

77

#define PDMA_OUT_DESCRQ_STAT_SIZE GENMASK(7, 4)

drivers/crypto/axis/artpec6_crypto.c

81

#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)

drivers/crypto/axis/artpec6_crypto.c

82

#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)

drivers/crypto/axis/artpec6_crypto.c

83

#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE GENMASK(14, 10)

drivers/crypto/axis/artpec6_crypto.c

91

#define PDMA_IN_STATQ_PUSH_LEN GENMASK(5, 0)

drivers/crypto/axis/artpec6_crypto.c

92

#define PDMA_IN_STATQ_PUSH_ADDR GENMASK(31, 6)

drivers/crypto/axis/artpec6_crypto.c

94

#define PDMA_IN_DESCRQ_PUSH_LEN GENMASK(5, 0)

drivers/crypto/axis/artpec6_crypto.c

95

#define PDMA_IN_DESCRQ_PUSH_ADDR GENMASK(31, 6)

drivers/crypto/axis/artpec6_crypto.c

97

#define PDMA_IN_DESCRQ_STAT_LEVEL GENMASK(3, 0)

drivers/crypto/axis/artpec6_crypto.c

98

#define PDMA_IN_DESCRQ_STAT_SIZE GENMASK(7, 4)

drivers/crypto/caam/dpseci_cmd.h

48

GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \

drivers/crypto/caam/regs.h

323

#define CHA_VER_MISC_AES_NUM_MASK GENMASK(7, 0)

drivers/crypto/caam/regs.h

429

#define CSTA_MOO GENMASK(9, 8)

drivers/crypto/cavium/cpt/cptpf_main.c

184

mcode->core_mask = GENMASK(mcode->num_cores, 0);

drivers/crypto/cavium/cpt/cptpf_main.c

213

mcode->core_mask = GENMASK(mcode->num_cores, 0);

drivers/crypto/ccp/platform-access.c

22

#define DOORBELL_CMDRESP_STS GENMASK(7, 0)

drivers/crypto/ccp/psp-dev.c

27

#define PSP_C2PMSG_17_CMDRESP_CMD GENMASK(19, 16)

drivers/crypto/ccp/sev-dev.h

28

#define SEV_CMDRESP_CMD GENMASK(26, 16)

drivers/crypto/ccp/sp-pci.c

30

#define AA GENMASK(31, 24)

drivers/crypto/ccp/sp-pci.c

31

#define BB GENMASK(23, 16)

drivers/crypto/ccp/sp-pci.c

32

#define CC GENMASK(15, 8)

drivers/crypto/ccp/sp-pci.c

33

#define DD GENMASK(7, 0)

drivers/crypto/ccree/cc_hw_queue_defs.h

22

#define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))

drivers/crypto/ccree/cc_lli_defs.h

39

#define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET)

drivers/crypto/ccree/cc_lli_defs.h

40

#define LLI_HADDR_MASK GENMASK( \

drivers/crypto/gemini/sl3516-ce-core.c

470

v & GENMASK(31, 4),

drivers/crypto/gemini/sl3516-ce-core.c

471

v & GENMASK(3, 0));

drivers/crypto/gemini/sl3516-ce-core.c

474

v & GENMASK(15, 4),

drivers/crypto/gemini/sl3516-ce-core.c

475

v & GENMASK(3, 0));

drivers/crypto/hisilicon/debugfs.c

16

#define QM_XQC_ADDR_MASK GENMASK(31, 0)

drivers/crypto/hisilicon/debugfs.c

17

#define CURRENT_FUN_MASK GENMASK(5, 0)

drivers/crypto/hisilicon/debugfs.c

18

#define CURRENT_Q_MASK GENMASK(31, 16)

drivers/crypto/hisilicon/debugfs.c

19

#define QM_SQE_ADDR_MASK GENMASK(7, 0)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

280

#define HREE_HW_ERR_MASK GENMASK(10, 0)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

281

#define HREE_SQE_DONE_MASK GENMASK(1, 0)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

282

#define HREE_ALG_TYPE_MASK GENMASK(4, 0)

drivers/crypto/hisilicon/hpre/hpre_main.c

205

{HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37},

drivers/crypto/hisilicon/hpre/hpre_main.c

206

{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},

drivers/crypto/hisilicon/hpre/hpre_main.c

207

{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},

drivers/crypto/hisilicon/hpre/hpre_main.c

208

{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

drivers/crypto/hisilicon/hpre/hpre_main.c

209

{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E},

drivers/crypto/hisilicon/hpre/hpre_main.c

210

{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},

drivers/crypto/hisilicon/hpre/hpre_main.c

211

{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},

drivers/crypto/hisilicon/hpre/hpre_main.c

212

{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},

drivers/crypto/hisilicon/hpre/hpre_main.c

213

{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1},

drivers/crypto/hisilicon/hpre/hpre_main.c

214

{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},

drivers/crypto/hisilicon/hpre/hpre_main.c

215

{HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},

drivers/crypto/hisilicon/hpre/hpre_main.c

216

{HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},

drivers/crypto/hisilicon/hpre/hpre_main.c

217

{HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF},

drivers/crypto/hisilicon/hpre/hpre_main.c

218

{HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27},

drivers/crypto/hisilicon/hpre/hpre_main.c

219

{HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

220

{HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

221

{HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

222

{HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

223

{HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

224

{HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

225

{HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

226

{HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

227

{HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},

drivers/crypto/hisilicon/hpre/hpre_main.c

228

{HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10},

drivers/crypto/hisilicon/hpre/hpre_main.c

229

{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}

drivers/crypto/hisilicon/hpre/hpre_main.c

287

.int_msk = GENMASK(15, 10),

drivers/crypto/hisilicon/hpre/hpre_main.c

290

.int_msk = GENMASK(21, 16),

drivers/crypto/hisilicon/hpre/hpre_main.c

42

#define HPRE_AXI_ERROR_MASK GENMASK(21, 10)

drivers/crypto/hisilicon/hpre/hpre_main.c

73

#define HPRE_QM_USR_CFG_MASK GENMASK(31, 1)

drivers/crypto/hisilicon/hpre/hpre_main.c

74

#define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/hpre/hpre_main.c

75

#define HPRE_QM_VFG_AX_MASK GENMASK(7, 0)

drivers/crypto/hisilicon/hpre/hpre_main.c

76

#define HPRE_BD_USR_MASK GENMASK(1, 0)

drivers/crypto/hisilicon/qm.c

124

#define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)

drivers/crypto/hisilicon/qm.c

126

#define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)

drivers/crypto/hisilicon/qm.c

163

#define QM_PEH_MSI_FINISH_MASK GENMASK(19, 16)

drivers/crypto/hisilicon/qm.c

165

#define ACC_PEH_MSI_DISABLE GENMASK(31, 0)

drivers/crypto/hisilicon/qm.c

1654

if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))

drivers/crypto/hisilicon/qm.c

1756

if (!(val & GENMASK(vfs_num, 1))) {

drivers/crypto/hisilicon/qm.c

188

#define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)

drivers/crypto/hisilicon/qm.c

189

#define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)

drivers/crypto/hisilicon/qm.c

200

#define QM_IFC_CMD_MASK GENMASK(31, 0)

drivers/crypto/hisilicon/qm.c

213

#define QM_CAPBILITY_VERSION GENMASK(7, 0)

drivers/crypto/hisilicon/qm.c

231

#define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)

drivers/crypto/hisilicon/qm.c

232

#define QM_SHAPER_CIR_U_MASK GENMASK(10, 8)

drivers/crypto/hisilicon/qm.c

233

#define QM_SHAPER_CIR_S_MASK GENMASK(14, 11)

drivers/crypto/hisilicon/qm.c

26

#define QM_IRQ_VECTOR_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/qm.c

27

#define QM_IRQ_TYPE_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/qm.c

29

#define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)

drivers/crypto/hisilicon/qm.c

33

#define QM_MB_STATUS_MASK GENMASK(12, 9)

drivers/crypto/hisilicon/qm.c

358

{QM_TOTAL_QP_NUM_CAP, 0x100158, 0, GENMASK(10, 0), 0x1000, 0x400, 0x400},

drivers/crypto/hisilicon/qm.c

359

{QM_FUNC_MAX_QP_CAP, 0x100158, 11, GENMASK(10, 0), 0x1000, 0x400, 0x400},

drivers/crypto/hisilicon/qm.c

360

{QM_XEQ_DEPTH_CAP, 0x3104, 0, GENMASK(31, 0), 0x800, 0x4000800, 0x4000800},

drivers/crypto/hisilicon/qm.c

361

{QM_QP_DEPTH_CAP, 0x3108, 0, GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},

drivers/crypto/hisilicon/qm.c

362

{QM_EQ_IRQ_TYPE_CAP, 0x310c, 0, GENMASK(31, 0), 0x10000, 0x10000, 0x10000},

drivers/crypto/hisilicon/qm.c

363

{QM_AEQ_IRQ_TYPE_CAP, 0x3110, 0, GENMASK(31, 0), 0x0, 0x10001, 0x10001},

drivers/crypto/hisilicon/qm.c

364

{QM_ABN_IRQ_TYPE_CAP, 0x3114, 0, GENMASK(31, 0), 0x0, 0x10003, 0x10003},

drivers/crypto/hisilicon/qm.c

365

{QM_PF2VF_IRQ_TYPE_CAP, 0x3118, 0, GENMASK(31, 0), 0x0, 0x0, 0x10002},

drivers/crypto/hisilicon/qm.c

366

{QM_PF_IRQ_NUM_CAP, 0x311c, 16, GENMASK(15, 0), 0x1, 0x4, 0x4},

drivers/crypto/hisilicon/qm.c

367

{QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3},

drivers/crypto/hisilicon/qm.c

49

#define QM_SQ_TYPE_MASK GENMASK(3, 0)

drivers/crypto/hisilicon/qm.c

71

#define QM_EQE_CQN_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/qm.c

76

#define QM_AEQE_CQN_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/qm.c

82

#define QM_XQ_DEPTH_MASK GENMASK(15, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

136

#define SEC_Q_DEPTH_CFG_DEPTH_M GENMASK(11, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

206

#define SEC_DEBUG_BD_INFO_SOFT_ERR_CHECK_M GENMASK(22, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

208

#define SEC_DEBUG_BD_INFO_HARD_ERR_CHECK_M GENMASK(9, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

211

#define SEC_DEBUG_BD_INFO_GET_ID_M GENMASK(19, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

218

#define SEC_OUT_BD_INFO_Q_ID_M GENMASK(11, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

90

#define SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M GENMASK(3, 0)

drivers/crypto/hisilicon/sec/sec_drv.c

92

#define SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_M GENMASK(6, 4)

drivers/crypto/hisilicon/sec/sec_drv.c

940

writel_relaxed(GENMASK(info->num_saas - 1, 0),

drivers/crypto/hisilicon/sec/sec_drv.h

107

#define SEC_BD_W2_C_GRAN_SIZE_15_0_M GENMASK(15, 0)

drivers/crypto/hisilicon/sec/sec_drv.h

109

#define SEC_BD_W2_GRAN_NUM_M GENMASK(31, 16)

drivers/crypto/hisilicon/sec/sec_drv.h

113

#define SEC_BD_W3_AUTH_LEN_OFFSET_M GENMASK(9, 0)

drivers/crypto/hisilicon/sec/sec_drv.h

115

#define SEC_BD_W3_CIPHER_LEN_OFFSET_M GENMASK(19, 10)

drivers/crypto/hisilicon/sec/sec_drv.h

117

#define SEC_BD_W3_MAC_LEN_M GENMASK(24, 20)

drivers/crypto/hisilicon/sec/sec_drv.h

119

#define SEC_BD_W3_A_KEY_LEN_M GENMASK(29, 25)

drivers/crypto/hisilicon/sec/sec_drv.h

121

#define SEC_BD_W3_C_KEY_LEN_M GENMASK(31, 30)

drivers/crypto/hisilicon/sec/sec_drv.h

23

#define SEC_BD_W0_T_LEN_M GENMASK(4, 0)

drivers/crypto/hisilicon/sec/sec_drv.h

26

#define SEC_BD_W0_C_WIDTH_M GENMASK(6, 5)

drivers/crypto/hisilicon/sec/sec_drv.h

35

#define SEC_BD_W0_C_MODE_M GENMASK(9, 7)

drivers/crypto/hisilicon/sec/sec_drv.h

46

#define SEC_BD_W0_DAT_SKIP_M GENMASK(13, 12)

drivers/crypto/hisilicon/sec/sec_drv.h

48

#define SEC_BD_W0_C_GRAN_SIZE_19_16_M GENMASK(17, 14)

drivers/crypto/hisilicon/sec/sec_drv.h

51

#define SEC_BD_W0_CIPHER_M GENMASK(19, 18)

drivers/crypto/hisilicon/sec/sec_drv.h

57

#define SEC_BD_W0_AUTH_M GENMASK(21, 20)

drivers/crypto/hisilicon/sec/sec_drv.h

66

#define SEC_BD_W0_HM_M GENMASK(26, 25)

drivers/crypto/hisilicon/sec/sec_drv.h

68

#define SEC_BD_W0_ICV_OR_SKEY_EN_M GENMASK(28, 27)

drivers/crypto/hisilicon/sec/sec_drv.h

72

#define SEC_BD_W0_FLAG_M GENMASK(30, 29)

drivers/crypto/hisilicon/sec/sec_drv.h

73

#define SEC_BD_W0_C_GRAN_SIZE_21_20_M GENMASK(30, 29)

drivers/crypto/hisilicon/sec/sec_drv.h

80

#define SEC_BD_W1_AUTH_GRAN_SIZE_M GENMASK(21, 0)

drivers/crypto/hisilicon/sec/sec_drv.h

86

#define SEC_BD_W1_A_ALG_M GENMASK(28, 25)

drivers/crypto/hisilicon/sec/sec_drv.h

99

#define SEC_BD_W1_C_ALG_M GENMASK(31, 29)

drivers/crypto/hisilicon/sec2/sec_main.c

100

#define SEC_SVA_PREFETCH_NUM GENMASK(2, 0)

drivers/crypto/hisilicon/sec2/sec_main.c

130

GENMASK(24, 21))

drivers/crypto/hisilicon/sec2/sec_main.c

155

{SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},

drivers/crypto/hisilicon/sec2/sec_main.c

156

{SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},

drivers/crypto/hisilicon/sec2/sec_main.c

157

{SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},

drivers/crypto/hisilicon/sec2/sec_main.c

158

{SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

drivers/crypto/hisilicon/sec2/sec_main.c

159

{SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},

drivers/crypto/hisilicon/sec2/sec_main.c

160

{SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},

drivers/crypto/hisilicon/sec2/sec_main.c

161

{SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},

drivers/crypto/hisilicon/sec2/sec_main.c

162

{SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},

drivers/crypto/hisilicon/sec2/sec_main.c

163

{SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},

drivers/crypto/hisilicon/sec2/sec_main.c

164

{SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},

drivers/crypto/hisilicon/sec2/sec_main.c

165

{SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},

drivers/crypto/hisilicon/sec2/sec_main.c

166

{SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},

drivers/crypto/hisilicon/sec2/sec_main.c

167

{SEC_CORE_ENABLE_BITMAP, 0x3140, 0, GENMASK(31, 0), 0x17F, 0x17F, 0xF},

drivers/crypto/hisilicon/sec2/sec_main.c

168

{SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF},

drivers/crypto/hisilicon/sec2/sec_main.c

169

{SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},

drivers/crypto/hisilicon/sec2/sec_main.c

170

{SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

drivers/crypto/hisilicon/sec2/sec_main.c

171

{SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

drivers/crypto/hisilicon/sec2/sec_main.c

172

{SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

drivers/crypto/hisilicon/sec2/sec_main.c

173

{SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

drivers/crypto/hisilicon/sec2/sec_main.c

174

{SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

drivers/crypto/hisilicon/sec2/sec_main.c

175

{SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

drivers/crypto/hisilicon/sec2/sec_main.c

176

{SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

drivers/crypto/hisilicon/sec2/sec_main.c

177

{SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

drivers/crypto/hisilicon/sec2/sec_main.c

178

{SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

drivers/crypto/hisilicon/sec2/sec_main.c

179

{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

drivers/crypto/hisilicon/sec2/sec_main.c

60

#define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)

drivers/crypto/hisilicon/sec2/sec_main.c

99

#define SEC_SVA_STALL_NUM GENMASK(23, 8)

drivers/crypto/hisilicon/trng/trng.c

22

#define HISI_TRNG_VER_V1 GENMASK(31, 0)

drivers/crypto/hisilicon/zip/zip_crypto.c

11

#define HZIP_BD_STATUS_M GENMASK(7, 0)

drivers/crypto/hisilicon/zip/zip_crypto.c

13

#define HZIP_IN_SGE_DATA_OFFSET_M GENMASK(23, 0)

drivers/crypto/hisilicon/zip/zip_crypto.c

14

#define HZIP_SQE_TYPE_M GENMASK(31, 28)

drivers/crypto/hisilicon/zip/zip_crypto.c

16

#define HZIP_OUT_SGE_DATA_OFFSET_M GENMASK(23, 0)

drivers/crypto/hisilicon/zip/zip_crypto.c

18

#define HZIP_REQ_TYPE_M GENMASK(7, 0)

drivers/crypto/hisilicon/zip/zip_crypto.c

21

#define HZIP_BUF_TYPE_M GENMASK(11, 8)

drivers/crypto/hisilicon/zip/zip_crypto.c

23

#define HZIP_WIN_SIZE_M GENMASK(15, 12)

drivers/crypto/hisilicon/zip/zip_crypto.c

29

#define HZIP_ALG_DEFLATE GENMASK(5, 4)

drivers/crypto/hisilicon/zip/zip_main.c

100

#define HZIP_SVA_PREFETCH_NUM GENMASK(18, 16)

drivers/crypto/hisilicon/zip/zip_main.c

101

#define HZIP_SVA_STALL_NUM GENMASK(15, 0)

drivers/crypto/hisilicon/zip/zip_main.c

114

#define HZIP_CORE_GATED_EN GENMASK(15, 8)

drivers/crypto/hisilicon/zip/zip_main.c

246

{ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77},

drivers/crypto/hisilicon/zip/zip_main.c

247

{ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77},

drivers/crypto/hisilicon/zip/zip_main.c

248

{ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},

drivers/crypto/hisilicon/zip/zip_main.c

249

{ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

drivers/crypto/hisilicon/zip/zip_main.c

250

{ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE},

drivers/crypto/hisilicon/zip/zip_main.c

251

{ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE},

drivers/crypto/hisilicon/zip/zip_main.c

252

{ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE},

drivers/crypto/hisilicon/zip/zip_main.c

253

{ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},

drivers/crypto/hisilicon/zip/zip_main.c

254

{ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1},

drivers/crypto/hisilicon/zip/zip_main.c

255

{ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2},

drivers/crypto/hisilicon/zip/zip_main.c

256

{ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5},

drivers/crypto/hisilicon/zip/zip_main.c

257

{ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2},

drivers/crypto/hisilicon/zip/zip_main.c

258

{ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3},

drivers/crypto/hisilicon/zip/zip_main.c

259

{ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C},

drivers/crypto/hisilicon/zip/zip_main.c

260

{ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3},

drivers/crypto/hisilicon/zip/zip_main.c

261

{ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30},

drivers/crypto/hisilicon/zip/zip_main.c

262

{ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F},

drivers/crypto/hisilicon/zip/zip_main.c

263

{ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},

drivers/crypto/hisilicon/zip/zip_main.c

264

{ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},

drivers/crypto/hisilicon/zip/zip_main.c

265

{ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},

drivers/crypto/hisilicon/zip/zip_main.c

266

{ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},

drivers/crypto/hisilicon/zip/zip_main.c

267

{ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},

drivers/crypto/hisilicon/zip/zip_main.c

268

{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}

drivers/crypto/hisilicon/zip/zip_main.c

67

#define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0)

drivers/crypto/hisilicon/zip/zip_main.c

80

#define HZIP_ALG_ZLIB_BIT GENMASK(1, 0)

drivers/crypto/hisilicon/zip/zip_main.c

81

#define HZIP_ALG_GZIP_BIT GENMASK(3, 2)

drivers/crypto/hisilicon/zip/zip_main.c

82

#define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4)

drivers/crypto/hisilicon/zip/zip_main.c

83

#define HZIP_ALG_LZ77_BIT GENMASK(7, 6)

drivers/crypto/hisilicon/zip/zip_main.c

84

#define HZIP_ALG_LZ4_BIT GENMASK(9, 8)

drivers/crypto/inside-secure/eip93/eip93-main.h

31

#define EIP93_ALG_MASK GENMASK(2, 0)

drivers/crypto/inside-secure/eip93/eip93-main.h

38

#define EIP93_HASH_MASK GENMASK(6, 3)

drivers/crypto/inside-secure/eip93/eip93-main.h

44

#define EIP93_MODE_MASK GENMASK(10, 8)

drivers/crypto/inside-secure/eip93/eip93-regs.h

101

#define EIP93_PE_CONFIG_PE_MODE GENMASK(9, 8)

drivers/crypto/inside-secure/eip93/eip93-regs.h

110

#define EIP93_PE_OUTBUF_THRESH GENMASK(23, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

111

#define EIP93_PE_INBUF_THRESH GENMASK(7, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

119

#define EIP93_PE_ENDIAN_TARGET_BYTE_SWAP GENMASK(23, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

12

#define EIP93_PE_CTRL_PE_PAD_CTRL_STAT GENMASK(31, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

120

#define EIP93_PE_ENDIAN_MASTER_BYTE_SWAP GENMASK(7, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

13

#define EIP93_PE_CTRL_PE_EXT_ERR_CODE GENMASK(23, 20)

drivers/crypto/inside-secure/eip93/eip93-regs.h

162

#define EIP93_PE_REVISION_MAJ_HW_REV GENMASK(27, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

163

#define EIP93_PE_REVISION_MIN_HW_REV GENMASK(23, 20)

drivers/crypto/inside-secure/eip93/eip93-regs.h

164

#define EIP93_PE_REVISION_HW_PATCH GENMASK(19, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

165

#define EIP93_PE_REVISION_EIP_NO GENMASK(7, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

201

#define EIP93_SA_CMD_HASH_SOURCE GENMASK(27, 26)

drivers/crypto/inside-secure/eip93/eip93-regs.h

205

#define EIP93_SA_CMD_IV_SOURCE GENMASK(25, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

210

#define EIP93_SA_CMD_DIGEST_LENGTH GENMASK(23, 20)

drivers/crypto/inside-secure/eip93/eip93-regs.h

224

#define EIP93_SA_CMD_HASH GENMASK(15, 12)

drivers/crypto/inside-secure/eip93/eip93-regs.h

230

#define EIP93_SA_CMD_CIPHER GENMASK(11, 8)

drivers/crypto/inside-secure/eip93/eip93-regs.h

236

#define EIP93_SA_CMD_PAD_TYPE GENMASK(7, 6)

drivers/crypto/inside-secure/eip93/eip93-regs.h

243

#define EIP93_SA_CMD_OPGROUP GENMASK(5, 4)

drivers/crypto/inside-secure/eip93/eip93-regs.h

248

#define EIP93_SA_CMD_OPCODE GENMASK(2, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

27

#define EIP93_PE_CTRL_PE_PAD_VALUE GENMASK(15, 8)

drivers/crypto/inside-secure/eip93/eip93-regs.h

275

#define EIP93_SA_CMD_ARC4_KEY_LENGHT GENMASK(28, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

277

#define EIP93_SA_CMD_AES_KEY_LENGTH GENMASK(26, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

28

#define EIP93_PE_CTRL_PE_PRNG_MODE GENMASK(7, 6)

drivers/crypto/inside-secure/eip93/eip93-regs.h

281

#define EIP93_SA_CMD_HASH_CRYPT_OFFSET GENMASK(23, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

286

#define EIP93_SA_CMD_CHIPER_MODE GENMASK(9, 8)

drivers/crypto/inside-secure/eip93/eip93-regs.h

31

#define EIP93_PE_CTRL_PE_READY_DES_TRING_OWN GENMASK(1, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

56

#define EIP93_PE_USER_ID_DESC_FLAGS GENMASK(31, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

57

#define EIP93_PE_USER_ID_CRYPTO_IDR GENMASK(15, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

59

#define EIP93_PE_LENGTH_BYPASS GENMASK(31, 24)

drivers/crypto/inside-secure/eip93/eip93-regs.h

60

#define EIP93_PE_LENGTH_HOST_PE_READY GENMASK(23, 22)

drivers/crypto/inside-secure/eip93/eip93-regs.h

63

#define EIP93_PE_LENGTH_LENGTH GENMASK(19, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

72

#define EIP93_PE_RING_SIZE GENMASK(9, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

75

#define EIPR93_PE_RD_TIMEOUT GENMASK(29, 26)

drivers/crypto/inside-secure/eip93/eip93-regs.h

76

#define EIPR93_PE_RDR_THRESH GENMASK(25, 16)

drivers/crypto/inside-secure/eip93/eip93-regs.h

77

#define EIPR93_PE_CDR_THRESH GENMASK(9, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

79

#define EIP93_PE_CD_COUNT GENMASK(10, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

84

#define EIP93_PE_CD_COUNT_INCR GENMASK(7, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

86

#define EIP93_PE_RD_COUNT GENMASK(10, 0)

drivers/crypto/inside-secure/eip93/eip93-regs.h

91

#define EIP93_PE_RD_COUNT_INCR GENMASK(7, 0)

drivers/crypto/inside-secure/safexcel.c

153

writel(GENMASK(29, 0),

drivers/crypto/inside-secure/safexcel.c

1717

writel(GENMASK(5, 0), EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_STAT);

drivers/crypto/inside-secure/safexcel.c

1718

writel(GENMASK(7, 0), EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_STAT);

drivers/crypto/inside-secure/safexcel.c

1942

writel(GENMASK(31, 0),

drivers/crypto/inside-secure/safexcel.c

531

writel(GENMASK(5, 0),

drivers/crypto/inside-secure/safexcel.c

582

writel(GENMASK(7, 0),

drivers/crypto/inside-secure/safexcel.c

623

writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);

drivers/crypto/inside-secure/safexcel.c

662

GENMASK(priv->config.rings - 1, 0),

drivers/crypto/inside-secure/safexcel.c

673

GENMASK(15, 12)) != GENMASK(15, 12))

drivers/crypto/inside-secure/safexcel.c

722

writel(GENMASK(31, 0),

drivers/crypto/inside-secure/safexcel.c

770

writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),

drivers/crypto/inside-secure/safexcel.c

774

writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),

drivers/crypto/inside-secure/safexcel.c

779

writel(GENMASK(30, 20), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);

drivers/crypto/inside-secure/safexcel.h

245

#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)

drivers/crypto/inside-secure/safexcel.h

261

#define EIP197_N_RINGS_MASK GENMASK(3, 0)

drivers/crypto/inside-secure/safexcel.h

263

#define EIP197_N_PES_MASK GENMASK(4, 0)

drivers/crypto/inside-secure/safexcel.h

264

#define EIP97_N_PES_MASK GENMASK(2, 0)

drivers/crypto/inside-secure/safexcel.h

266

#define EIP197_HWDATAW_MASK GENMASK(3, 0)

drivers/crypto/inside-secure/safexcel.h

267

#define EIP97_HWDATAW_MASK GENMASK(2, 0)

drivers/crypto/inside-secure/safexcel.h

271

#define EIP197_CFSIZE_MASK GENMASK(2, 0)

drivers/crypto/inside-secure/safexcel.h

272

#define EIP97_CFSIZE_MASK GENMASK(3, 0)

drivers/crypto/inside-secure/safexcel.h

276

#define EIP197_RFSIZE_MASK GENMASK(2, 0)

drivers/crypto/inside-secure/safexcel.h

277

#define EIP97_RFSIZE_MASK GENMASK(3, 0)

drivers/crypto/inside-secure/safexcel.h

287

#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)

drivers/crypto/inside-secure/safexcel.h

291

#define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)

drivers/crypto/inside-secure/safexcel.h

293

#define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)

drivers/crypto/inside-secure/safexcel.h

320

#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)

drivers/crypto/inside-secure/safexcel.h

467

#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)

drivers/crypto/inside-secure/safexcel.h

468

#define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)

drivers/crypto/inside-secure/safexcel.h

564

#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)

drivers/crypto/inside-secure/safexcel.h

606

#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)

drivers/crypto/inside-secure/safexcel.h

607

#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

24

#define ADF_AE_GROUP_0 GENMASK(3, 0)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

25

#define ADF_AE_GROUP_1 GENMASK(7, 4)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

26

#define ADF_AE_GROUP_2 GENMASK(11, 8)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

27

#define ADF_AE_GROUP_3 GENMASK(15, 12)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

30

#define ENA_THD_MASK_ASYM GENMASK(1, 0)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

31

#define ENA_THD_MASK_SYM GENMASK(3, 0)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

32

#define ENA_THD_MASK_DC GENMASK(1, 0)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

24

#define ADF_AE_GROUP_0 GENMASK(3, 0)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

25

#define ADF_AE_GROUP_1 GENMASK(7, 4)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

28

#define ENA_THD_MASK_ASYM GENMASK(1, 0)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

29

#define ENA_THD_MASK_ASYM_401XX GENMASK(5, 0)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

30

#define ENA_THD_MASK_SYM GENMASK(6, 0)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

31

#define ENA_THD_MASK_DC GENMASK(1, 0)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

32

#define ADF_AE_GROUP_0 GENMASK(3, 0)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

33

#define ADF_AE_GROUP_1 GENMASK(7, 4)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

101

#define ADF_GEN6_PVC0CTL_TCVCMAP_MASK GENMASK(7, 1)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

107

#define ADF_GEN6_PVC1CTL_TCVCMAP_MASK GENMASK(7, 1)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

133

#define ADF_6XXX_ACCELENGINES_MASK GENMASK(8, 0)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

134

#define ADF_6XXX_ADMIN_AE_MASK GENMASK(8, 8)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

86

#define ADF_GEN6_RINGMODECTL_TC_MASK GENMASK(18, 16)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

90

#define ADF_GEN6_RINGMODECTL_TC_EN_MASK GENMASK(20, 19)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

14

#define ADF_RP_INT_SRC_SEL_F_RISE_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

15

#define ADF_RP_INT_SRC_SEL_F_FALL_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c

17

#define CNV_ERR_INFO_MASK GENMASK(11, 0)

drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c

18

#define CNV_ERR_TYPE_MASK GENMASK(15, 12)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

117

#define ADF_GEN4_ENA_THD_MASK_ERROR GENMASK(ADF_NUM_THREADS_PER_AE, 0)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

43

#define ADF_GEN4_PM_MSG_PAYLOAD_BIT_MASK GENMASK(28, 1)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

50

#define ADF_GEN4_PM_DOMAIN_POWER_GATED_MASK GENMASK(15, 0)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

51

#define ADF_GEN4_PM_SSM_PM_ENABLE_MASK GENMASK(15, 0)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

52

#define ADF_GEN4_PM_IDLE_FILTER_MASK GENMASK(5, 3)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

57

#define ADF_GEN4_PM_CURRENT_WP_MASK GENMASK(19, 11)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

58

#define ADF_GEN4_PM_CPM_PM_STATE_MASK GENMASK(22, 20)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

59

#define ADF_GEN4_PM_PENDING_WP_MASK GENMASK(31, 23)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

60

#define ADF_GEN4_PM_THR_VALUE_MASK GENMASK(6, 4)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

67

#define ADF_GEN4_PM_DCPR_ACTIVE_COUNT_MASK GENMASK(3, 2)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

68

#define ADF_GEN4_PM_DCPR_MANAGED_COUNT_MASK GENMASK(3, 2)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

69

#define ADF_GEN4_PM_PKE_ACTIVE_COUNT_MASK GENMASK(8, 4)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

70

#define ADF_GEN4_PM_PKE_MANAGED_COUNT_MASK GENMASK(8, 4)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

71

#define ADF_GEN4_PM_WAT_ACTIVE_COUNT_MASK GENMASK(13, 9)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

72

#define ADF_GEN4_PM_WAT_MANAGED_COUNT_MASK GENMASK(13, 9)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

73

#define ADF_GEN4_PM_WCP_ACTIVE_COUNT_MASK GENMASK(18, 14)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

74

#define ADF_GEN4_PM_WCP_MANAGED_COUNT_MASK GENMASK(18, 14)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

75

#define ADF_GEN4_PM_UCS_ACTIVE_COUNT_MASK GENMASK(20, 19)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

76

#define ADF_GEN4_PM_UCS_MANAGED_COUNT_MASK GENMASK(20, 19)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

77

#define ADF_GEN4_PM_CPH_ACTIVE_COUNT_MASK GENMASK(24, 21)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

78

#define ADF_GEN4_PM_CPH_MANAGED_COUNT_MASK GENMASK(24, 21)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

79

#define ADF_GEN4_PM_ATH_ACTIVE_COUNT_MASK GENMASK(28, 25)

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

80

#define ADF_GEN4_PM_ATH_MANAGED_COUNT_MASK GENMASK(28, 25)

drivers/crypto/intel/qat/qat_common/adf_gen6_pm.h

27

#define ADF_GEN6_PM_CPM_PM_STATE_MASK GENMASK(22, 20)

drivers/crypto/intel/qat/qat_common/adf_gen6_pm.h

35

#define ADF_GEN6_PM_IDLE_FILTER_MASK GENMASK(5, 3)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h

496

#define ADF_GEN6_GENSTS_DEVICE_STATE_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h

497

#define ADF_GEN6_GENSTS_RESET_TYPE_MASK GENMASK(3, 2)

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

121

ae_thr_map &= ~(GENMASK(3, 0) << (thr * BIT(2)));

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

137

#define ADF_PF2VF_VERSION_RESP_VERS_MASK GENMASK(7, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

138

#define ADF_PF2VF_VERSION_RESP_RESULT_MASK GENMASK(9, 8)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

153

#define ADF_VF2PF_RNG_RESET_RP_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

154

#define ADF_VF2PF_RNG_RESET_RSVD_MASK GENMASK(25, 2)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

157

#define ADF_PF2VF_BLKMSG_RESP_TYPE_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

158

#define ADF_PF2VF_BLKMSG_RESP_DATA_MASK GENMASK(9, 2)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

175

#define ADF_VF2PF_LARGE_BLOCK_TYPE_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

176

#define ADF_VF2PF_LARGE_BLOCK_BYTE_MASK GENMASK(8, 2)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

177

#define ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

178

#define ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK GENMASK(8, 3)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

179

#define ADF_VF2PF_SMALL_BLOCK_TYPE_MASK GENMASK(3, 0)

drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h

180

#define ADF_VF2PF_SMALL_BLOCK_BYTE_MASK GENMASK(8, 4)

drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.h

22

PM_INFO_REGSET_ENTRY_MASK(_reg_, _field_, GENMASK(31, 0))

drivers/crypto/intel/qat/qat_common/adf_rl.c

27

#define RL_CAPABILITY_MASK GENMASK(6, 4)

drivers/crypto/intel/qat/qat_common/adf_rl.c

30

#define ROOT_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/adf_rl.c

31

#define CLUSTER_MASK GENMASK(3, 0)

drivers/crypto/intel/qat/qat_common/adf_rl.c

32

#define LEAF_MASK GENMASK(5, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

103

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

112

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

121

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

130

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

139

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

148

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

157

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

166

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

175

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK GENMASK(3, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

186

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

197

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

20

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

206

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

215

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

224

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

233

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

242

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

251

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

262

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

271

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

280

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

289

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

29

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

298

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_MASK GENMASK(2, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

309

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

38

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

47

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

56

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

67

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

76

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

85

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK GENMASK(0, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

9

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK GENMASK(1, 0)

drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

94

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_MASK GENMASK(0, 0)

drivers/crypto/marvell/cesa/cesa.h

101

#define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)

drivers/crypto/marvell/cesa/cesa.h

105

#define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)

drivers/crypto/marvell/cesa/cesa.h

116

#define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)

drivers/crypto/marvell/cesa/cesa.h

121

#define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)

drivers/crypto/marvell/cesa/cesa.h

177

#define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))

drivers/crypto/marvell/cesa/cesa.h

180

#define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))

drivers/crypto/marvell/cesa/cesa.h

186

#define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))

drivers/crypto/marvell/cesa/cesa.h

189

#define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))

drivers/crypto/marvell/cesa/cesa.h

19

#define CESA_TDMA_DST_BURST GENMASK(2, 0)

drivers/crypto/marvell/cesa/cesa.h

23

#define CESA_TDMA_SRC_BURST GENMASK(8, 6)

drivers/crypto/marvell/cesa/cesa.h

277

#define CESA_TDMA_TYPE_MSK GENMASK(26, 0)

drivers/crypto/marvell/cesa/cesa.h

53

#define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)

drivers/crypto/marvell/cesa/cesa.h

94

#define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)

drivers/crypto/omap-aes.h

30

#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)

drivers/crypto/omap-aes.h

34

#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)

drivers/crypto/omap-aes.h

35

#define AES_REG_CTRL_GCM GENMASK(17, 16)

drivers/crypto/omap-aes.h

38

#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)

drivers/crypto/omap-aes.h

42

#define AES_REG_CTRL_MASK GENMASK(24, 2)

drivers/crypto/qce/common.h

53

#define QCE_MODE_MASK GENMASK(12, 8)

drivers/crypto/qce/regs-v5.h

107

#define CORE_STEP_REV_MASK GENMASK(15, 0)

drivers/crypto/qce/regs-v5.h

109

#define CORE_MINOR_REV_MASK GENMASK(23, 16)

drivers/crypto/qce/regs-v5.h

111

#define CORE_MAJOR_REV_MASK GENMASK(31, 24)

drivers/crypto/qce/regs-v5.h

116

#define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26)

drivers/crypto/qce/regs-v5.h

118

#define DIN_SIZE_AVAIL_MASK GENMASK(25, 21)

drivers/crypto/qce/regs-v5.h

127

#define CRYPTO_STATE_MASK GENMASK(13, 10)

drivers/crypto/qce/regs-v5.h

145

#define REQ_SIZE_MASK GENMASK(20, 17)

drivers/crypto/qce/regs-v5.h

164

#define MAX_QUEUED_REQ_MASK GENMASK(24, 16)

drivers/crypto/qce/regs-v5.h

170

#define IRQ_ENABLES_MASK GENMASK(13, 10)

drivers/crypto/qce/regs-v5.h

174

#define PIPE_SET_SELECT_MASK GENMASK(8, 5)

drivers/crypto/qce/regs-v5.h

192

#define AUTH_NONCE_NUM_WORDS_MASK GENMASK(22, 20)

drivers/crypto/qce/regs-v5.h

200

#define AUTH_POS_MASK GENMASK(15, 14)

drivers/crypto/qce/regs-v5.h

205

#define AUTH_SIZE_MASK GENMASK(13, 9)

drivers/crypto/qce/regs-v5.h

226

#define AUTH_MODE_MASK GENMASK(8, 6)

drivers/crypto/qce/regs-v5.h

233

#define AUTH_KEY_SIZE_MASK GENMASK(5, 3)

drivers/crypto/qce/regs-v5.h

238

#define AUTH_ALG_MASK GENMASK(2, 0)

drivers/crypto/qce/regs-v5.h

248

#define ENCR_XTS_DU_SIZE_MASK GENMASK(19, 0)

drivers/crypto/qce/regs-v5.h

272

#define CNTR_ALG_MASK GENMASK(12, 11)

drivers/crypto/qce/regs-v5.h

278

#define ENCR_MODE_MASK GENMASK(9, 6)

drivers/crypto/qce/regs-v5.h

286

#define ENCR_KEY_SZ_MASK GENMASK(5, 3)

drivers/crypto/qce/regs-v5.h

293

#define ENCR_ALG_MASK GENMASK(2, 0)

drivers/crypto/qce/regs-v5.h

317

#define BAM_PIPE_SETS_MASK GENMASK(12, 9)

drivers/crypto/qce/regs-v5.h

319

#define AXI_WR_BEATS_MASK GENMASK(18, 13)

drivers/crypto/qce/regs-v5.h

321

#define AXI_RD_BEATS_MASK GENMASK(24, 19)

drivers/crypto/starfive/jh7110-aes.c

45

#define FLG_MODE_MASK GENMASK(2, 0)

drivers/crypto/stm32/stm32-cryp.c

45

#define FLG_MODE_MASK GENMASK(15, 0)

drivers/crypto/stm32/stm32-hash.c

67

#define HASH_STR_NBLW_MASK GENMASK(4, 0)

drivers/crypto/stm32/stm32-hash.c

71

#define HASH_HWCFG_DMA_MASK GENMASK(3, 0)

drivers/crypto/stm32/stm32-hash.c

92

#define HASH_FLAGS_ALGO_MASK GENMASK(20, 17)

drivers/crypto/tegra/tegra-se-key.c

13

#define SE_KEY_FULL_MASK GENMASK(SE_MAX_KEYSLOT, 0)

drivers/crypto/tegra/tegra-se-key.c

31

if (tegra_se_keyslots == GENMASK(SE_MAX_KEYSLOT, 0)) {

drivers/crypto/tegra/tegra-se.h

123

#define SE_AES_CFG_ENC_MODE(x) FIELD_PREP(GENMASK(31, 24), x)

drivers/crypto/tegra/tegra-se.h

130

#define SE_AES_CFG_DEC_MODE(x) FIELD_PREP(GENMASK(23, 16), x)

drivers/crypto/tegra/tegra-se.h

136

#define SE_AES_CFG_ENC_ALG(x) FIELD_PREP(GENMASK(15, 12), x)

drivers/crypto/tegra/tegra-se.h

145

#define SE_AES_CFG_DEC_ALG(x) FIELD_PREP(GENMASK(11, 8), x)

drivers/crypto/tegra/tegra-se.h

149

#define SE_AES_CFG_DST(x) FIELD_PREP(GENMASK(4, 2), x)

drivers/crypto/tegra/tegra-se.h

156

#define SE_AES_KEY2_INDEX(x) FIELD_PREP(GENMASK(31, 28), x)

drivers/crypto/tegra/tegra-se.h

157

#define SE_AES_KEY_INDEX(x) FIELD_PREP(GENMASK(27, 24), x)

drivers/crypto/tegra/tegra-se.h

161

#define SE_AES_CRYPTO_CFG_CTR_CNTN(x) FIELD_PREP(GENMASK(18, 11), x)

drivers/crypto/tegra/tegra-se.h

171

#define SE_AES_CRYPTO_CFG_IV_SEL(x) FIELD_PREP(GENMASK(8, 7), x)

drivers/crypto/tegra/tegra-se.h

176

#define SE_AES_CRYPTO_CFG_VCTRAM_SEL(x) FIELD_PREP(GENMASK(6, 5), x)

drivers/crypto/tegra/tegra-se.h

182

#define SE_AES_CRYPTO_CFG_INPUT_SEL(x) FIELD_PREP(GENMASK(4, 3), x)

drivers/crypto/tegra/tegra-se.h

189

#define SE_AES_CRYPTO_CFG_XOR_POS(x) FIELD_PREP(GENMASK(2, 1), x)

drivers/crypto/tegra/tegra-se.h

199

#define SE_LAST_BLOCK_VAL(x) FIELD_PREP(GENMASK(19, 0), x)

drivers/crypto/tegra/tegra-se.h

200

#define SE_LAST_BLOCK_RES_BITS(x) FIELD_PREP(GENMASK(26, 20), x)

drivers/crypto/tegra/tegra-se.h

207

#define SE_AES_OP_OP(x) FIELD_PREP(GENMASK(2, 0), x)

drivers/crypto/tegra/tegra-se.h

21

#define SE_OWNERSHIP_UID(x) FIELD_GET(GENMASK(7, 0), x)

drivers/crypto/tegra/tegra-se.h

214

#define SE_KAC_SIZE(x) FIELD_PREP(GENMASK(15, 14), x)

drivers/crypto/tegra/tegra-se.h

221

#define SE_KAC_PURPOSE(x) FIELD_PREP(GENMASK(11, 8), x)

drivers/crypto/tegra/tegra-se.h

232

#define SE_KAC_USER_NS FIELD_PREP(GENMASK(6, 4), 3)

drivers/crypto/tegra/tegra-se.h

234

#define SE_AES_KEY_DST_INDEX(x) FIELD_PREP(GENMASK(11, 8), x)

drivers/crypto/tegra/tegra-se.h

235

#define SE_ADDR_HI_MSB(x) FIELD_PREP(GENMASK(31, 24), x)

drivers/crypto/tegra/tegra-se.h

236

#define SE_ADDR_HI_SZ(x) FIELD_PREP(GENMASK(23, 0), x)

drivers/crypto/tegra/tegra-se.h

39

#define SE_SHA_ENC_MODE(x) FIELD_PREP(GENMASK(31, 24), x)

drivers/crypto/tegra/tegra-se.h

56

#define SE_SHA_CFG_ENC_ALG(x) FIELD_PREP(GENMASK(15, 12), x)

drivers/crypto/tegra/tegra-se.h

71

#define SE_SHA_OP_OP(x) FIELD_PREP(GENMASK(2, 0), x)

drivers/crypto/tegra/tegra-se.h

78

#define SE_SHA_CFG_DEC_ALG(x) FIELD_PREP(GENMASK(11, 8), x)

drivers/crypto/tegra/tegra-se.h

84

#define SE_SHA_CFG_DST(x) FIELD_PREP(GENMASK(4, 2), x)

drivers/crypto/ti/dthev2-aes.c

69

#define DTHE_AES_CTRL_MODE_CLEAR_MASK ~GENMASK(28, 5)

drivers/crypto/ti/dthev2-aes.c

84

#define DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN GENMASK(6, 5)

drivers/crypto/ti/dthev2-aes.c

85

#define DTHE_AES_IRQENABLE_EN_ALL GENMASK(3, 0)

drivers/crypto/xilinx/xilinx-trng.c

45

#define TRNG_STATUS_QCNT_MASK GENMASK(11, 9)

drivers/cxl/core/core.h

116

#define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0)

drivers/cxl/core/core.h

117

#define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0)

drivers/cxl/core/core.h

118

#define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8)

drivers/cxl/core/edac.c

511

#define CXL_ECS_LOG_ENTRY_TYPE_MASK GENMASK(1, 0)

drivers/cxl/core/edac.c

513

#define CXL_ECS_THRESHOLD_COUNT_MASK GENMASK(2, 0)

drivers/cxl/core/edac.c

61

#define CXL_SCRUB_CONTROL_CYCLE_MASK GENMASK(7, 0)

drivers/cxl/core/edac.c

62

#define CXL_SCRUB_CONTROL_MIN_CYCLE_MASK GENMASK(15, 8)

drivers/cxl/core/hdm.c

716

*tgt = FIELD_PREP(GENMASK(7, 0), t[0]->port_id);

drivers/cxl/core/hdm.c

718

*tgt |= FIELD_PREP(GENMASK(15, 8), t[1]->port_id);

drivers/cxl/core/hdm.c

720

*tgt |= FIELD_PREP(GENMASK(23, 16), t[2]->port_id);

drivers/cxl/core/hdm.c

722

*tgt |= FIELD_PREP(GENMASK(31, 24), t[3]->port_id);

drivers/cxl/core/hdm.c

82

cxlhdm->interleave_mask |= GENMASK(11, 8);

drivers/cxl/core/hdm.c

84

cxlhdm->interleave_mask |= GENMASK(14, 12);

drivers/cxl/core/region.c

1371

interleave_mask = GENMASK(high_pos, low_pos);

drivers/cxl/core/region.c

3077

pos = (hpa_offset >> (eig + 8)) & GENMASK(eiw - 1, 0);

drivers/cxl/core/trace.h

318

#define CXL_DPA_FLAGS_MASK GENMASK(1, 0)

drivers/cxl/cxl.h

137

#define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))

drivers/cxl/cxl.h

139

#define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))

drivers/cxl/cxl.h

142

#define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))

drivers/cxl/cxl.h

144

#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)

drivers/cxl/cxl.h

146

#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)

drivers/cxl/cxl.h

148

#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)

drivers/cxl/cxl.h

160

#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)

drivers/cxl/cxl.h

180

#define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)

drivers/cxl/cxl.h

181

#define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4)

drivers/cxl/cxl.h

185

#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)

drivers/cxl/cxl.h

187

#define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)

drivers/cxl/cxl.h

32

#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)

drivers/cxl/cxl.h

34

#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)

drivers/cxl/cxl.h

36

#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)

drivers/cxl/cxl.h

38

#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)

drivers/cxl/cxl.h

39

#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)

drivers/cxl/cxl.h

47

#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)

drivers/cxl/cxl.h

48

#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)

drivers/cxl/cxl.h

60

#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)

drivers/cxl/cxl.h

61

#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)

drivers/cxl/cxlmem.h

18

#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)

drivers/cxl/cxlmem.h

27

#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)

drivers/cxl/cxlmem.h

294

#define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)

drivers/cxl/cxlmem.h

295

#define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)

drivers/cxl/cxlmem.h

765

#define CXL_POISON_SOURCE_MASK GENMASK(2, 0)

drivers/cxl/pci.c

1073

#define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0)

drivers/devfreq/event/rockchip-dfi.c

43

#define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7)

drivers/devfreq/event/rockchip-dfi.c

728

dfi->channel_mask = GENMASK(1, 0);

drivers/devfreq/rk3399_dmc.c

31

#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0)

drivers/devfreq/rk3399_dmc.c

32

#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8)

drivers/devfreq/rk3399_dmc.c

33

#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16)

drivers/devfreq/rk3399_dmc.c

35

#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0)

drivers/devfreq/rk3399_dmc.c

36

#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16)

drivers/dma/altera-msgdma.c

124

#define MSGDMA_CSR_STAT_MASK GENMASK(9, 0)

drivers/dma/altera-msgdma.c

125

#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ GENMASK(8, 0)

drivers/dma/altera-msgdma.c

64

#define MSGDMA_DESC_CTL_TR_ERR_IRQ GENMASK(23, 16)

drivers/dma/amd/ae4dma/ae4dma-dev.c

64

status &= GENMASK(31, 1);

drivers/dma/amd/ptdma/ptdma.h

74

#define CMD_QUEUE_PRIO GENMASK(2, 1)

drivers/dma/amd/ptdma/ptdma.h

91

#define CMD_Q_SIZE_MASK GENMASK(4, 0)

drivers/dma/amd/ptdma/ptdma.h

92

#define CMD_Q_SIZE GENMASK(7, 3)

drivers/dma/amd/ptdma/ptdma.h

93

#define CMD_Q_SHIFT GENMASK(1, 0)

drivers/dma/amd/qdma/qdma.c

62

mask = GENMASK(hi_bit, low_bit);

drivers/dma/amd/qdma/qdma.c

73

mask = GENMASK(hi_bit, 0);

drivers/dma/amd/qdma/qdma.c

79

mask = GENMASK(31, 32 - low_bit);

drivers/dma/amd/qdma/qdma.h

38

#define QDMA_INTR_RING_IDX_MASK GENMASK(9, 0)

drivers/dma/amd/qdma/qdma.h

42

#define QDMA_IDENTIFIER_MASK GENMASK(31, 16)

drivers/dma/apple-admac.c

31

#define RING_WRITE_SLOT GENMASK(1, 0)

drivers/dma/apple-admac.c

32

#define RING_READ_SLOT GENMASK(5, 4)

drivers/dma/apple-admac.c

60

#define BUS_WIDTH_WORD_SIZE GENMASK(3, 0)

drivers/dma/apple-admac.c

61

#define BUS_WIDTH_FRAME_SIZE GENMASK(7, 4)

drivers/dma/apple-admac.c

69

#define CHAN_SRAM_CARVEOUT_SIZE GENMASK(31, 16)

drivers/dma/apple-admac.c

70

#define CHAN_SRAM_CARVEOUT_BASE GENMASK(15, 0)

drivers/dma/apple-admac.c

73

#define CHAN_FIFOCTL_LIMIT GENMASK(31, 16)

drivers/dma/apple-admac.c

74

#define CHAN_FIFOCTL_THRESHOLD GENMASK(15, 0)

drivers/dma/arm-dma350.c

101

#define CH_LINK_SHAREATTR GENMASK(9, 8)

drivers/dma/arm-dma350.c

102

#define CH_LINK_MEMATTR GENMASK(7, 0)

drivers/dma/arm-dma350.c

115

#define CH_CFG_INC_WIDTH GENMASK(29, 26)

drivers/dma/arm-dma350.c

116

#define CH_CFG_DATA_WIDTH GENMASK(24, 22)

drivers/dma/arm-dma350.c

117

#define CH_CFG_DATA_BUF_SIZE GENMASK(7, 0)

drivers/dma/arm-dma350.c

19

#define DMA_CFG_DATA_WIDTH GENMASK(18, 16)

drivers/dma/arm-dma350.c

20

#define DMA_CFG_ADDR_WIDTH GENMASK(15, 10)

drivers/dma/arm-dma350.c

21

#define DMA_CFG_NUM_CHANNELS GENMASK(9, 4)

drivers/dma/arm-dma350.c

24

#define DMA_CFG_NUM_TRIGGER_IN GENMASK(8, 0)

drivers/dma/arm-dma350.c

27

#define IIDR_PRODUCTID GENMASK(31, 20)

drivers/dma/arm-dma350.c

28

#define IIDR_VARIANT GENMASK(19, 16)

drivers/dma/arm-dma350.c

29

#define IIDR_REVISION GENMASK(15, 12)

drivers/dma/arm-dma350.c

30

#define IIDR_IMPLEMENTER GENMASK(11, 0)

drivers/dma/arm-dma350.c

62

#define CH_CTRL_DONETYPE GENMASK(23, 21)

drivers/dma/arm-dma350.c

63

#define CH_CTRL_REGRELOADTYPE GENMASK(20, 18)

drivers/dma/arm-dma350.c

64

#define CH_CTRL_XTYPE GENMASK(11, 9)

drivers/dma/arm-dma350.c

65

#define CH_CTRL_TRANSIZE GENMASK(2, 0)

drivers/dma/arm-dma350.c

75

#define CH_CFG_MAXBURSTLEN GENMASK(19, 16)

drivers/dma/arm-dma350.c

77

#define CH_CFG_SHAREATTR GENMASK(9, 8)

drivers/dma/arm-dma350.c

78

#define CH_CFG_MEMATTR GENMASK(7, 0)

drivers/dma/arm-dma350.c

94

#define CH_XY_DES GENMASK(31, 16)

drivers/dma/arm-dma350.c

95

#define CH_XY_SRC GENMASK(15, 0)

drivers/dma/at_hdmac.c

115

#define ATC_DSCR_IF GENMASK(1, 0) /* Dsc feched via AHB-Lite Interface */

drivers/dma/at_hdmac.c

118

#define ATC_BTSIZE_MAX GENMASK(15, 0) /* Maximum Buffer Transfer Size */

drivers/dma/at_hdmac.c

119

#define ATC_BTSIZE GENMASK(15, 0) /* Buffer Transfer Size */

drivers/dma/at_hdmac.c

120

#define ATC_SCSIZE GENMASK(18, 16) /* Source Chunk Transfer Size */

drivers/dma/at_hdmac.c

121

#define ATC_DCSIZE GENMASK(22, 20) /* Destination Chunk Transfer Size */

drivers/dma/at_hdmac.c

122

#define ATC_SRC_WIDTH GENMASK(25, 24) /* Source Single Transfer Size */

drivers/dma/at_hdmac.c

123

#define ATC_DST_WIDTH GENMASK(29, 28) /* Destination Single Transfer Size */

drivers/dma/at_hdmac.c

127

#define ATC_SIF GENMASK(1, 0) /* Src tx done via AHB-Lite Interface i */

drivers/dma/at_hdmac.c

128

#define ATC_DIF GENMASK(5, 4) /* Dst tx done via AHB-Lite Interface i */

drivers/dma/at_hdmac.c

135

#define ATC_FC GENMASK(23, 21) /* Choose Flow Controller */

drivers/dma/at_hdmac.c

144

#define ATC_SRC_ADDR_MODE GENMASK(25, 24)

drivers/dma/at_hdmac.c

148

#define ATC_DST_ADDR_MODE GENMASK(29, 28)

drivers/dma/at_hdmac.c

156

#define ATC_SRC_PER GENMASK(3, 0) /* Channel src rq associated with periph handshaking ifc h */

drivers/dma/at_hdmac.c

157

#define ATC_DST_PER GENMASK(7, 4) /* Channel dst rq associated with periph handshaking ifc h */

drivers/dma/at_hdmac.c

160

#define ATC_SRC_PER_MSB GENMASK(11, 10) /* Channel src rq (most significant bits) */

drivers/dma/at_hdmac.c

163

#define ATC_DST_PER_MSB GENMASK(15, 14) /* Channel dst rq (most significant bits) */

drivers/dma/at_hdmac.c

168

#define ATC_AHB_PROT GENMASK(26, 24) /* AHB Protection */

drivers/dma/at_hdmac.c

169

#define ATC_FIFOCFG GENMASK(29, 28) /* FIFO Request Configuration */

drivers/dma/at_hdmac.c

175

#define ATC_SPIP_HOLE GENMASK(15, 0)

drivers/dma/at_hdmac.c

176

#define ATC_SPIP_BOUNDARY GENMASK(25, 16)

drivers/dma/at_hdmac.c

179

#define ATC_DPIP_HOLE GENMASK(15, 0)

drivers/dma/at_hdmac.c

180

#define ATC_DPIP_BOUNDARY GENMASK(25, 16)

drivers/dma/at_hdmac.c

182

#define ATC_PER_MSB GENMASK(5, 4) /* Extract MSBs of a handshaking identifier */

drivers/dma/at_xdmac.c

103

#define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27)

drivers/dma/bcm-sba-raid.c

49

#define SBA_TYPE_MASK GENMASK(1, 0)

drivers/dma/bcm-sba-raid.c

54

#define SBA_USER_DEF_MASK GENMASK(15, 0)

drivers/dma/bcm-sba-raid.c

56

#define SBA_R_MDATA_MASK GENMASK(7, 0)

drivers/dma/bcm-sba-raid.c

58

#define SBA_C_MDATA_MS_MASK GENMASK(1, 0)

drivers/dma/bcm-sba-raid.c

64

#define SBA_C_MDATA_MASK GENMASK(7, 0)

drivers/dma/bcm-sba-raid.c

66

#define SBA_C_MDATA_BNUMx_MASK GENMASK(1, 0)

drivers/dma/bcm-sba-raid.c

68

#define SBA_C_MDATA_DNUM_MASK GENMASK(4, 0)

drivers/dma/bcm-sba-raid.c

72

#define SBA_CMD_MASK GENMASK(3, 0)

drivers/dma/cv1800b-dmamux.c

30

#define DMAMUX_CH_MASk GENMASK(5, 0)

drivers/dma/dma-axi-dmac.c

52

#define AXI_DMAC_DMA_SRC_TYPE_MSK GENMASK(13, 12)

drivers/dma/dma-axi-dmac.c

54

#define AXI_DMAC_DMA_SRC_WIDTH_MSK GENMASK(11, 8)

drivers/dma/dma-axi-dmac.c

56

#define AXI_DMAC_DMA_DST_TYPE_MSK GENMASK(5, 4)

drivers/dma/dma-axi-dmac.c

58

#define AXI_DMAC_DMA_DST_WIDTH_MSK GENMASK(3, 0)

drivers/dma/dma-jz4780.c

632

count += desc->desc[i].dtc & GENMASK(23, 0);

drivers/dma/dw-axi-dmac/dw-axi-dmac.h

390

DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)),

drivers/dma/dw-axi-dmac/dw-axi-dmac.h

391

DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)

drivers/dma/dw-edma/dw-edma-pcie.c

21

#define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8)

drivers/dma/dw-edma/dw-edma-pcie.c

22

#define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0)

drivers/dma/dw-edma/dw-edma-pcie.c

23

#define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0)

drivers/dma/dw-edma/dw-edma-pcie.c

24

#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16)

drivers/dma/dw-edma/dw-edma-v0-regs.h

15

#define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)

drivers/dma/dw-edma/dw-edma-v0-regs.h

16

#define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)

drivers/dma/dw-edma/dw-edma-v0-regs.h

17

#define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)

drivers/dma/dw-edma/dw-edma-v0-regs.h

18

#define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)

drivers/dma/dw-edma/dw-edma-v0-regs.h

19

#define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)

drivers/dma/dw-edma/dw-edma-v0-regs.h

20

#define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)

drivers/dma/dw-edma/dw-edma-v0-regs.h

21

#define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)

drivers/dma/dw-edma/dw-edma-v0-regs.h

22

#define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)

drivers/dma/dw-edma/dw-edma-v0-regs.h

24

#define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)

drivers/dma/dw-edma/dw-edma-v0-regs.h

25

#define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)

drivers/dma/dw-edma/dw-hdma-v0-regs.h

25

#define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)

drivers/dma/dw/idma32.c

20

#define CTL_CH_TRANSFER_MODE_MASK GENMASK(1, 0)

drivers/dma/dw/idma32.c

25

#define CTL_CH_RD_RS_MASK GENMASK(4, 3)

drivers/dma/dw/idma32.c

26

#define CTL_CH_WR_RS_MASK GENMASK(6, 5)

drivers/dma/dw/idma32.c

30

#define XBAR_SEL_DEVID_MASK GENMASK(15, 0)

drivers/dma/dw/idma32.c

34

#define REGACCESS_CHID_MASK GENMASK(2, 0)

drivers/dma/dw/regs.h

173

#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)

drivers/dma/dw/regs.h

235

#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)

drivers/dma/fsl-edma-common.h

23

#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))

drivers/dma/fsl-edma-common.h

24

#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))

drivers/dma/fsl-edma-common.h

25

#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))

drivers/dma/fsl-edma-common.h

26

#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))

drivers/dma/fsl-edma-common.h

28

#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))

drivers/dma/fsl-edma-common.h

29

#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)

drivers/dma/fsl-edma-common.h

30

#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)

drivers/dma/fsl-edma-common.h

31

#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)

drivers/dma/fsl-edma-common.h

33

#define EDMA_TCD_ITER_MASK GENMASK(14, 0)

drivers/dma/fsl-edma-common.h

46

#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))

drivers/dma/fsl-qdma.c

62

#define QDMA_SG_LEN_MASK GENMASK(29, 0)

drivers/dma/fsl-qdma.c

63

#define QDMA_CCDF_MASK GENMASK(28, 20)

drivers/dma/fsl-qdma.c

65

#define FSL_QDMA_DEDR_CLEAR GENMASK(31, 0)

drivers/dma/fsl-qdma.c

66

#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0)

drivers/dma/fsl-qdma.c

67

#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0)

drivers/dma/hisi_dma.c

114

#define OPCODE_MASK GENMASK(3, 0)

drivers/dma/hisi_dma.c

118

#define ATTR_SRC_MASK GENMASK(14, 12)

drivers/dma/hisi_dma.c

121

#define ATTR_DST_MASK GENMASK(26, 24)

drivers/dma/hisi_dma.c

134

#define STATUS_MASK GENMASK(15, 1)

drivers/dma/hisi_dma.c

28

#define HISI_DMA_Q_FSM_STS_MASK GENMASK(3, 0)

drivers/dma/hisi_dma.c

39

#define HISI_DMA_HIP08_Q_INT_STS_MASK GENMASK(14, 0)

drivers/dma/hisi_dma.c

50

#define HISI_DMA_HIP09_Q_CTRL0_ERR_ABORT_EN GENMASK(31, 28)

drivers/dma/hisi_dma.c

59

#define HISI_DMA_HIP09_Q_ERR_INT_STS_MASK GENMASK(18, 1)

drivers/dma/hsu/hsu.h

43

#define HSU_CH_SR_DESCTO_ANY GENMASK(11, 8)

drivers/dma/hsu/hsu.h

46

#define HSU_CH_SR_DESCE_ANY GENMASK(19, 16)

drivers/dma/hsu/hsu.h

47

#define HSU_CH_SR_CDESC_ANY GENMASK(31, 30)

drivers/dma/hsu/hsu.h

63

#define HSU_CH_DxTSR_MASK GENMASK(15, 0)

drivers/dma/idma64.c

175

if (status == GENMASK(31, 0))

drivers/dma/idxd/device.c

538

idxd->cmd_status = stat & GENMASK(7, 0);

drivers/dma/idxd/device.c

623

operand = idx & GENMASK(15, 0);

drivers/dma/idxd/device.c

636

*handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);

drivers/dma/idxd/device.c

655

operand = handle & GENMASK(15, 0);

drivers/dma/idxd/device.c

801

evlcfg.bits[0] = dma_addr & GENMASK(63, 12);

drivers/dma/idxd/sysfs.c

466

if (val & ~GENMASK(1, 0))

drivers/dma/idxd/sysfs.c

497

if (val & ~GENMASK(1, 0))

drivers/dma/imx-sdma.c

192

#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)

drivers/dma/imx-sdma.c

193

#define SDMA_WATERMARK_LEVEL_OFF_FIFOS GENMASK(19, 16)

drivers/dma/imx-sdma.c

194

#define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO GENMASK(31, 28)

drivers/dma/lgm/lgm-dma.c

102

#define DMA_C_DP_TICK_TIKNARB GENMASK(15, 0)

drivers/dma/lgm/lgm-dma.c

103

#define DMA_C_DP_TICK_TIKARB GENMASK(31, 16)

drivers/dma/lgm/lgm-dma.c

118

#define DMA_C_BOFF_BOF_LEN GENMASK(7, 0)

drivers/dma/lgm/lgm-dma.c

122

#define DMA_ORRC_ORRCNT GENMASK(8, 4)

drivers/dma/lgm/lgm-dma.c

126

#define DMA_C_END_DATAENDI GENMASK(1, 0)

drivers/dma/lgm/lgm-dma.c

128

#define DMA_C_END_DESENDI GENMASK(9, 8)

drivers/dma/lgm/lgm-dma.c

1633

d->channels_mask = GENMASK(d->chan_nrs - 1, 0);

drivers/dma/lgm/lgm-dma.c

164

#define DESC_DATA_LEN GENMASK(15, 0)

drivers/dma/lgm/lgm-dma.c

165

#define DESC_BYTE_OFF GENMASK(25, 23)

drivers/dma/lgm/lgm-dma.c

174

#define MASK_LOWER_CHANS GENMASK(4, 0)

drivers/dma/lgm/lgm-dma.c

176

#define HIGH_4_BITS GENMASK(3, 0)

drivers/dma/lgm/lgm-dma.c

28

#define DMA_ID_REV GENMASK(7, 0)

drivers/dma/lgm/lgm-dma.c

29

#define DMA_ID_PNR GENMASK(19, 16)

drivers/dma/lgm/lgm-dma.c

30

#define DMA_ID_CHNR GENMASK(26, 20)

drivers/dma/lgm/lgm-dma.c

46

#define DMA_CTRL_DESC_TMOUT_CNT_V31 GENMASK(27, 16)

drivers/dma/lgm/lgm-dma.c

51

#define DMA_CPOLL_CNT GENMASK(15, 4)

drivers/dma/lgm/lgm-dma.c

55

#define DMA_CS_MASK GENMASK(5, 0)

drivers/dma/lgm/lgm-dma.c

62

#define DMA_CDBA_MSB GENMASK(7, 4)

drivers/dma/lgm/lgm-dma.c

64

#define DMA_CCTRL_CLASS GENMASK(11, 9)

drivers/dma/lgm/lgm-dma.c

65

#define DMA_CCTRL_CLASSH GENMASK(19, 18)

drivers/dma/lgm/lgm-dma.c

86

#define DMA_PCTRL_RXBL GENMASK(3, 2)

drivers/dma/lgm/lgm-dma.c

88

#define DMA_PCTRL_TXBL GENMASK(5, 4)

drivers/dma/lgm/lgm-dma.c

92

#define DMA_PCTRL_RXENDI GENMASK(9, 8)

drivers/dma/lgm/lgm-dma.c

93

#define DMA_PCTRL_TXENDI GENMASK(11, 10)

drivers/dma/loongson1-apb-dma.c

39

#define LS1X_DMA_LLI_ADDR_MASK GENMASK(31, __ffs(LS1X_DMA_LLI_ALIGNMENT))

drivers/dma/loongson2-apb-dma.c

38

#define LDMA_DESC_ADDR_LOW GENMASK(31, 1)

drivers/dma/mcf-edma-main.c

15

#define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0))

drivers/dma/mediatek/mtk-cqdma.c

62

#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)

drivers/dma/mediatek/mtk-cqdma.c

63

#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)

drivers/dma/milbeaut-hdmac.c

25

#define MLB_HDMAC_DH GENMASK(27, 24)

drivers/dma/milbeaut-hdmac.c

33

#define MLB_HDMAC_IS GENMASK(28, 24)

drivers/dma/milbeaut-hdmac.c

34

#define MLB_HDMAC_BT GENMASK(23, 20)

drivers/dma/milbeaut-hdmac.c

35

#define MLB_HDMAC_BC GENMASK(19, 16)

drivers/dma/milbeaut-hdmac.c

36

#define MLB_HDMAC_TC GENMASK(15, 0)

drivers/dma/milbeaut-hdmac.c

38

#define MLB_HDMAC_TT GENMASK(31, 30)

drivers/dma/milbeaut-hdmac.c

39

#define MLB_HDMAC_MS GENMASK(29, 28)

drivers/dma/milbeaut-hdmac.c

40

#define MLB_HDMAC_TW GENMASK(27, 26)

drivers/dma/milbeaut-hdmac.c

49

#define MLB_HDMAC_SS GENMASK(18, 16)

drivers/dma/milbeaut-hdmac.c

50

#define MLB_HDMAC_SP GENMASK(15, 12)

drivers/dma/milbeaut-hdmac.c

51

#define MLB_HDMAC_DP GENMASK(11, 8)

drivers/dma/milbeaut-xdmac.c

40

#define M10V_XDSAC_SBS GENMASK(17, 16)

drivers/dma/milbeaut-xdmac.c

41

#define M10V_XDSAC_SBL GENMASK(11, 8)

drivers/dma/milbeaut-xdmac.c

43

#define M10V_XDDAC_DBS GENMASK(17, 16)

drivers/dma/milbeaut-xdmac.c

44

#define M10V_XDDAC_DBL GENMASK(11, 8)

drivers/dma/milbeaut-xdmac.c

49

#define M10V_XDDES_TF GENMASK(23, 20)

drivers/dma/milbeaut-xdmac.c

53

#define M10V_XDDSD_IS_MASK GENMASK(3, 0)

drivers/dma/owl-dma.c

100

#define OWL_DMA_LLC_DAV(x) (((x) & GENMASK(1, 0)) << 10)

drivers/dma/owl-dma.c

339

return lli->hw[OWL_DMADESC_FLEN] & GENMASK(19, 0);

drivers/dma/owl-dma.c

69

#define OWL_DMA_MODE_TS(x) (((x) & GENMASK(5, 0)) << 0)

drivers/dma/owl-dma.c

70

#define OWL_DMA_MODE_ST(x) (((x) & GENMASK(1, 0)) << 8)

drivers/dma/owl-dma.c

74

#define OWL_DMA_MODE_DT(x) (((x) & GENMASK(1, 0)) << 10)

drivers/dma/owl-dma.c

78

#define OWL_DMA_MODE_SAM(x) (((x) & GENMASK(1, 0)) << 16)

drivers/dma/owl-dma.c

82

#define OWL_DMA_MODE_DAM(x) (((x) & GENMASK(1, 0)) << 18)

drivers/dma/owl-dma.c

86

#define OWL_DMA_MODE_PW(x) (((x) & GENMASK(2, 0)) << 20)

drivers/dma/owl-dma.c

96

#define OWL_DMA_LLC_SAV(x) (((x) & GENMASK(1, 0)) << 8)

drivers/dma/qcom/gpi.c

108

#define GPII_n_EV_k_CNTXT_0_EL_SIZE GENMASK(31, 24)

drivers/dma/qcom/gpi.c

109

#define GPII_n_EV_k_CNTXT_0_CHSTATE GENMASK(23, 20)

drivers/dma/qcom/gpi.c

111

#define GPII_n_EV_k_CNTXT_0_CHTYPE GENMASK(3, 0)

drivers/dma/qcom/gpi.c

140

#define GPII_n_EV_CMD_OPCODE GENMASK(31, 24)

drivers/dma/qcom/gpi.c

141

#define GPII_n_EV_CMD_CHID GENMASK(7, 0)

drivers/dma/qcom/gpi.c

154

#define GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK GENMASK(6, 0)

drivers/dma/qcom/gpi.c

166

#define GPII_n_CNTXT_SRC_CH_IRQ_MSK_BMSK GENMASK(1, 0)

drivers/dma/qcom/gpi.c

190

#define GPII_n_CNTXT_GPII_IRQ_EN_BMSK GENMASK(3, 0)

drivers/dma/qcom/gpi.c

210

#define GPII_n_CH_k_SCRATCH_0_SEID GENMASK(2, 0)

drivers/dma/qcom/gpi.c

211

#define GPII_n_CH_k_SCRATCH_0_PROTO GENMASK(7, 4)

drivers/dma/qcom/gpi.c

212

#define GPII_n_CH_k_SCRATCH_0_PAIR GENMASK(20, 16)

drivers/dma/qcom/gpi.c

31

#define TRE_FLAGS_TYPE GENMASK(23, 16)

drivers/dma/qcom/gpi.c

34

#define TRE_SPI_C0_WORD_SZ GENMASK(4, 0)

drivers/dma/qcom/gpi.c

43

#define TRE_C0_CLK_DIV GENMASK(11, 0)

drivers/dma/qcom/gpi.c

44

#define TRE_C0_CLK_SRC GENMASK(19, 16)

drivers/dma/qcom/gpi.c

47

#define TRE_SPI_GO_CMD GENMASK(4, 0)

drivers/dma/qcom/gpi.c

48

#define TRE_SPI_GO_CS GENMASK(10, 8)

drivers/dma/qcom/gpi.c

52

#define TRE_RX_LEN GENMASK(23, 0)

drivers/dma/qcom/gpi.c

55

#define TRE_I2C_C0_TLOW GENMASK(7, 0)

drivers/dma/qcom/gpi.c

56

#define TRE_I2C_C0_THIGH GENMASK(15, 8)

drivers/dma/qcom/gpi.c

57

#define TRE_I2C_C0_TCYL GENMASK(23, 16)

drivers/dma/qcom/gpi.c

62

#define TRE_I2C_GO_CMD GENMASK(4, 0)

drivers/dma/qcom/gpi.c

63

#define TRE_I2C_GO_ADDR GENMASK(14, 8)

drivers/dma/qcom/gpi.c

67

#define TRE_DMA_LEN GENMASK(23, 0)

drivers/dma/qcom/gpi.c

68

#define TRE_DMA_IMMEDIATE_LEN GENMASK(3, 0)

drivers/dma/qcom/gpi.c

72

#define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24)

drivers/dma/qcom/gpi.c

73

#define GPII_n_CH_k_CNTXT_0_CHSTATE GENMASK(23, 20)

drivers/dma/qcom/gpi.c

74

#define GPII_n_CH_k_CNTXT_0_ERIDX GENMASK(18, 14)

drivers/dma/qcom/gpi.c

76

#define GPII_n_CH_k_CNTXT_0_PROTO GENMASK(2, 0)

drivers/dma/qcom/gpi.c

91

#define GPII_n_CH_CMD_OPCODE GENMASK(31, 24)

drivers/dma/qcom/gpi.c

92

#define GPII_n_CH_CMD_CHID GENMASK(7, 0)

drivers/dma/qcom/hidma_ll.c

47

#define HIDMA_EVRE_ERRINFO_MASK GENMASK(3, 0)

drivers/dma/qcom/hidma_ll.c

48

#define HIDMA_EVRE_CODE_MASK GENMASK(3, 0)

drivers/dma/qcom/hidma_ll.c

50

#define HIDMA_CH_CONTROL_MASK GENMASK(7, 0)

drivers/dma/qcom/hidma_ll.c

51

#define HIDMA_CH_STATE_MASK GENMASK(7, 0)

drivers/dma/qcom/hidma_ll.c

619

tre_local[HIDMA_TRE_CFG_IDX] &= ~GENMASK(7, 0);

drivers/dma/qcom/hidma_mgmt.c

28

#define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0)

drivers/dma/qcom/hidma_mgmt.c

29

#define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0)

drivers/dma/qcom/hidma_mgmt.c

30

#define HIDMA_WEIGHT_MASK GENMASK(6, 0)

drivers/dma/qcom/hidma_mgmt.c

31

#define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0)

drivers/dma/qcom/hidma_mgmt.c

32

#define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0)

drivers/dma/sf-pdma/sf-pdma.h

43

#define PDMA_CLAIM_MASK GENMASK(0, 0)

drivers/dma/sf-pdma/sf-pdma.h

44

#define PDMA_RUN_MASK GENMASK(1, 1)

drivers/dma/sf-pdma/sf-pdma.h

45

#define PDMA_ENABLE_DONE_INT_MASK GENMASK(14, 14)

drivers/dma/sf-pdma/sf-pdma.h

46

#define PDMA_ENABLE_ERR_INT_MASK GENMASK(15, 15)

drivers/dma/sf-pdma/sf-pdma.h

47

#define PDMA_DONE_STATUS_MASK GENMASK(30, 30)

drivers/dma/sf-pdma/sf-pdma.h

48

#define PDMA_ERR_STATUS_MASK GENMASK(31, 31)

drivers/dma/sh/rcar-dmac.c

1830

dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);

drivers/dma/sh/rcar-dmac.c

1834

dmac->channels_mask &= GENMASK(dmac->n_channels - 1, 0);

drivers/dma/sh/rz-dmac.c

158

#define CHCFG_FILL_DDS_MASK GENMASK(19, 16)

drivers/dma/sh/rz-dmac.c

159

#define CHCFG_FILL_SDS_MASK GENMASK(15, 12)

drivers/dma/sh/rz-dmac.c

161

#define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6)

drivers/dma/sh/rz-dmac.c

165

#define MID_RID_MASK GENMASK(9, 0)

drivers/dma/sh/rz-dmac.c

166

#define CHCFG_MASK GENMASK(15, 10)

drivers/dma/sprd-dma.c

100

#define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28)

drivers/dma/sprd-dma.c

101

#define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0)

drivers/dma/sprd-dma.c

102

#define SPRD_DMA_WRAP_ADDR_MASK GENMASK(27, 0)

drivers/dma/sprd-dma.c

121

#define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)

drivers/dma/sprd-dma.c

127

#define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)

drivers/dma/sprd-dma.c

130

#define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0)

drivers/dma/sprd-dma.c

133

#define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0)

drivers/dma/sprd-dma.c

138

#define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)

drivers/dma/sprd-dma.c

141

#define SPRD_DMA_LLIST_HIGH_MASK GENMASK(31, 28)

drivers/dma/sprd-dma.c

145

#define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)

drivers/dma/sprd-dma.c

146

#define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)

drivers/dma/sprd-dma.c

147

#define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0)

drivers/dma/sprd-dma.c

64

#define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)

drivers/dma/sprd-dma.c

72

#define SPRD_DMA_GLB_DEST_CHN_MASK GENMASK(13, 8)

drivers/dma/sprd-dma.c

74

#define SPRD_DMA_GLB_SRC_CHN_MASK GENMASK(5, 0)

drivers/dma/sprd-dma.c

77

#define SPRD_DMA_INT_MASK GENMASK(4, 0)

drivers/dma/st_fdma.h

174

#define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)

drivers/dma/st_fdma.h

179

#define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2)

drivers/dma/st_fdma.h

183

#define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5)

drivers/dma/st_fdma.h

219

#define FDMA_REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24)

drivers/dma/st_fdma.h

228

#define FDMA_REQ_CTRL_OPCODE_MASK GENMASK(7, 4)

drivers/dma/st_fdma.h

236

#define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)

drivers/dma/st_fdma.h

63

#define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)

drivers/dma/st_fdma.h

67

#define FDMA_NODE_CTRL_SRC_MASK GENMASK(6, 5)

drivers/dma/st_fdma.h

70

#define FDMA_NODE_CTRL_DST_MASK GENMASK(8, 7)

drivers/dma/stm32/stm32-dma.c

139

#define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)

drivers/dma/stm32/stm32-dma.c

142

#define STM32_DMA_MDMA_STREAM_ID_MASK GENMASK(19, 16)

drivers/dma/stm32/stm32-dma.c

57

#define STM32_DMA_SCR_REQ_MASK GENMASK(27, 25)

drivers/dma/stm32/stm32-dma.c

58

#define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)

drivers/dma/stm32/stm32-dma.c

59

#define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)

drivers/dma/stm32/stm32-dma.c

60

#define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)

drivers/dma/stm32/stm32-dma.c

61

#define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)

drivers/dma/stm32/stm32-dma.c

62

#define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)

drivers/dma/stm32/stm32-dma.c

63

#define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)

drivers/dma/stm32/stm32-dma.c

99

#define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)

drivers/dma/stm32/stm32-dma3.c

109

#define CCR_ALLIE GENMASK(13, 8)

drivers/dma/stm32/stm32-dma3.c

112

#define CCR_PRIO GENMASK(23, 22)

drivers/dma/stm32/stm32-dma3.c

123

#define CTR1_SBL_1 GENMASK(9, 4)

drivers/dma/stm32/stm32-dma3.c

125

#define CTR1_DBL_1 GENMASK(25, 20)

drivers/dma/stm32/stm32-dma3.c

126

#define CTR1_SDW_LOG2 GENMASK(1, 0)

drivers/dma/stm32/stm32-dma3.c

127

#define CTR1_PAM GENMASK(12, 11)

drivers/dma/stm32/stm32-dma3.c

129

#define CTR1_DDW_LOG2 GENMASK(17, 16)

drivers/dma/stm32/stm32-dma3.c

146

#define CTR2_REQSEL GENMASK(7, 0)

drivers/dma/stm32/stm32-dma3.c

151

#define CTR2_TCEM GENMASK(31, 30)

drivers/dma/stm32/stm32-dma3.c

161

#define CBR1_BNDT GENMASK(15, 0)

drivers/dma/stm32/stm32-dma3.c

164

#define CLLR_LA GENMASK(15, 2)

drivers/dma/stm32/stm32-dma3.c

183

#define G_MAX_REQ_ID GENMASK(7, 0)

drivers/dma/stm32/stm32-dma3.c

1846

if (chan_reserved == GENMASK(ddata->dma_channels - 1, 0)) {

drivers/dma/stm32/stm32-dma3.c

186

#define G_MASTER_PORTS GENMASK(2, 0)

drivers/dma/stm32/stm32-dma3.c

187

#define G_NUM_CHANNELS GENMASK(12, 8)

drivers/dma/stm32/stm32-dma3.c

188

#define G_M0_DATA_WIDTH_ENC GENMASK(25, 24)

drivers/dma/stm32/stm32-dma3.c

189

#define G_M1_DATA_WIDTH_ENC GENMASK(29, 28)

drivers/dma/stm32/stm32-dma3.c

208

#define VERR_MINREV GENMASK(3, 0)

drivers/dma/stm32/stm32-dma3.c

209

#define VERR_MAJREV GENMASK(7, 4)

drivers/dma/stm32/stm32-dma3.c

214

#define STM32_DMA3_DT_PRIO GENMASK(1, 0) /* CCR_PRIO */

drivers/dma/stm32/stm32-dma3.c

215

#define STM32_DMA3_DT_FIFO GENMASK(7, 4)

drivers/dma/stm32/stm32-dma3.c

223

#define STM32_DMA3_DT_TCEM GENMASK(13, 12) /* CTR2_TCEM */

drivers/dma/stm32/stm32-dma3.c

60

#define CLBAR_LBA GENMASK(31, 16)

drivers/dma/stm32/stm32-dma3.c

65

#define CCIDCFGR_SCID GENMASK(5, 4)

drivers/dma/stm32/stm32-dma3.c

78

#define CSEMCR_SEM_CCID GENMASK(5, 4)

drivers/dma/stm32/stm32-dma3.c

96

#define CSR_ALL_F GENMASK(13, 8)

drivers/dma/stm32/stm32-dma3.c

97

#define CSR_FIFOL GENMASK(24, 16)

drivers/dma/stm32/stm32-mdma.c

102

#define STM32_MDMA_CTCR_LEN2_MSK GENMASK(25, 18)

drivers/dma/stm32/stm32-mdma.c

105

#define STM32_MDMA_CTCR_DBURST_MASK GENMASK(17, 15)

drivers/dma/stm32/stm32-mdma.c

107

#define STM32_MDMA_CTCR_SBURST_MASK GENMASK(14, 12)

drivers/dma/stm32/stm32-mdma.c

109

#define STM32_MDMA_CTCR_DINCOS_MASK GENMASK(11, 10)

drivers/dma/stm32/stm32-mdma.c

111

#define STM32_MDMA_CTCR_SINCOS_MASK GENMASK(9, 8)

drivers/dma/stm32/stm32-mdma.c

113

#define STM32_MDMA_CTCR_DSIZE_MASK GENMASK(7, 6)

drivers/dma/stm32/stm32-mdma.c

115

#define STM32_MDMA_CTCR_SSIZE_MASK GENMASK(5, 4)

drivers/dma/stm32/stm32-mdma.c

117

#define STM32_MDMA_CTCR_DINC_MASK GENMASK(3, 2)

drivers/dma/stm32/stm32-mdma.c

119

#define STM32_MDMA_CTCR_SINC_MASK GENMASK(1, 0)

drivers/dma/stm32/stm32-mdma.c

130

#define STM32_MDMA_CBNDTR_BRC_MK GENMASK(31, 20)

drivers/dma/stm32/stm32-mdma.c

136

#define STM32_MDMA_CBNDTR_BNDT_MASK GENMASK(16, 0)

drivers/dma/stm32/stm32-mdma.c

147

#define STM32_MDMA_CBRUR_DUV_MASK GENMASK(31, 16)

drivers/dma/stm32/stm32-mdma.c

149

#define STM32_MDMA_CBRUR_SUV_MASK GENMASK(15, 0)

drivers/dma/stm32/stm32-mdma.c

159

#define STM32_MDMA_CTBR_TSEL_MASK GENMASK(5, 0)

drivers/dma/stm32/stm32-mdma.c

66

#define STM32_MDMA_CESR_TEA_MASK GENMASK(6, 0)

drivers/dma/stm32/stm32-mdma.c

75

#define STM32_MDMA_CCR_PL_MASK GENMASK(7, 6)

drivers/dma/stm32/stm32-mdma.c

93

#define STM32_MDMA_CTCR_TRGM_MSK GENMASK(29, 28)

drivers/dma/stm32/stm32-mdma.c

96

#define STM32_MDMA_CTCR_PAM_MASK GENMASK(27, 26)

drivers/dma/stm32/stm32-mdma.c

99

#define STM32_MDMA_CTCR_TLEN_MSK GENMASK(24, 18)

drivers/dma/tegra186-gpc-dma.c

100

#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)

drivers/dma/tegra186-gpc-dma.c

101

#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)

drivers/dma/tegra186-gpc-dma.c

106

#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)

drivers/dma/tegra186-gpc-dma.c

118

(GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)

drivers/dma/tegra186-gpc-dma.c

119

#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)

drivers/dma/tegra186-gpc-dma.c

120

#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)

drivers/dma/tegra186-gpc-dma.c

121

#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)

drivers/dma/tegra186-gpc-dma.c

30

#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)

drivers/dma/tegra186-gpc-dma.c

40

#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)

drivers/dma/tegra186-gpc-dma.c

54

#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)

drivers/dma/tegra186-gpc-dma.c

58

#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)

drivers/dma/tegra186-gpc-dma.c

84

#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)

drivers/dma/tegra186-gpc-dma.c

85

#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)

drivers/dma/tegra186-gpc-dma.c

90

#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)

drivers/dma/tegra186-gpc-dma.c

91

#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)

drivers/dma/tegra186-gpc-dma.c

96

#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)

drivers/dma/tegra186-gpc-dma.c

97

#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)

drivers/dma/ti/k3-udma-glue.c

1574

*addr &= (u64)GENMASK(K3_ADDRESS_ASEL_SHIFT - 1, 0);

drivers/dma/ti/k3-udma-glue.c

668

*addr &= (u64)GENMASK(K3_ADDRESS_ASEL_SHIFT - 1, 0);

drivers/dma/ti/k3-udma.c

4301

.statictr_z_mask = GENMASK(11, 0),

drivers/dma/ti/k3-udma.c

4313

.statictr_z_mask = GENMASK(11, 0),

drivers/dma/ti/k3-udma.c

4326

.statictr_z_mask = GENMASK(23, 0),

drivers/dma/ti/k3-udma.c

4339

.statictr_z_mask = GENMASK(23, 0),

drivers/dma/ti/k3-udma.c

4380

.statictr_z_mask = GENMASK(23, 0),

drivers/dma/ti/k3-udma.c

4393

.statictr_z_mask = GENMASK(23, 0),

drivers/dma/ti/k3-udma.h

78

#define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)

drivers/dma/ti/k3-udma.h

80

#define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)

drivers/dma/uniphier-xdmac.c

23

#define XDMAC_TFA_MCNT_MASK GENMASK(23, 16)

drivers/dma/uniphier-xdmac.c

24

#define XDMAC_TFA_MASK GENMASK(5, 0)

drivers/dma/uniphier-xdmac.c

26

#define XDMAC_SADM_STW_MASK GENMASK(25, 24)

drivers/dma/uniphier-xdmac.c

40

#define XDMAC_ITS_MASK GENMASK(25, 0)

drivers/dma/uniphier-xdmac.c

42

#define XDMAC_TNUM_MASK GENMASK(15, 0)

drivers/dma/uniphier-xdmac.c

62

#define XDMAC_MAX_WORD_SIZE (XDMAC_ITS_MASK & ~GENMASK(3, 0))

drivers/dma/xilinx/xdma-regs.h

106

#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)

drivers/dma/xilinx/xdma-regs.h

107

#define CHAN_CTRL_IE_WRITE_ERROR GENMASK(18, 14)

drivers/dma/xilinx/xdma-regs.h

108

#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)

drivers/dma/xilinx/xdma-regs.h

32

#define XDMA_DESC_ADJACENT_BITS GENMASK(13, 8)

drivers/dma/xilinx/xdma-regs.h

34

#define XDMA_DESC_MAGIC_BITS GENMASK(31, 16)

drivers/dma/xilinx/xdma-regs.h

35

#define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)

drivers/dma/xilinx/xilinx_dma.c

109

#define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)

drivers/dma/xilinx/xilinx_dma.c

111

#define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)

drivers/dma/xilinx/xilinx_dma.c

116

#define XILINX_DMA_VSIZE_MASK GENMASK(12, 0)

drivers/dma/xilinx/xilinx_dma.c

118

#define XILINX_DMA_HSIZE_MASK GENMASK(15, 0)

drivers/dma/xilinx/xilinx_dma.c

179

#define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)

drivers/dma/xilinx/xilinx_dma.c

180

#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24)

drivers/dma/xilinx/xilinx_dma.c

216

#define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5)

drivers/dma/xilinx/xilinx_dma.c

217

#define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16)

drivers/dma/xilinx/xilinx_dma.c

3229

xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);

drivers/dma/xilinx/xilinx_dma.c

3244

GENMASK(len_width - 1, 0);

drivers/dma/xilinx/xilinx_dma.c

77

#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)

drivers/dma/xilinx/xilinx_dma.c

78

#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)

drivers/dma/xilinx/xilinx_dma.c

79

#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)

drivers/dma/xilinx/xilinx_dma.c

80

#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)

drivers/dma/xilinx/xilinx_dma.c

98

#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)

drivers/dma/xilinx/xilinx_dma.c

99

#define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)

drivers/dma/xilinx/xilinx_dpdma.c

108

#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)

drivers/dma/xilinx/xilinx_dpdma.c

109

#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)

drivers/dma/xilinx/xilinx_dpdma.c

110

#define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)

drivers/dma/xilinx/xilinx_dpdma.c

113

#define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)

drivers/dma/xilinx/xilinx_dpdma.c

117

#define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)

drivers/dma/xilinx/xilinx_dpdma.c

128

#define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)

drivers/dma/xilinx/xilinx_dpdma.c

129

#define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)

drivers/dma/xilinx/xilinx_dpdma.c

130

#define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)

drivers/dma/xilinx/xilinx_dpdma.c

131

#define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)

drivers/dma/xilinx/xilinx_dpdma.c

132

#define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)

drivers/dma/xilinx/xilinx_dpdma.c

40

#define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)

drivers/dma/xilinx/xilinx_dpdma.c

42

#define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)

drivers/dma/xilinx/xilinx_dpdma.c

44

#define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)

drivers/dma/xilinx/xilinx_dpdma.c

46

#define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)

drivers/dma/xilinx/xilinx_dpdma.c

529

addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);

drivers/dma/xilinx/xilinx_dpdma.c

64

#define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)

drivers/dma/xilinx/xilinx_dpdma.c

66

#define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)

drivers/dma/xilinx/xilinx_dpdma.c

68

#define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)

drivers/dma/xilinx/xilinx_dpdma.c

70

#define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)

drivers/dma/xilinx/xilinx_dpdma.c

72

#define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)

drivers/dma/xilinx/xilinx_dpdma.c

99

#define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)

drivers/dma/xilinx/zynqmp_dma.c

69

#define ZYNQMP_DMA_SRC_ISSUE GENMASK(4, 0)

drivers/dma/xilinx/zynqmp_dma.c

72

#define ZYNQMP_DMA_ARBURST GENMASK(27, 26)

drivers/dma/xilinx/zynqmp_dma.c

73

#define ZYNQMP_DMA_ARCACHE GENMASK(25, 22)

drivers/dma/xilinx/zynqmp_dma.c

75

#define ZYNQMP_DMA_ARQOS GENMASK(21, 18)

drivers/dma/xilinx/zynqmp_dma.c

77

#define ZYNQMP_DMA_ARLEN GENMASK(17, 14)

drivers/dma/xilinx/zynqmp_dma.c

79

#define ZYNQMP_DMA_AWBURST GENMASK(13, 12)

drivers/dma/xilinx/zynqmp_dma.c

80

#define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)

drivers/dma/xilinx/zynqmp_dma.c

82

#define ZYNQMP_DMA_AWQOS GENMASK(7, 4)

drivers/dma/xilinx/zynqmp_dma.c

84

#define ZYNQMP_DMA_AWLEN GENMASK(3, 0)

drivers/dma/xilinx/zynqmp_dma.c

89

#define ZYNQMP_DMA_AXCACHE GENMASK(7, 4)

drivers/dma/xilinx/zynqmp_dma.c

91

#define ZYNQMP_DMA_AXQOS GENMASK(3, 0)

drivers/dpll/zl3073x/core.c

100

#define ZL_PAGE_SEL_MASK GENMASK(7, 0)

drivers/dpll/zl3073x/core.c

1041

FIELD_GET(GENMASK(31, 24), cfg_ver),

drivers/dpll/zl3073x/core.c

1042

FIELD_GET(GENMASK(23, 16), cfg_ver),

drivers/dpll/zl3073x/core.c

1043

FIELD_GET(GENMASK(15, 8), cfg_ver),

drivers/dpll/zl3073x/core.c

1044

FIELD_GET(GENMASK(7, 0), cfg_ver));

drivers/dpll/zl3073x/core.c

684

GENMASK(7, 0)); /* REF0P..REF3N */

drivers/dpll/zl3073x/core.c

688

GENMASK(1, 0)); /* REF4P..REF4N */

drivers/dpll/zl3073x/devlink.c

76

FIELD_GET(GENMASK(31, 24), cfg_ver),

drivers/dpll/zl3073x/devlink.c

77

FIELD_GET(GENMASK(23, 16), cfg_ver),

drivers/dpll/zl3073x/devlink.c

78

FIELD_GET(GENMASK(15, 8), cfg_ver),

drivers/dpll/zl3073x/devlink.c

79

FIELD_GET(GENMASK(7, 0), cfg_ver));

drivers/dpll/zl3073x/flash.c

546

HWREG_SEQ_ITEM(0x10000000, 1, GENMASK(10, 9), 0),

drivers/dpll/zl3073x/regs.h

100

#define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4)

drivers/dpll/zl3073x/regs.h

114

#define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0)

drivers/dpll/zl3073x/regs.h

127

#define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX GENMASK(6, 4)

drivers/dpll/zl3073x/regs.h

138

#define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0)

drivers/dpll/zl3073x/regs.h

144

#define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4)

drivers/dpll/zl3073x/regs.h

148

#define ZL_DPLL_MEAS_CTRL_AVG_FACTOR GENMASK(7, 4)

drivers/dpll/zl3073x/regs.h

151

#define ZL_DPLL_MEAS_IDX GENMASK(2, 0)

drivers/dpll/zl3073x/regs.h

165

#define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4)

drivers/dpll/zl3073x/regs.h

175

#define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4)

drivers/dpll/zl3073x/regs.h

200

#define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0)

drivers/dpll/zl3073x/regs.h

219

#define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0)

drivers/dpll/zl3073x/regs.h

220

#define ZL_DPLL_REF_PRIO_REF_N GENMASK(7, 4)

drivers/dpll/zl3073x/regs.h

24

#define ZL_REG_OFFSET_MASK GENMASK(6, 0)

drivers/dpll/zl3073x/regs.h

249

#define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0)

drivers/dpll/zl3073x/regs.h

25

#define ZL_REG_PAGE_MASK GENMASK(15, 7)

drivers/dpll/zl3073x/regs.h

252

#define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4)

drivers/dpll/zl3073x/regs.h

26

#define ZL_REG_SIZE_MASK GENMASK(18, 16)

drivers/dpll/zl3073x/regs.h

27

#define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19)

drivers/dpll/zl3073x/regs.h

28

#define ZL_REG_ADDR_MASK GENMASK(15, 0)

drivers/dpll/zl3073x/regs.h

299

#define ZL_WRITE_FLASH_OP GENMASK(2, 0)

drivers/dpll/zl3073x/regs.h

306

#define ZL_FLASH_INFO_SECTOR_SIZE GENMASK(3, 0)

drivers/dpll/zl3073x/regs.h

91

#define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0)

drivers/dpll/zl3073x/regs.h

99

#define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0)

drivers/edac/a72_edac.c

25

#define CPUMERRSR_EL1_RAMID GENMASK(30, 24)

drivers/edac/a72_edac.c

26

#define L2MERRSR_EL1_CPUID_WAY GENMASK(21, 18)

drivers/edac/al_mc_edac.c

36

#define AL_MC_ECC_ERR_COUNT_UE GENMASK(31, 16)

drivers/edac/al_mc_edac.c

37

#define AL_MC_ECC_ERR_COUNT_CE GENMASK(15, 0)

drivers/edac/al_mc_edac.c

39

#define AL_MC_ECC_CE_ADDR0_RANK GENMASK(25, 24)

drivers/edac/al_mc_edac.c

40

#define AL_MC_ECC_CE_ADDR0_ROW GENMASK(17, 0)

drivers/edac/al_mc_edac.c

42

#define AL_MC_ECC_CE_ADDR1_BG GENMASK(25, 24)

drivers/edac/al_mc_edac.c

43

#define AL_MC_ECC_CE_ADDR1_BANK GENMASK(18, 16)

drivers/edac/al_mc_edac.c

44

#define AL_MC_ECC_CE_ADDR1_COLUMN GENMASK(11, 0)

drivers/edac/al_mc_edac.c

46

#define AL_MC_ECC_UE_ADDR0_RANK GENMASK(25, 24)

drivers/edac/al_mc_edac.c

47

#define AL_MC_ECC_UE_ADDR0_ROW GENMASK(17, 0)

drivers/edac/al_mc_edac.c

49

#define AL_MC_ECC_UE_ADDR1_BG GENMASK(25, 24)

drivers/edac/al_mc_edac.c

50

#define AL_MC_ECC_UE_ADDR1_BANK GENMASK(18, 16)

drivers/edac/al_mc_edac.c

51

#define AL_MC_ECC_UE_ADDR1_COLUMN GENMASK(11, 0)

drivers/edac/amd64_edac.c

1259

deinterleaved_mask = GENMASK(msb - num_zero_bits, 1);

drivers/edac/amd64_edac.c

1570

if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {

drivers/edac/amd64_edac.c

2804

err->channel = (m->ipid & GENMASK(31, 0)) >> 20;

drivers/edac/amd64_edac.c

2839

err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);

drivers/edac/amd64_edac.c

3519

u8 ch = (m->ipid & GENMASK(31, 0)) >> 20;

drivers/edac/amd64_edac.c

998

#define LNTM_NODE_COUNT GENMASK(27, 16)

drivers/edac/amd64_edac.c

999

#define LNTM_BASE_NODE_ID GENMASK(11, 0)

drivers/edac/aspeed_edac.c

33

#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)

drivers/edac/aspeed_edac.c

34

#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)

drivers/edac/bluefield_edac.c

25

#define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)

drivers/edac/bluefield_edac.c

26

#define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)

drivers/edac/bluefield_edac.c

42

#define MLXBF_SYNDROM__SYN GENMASK(25, 16)

drivers/edac/bluefield_edac.c

45

#define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)

drivers/edac/dmc520_edac.c

54

#define MEMORY_WIDTH_MASK GENMASK(1, 0)

drivers/edac/dmc520_edac.c

55

#define SCRUB_TRIGGER0_NEXT_MASK GENMASK(1, 0)

drivers/edac/dmc520_edac.c

56

#define REG_FIELD_DRAM_ECC_ENABLED GENMASK(1, 0)

drivers/edac/dmc520_edac.c

57

#define REG_FIELD_MEMORY_TYPE GENMASK(2, 0)

drivers/edac/dmc520_edac.c

58

#define REG_FIELD_DEVICE_WIDTH GENMASK(9, 8)

drivers/edac/dmc520_edac.c

59

#define REG_FIELD_ADDRESS_CONTROL_COL GENMASK(2, 0)

drivers/edac/dmc520_edac.c

60

#define REG_FIELD_ADDRESS_CONTROL_ROW GENMASK(10, 8)

drivers/edac/dmc520_edac.c

61

#define REG_FIELD_ADDRESS_CONTROL_BANK GENMASK(18, 16)

drivers/edac/dmc520_edac.c

62

#define REG_FIELD_ADDRESS_CONTROL_RANK GENMASK(25, 24)

drivers/edac/dmc520_edac.c

64

#define REG_FIELD_ERR_INFO_LOW_COL GENMASK(10, 1)

drivers/edac/dmc520_edac.c

65

#define REG_FIELD_ERR_INFO_LOW_ROW GENMASK(28, 11)

drivers/edac/dmc520_edac.c

66

#define REG_FIELD_ERR_INFO_LOW_RANK GENMASK(31, 29)

drivers/edac/dmc520_edac.c

67

#define REG_FIELD_ERR_INFO_HIGH_BANK GENMASK(3, 0)

drivers/edac/ie31200_edac.c

679

.reg_mad_dimm_size_mask[0] = GENMASK(7, 0),

drivers/edac/ie31200_edac.c

680

.reg_mad_dimm_size_mask[1] = GENMASK(15, 8),

drivers/edac/ie31200_edac.c

701

.reg_mad_dimm_size_mask[0] = GENMASK(5, 0),

drivers/edac/ie31200_edac.c

702

.reg_mad_dimm_size_mask[1] = GENMASK(21, 16),

drivers/edac/ie31200_edac.c

705

.reg_mad_dimm_width_mask[0] = GENMASK(9, 8),

drivers/edac/ie31200_edac.c

706

.reg_mad_dimm_width_mask[1] = GENMASK(25, 24),

drivers/edac/ie31200_edac.c

727

.reg_mad_dimm_size_mask[0] = GENMASK(6, 0),

drivers/edac/ie31200_edac.c

728

.reg_mad_dimm_size_mask[1] = GENMASK(22, 16),

drivers/edac/ie31200_edac.c

729

.reg_mad_dimm_rank_mask[0] = GENMASK(10, 9),

drivers/edac/ie31200_edac.c

730

.reg_mad_dimm_rank_mask[1] = GENMASK(27, 26),

drivers/edac/ie31200_edac.c

731

.reg_mad_dimm_width_mask[0] = GENMASK(8, 7),

drivers/edac/ie31200_edac.c

732

.reg_mad_dimm_width_mask[1] = GENMASK(25, 24),

drivers/edac/igen6_edac.c

1248

igen6_tolud &= GENMASK(31, 20);

drivers/edac/npcm_edac.c

449

.int_status_ce_mask = GENMASK(4, 3),

drivers/edac/npcm_edac.c

450

.int_status_ue_mask = GENMASK(6, 5),

drivers/edac/npcm_edac.c

451

.int_ack_ce_mask = GENMASK(4, 3),

drivers/edac/npcm_edac.c

452

.int_ack_ue_mask = GENMASK(6, 5),

drivers/edac/npcm_edac.c

453

.int_mask_master_non_ecc_mask = GENMASK(30, 7) | GENMASK(2, 0),

drivers/edac/npcm_edac.c

455

.ce_synd_mask = GENMASK(6, 0),

drivers/edac/npcm_edac.c

457

.ue_synd_mask = GENMASK(6, 0),

drivers/edac/npcm_edac.c

459

.source_id_ce_mask = GENMASK(29, 16),

drivers/edac/npcm_edac.c

461

.source_id_ue_mask = GENMASK(13, 0),

drivers/edac/npcm_edac.c

489

.ecc_en_mask = GENMASK(17, 16),

drivers/edac/npcm_edac.c

490

.int_status_ce_mask = GENMASK(1, 0),

drivers/edac/npcm_edac.c

491

.int_status_ue_mask = GENMASK(3, 2),

drivers/edac/npcm_edac.c

492

.int_ack_ce_mask = GENMASK(1, 0),

drivers/edac/npcm_edac.c

493

.int_ack_ue_mask = GENMASK(3, 2),

drivers/edac/npcm_edac.c

494

.int_mask_master_non_ecc_mask = GENMASK(30, 3) | GENMASK(1, 0),

drivers/edac/npcm_edac.c

496

.int_mask_ecc_non_event_mask = GENMASK(8, 4),

drivers/edac/npcm_edac.c

497

.ce_addr_h_mask = GENMASK(1, 0),

drivers/edac/npcm_edac.c

498

.ce_synd_mask = GENMASK(15, 8),

drivers/edac/npcm_edac.c

500

.ue_addr_h_mask = GENMASK(1, 0),

drivers/edac/npcm_edac.c

501

.ue_synd_mask = GENMASK(15, 8),

drivers/edac/npcm_edac.c

503

.source_id_ce_mask = GENMASK(29, 16),

drivers/edac/npcm_edac.c

505

.source_id_ue_mask = GENMASK(13, 0),

drivers/edac/npcm_edac.c

508

.xor_check_bits_mask = GENMASK(23, 16),

drivers/edac/pnd2_edac.c

187

ret = (status >> 1) & GENMASK(1, 0);

drivers/edac/qcom_edac.c

24

#define LLCC_LB_CNT_MASK GENMASK(31, 28)

drivers/edac/qcom_edac.c

28

#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)

drivers/edac/qcom_edac.c

29

#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)

drivers/edac/qcom_edac.c

32

#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)

drivers/edac/qcom_edac.c

34

#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)

drivers/edac/qcom_edac.c

39

#define DRP_TRP_INT_CLEAR GENMASK(1, 0)

drivers/edac/qcom_edac.c

40

#define DRP_TRP_CNT_CLEAR GENMASK(1, 0)

drivers/edac/thunderx_edac.c

1027

#define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))

drivers/edac/thunderx_edac.c

1028

#define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))

drivers/edac/thunderx_edac.c

1029

#define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \

drivers/edac/thunderx_edac.c

1030

GENMASK(9, 7) | GENMASK(5, 0))

drivers/edac/thunderx_edac.c

148

#define LMC_INT_ENA_ALL GENMASK(5, 0)

drivers/edac/thunderx_edac.c

30

#define THUNDERX_NODE GENMASK(45, 44)

drivers/edac/thunderx_edac.c

836

#define OCX_COM_RX_LANE GENMASK(23, 0)

drivers/edac/ti_edac.c

42

#define SDRAM_TYPE_MASK GENMASK(31, 29)

drivers/edac/ti_edac.c

45

#define SDRAM_NARROW_MODE_MASK GENMASK(15, 14)

drivers/edac/ti_edac.c

47

#define SDRAM_K2_NARROW_MODE_MASK GENMASK(13, 12)

drivers/edac/ti_edac.c

49

#define SDRAM_ROWSIZE_MASK GENMASK(9, 7)

drivers/edac/ti_edac.c

51

#define SDRAM_IBANK_MASK GENMASK(6, 4)

drivers/edac/ti_edac.c

53

#define SDRAM_K2_IBANK_MASK GENMASK(6, 5)

drivers/edac/ti_edac.c

57

#define SDRAM_PAGESIZE_MASK GENMASK(2, 0)

drivers/edac/ti_edac.c

59

#define SDRAM_K2_PAGESIZE_MASK GENMASK(1, 0)

drivers/edac/versal_edac.c

101

#define XDDR_NOC_ROW_MATCH_MASK GENMASK(17, 0)

drivers/edac/versal_edac.c

102

#define XDDR_NOC_COL_MATCH_MASK GENMASK(27, 18)

drivers/edac/versal_edac.c

103

#define XDDR_NOC_BANK_MATCH_MASK GENMASK(29, 28)

drivers/edac/versal_edac.c

104

#define XDDR_NOC_GRP_MATCH_MASK GENMASK(31, 30)

drivers/edac/versal_edac.c

107

#define XDDR_NOC_RANK_MATCH_MASK GENMASK(1, 0)

drivers/edac/versal_edac.c

108

#define XDDR_NOC_LRANK_MATCH_MASK GENMASK(4, 2)

drivers/edac/versal_edac.c

113

#define ECCR_UE_CE_ADDR_HI_ROW_MASK GENMASK(7, 0)

drivers/edac/versal_edac.c

31

#define XDDR_IRQ_CE_MASK GENMASK(18, 15)

drivers/edac/versal_edac.c

32

#define XDDR_IRQ_UE_MASK GENMASK(14, 11)

drivers/edac/versal_edac.c

35

#define XDDR_REG_CONFIG0_BUS_WIDTH_MASK GENMASK(19, 18)

drivers/edac/versal_edac.c

37

#define XDDR_REG_CONFIG0_NUM_RANKS_MASK GENMASK(15, 14)

drivers/edac/versal_edac.c

38

#define XDDR_REG_CONFIG0_SIZE_MASK GENMASK(10, 8)

drivers/edac/versal_edac.c

41

#define XDDR_REG_PINOUT_ECC_EN_MASK GENMASK(7, 5)

drivers/edac/versal_edac.c

79

#define RANK_1_MASK GENMASK(11, 6)

drivers/edac/versal_edac.c

80

#define LRANK_0_MASK GENMASK(17, 12)

drivers/edac/versal_edac.c

81

#define LRANK_1_MASK GENMASK(23, 18)

drivers/edac/versal_edac.c

82

#define MASK_24 GENMASK(29, 24)

drivers/edac/versal_edac.c

92

#define MASK_0 GENMASK(5, 0)

drivers/edac/versal_edac.c

93

#define GRP_0_MASK GENMASK(11, 6)

drivers/edac/versal_edac.c

94

#define GRP_1_MASK GENMASK(17, 12)

drivers/edac/versal_edac.c

95

#define CH_0_MASK GENMASK(23, 18)

drivers/edac/versalnet_edac.c

23

#define MC5_IRQ_CE_MASK GENMASK(18, 15)

drivers/edac/versalnet_edac.c

24

#define MC5_IRQ_UE_MASK GENMASK(14, 11)

drivers/edac/versalnet_edac.c

26

#define MC5_RANK_1_MASK GENMASK(11, 6)

drivers/edac/versalnet_edac.c

27

#define MASK_24 GENMASK(29, 24)

drivers/edac/versalnet_edac.c

28

#define MASK_0 GENMASK(5, 0)

drivers/edac/versalnet_edac.c

30

#define MC5_LRANK_1_MASK GENMASK(11, 6)

drivers/edac/versalnet_edac.c

31

#define MC5_LRANK_2_MASK GENMASK(17, 12)

drivers/edac/versalnet_edac.c

32

#define MC5_BANK1_MASK GENMASK(11, 6)

drivers/edac/versalnet_edac.c

33

#define MC5_GRP_0_MASK GENMASK(17, 12)

drivers/edac/versalnet_edac.c

34

#define MC5_GRP_1_MASK GENMASK(23, 18)

drivers/edac/versalnet_edac.c

41

#define MC5_MEM_MASK GENMASK(19, 0)

drivers/edac/versalnet_edac.c

48

#define MC5_ILC_MEM GENMASK(27, 0)

drivers/edac/versalnet_edac.c

49

#define MC5_INTERLEAVE_SEL GENMASK(3, 0)

drivers/edac/versalnet_edac.c

50

#define MC5_BUS_WIDTH_MASK GENMASK(19, 18)

drivers/edac/versalnet_edac.c

52

#define MC5_RANK_MASK GENMASK(15, 14)

drivers/edac/zynqmp_edac.c

67

#define OCM_FICOUNT_MASK GENMASK(23, 0)

drivers/extcon/extcon-axp288.c

143

bits = val & GENMASK(ARRAY_SIZE(axp288_pwr_up_down_info) - 1, 0);

drivers/extcon/extcon-intel-cht-wc.c

49

#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)

drivers/extcon/extcon-intel-cht-wc.c

53

#define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)

drivers/extcon/extcon-intel-cht-wc.c

78

#define CHT_WC_PWRSRC_USBID_MASK GENMASK(4, 3)

drivers/extcon/extcon-intel-mrfld.c

27

#define BCOVE_USBIDSTS_RARBRC_MASK GENMASK(2, 1)

drivers/extcon/extcon-lc824206xa.c

42

#define STATUS_USB_ID GENMASK(7, 3)

drivers/extcon/extcon-lc824206xa.c

71

#define INTR_ALL GENMASK(6, 0)

drivers/extcon/extcon-ptn5150.c

38

#define PTN5150_REG_DEVICE_ID_VERSION GENMASK(7, 3)

drivers/extcon/extcon-ptn5150.c

39

#define PTN5150_REG_DEVICE_ID_VENDOR GENMASK(2, 0)

drivers/extcon/extcon-ptn5150.c

41

#define PTN5150_REG_CC_PORT_ATTACHMENT GENMASK(4, 2)

drivers/extcon/extcon-usbc-tusb320.c

23

#define TUSB320_REG8_CURRENT_MODE_ADVERTISE GENMASK(7, 6)

drivers/extcon/extcon-usbc-tusb320.c

27

#define TUSB320_REG8_CURRENT_MODE_DETECT GENMASK(5, 4)

drivers/extcon/extcon-usbc-tusb320.c

32

#define TUSB320_REG8_ACCESSORY_CONNECTED GENMASK(3, 1)

drivers/extcon/extcon-usbc-tusb320.c

41

#define TUSB320_REG9_ATTACHED_STATE GENMASK(7, 6)

drivers/firmware/arm_ffa/driver.c

314

#define LAST_INDEX_MASK GENMASK(15, 0)

drivers/firmware/arm_ffa/driver.c

315

#define CURRENT_INDEX_MASK GENMASK(31, 16)

drivers/firmware/arm_ffa/driver.c

316

#define UUID_INFO_TAG_MASK GENMASK(47, 32)

drivers/firmware/arm_ffa/driver.c

317

#define PARTITION_INFO_SZ_MASK GENMASK(63, 48)

drivers/firmware/arm_ffa/driver.c

322

#define PART_INFO_ID_MASK GENMASK(15, 0)

drivers/firmware/arm_ffa/driver.c

323

#define PART_INFO_EXEC_CXT_MASK GENMASK(31, 16)

drivers/firmware/arm_ffa/driver.c

324

#define PART_INFO_PROPS_MASK GENMASK(63, 32)

drivers/firmware/arm_ffa/driver.c

433

#define VM_ID_MASK GENMASK(15, 0)

drivers/firmware/arm_ffa/driver.c

50

#define SENDER_ID_MASK GENMASK(31, 16)

drivers/firmware/arm_ffa/driver.c

51

#define RECEIVER_ID_MASK GENMASK(15, 0)

drivers/firmware/arm_ffa/driver.c

57

#define RXTX_MAP_MIN_BUFSZ_MASK GENMASK(1, 0)

drivers/firmware/arm_ffa/driver.c

839

#define NOTIFICATION_LOW_MASK GENMASK(31, 0)

drivers/firmware/arm_ffa/driver.c

840

#define NOTIFICATION_HIGH_MASK GENMASK(63, 32)

drivers/firmware/arm_ffa/driver.c

849

#define RECEIVER_VCPU_MASK GENMASK(31, 16)

drivers/firmware/arm_ffa/driver.c

855

#define NOTIFICATION_INFO_GET_ID_COUNT GENMASK(11, 7)

drivers/firmware/arm_ffa/driver.c

856

#define ID_LIST_MASK_64 GENMASK(51, 12)

drivers/firmware/arm_ffa/driver.c

857

#define ID_LIST_MASK_32 GENMASK(31, 12)

drivers/firmware/arm_scmi/base.c

54

#define ERROR_CMD_COUNT(x) FIELD_GET(GENMASK(9, 0), (x))

drivers/firmware/arm_scmi/clock.c

91

#define REGMASK_OEM_TYPE_SET GENMASK(23, 16)

drivers/firmware/arm_scmi/clock.c

92

#define REGMASK_CLK_STATE GENMASK(1, 0)

drivers/firmware/arm_scmi/clock.c

99

#define REGMASK_OEM_TYPE_GET GENMASK(7, 0)

drivers/firmware/arm_scmi/common.h

74

#define MSG_ID_MASK GENMASK(7, 0)

drivers/firmware/arm_scmi/common.h

76

#define MSG_TYPE_MASK GENMASK(9, 8)

drivers/firmware/arm_scmi/common.h

81

#define MSG_PROTOCOL_ID_MASK GENMASK(17, 10)

drivers/firmware/arm_scmi/common.h

83

#define MSG_TOKEN_ID_MASK GENMASK(27, 18)

drivers/firmware/arm_scmi/driver.c

1880

#define DOORBELL_REG_WIDTH(x) FIELD_GET(GENMASK(2, 1), (x))

drivers/firmware/arm_scmi/driver.c

1960

*rate_limit = le32_to_cpu(resp->rate_limit) & GENMASK(19, 0);

drivers/firmware/arm_scmi/notify.c

100

#define EVT_ID_MASK GENMASK(23, 16)

drivers/firmware/arm_scmi/notify.c

101

#define SRC_ID_MASK GENMASK(15, 0)

drivers/firmware/arm_scmi/notify.c

99

#define PROTO_ID_MASK GENMASK(31, 24)

drivers/firmware/arm_scmi/perf.c

285

GENMASK(19, 0);

drivers/firmware/arm_scmi/pinctrl.c

25

#define GET_GROUPS_NR(x) le32_get_bits((x), GENMASK(31, 16))

drivers/firmware/arm_scmi/pinctrl.c

26

#define GET_PINS_NR(x) le32_get_bits((x), GENMASK(15, 0))

drivers/firmware/arm_scmi/pinctrl.c

27

#define GET_FUNCTIONS_NR(x) le32_get_bits((x), GENMASK(15, 0))

drivers/firmware/arm_scmi/pinctrl.c

30

#define NUM_ELEMS(x) le32_get_bits((x), GENMASK(15, 0))

drivers/firmware/arm_scmi/pinctrl.c

32

#define REMAINING(x) le32_get_bits((x), GENMASK(31, 16))

drivers/firmware/arm_scmi/pinctrl.c

33

#define RETURNED(x) le32_get_bits((x), GENMASK(11, 0))

drivers/firmware/arm_scmi/pinctrl.c

35

#define CONFIG_FLAG_MASK GENMASK(19, 18)

drivers/firmware/arm_scmi/pinctrl.c

358

st->num_returned = le32_get_bits(r->num_configs, GENMASK(7, 0));

drivers/firmware/arm_scmi/pinctrl.c

359

st->num_remaining = le32_get_bits(r->num_configs, GENMASK(31, 24));

drivers/firmware/arm_scmi/pinctrl.c

36

#define SELECTOR_MASK GENMASK(17, 16)

drivers/firmware/arm_scmi/pinctrl.c

37

#define SKIP_CONFIGS_MASK GENMASK(15, 8)

drivers/firmware/arm_scmi/pinctrl.c

376

u32 type = le32_get_bits(r->configs[st->loop_idx * 2], GENMASK(7, 0));

drivers/firmware/arm_scmi/pinctrl.c

38

#define CONFIG_TYPE_MASK GENMASK(7, 0)

drivers/firmware/arm_scmi/pinctrl.c

498

attributes = FIELD_PREP(GENMASK(1, 0), type) |

drivers/firmware/arm_scmi/pinctrl.c

499

FIELD_PREP(GENMASK(9, 2), chunk);

drivers/firmware/arm_scmi/pinctrl.c

544

attributes = FIELD_PREP(GENMASK(1, 0), type) | BIT(10);

drivers/firmware/arm_scmi/powercap.c

157

pi->num_domains = FIELD_GET(GENMASK(15, 0), attributes);

drivers/firmware/arm_scmi/powercap.c

53

(FIELD_GET(GENMASK(24, 23), (x)))

drivers/firmware/arm_scmi/protocols.h

27

#define PROTOCOL_REV_MINOR_MASK GENMASK(15, 0)

drivers/firmware/arm_scmi/protocols.h

28

#define PROTOCOL_REV_MAJOR_MASK GENMASK(31, 16)

drivers/firmware/arm_scmi/sensors.c

119

#define NUM_AXIS_RETURNED(x) FIELD_GET(GENMASK(5, 0), (x))

drivers/firmware/arm_scmi/sensors.c

120

#define NUM_AXIS_REMAINING(x) FIELD_GET(GENMASK(31, 26), (x))

drivers/firmware/arm_scmi/sensors.c

150

#define NUM_INTERVALS_RETURNED(x) FIELD_GET(GENMASK(11, 0), (x))

drivers/firmware/arm_scmi/sensors.c

152

#define NUM_INTERVALS_REMAINING(x) FIELD_GET(GENMASK(31, 16), (x))

drivers/firmware/arm_scmi/sensors.c

48

#define SENSOR_TSTAMP_EXP(x) FIELD_GET(GENMASK(14, 10), (x))

drivers/firmware/arm_scmi/sensors.c

53

#define SENSOR_UPDATE_BASE(x) FIELD_GET(GENMASK(31, 27), (x))

drivers/firmware/arm_scmi/sensors.c

54

#define SENSOR_UPDATE_SCALE(x) FIELD_GET(GENMASK(26, 22), (x))

drivers/firmware/arm_scmi/sensors.c

57

#define SENSOR_AXIS_NUMBER(x) FIELD_GET(GENMASK(21, 16), (x))

drivers/firmware/arm_scmi/sensors.c

61

#define SENSOR_RES(x) FIELD_GET(GENMASK(26, 0), (x))

drivers/firmware/arm_scmi/sensors.c

62

#define SENSOR_RES_EXP(x) FIELD_GET(GENMASK(31, 27), (x))

drivers/firmware/arm_scmi/sensors.c

84

#define NUM_TRIP_POINTS(x) FIELD_GET(GENMASK(7, 0), (x))

drivers/firmware/arm_scmi/sensors.c

87

#define SENSOR_SCALE(x) FIELD_GET(GENMASK(15, 11), (x))

drivers/firmware/arm_scmi/sensors.c

89

#define SENSOR_SCALE_EXTEND GENMASK(31, 5)

drivers/firmware/arm_scmi/sensors.c

90

#define SENSOR_TYPE(x) FIELD_GET(GENMASK(7, 0), (x))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-bbm.c

35

#define GET_RTCS_NR(x) le32_get_bits((x), GENMASK(23, 16))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-bbm.c

36

#define GET_GPRS_NR(x) le32_get_bits((x), GENMASK(15, 0))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-bbm.c

48

#define SCMI_IMX_BBM_EVENT_RTC_MASK GENMASK(31, 24)

drivers/firmware/arm_scmi/vendors/imx/imx-sm-cpu.c

33

#define SCMI_IMX_CPU_NR_CPU_MASK GENMASK(15, 0)

drivers/firmware/arm_scmi/vendors/imx/imx-sm-lmm.c

38

#define SCMI_IMX_LMM_NR_LM_MASK GENMASK(5, 0)

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

23

#define MAX_MISC_CTRL_SOURCES GENMASK(15, 0)

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

45

#define GET_BRD_CTRLS_NR(x) le32_get_bits((x), GENMASK(31, 24))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

46

#define GET_REASONS_NR(x) le32_get_bits((x), GENMASK(23, 16))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

47

#define GET_DEV_CTRLS_NR(x) le32_get_bits((x), GENMASK(15, 0))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

97

#define REMAINING(x) le32_get_bits((x), GENMASK(31, 20))

drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c

98

#define RETURNED(x) le32_get_bits((x), GENMASK(11, 0))

drivers/firmware/arm_scmi/voltage.c

16

#define VOLTAGE_DOMS_NUM_MASK GENMASK(15, 0)

drivers/firmware/arm_scmi/voltage.c

17

#define REMAINING_LEVELS_MASK GENMASK(31, 16)

drivers/firmware/arm_scmi/voltage.c

18

#define RETURNED_LEVELS_MASK GENMASK(11, 0)

drivers/firmware/arm_scmi/voltage.c

305

cmd->config = cpu_to_le32(config & GENMASK(3, 0));

drivers/firmware/arm_scpi.c

42

#define CMD_ID_MASK GENMASK(6, 0)

drivers/firmware/arm_scpi.c

43

#define CMD_TOKEN_ID_MASK GENMASK(15, 8)

drivers/firmware/arm_scpi.c

44

#define CMD_DATA_SIZE_MASK GENMASK(24, 16)

drivers/firmware/arm_scpi.c

45

#define CMD_LEGACY_DATA_SIZE_MASK GENMASK(28, 20)

drivers/firmware/arm_scpi.c

62

#define PROTO_REV_MAJOR_MASK GENMASK(31, 16)

drivers/firmware/arm_scpi.c

63

#define PROTO_REV_MINOR_MASK GENMASK(15, 0)

drivers/firmware/arm_scpi.c

65

#define FW_REV_MAJOR_MASK GENMASK(31, 24)

drivers/firmware/arm_scpi.c

66

#define FW_REV_MINOR_MASK GENMASK(23, 16)

drivers/firmware/arm_scpi.c

67

#define FW_REV_PATCH_MASK GENMASK(15, 0)

drivers/firmware/qcom/qcom_scm.c

1208

#define QCOM_SCM_CP_APERTURE_CONTEXT_MASK GENMASK(7, 0)

drivers/firmware/qcom/qcom_scm.c

138

#define QCOM_DLOAD_MASK GENMASK(5, 4)

drivers/firmware/qcom/qcom_scm.c

2544

return res.result[0] & GENMASK(7, 0);

drivers/firmware/qcom/qcom_scm.c

2564

hwirq = res.result[1] & GENMASK(15, 0);

drivers/firmware/samsung/exynos-acpm-dvfs.c

17

#define ACPM_DVFS_ID GENMASK(11, 0)

drivers/firmware/samsung/exynos-acpm-dvfs.c

18

#define ACPM_DVFS_REQ_TYPE GENMASK(15, 0)

drivers/firmware/samsung/exynos-acpm-pmic.c

17

#define ACPM_PMIC_CHANNEL GENMASK(15, 12)

drivers/firmware/samsung/exynos-acpm-pmic.c

18

#define ACPM_PMIC_TYPE GENMASK(11, 8)

drivers/firmware/samsung/exynos-acpm-pmic.c

19

#define ACPM_PMIC_REG GENMASK(7, 0)

drivers/firmware/samsung/exynos-acpm-pmic.c

21

#define ACPM_PMIC_RETURN GENMASK(31, 24)

drivers/firmware/samsung/exynos-acpm-pmic.c

22

#define ACPM_PMIC_MASK GENMASK(23, 16)

drivers/firmware/samsung/exynos-acpm-pmic.c

23

#define ACPM_PMIC_VALUE GENMASK(15, 8)

drivers/firmware/samsung/exynos-acpm-pmic.c

24

#define ACPM_PMIC_FUNC GENMASK(7, 0)

drivers/firmware/samsung/exynos-acpm-pmic.c

27

#define ACPM_PMIC_BULK_MASK GENMASK(7, 0)

drivers/firmware/samsung/exynos-acpm.c

35

#define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16)

drivers/firmware/smccc/soc_id.c

16

#define SMCCC_SOC_ID_JEP106_BANK_IDX_MASK GENMASK(30, 24)

drivers/firmware/smccc/soc_id.c

22

#define SMCCC_SOC_ID_JEP106_ID_CODE_MASK GENMASK(22, 16)

drivers/firmware/smccc/soc_id.c

23

#define SMCCC_SOC_ID_IMP_DEF_SOC_ID_MASK GENMASK(15, 0)

drivers/firmware/stratix10-svc.c

70

#define STRATIX10_JOB_FIELD GENMASK(3, 0)

drivers/firmware/stratix10-svc.c

72

#define STRATIX10_CLIENT_FIELD GENMASK(7, 4)

drivers/firmware/stratix10-svc.c

74

#define STRATIX10_TRANS_ID_FIELD GENMASK(7, 0)

drivers/firmware/stratix10-svc.c

93

#define STRATIX10_SDM_STATUS_MASK GENMASK(9, 0)

drivers/firmware/ti_sci.h

717

#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)

drivers/firmware/ti_sci.h

718

#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)

drivers/firmware/xilinx/zynqmp-ufs.c

104

GENMASK(2, 1), sram_csr);

drivers/firmware/xilinx/zynqmp-ufs.c

25

#define TX_RX_CFG_RDY_MASK GENMASK(3, 0)

drivers/firmware/xilinx/zynqmp.c

896

u32 mask = (node_id == NODE_SD_0) ? GENMASK(15, 0) : GENMASK(31, 16);

drivers/fpga/altera-cvp.c

37

#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)

drivers/fpga/altera-cvp.c

43

#define VSE_CVP_PROG_CTRL_MASK GENMASK(1, 0)

drivers/fpga/dfl-n3000-nios.c

57

#define N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK GENMASK(9, 8)

drivers/fpga/dfl-n3000-nios.c

58

#define N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK GENMASK(11, 10)

drivers/fpga/dfl-n3000-nios.c

59

#define N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK GENMASK(13, 12)

drivers/fpga/dfl-n3000-nios.c

60

#define N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK GENMASK(15, 14)

drivers/fpga/dfl-n3000-nios.c

61

#define N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK GENMASK(17, 16)

drivers/fpga/dfl-n3000-nios.c

62

#define N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK GENMASK(19, 18)

drivers/fpga/dfl-n3000-nios.c

63

#define N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK GENMASK(21, 20)

drivers/fpga/dfl-n3000-nios.c

64

#define N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK GENMASK(23, 22)

drivers/fpga/dfl-n3000-nios.c

70

#define N3000_NIOS_FW_VERSION_PATCH GENMASK(23, 20)

drivers/fpga/dfl-n3000-nios.c

71

#define N3000_NIOS_FW_VERSION_MINOR GENMASK(27, 24)

drivers/fpga/dfl-n3000-nios.c

72

#define N3000_NIOS_FW_VERSION_MAJOR GENMASK(31, 28)

drivers/fpga/dfl-n3000-nios.c

77

#define N3000_NIOS_PKVL_MODE_STS_GROUP_MSK GENMASK(15, 8)

drivers/fpga/dfl-n3000-nios.c

79

#define N3000_NIOS_PKVL_MODE_STS_ID_MSK GENMASK(7, 0)

drivers/fpga/dfl-pci.c

181

dfl_res = GENMASK(31, 0);

drivers/fpga/dfl-pci.c

35

#define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)

drivers/fpga/dfl-pci.c

36

#define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)

drivers/fpga/intel-m10-bmc-sec-update.c

38

#define REH_MAGIC GENMASK(15, 0)

drivers/fpga/intel-m10-bmc-sec-update.c

39

#define REH_SHA_NUM_BYTES GENMASK(31, 16)

drivers/fpga/lattice-sysconfig.h

18

#define SYSCONFIG_STATUS_ERR GENMASK(25, 23)

drivers/fpga/microchip-spi.c

190

component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);

drivers/fpga/zynq-fpga.c

96

#define DMA_INVALID_ADDRESS GENMASK(31, 0)

drivers/fsi/fsi-core.c

33

#define FSI_SLAVE_CONF_NEXT_MASK GENMASK(31, 31)

drivers/fsi/fsi-core.c

34

#define FSI_SLAVE_CONF_SLOTS_MASK GENMASK(23, 16)

drivers/fsi/fsi-core.c

36

#define FSI_SLAVE_CONF_VERSION_MASK GENMASK(15, 12)

drivers/fsi/fsi-core.c

38

#define FSI_SLAVE_CONF_TYPE_MASK GENMASK(11, 4)

drivers/fsi/fsi-core.c

41

#define FSI_SLAVE_CONF_CRC_MASK GENMASK(3, 0)

drivers/gpio/gpio-74xx-mmio.c

19

#define MMIO_74XX_BIT_CNT(x) ((x) & GENMASK(7, 0))

drivers/gpio/gpio-aspeed-sgpio.c

188

#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))

drivers/gpio/gpio-aspeed-sgpio.c

39

#define SGPIO_G7_SERIAL_OUT_SEL GENMASK(17, 16)

drivers/gpio/gpio-aspeed-sgpio.c

40

#define SGPIO_G7_PARALLEL_OUT_SEL GENMASK(19, 18)

drivers/gpio/gpio-aspeed-sgpio.c

48

#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)

drivers/gpio/gpio-aspeed-sgpio.c

507

.pin_mask = GENMASK(9, 6),

drivers/gpio/gpio-aspeed-sgpio.c

537

.pin_mask = GENMASK(10, 6),

drivers/gpio/gpio-aspeed-sgpio.c

591

.pin_mask = GENMASK(11, 6),

drivers/gpio/gpio-bd71815.c

93

#define BD71815_TWO_GPIOS GENMASK(1, 0)

drivers/gpio/gpio-cadence.c

225

iowrite32(GENMASK(num_gpios - 1, 0),

drivers/gpio/gpio-cadence.c

294

iowrite32(GENMASK(num_gpios - 1, 0),

drivers/gpio/gpio-creg-snps.c

46

reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);

drivers/gpio/gpio-creg-snps.c

68

if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])

drivers/gpio/gpio-creg-snps.c

72

if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])

drivers/gpio/gpio-davinci.c

525

binten = GENMASK(chips->gpio_unbanked / 16, 0);

drivers/gpio/gpio-davinci.c

615

writel_relaxed(GENMASK(31, 0), &g->intstat);

drivers/gpio/gpio-eic-sprd.c

59

#define SPRD_EIC_DATA_MASK GENMASK(7, 0)

drivers/gpio/gpio-eic-sprd.c

61

#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)

drivers/gpio/gpio-exar.c

185

if (pcidev->device & GENMASK(15, 12)) {

drivers/gpio/gpio-exar.c

187

exar_gpio->cascaded_offset = (pcidev->device & GENMASK(3, 0)) *

drivers/gpio/gpio-graniterapids.c

41

#define GNR_CFG_DW_RX_MASK GENMASK(23, 22)

drivers/gpio/gpio-graniterapids.c

42

#define GNR_CFG_DW_INTSEL_MASK GENMASK(21, 14)

drivers/gpio/gpio-ixp4xx.c

40

#define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)

drivers/gpio/gpio-ixp4xx.c

48

#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)

drivers/gpio/gpio-ixp4xx.c

52

#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)

drivers/gpio/gpio-macsmc.c

49

#define CONFIG_MASK GENMASK(23, 16)

drivers/gpio/gpio-macsmc.c

50

#define CONFIG_VAL GENMASK(7, 0)

drivers/gpio/gpio-macsmc.c

52

#define CONFIG_OUTMODE GENMASK(7, 6)

drivers/gpio/gpio-macsmc.c

53

#define CONFIG_IRQMODE GENMASK(5, 3)

drivers/gpio/gpio-max7360.c

106

*mask = GENMASK(7, 0);

drivers/gpio/gpio-mlxbf3.c

43

#define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0)

drivers/gpio/gpio-moxtet.c

23

.in_mask = GENMASK(2, 0),

drivers/gpio/gpio-moxtet.c

24

.out_mask = GENMASK(5, 4),

drivers/gpio/gpio-mpfs.c

25

#define MPFS_GPIO_DIR_MASK GENMASK(2, 0)

drivers/gpio/gpio-mpfs.c

32

#define MPFS_GPIO_TYPE_INT_MASK GENMASK(7, 5)

drivers/gpio/gpio-nomadik.c

285

unsigned long mask = GENMASK(chip->ngpio - 1, 0);

drivers/gpio/gpio-npcm-sgpio.c

23

#define NPCM_IOXCFG1_SFT_CLK GENMASK(3, 0)

drivers/gpio/gpio-npcm-sgpio.c

29

#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1)

drivers/gpio/gpio-npcm-sgpio.c

33

#define NPCM_IOXCFG2_PORT GENMASK(3, 0)

drivers/gpio/gpio-npcm-sgpio.c

35

#define NPCM_IXOEVCFG_MASK GENMASK(1, 0)

drivers/gpio/gpio-pca953x.c

45

#define REG_ADDR_MASK GENMASK(5, 0)

drivers/gpio/gpio-pca953x.c

72

#define PCA_GPIO_MASK GENMASK(7, 0)

drivers/gpio/gpio-pca953x.c

74

#define PCAL_GPIO_MASK GENMASK(4, 0)

drivers/gpio/gpio-pca953x.c

75

#define PCAL_PINCTRL_MASK GENMASK(6, 5)

drivers/gpio/gpio-pca953x.c

84

#define PCA_TYPE_MASK GENMASK(16, 12)

drivers/gpio/gpio-pch.c

19

#define PCH_IM_MASK GENMASK(2, 0)

drivers/gpio/gpio-pcie-idio-24.c

336

idio24gpio->irq_type = GENMASK(7, 0);

drivers/gpio/gpio-pmic-eic-sprd.c

32

#define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0)

drivers/gpio/gpio-pmic-eic-sprd.c

34

#define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0)

drivers/gpio/gpio-rcar.c

334

u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);

drivers/gpio/gpio-rcar.c

374

u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);

drivers/gpio/gpio-rcar.c

481

u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);

drivers/gpio/gpio-realtek-otto.c

310

u32 mask_all = GENMASK(gc->ngpio - 1, 0);

drivers/gpio/gpio-realtek-otto.c

34

#define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0)

drivers/gpio/gpio-rockchip.c

212

max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;

drivers/gpio/gpio-sprd.c

32

#define SPRD_GPIO_BANK_MASK GENMASK(15, 0)

drivers/gpio/gpio-thunderx.c

30

#define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)

drivers/gpio/gpio-thunderx.c

34

#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)

drivers/gpio/gpio-wcove.c

47

#define GPIO_IRQ0_MASK GENMASK(6, 0)

drivers/gpio/gpio-wcove.c

48

#define GPIO_IRQ1_MASK GENMASK(5, 0)

drivers/gpio/gpio-winbond.c

32

#define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4)

drivers/gpio/gpio-winbond.c

59

#define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0)

drivers/gpio/gpio-winbond.c

621

gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,

drivers/gpio/gpio-ws16c48.c

40

#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)

drivers/gpu/drm/adp/adp_drv.c

30

#define ADP_SCREEN_HSIZE GENMASK(15, 0)

drivers/gpu/drm/adp/adp_drv.c

31

#define ADP_SCREEN_VSIZE GENMASK(31, 16)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

155

#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

1052

uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

450

mask = GENMASK(num_xcc - 1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

453

mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

457

mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

45

(num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0)

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2554

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

832

xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

869

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

897

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

522

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

565

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

650

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

806

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

88

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

441

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

482

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

540

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

589

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

70

xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1429

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

1048

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

821

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1559

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1577

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2016

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2489

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2514

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2567

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

662

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

511

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1363

inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

748

inst_mask = GENMASK(NUM_XCC(adev->sdma.sdma_mask) - 1, 0);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

831

GENMASK(adev->sdma.num_instances - 1, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2172

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1756

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3483

instlo &= GENMASK(31, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3503

instlo &= GENMASK(31, 1);

drivers/gpu/drm/arm/display/komeda/komeda_crtc.c

45

*color_depths = GENMASK(min_bpc, 0);

drivers/gpu/drm/arm/malidp_drv.c

50

const u32 gamma_write_mask = GENMASK(18, 16);

drivers/gpu/drm/aspeed/aspeed_gfx.h

75

#define CRT_CTRL_COLOR_MASK GENMASK(9, 7)

drivers/gpu/drm/aspeed/aspeed_gfx.h

84

#define CRT_CTRL_VBLANK_LINE_MASK GENMASK(31, 20)

drivers/gpu/drm/ast/ast_drv.h

381

#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)

drivers/gpu/drm/ast/ast_reg.h

34

#define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0)

drivers/gpu/drm/ast/ast_reg.h

38

#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0)

drivers/gpu/drm/ast/ast_reg.h

45

#define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK GENMASK(7, 6)

drivers/gpu/drm/ast/ast_reg.h

52

#define AST_IO_VGACRD1_TX_TYPE_MASK GENMASK(3, 1)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

315

#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

316

#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

111

GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

46

#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

100

#define CLK_DIV_MAX GENMASK(3, 0)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

150

#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

157

(((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

159

#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

214

#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

237

#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

238

#define RD_SIZE(val) ((val) & GENMASK(15, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

270

#define VID_PIXEL_MODE_MASK GENMASK(17, 14)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

32

#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

326

#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

327

#define LINE_POS(val) ((val) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

33

#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

330

#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

331

#define HORIZ_POS(val) ((val) & GENMASK(2, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

34

#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

35

#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

359

#define TVG_MODE_MASK GENMASK(4, 3)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

363

#define TVG_STOPMODE_MASK GENMASK(2, 1)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

40

#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

405

#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

41

#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

412

#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

413

#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

414

#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

415

#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

416

#define REV_MINOR(x) ((x) & GENMASK(3, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

42

#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

43

#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

59

#define IF_VID_SELECT_MASK GENMASK(3, 2)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

87

#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

91

#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

92

#define DPHY_ALL_D_PDN GENMASK(7, 4)

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

98

#define HSTX_TIMEOUT_MAX GENMASK(17, 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1262

reg32 &= ~GENMASK(1, 0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1903

line_thresh & GENMASK(5, 0));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

107

#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

108

#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

120

#define CDNS_DP_LANE_EN_LANES(x) GENMASK((x) - 1, 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

254

#define CDNS_VOLT_SWING(x) ((x) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

257

#define CDNS_PRE_EMPHASIS(x) ((x) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

264

#define CDNS_LANE_MAPPING_TYPE_C_LANE_0(x) ((x) & GENMASK(1, 0))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

265

#define CDNS_LANE_MAPPING_TYPE_C_LANE_1(x) ((x) & GENMASK(3, 2))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

266

#define CDNS_LANE_MAPPING_TYPE_C_LANE_2(x) ((x) & GENMASK(5, 4))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

267

#define CDNS_LANE_MAPPING_TYPE_C_LANE_3(x) ((x) & GENMASK(7, 6))

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

35

#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

72

#define CDNS_IP_DTCT_WIN GENMASK(11, 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

83

#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

88

#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

89

#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

90

#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

91

#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18)

drivers/gpu/drm/bridge/chipone-icn6211.c

33

#define SYS_CTRL_1_CLK_PHASE_MSK GENMASK(5, 4)

drivers/gpu/drm/bridge/chrontel-ch7033.c

102

HWO_HDMI_HI = GENMASK(5, 3),

drivers/gpu/drm/bridge/chrontel-ch7033.c

103

HOO_HDMI_HI = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

109

VWO_HDMI_HI = GENMASK(5, 3),

drivers/gpu/drm/bridge/chrontel-ch7033.c

110

VOO_HDMI_HI = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

119

R_INT = GENMASK(3, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

139

DRI_IT_LVDS = GENMASK(2, 1),

drivers/gpu/drm/bridge/chrontel-ch7033.c

145

DRI_PLL_CP = GENMASK(7, 6),

drivers/gpu/drm/bridge/chrontel-ch7033.c

156

VCO3CS = GENMASK(7, 6),

drivers/gpu/drm/bridge/chrontel-ch7033.c

157

ICPGBK2_0 = GENMASK(5, 3),

drivers/gpu/drm/bridge/chrontel-ch7033.c

165

PLL2N11 = GENMASK(7, 4),

drivers/gpu/drm/bridge/chrontel-ch7033.c

174

DIFF_EN = GENMASK(7, 6),

drivers/gpu/drm/bridge/chrontel-ch7033.c

175

CORREC_EN = GENMASK(5, 4),

drivers/gpu/drm/bridge/chrontel-ch7033.c

188

THRWL = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

28

DRI_PDDRI = GENMASK(7, 4),

drivers/gpu/drm/bridge/chrontel-ch7033.c

29

PDDAC = GENMASK(3, 1),

drivers/gpu/drm/bridge/chrontel-ch7033.c

59

IDF = GENMASK(7, 4),

drivers/gpu/drm/bridge/chrontel-ch7033.c

61

SWAP = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

79

GCLKFREQ = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

89

TE = GENMASK(2, 0),

drivers/gpu/drm/bridge/chrontel-ch7033.c

94

SWAPS = GENMASK(7, 4),

drivers/gpu/drm/bridge/chrontel-ch7033.c

95

VFMT = GENMASK(3, 0),

drivers/gpu/drm/bridge/fsl-ldb.c

34

#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25)

drivers/gpu/drm/bridge/fsl-ldb.c

47

#define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5)

drivers/gpu/drm/bridge/fsl-ldb.c

49

#define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8)

drivers/gpu/drm/bridge/fsl-ldb.c

51

#define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11)

drivers/gpu/drm/bridge/fsl-ldb.c

53

#define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14)

drivers/gpu/drm/bridge/fsl-ldb.c

55

#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

20

#define WTMK_HIGH_MASK GENMASK(31, 24)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

21

#define WTMK_LOW_MASK GENMASK(23, 16)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

22

#define NUM_CH_MASK GENMASK(10, 8)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

28

#define PRE_SEL GENMASK(28, 24)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

29

#define D_SEL GENMASK(23, 20)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

30

#define V_SEL GENMASK(19, 15)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

31

#define U_SEL GENMASK(14, 10)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

32

#define C_SEL GENMASK(9, 5)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

33

#define P_SEL GENMASK(4, 0)

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c

25

#define PVI_CTRL_MODE_MASK GENMASK(2, 1)

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

33

#define PC_SKIP_NUMBER_MASK GENMASK(12, 7)

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

35

#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16)

drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

38

#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

28

#define CFGCLKFREQRANGE_MASK GENMASK(5, 0)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

30

#define CLKSEL_MASK GENMASK(7, 6)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

34

#define HSFREQRANGE_MASK GENMASK(14, 8)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

41

#define M_MASK GENMASK(9, 0)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

43

#define N_MASK GENMASK(13, 10)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

45

#define VCO_CTRL_MASK GENMASK(19, 14)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

47

#define PROP_CTRL_MASK GENMASK(25, 20)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

49

#define INT_CTRL_MASK GENMASK(31, 26)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

53

#define GMP_CTRL_MASK GENMASK(1, 0)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

55

#define CPBIAS_CTRL_MASK GENMASK(8, 2)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

61

#define MIPI_DSI_RGB666_MAP_CFG GENMASK(7, 6)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

64

#define MIPI_DSI_RGB565_MAP_CFG GENMASK(5, 4)

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

68

#define LCDIF_CROSS_LINE_PATTERN GENMASK(3, 0)

drivers/gpu/drm/bridge/ite-it6263.c

145

#define HDMI_COLOR_DEPTH GENMASK(6, 4)

drivers/gpu/drm/bridge/ite-it6263.c

48

#define REG_COL_DEP GENMASK(1, 0)

drivers/gpu/drm/bridge/ite-it6505.c

856

GENMASK(7, 8 - it6505->lane_count) :

drivers/gpu/drm/bridge/ite-it6505.c

857

GENMASK(3 + it6505->lane_count, 4)) |

drivers/gpu/drm/bridge/ite-it66121.c

210

#define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2)

drivers/gpu/drm/bridge/ite-it66121.c

37

#define IT66121_REVISION_MASK GENMASK(7, 4)

drivers/gpu/drm/bridge/ite-it66121.c

38

#define IT66121_DEVICE_ID1_MASK GENMASK(3, 0)

drivers/gpu/drm/bridge/microchip-lvds.c

52

#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8)

drivers/gpu/drm/bridge/nwl-dsi.h

109

#define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

110

#define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

111

#define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

112

#define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

113

#define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

114

#define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

122

#define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x))

drivers/gpu/drm/bridge/nwl-dsi.h

123

#define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x))

drivers/gpu/drm/bridge/parade-ps8640.c

30

#define SWAUX_ADDR_MASK GENMASK(19, 0)

drivers/gpu/drm/bridge/parade-ps8640.c

32

#define SWAUX_LENGTH_MASK GENMASK(3, 0)

drivers/gpu/drm/bridge/parade-ps8640.c

39

#define SWAUX_M_MASK GENMASK(4, 0)

drivers/gpu/drm/bridge/parade-ps8640.c

40

#define SWAUX_STATUS_MASK GENMASK(7, 5)

drivers/gpu/drm/bridge/sii902x.c

71

#define SII902X_AVI_POWER_STATE_MSK GENMASK(1, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

103

#define HBLANK_INTERVAL GENMASK(15, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

106

#define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

107

#define AUDIO_PACKET_ID GENMASK(23, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

109

#define NUM_CHANNELS GENMASK(14, 12)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

111

#define AUDIO_DATA_WIDTH GENMASK(9, 5)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

112

#define AUDIO_DATA_IN_EN GENMASK(4, 1)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

126

#define SDP_REGS GENMASK(31, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

130

#define PHY_POWERDOWN GENMASK(20, 17)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

131

#define PHY_BUSY GENMASK(15, 12)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

133

#define XMIT_ENABLE GENMASK(11, 8)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

134

#define PHY_LANES GENMASK(7, 6)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

135

#define PHY_RATE GENMASK(5, 4)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

136

#define TPS_SEL GENMASK(3, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

146

#define AUX_CMD_TYPE GENMASK(31, 28)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

147

#define AUX_ADDR GENMASK(27, 8)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

149

#define AUX_LEN_REQ GENMASK(3, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

153

#define AUX_BYTES_READ GENMASK(23, 19)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

154

#define AUX_STATUS GENMASK(7, 4)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

176

#define HPD_STATE GENMASK(11, 9)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

203

#define HDCP22_STATE GENMASK(26, 24)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

205

#define HDCP13_BSTATUS GENMASK(22, 19)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

208

#define STATEE GENMASK(16, 14)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

209

#define STATEOEG GENMASK(13, 11)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

210

#define STATER GENMASK(10, 8)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

211

#define STATEA GENMASK(7, 4)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

212

#define SUBSTATEA GENMASK(3, 1)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

244

#define IDPK_DATA_INDEX GENMASK(5, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

454

xmit_enable = GENMASK(lanes - 1, 0);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

54

#define PIXEL_MODE_SELECT GENMASK(22, 21)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

55

#define VIDEO_MAPPING GENMASK(20, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

68

#define HACTIVE GENMASK(31, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

69

#define HBLANK GENMASK(15, 2)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

74

#define VBLANK GENMASK(31, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

75

#define VACTIVE GENMASK(15, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

78

#define H_SYNC_WIDTH GENMASK(31, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

79

#define H_FRONT_PORCH GENMASK(15, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

82

#define V_SYNC_WIDTH GENMASK(31, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

83

#define V_FRONT_PORCH GENMASK(15, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

86

#define INIT_THRESHOLD_HI GENMASK(22, 21)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

87

#define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

88

#define INIT_THRESHOLD GENMASK(13, 7)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

89

#define AVERAGE_BYTES_PER_TU GENMASK(6, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

92

#define VSTART GENMASK(31, 16)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

93

#define HSTART GENMASK(15, 0)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

96

#define MISC0 GENMASK(31, 24)

drivers/gpu/drm/bridge/synopsys/dw-dp.c

99

#define MISC1 GENMASK(31, 24)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

434

if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) {

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

114

#define I2S_LINES_EN_MSK GENMASK(7, 4)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

119

#define SPDIF_LINES_EN GENMASK(19, 16)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

120

#define AUD_FORMAT_MSK GENMASK(26, 24)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

406

#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

414

#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h

427

#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

38

#define VERSION GENMASK(31, 8)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

109

#define VID_MODE_TYPE(x) FIELD_PREP(GENMASK(1, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

117

#define IPI_DEPTH(x) FIELD_PREP(GENMASK(7, 4), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

122

#define IPI_FORMAT(x) FIELD_PREP(GENMASK(3, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

126

#define VID_HSA_TIME(x) FIELD_PREP(GENMASK(29, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

128

#define VID_HBP_TIME(x) FIELD_PREP(GENMASK(29, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

130

#define VID_HACT_TIME(x) FIELD_PREP(GENMASK(29, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

132

#define VID_HLINE_TIME(x) FIELD_PREP(GENMASK(29, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

134

#define VID_VSA_LINES(x) FIELD_PREP(GENMASK(9, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

136

#define VID_VBP_LINES(x) FIELD_PREP(GENMASK(9, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

138

#define VID_VACT_LINES(x) FIELD_PREP(GENMASK(13, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

140

#define VID_VFP_LINES(x) FIELD_PREP(GENMASK(9, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

142

#define MAX_PIX_PKT(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

54

#define TO_HSTX(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

56

#define TO_HSTXRDY(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

58

#define TO_LPRXRDY(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

60

#define TO_LPTXRDY(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

62

#define TO_LPTXTRIG(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

64

#define TO_LPTXULPS(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

66

#define TO_BTA(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

69

#define PPI_WIDTH(x) FIELD_PREP(GENMASK(9, 8), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

70

#define PHY_LANES(x) FIELD_PREP(GENMASK(5, 4), (x) - 1)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

73

#define PHY_LPTX_CLK_DIV(x) FIELD_PREP(GENMASK(12, 8), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

78

#define PHY_LP2HS_TIME(x) FIELD_PREP(GENMASK(28, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

80

#define PHY_HS2LP_TIME(x) FIELD_PREP(GENMASK(28, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

82

#define PHY_MAX_RD_TIME(x) FIELD_PREP(GENMASK(26, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

84

#define PHY_ESC_CMD_TIME(x) FIELD_PREP(GENMASK(28, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

86

#define PHY_ESC_BYTE_TIME(x) FIELD_PREP(GENMASK(28, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

89

#define PHY_IPI_RATIO(x) FIELD_PREP(GENMASK(21, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

91

#define PHY_SYS_RATIO(x) FIELD_PREP(GENMASK(16, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

97

#define TX_VCID(x) FIELD_PREP(GENMASK(1, 0), x)

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c

99

#define SCRAMBLING_SEED(x) FIELD_PREP(GENMASK(31, 16), x)

drivers/gpu/drm/bridge/tc358767.c

125

#define VSDELAY GENMASK(31, 20)

drivers/gpu/drm/bridge/tc358767.c

133

#define HPW GENMASK(8, 0)

drivers/gpu/drm/bridge/tc358767.c

134

#define HBPR GENMASK(24, 16)

drivers/gpu/drm/bridge/tc358767.c

136

#define HDISPR GENMASK(10, 0)

drivers/gpu/drm/bridge/tc358767.c

137

#define HFPR GENMASK(24, 16)

drivers/gpu/drm/bridge/tc358767.c

139

#define VSPR GENMASK(7, 0)

drivers/gpu/drm/bridge/tc358767.c

140

#define VBPR GENMASK(23, 16)

drivers/gpu/drm/bridge/tc358767.c

142

#define VFPR GENMASK(23, 16)

drivers/gpu/drm/bridge/tc358767.c

143

#define VDISPR GENMASK(10, 0)

drivers/gpu/drm/bridge/tc358767.c

200

#define VID_SYNC_DLY GENMASK(15, 0)

drivers/gpu/drm/bridge/tc358767.c

201

#define THRESH_DLY GENMASK(31, 16)

drivers/gpu/drm/bridge/tc358767.c

204

#define H_TOTAL GENMASK(15, 0)

drivers/gpu/drm/bridge/tc358767.c

205

#define V_TOTAL GENMASK(31, 16)

drivers/gpu/drm/bridge/tc358767.c

207

#define H_START GENMASK(15, 0)

drivers/gpu/drm/bridge/tc358767.c

208

#define V_START GENMASK(31, 16)

drivers/gpu/drm/bridge/tc358767.c

210

#define H_ACT GENMASK(15, 0)

drivers/gpu/drm/bridge/tc358767.c

211

#define V_ACT GENMASK(31, 16)

drivers/gpu/drm/bridge/tc358767.c

214

#define VS_WIDTH GENMASK(30, 16)

drivers/gpu/drm/bridge/tc358767.c

215

#define HS_WIDTH GENMASK(14, 0)

drivers/gpu/drm/bridge/tc358767.c

220

#define MAX_TU_SYMBOL GENMASK(28, 23)

drivers/gpu/drm/bridge/tc358767.c

221

#define TU_SIZE GENMASK(21, 16)

drivers/gpu/drm/bridge/tc358767.c

227

#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)

drivers/gpu/drm/bridge/tc358767.c

236

#define AUX_BYTES GENMASK(15, 8)

drivers/gpu/drm/bridge/tc358767.c

237

#define AUX_STATUS GENMASK(7, 4)

drivers/gpu/drm/bridge/tc358767.c

244

#define DP0_SRCCTRL_PRE1 GENMASK(29, 28)

drivers/gpu/drm/bridge/tc358767.c

245

#define DP0_SRCCTRL_SWG1 GENMASK(25, 24)

drivers/gpu/drm/bridge/tc358767.c

246

#define DP0_SRCCTRL_PRE0 GENMASK(21, 20)

drivers/gpu/drm/bridge/tc358767.c

247

#define DP0_SRCCTRL_SWG0 GENMASK(17, 16)

drivers/gpu/drm/bridge/tc358767.c

285

#define DP1_SRCCTRL_PRE GENMASK(21, 20)

drivers/gpu/drm/bridge/tc358767.c

286

#define DP1_SRCCTRL_SWG GENMASK(17, 16)

drivers/gpu/drm/bridge/tc358767.c

339

#define COLOR_R GENMASK(31, 24)

drivers/gpu/drm/bridge/tc358767.c

340

#define COLOR_G GENMASK(23, 16)

drivers/gpu/drm/bridge/tc358767.c

341

#define COLOR_B GENMASK(15, 8)

drivers/gpu/drm/bridge/tc358767.c

343

#define COLOR_BAR_MODE GENMASK(1, 0)

drivers/gpu/drm/bridge/tc358775.c

31

#define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)

drivers/gpu/drm/bridge/ti-dlpc3433.c

45

#define DEV_ID_MASK GENMASK(3, 0)

drivers/gpu/drm/bridge/ti-dlpc3433.c

52

#define LED_MASK GENMASK(2, 0)

drivers/gpu/drm/bridge/ti-sn65dsi86.c

42

#define REFCLK_FREQ_MASK GENMASK(3, 1)

drivers/gpu/drm/bridge/ti-sn65dsi86.c

47

#define CHA_DSI_LANES_MASK GENMASK(4, 3)

drivers/gpu/drm/bridge/ti-sn65dsi86.c

85

#define SN_AUX_ADDR_MASK GENMASK(19, 0)

drivers/gpu/drm/bridge/ti-sn65dsi86.c

92

#define DP_NUM_LANES_MASK GENMASK(5, 4)

drivers/gpu/drm/bridge/ti-sn65dsi86.c

95

#define DP_DATARATE_MASK GENMASK(7, 5)

drivers/gpu/drm/display/drm_dp_mst_topology.c

1030

reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;

drivers/gpu/drm/display/drm_dp_mst_topology.c

454

buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);

drivers/gpu/drm/display/drm_dp_mst_topology.c

456

buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);

drivers/gpu/drm/display/drm_dp_mst_topology.c

594

req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),

drivers/gpu/drm/display/drm_dp_mst_topology.c

598

req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),

drivers/gpu/drm/drm_client_modeset.c

654

mask = GENMASK(count - 1, 0);

drivers/gpu/drm/drm_displayid_internal.h

145

#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)

drivers/gpu/drm/drm_displayid_internal.h

146

#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)

drivers/gpu/drm/drm_format_internal.h

108

return GENMASK(31, 24) | /* fill alpha bits */

drivers/gpu/drm/drm_format_internal.h

130

return GENMASK(31, 24) | /* fill alpha bits */

drivers/gpu/drm/drm_format_internal.h

144

return GENMASK(31, 30) | /* set alpha bits */

drivers/gpu/drm/drm_format_internal.h

158

return GENMASK(31, 30) | /* set alpha bits */

drivers/gpu/drm/drm_format_internal.h

96

return pix & GENMASK(23, 0);

drivers/gpu/drm/exynos/regs-decon5433.h

120

#define SHADOWCON_PROTECT_MASK GENMASK(14, 10)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

13

#define HIBMC_AUX_CMD_REQ_LEN GENMASK(7, 4)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

14

#define HIBMC_AUX_CMD_ADDR GENMASK(27, 8)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

303

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(8, 1),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

312

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(23, 12),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

314

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(23, 12),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

316

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(11, 0),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

101

#define HIBMC_DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1 GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

116

#define HIBMC_DP_PMA_TXDEEMPH GENMASK(18, 1)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

19

#define HIBMC_DP_CFG_AUX_MIN_PULSE_NUM GENMASK(13, 9)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

23

#define HIBMC_DP_CFG_AUX_STATUS GENMASK(11, 4)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

24

#define HIBMC_DP_CFG_AUX_READY_DATA_BYTE GENMASK(16, 12)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

25

#define HIBMC_DP_CFG_AUX GENMASK(24, 17)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

28

#define HIBMC_DP_HPD_CUR_STATE GENMASK(7, 4)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

32

#define HIBMC_DP_CFG_PAT_SEL GENMASK(7, 4)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

33

#define HIBMC_DP_CFG_LANE_DATA_EN GENMASK(11, 8)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

37

#define HIBMC_DP_CFG_STREAM_VIDEO_MAPPING GENMASK(5, 2)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

43

#define HIBMC_DP_CFG_STREAM_HACTIVE GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

44

#define HIBMC_DP_CFG_STREAM_HBLANK GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

47

#define HIBMC_DP_CFG_STREAM_VACTIVE GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

48

#define HIBMC_DP_CFG_STREAM_VBLANK GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

51

#define HIBMC_DP_CFG_STREAM_HSYNC_WIDTH GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

54

#define HIBMC_DP_CFG_STREAM_VSYNC_WIDTH GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

55

#define HIBMC_DP_CFG_STREAM_VFRONT_PORCH GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

58

#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE GENMASK(5, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

59

#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE GENMASK(9, 6)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

60

#define HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION GENMASK(31, 20)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

63

#define HIBMC_DP_CFG_STREAM_VSTART GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

64

#define HIBMC_DP_CFG_STREAM_HSTART GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

70

#define HIBMC_DP_CFG_STREAM_HTOTAL_SIZE GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

71

#define HIBMC_DP_CFG_STREAM_HBLANK_SIZE GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

77

#define HIBMC_DP_CFG_TIMING_GEN0_HACTIVE GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

78

#define HIBMC_DP_CFG_TIMING_GEN0_HBLANK GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

81

#define HIBMC_DP_CFG_TIMING_GEN0_VACTIVE GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

82

#define HIBMC_DP_CFG_TIMING_GEN0_VBLANK GENMASK(15, 0)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

85

#define HIBMC_DP_CFG_TIMING_GEN0_VFRONT_PORCH GENMASK(31, 16)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h

95

#define HIBMC_DP_CFG_PHY_LANE_NUM GENMASK(2, 1)

drivers/gpu/drm/i915/display/intel_bw.c

169

qgv_points = GENMASK(num_qgv_points - 1, 0);

drivers/gpu/drm/i915/display/intel_bw.c

172

psf_points = GENMASK(num_psf_gv_points - 1, 0);

drivers/gpu/drm/i915/display/intel_display.c

3577

primary_pipes &= GENMASK(pipe, 0);

drivers/gpu/drm/i915/display/intel_display_device.c

1122

.abox_mask = GENMASK(1, 0), \

drivers/gpu/drm/i915/display/intel_display_device.c

1300

.abox_mask = GENMASK(1, 0), \

drivers/gpu/drm/i915/display/intel_display_device.c

960

.abox_mask = GENMASK(2, 1), \

drivers/gpu/drm/i915/display/intel_dp.c

2792

pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

85

# define INTEL_EDP_TCON_USAGE_MASK GENMASK(0, 3)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

93

# define INTEL_EDP_TCON_OPTIMIZATION_STRENGTH_MASK GENMASK(5, 7)

drivers/gpu/drm/i915/display/intel_dp_mst.c

626

pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

drivers/gpu/drm/i915/display/intel_frontbuffer.h

63

GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \

drivers/gpu/drm/i915/display/intel_vbt_defs.h

454

#define BDB_263_VBT_EDP_RATES_MASK GENMASK(BDB_263_VBT_EDP_NUM_RATES - 1, 0)

drivers/gpu/drm/i915/gt/intel_engine.h

88

((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \

drivers/gpu/drm/i915/gt/intel_engine_cs.c

896

info->engine_mask &= ~GENMASK(CCS3, CCS0);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

964

GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

162

#define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

168

#define XEHP_CSB_SW_CTX_ID_MASK GENMASK(31, 10)

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2464

if (engine->execlists.error_interrupt & GENMASK(15, 0))

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2494

eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3579

engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

232

#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

244

#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)

drivers/gpu/drm/i915/gt/intel_gt_regs.h

1596

#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)

drivers/gpu/drm/i915/gt/intel_gt_regs.h

1597

#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)

drivers/gpu/drm/i915/gt/intel_lrc.h

90

#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)

drivers/gpu/drm/i915/gt/intel_lrc.h

97

#define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9)

drivers/gpu/drm/i915/gt/intel_sseu.c

155

u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);

drivers/gpu/drm/i915/gt/intel_sseu.c

498

subslice_mask = GENMASK(sseu->max_subslices - 1, 0);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1022

if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {

drivers/gpu/drm/i915/gt/selftest_lrc.c

1182

if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {

drivers/gpu/drm/i915/gt/selftest_lrc.c

1335

if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) {

drivers/gpu/drm/i915/gt/selftest_lrc.c

209

if ((lri & GENMASK(31, 23)) != LRI_HEADER) {

drivers/gpu/drm/i915/gt/selftest_lrc.c

32

#define LRI_LENGTH_MASK GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

115

#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

117

#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

118

#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

119

#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

123

#define CAP_HDR_NUM_MMIOS GENMASK(9, 0)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

139

#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

141

#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

142

#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

71

#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)

drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h

102

#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)

drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h

72

#define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)

drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c

60

#define GSC_PROXY_TYPE GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c

61

#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

378

#define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

379

#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

67

#define WQ_TYPE_MASK GENMASK(7, 0)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

68

#define WQ_LEN_MASK GENMASK(26, 16)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

70

#define WQ_GUC_ID_MASK GENMASK(15, 0)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

71

#define WQ_RING_TAIL_MASK GENMASK(28, 18)

drivers/gpu/drm/i915/gvt/cmd_parser.c

1041

(cmd_val(s, i) & GENMASK(22, 2))

drivers/gpu/drm/i915/gvt/cmd_parser.c

1044

(cmd_val(s, i) & GENMASK(22, 18))

drivers/gpu/drm/i915/gvt/cmd_parser.c

1047

(cmd_val(s, i) & GENMASK(31, 2))

drivers/gpu/drm/i915/gvt/cmd_parser.c

1050

(cmd_val(s, i) & GENMASK(15, 0))

drivers/gpu/drm/i915/gvt/cmd_parser.c

1209

gma = cmd_val(s, 2) & GENMASK(31, 3);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1311

v = (dword0 & GENMASK(21, 19)) >> 19;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1318

info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1320

info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1321

info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1347

u32 plane = (dword0 & GENMASK(12, 8)) >> 8;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1386

info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1387

info->tile_val = (dword1 & GENMASK(2, 0));

drivers/gpu/drm/i915/gvt/cmd_parser.c

1388

info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1389

info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1407

stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1409

GENMASK(12, 10)) >> 10;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1412

GENMASK(15, 6)) >> 6;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1433

set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1436

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1438

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1441

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1443

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1632

gma = cmd_val(s, 2) & GENMASK(31, 2);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1635

gma_low = cmd_val(s, 1) & GENMASK(31, 2);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1636

gma_high = cmd_val(s, 2) & GENMASK(15, 0);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1671

int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *

drivers/gpu/drm/i915/gvt/cmd_parser.c

1688

gma = cmd_val(s, 1) & GENMASK(31, 2);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1690

gma_high = cmd_val(s, 2) & GENMASK(15, 0);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1738

gma = cmd_val(s, 1) & GENMASK(31, 3);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1740

gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;

drivers/gpu/drm/i915/gvt/cmd_parser.c

400

FIELD_GET(GENMASK(end, start), cmd_val(s, dword))

drivers/gpu/drm/i915/gvt/gvt.h

486

*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));

drivers/gpu/drm/i915/gvt/handlers.c

177

offset &= ~GENMASK(11, 0);

drivers/gpu/drm/i915/gvt/handlers.c

293

(((new) & GENMASK(31, 16)) \

drivers/gpu/drm/i915/gvt/handlers.c

294

| ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \

drivers/gpu/drm/i915/gvt/handlers.c

327

vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));

drivers/gpu/drm/i915/gvt/handlers.c

976

data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;

drivers/gpu/drm/i915/gvt/handlers.c

991

sticky_mask = GENMASK(27, 26) | (1 << 24);

drivers/gpu/drm/i915/gvt/interrupt.c

442

if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))

drivers/gpu/drm/i915/i915_cmd_parser.c

501

#define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)

drivers/gpu/drm/i915/i915_params.h

35

#define ENABLE_GUC_MASK GENMASK(1, 0)

drivers/gpu/drm/i915/intel_wakeref.h

139

#define INTEL_WAKEREF_PUT_DELAY_MASK GENMASK(BITS_PER_LONG - 1, 1)

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h

47

#define PXP43_INIT_SESSION_APPID GENMASK(17, 2)

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

34

#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

35

#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

36

#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)

drivers/gpu/drm/imx/dc/dc-cf.c

21

#define HEIGHT(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-cf.c

22

#define WIDTH(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-cf.c

25

#define BLUE(x) FIELD_PREP(GENMASK(15, 8), (x))

drivers/gpu/drm/imx/dc/dc-ed.c

18

#define DIV_MASK GENMASK(23, 16)

drivers/gpu/drm/imx/dc/dc-fg.c

24

#define FGSYNCMODE_MASK GENMASK(2, 1)

drivers/gpu/drm/imx/dc/dc-fg.c

29

#define HTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

30

#define HACT(x) FIELD_PREP(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

34

#define HSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

35

#define HSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

38

#define VTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

39

#define VACT(x) FIELD_PREP(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

43

#define VSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

44

#define VSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))

drivers/gpu/drm/imx/dc/dc-fg.c

49

#define ROW(x) FIELD_PREP(GENMASK(29, 16), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

50

#define COL(x) FIELD_PREP(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

54

#define STARTY(x) FIELD_PREP(GENMASK(29, 16), ((x) + 1))

drivers/gpu/drm/imx/dc/dc-fg.c

55

#define STARTX(x) FIELD_PREP(GENMASK(13, 0), ((x) + 1))

drivers/gpu/drm/imx/dc/dc-fg.c

61

#define FGDM_MASK GENMASK(2, 0)

drivers/gpu/drm/imx/dc/dc-fg.c

64

#define CCGREEN(x) FIELD_PREP(GENMASK(19, 10), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

73

#define FRAMEINDEX(x) FIELD_GET(GENMASK(31, 14), (x))

drivers/gpu/drm/imx/dc/dc-fg.c

74

#define LINEINDEX(x) FIELD_GET(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

15

#define SHDLDREQSTICKY_MASK GENMASK(31, 24)

drivers/gpu/drm/imx/dc/dc-fu.c

17

#define BASEADDRESSAUTOUPDATE_MASK GENMASK(23, 16)

drivers/gpu/drm/imx/dc/dc-fu.c

22

#define SETBURSTLENGTH_MASK GENMASK(12, 8)

drivers/gpu/drm/imx/dc/dc-fu.c

24

#define SETNUMBUFFERS_MASK GENMASK(7, 0)

drivers/gpu/drm/imx/dc/dc-fu.c

28

#define BITSPERPIXEL_MASK GENMASK(21, 16)

drivers/gpu/drm/imx/dc/dc-fu.c

30

#define STRIDE_MASK GENMASK(15, 0)

drivers/gpu/drm/imx/dc/dc-fu.c

34

#define LINECOUNT(x) FIELD_PREP(GENMASK(29, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

35

#define LINEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

38

#define LAYERYOFFSET(x) FIELD_PREP(GENMASK(30, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

39

#define LAYERXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

42

#define CLIPWINDOWYOFFSET(x) FIELD_PREP(GENMASK(30, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

43

#define CLIPWINDOWXOFFSET(x) FIELD_PREP(GENMASK(14, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.c

46

#define CLIPWINDOWHEIGHT(x) FIELD_PREP(GENMASK(29, 16), (x) - 1)

drivers/gpu/drm/imx/dc/dc-fu.c

47

#define CLIPWINDOWWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x) - 1)

drivers/gpu/drm/imx/dc/dc-fu.h

24

#define R_BITS(x) FIELD_PREP_CONST(GENMASK(27, 24), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

25

#define G_BITS(x) FIELD_PREP_CONST(GENMASK(19, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

26

#define B_BITS(x) FIELD_PREP_CONST(GENMASK(11, 8), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

27

#define A_BITS(x) FIELD_PREP_CONST(GENMASK(3, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

30

#define R_SHIFT(x) FIELD_PREP_CONST(GENMASK(28, 24), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

31

#define G_SHIFT(x) FIELD_PREP_CONST(GENMASK(20, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

32

#define B_SHIFT(x) FIELD_PREP_CONST(GENMASK(12, 8), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

33

#define A_SHIFT(x) FIELD_PREP_CONST(GENMASK(4, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

37

#define YUVCONVERSIONMODE_MASK GENMASK(18, 17)

drivers/gpu/drm/imx/dc/dc-fu.h

41

#define FRAMEHEIGHT(x) FIELD_PREP(GENMASK(29, 16), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

42

#define FRAMEWIDTH(x) FIELD_PREP(GENMASK(13, 0), (x))

drivers/gpu/drm/imx/dc/dc-fu.h

45

#define INPUTSELECT_MASK GENMASK(4, 3)

drivers/gpu/drm/imx/dc/dc-fu.h

47

#define RASTERMODE_MASK GENMASK(2, 0)

drivers/gpu/drm/imx/dc/dc-lb.c

20

#define PIXENGCFG_DYNAMIC_SEC_SEL_MASK GENMASK(13, 8)

drivers/gpu/drm/imx/dc/dc-lb.c

23

#define PIXENGCFG_DYNAMIC_PRIM_SEL_MASK GENMASK(5, 0)

drivers/gpu/drm/imx/dc/dc-lb.c

28

#define SHDTOKSEL_MASK GENMASK(4, 3)

drivers/gpu/drm/imx/dc/dc-lb.c

30

#define SHDLDSEL_MASK GENMASK(2, 1)

drivers/gpu/drm/imx/dc/dc-lb.c

38

#define ALPHA_MASK GENMASK(23, 16)

drivers/gpu/drm/imx/dc/dc-lb.c

40

#define SEC_A_BLD_FUNC_MASK GENMASK(14, 12)

drivers/gpu/drm/imx/dc/dc-lb.c

43

#define PRIM_A_BLD_FUNC_MASK GENMASK(10, 8)

drivers/gpu/drm/imx/dc/dc-lb.c

46

#define SEC_C_BLD_FUNC_MASK GENMASK(6, 4)

drivers/gpu/drm/imx/dc/dc-lb.c

49

#define PRIM_C_BLD_FUNC_MASK GENMASK(2, 0)

drivers/gpu/drm/imx/dc/dc-lb.c

54

#define YPOS_MASK GENMASK(31, 16)

drivers/gpu/drm/imx/dc/dc-lb.c

56

#define XPOS_MASK GENMASK(15, 0)

drivers/gpu/drm/imx/dcss/dcss-blkctl.c

20

#define DISPMIX_REFCLK_SEL_MASK GENMASK(5, 4)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

33

#define TILE_TYPE_MASK GENMASK(4, 2)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

37

#define PIX_SIZE_MASK GENMASK(9, 8)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

41

#define B_COMP_SEL_MASK GENMASK(13, 12)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

43

#define G_COMP_SEL_MASK GENMASK(15, 14)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

45

#define R_COMP_SEL_MASK GENMASK(17, 16)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

47

#define A_COMP_SEL_MASK GENMASK(19, 18)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

52

#define ROT_ENC_MASK GENMASK(3, 2)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

55

#define PITCH_MASK GENMASK(31, 16)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

65

#define STATUS_MUX_SEL_MASK GENMASK(2, 0)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

67

#define STATUS_SRC_SEL_MASK GENMASK(18, 16)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

72

#define THRES_HIGH_MASK GENMASK(3, 1)

drivers/gpu/drm/imx/dcss/dcss-dpr.c

74

#define THRES_LOW_MASK GENMASK(6, 4)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

25

#define CSS_PIX_COMP_SWAP_MASK GENMASK(14, 12)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

27

#define DEFAULT_FG_ALPHA_MASK GENMASK(31, 24)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

38

#define TC_X_MASK GENMASK(12, 0)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

40

#define TC_Y_MASK GENMASK(28, 16)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

43

#define TC_CTXLD_DB_Y_MASK GENMASK(12, 0)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

45

#define TC_CTXLD_SB_Y_MASK GENMASK(28, 16)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

49

#define BKRND_R_Y_COMP_MASK GENMASK(29, 20)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

51

#define BKRND_G_U_COMP_MASK GENMASK(19, 10)

drivers/gpu/drm/imx/dcss/dcss-dtg.c

53

#define BKRND_B_V_COMP_MASK GENMASK(9, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

20

#define OFIFO_LOW_THRES_MASK GENMASK(9, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

22

#define OFIFO_HIGH_THRES_MASK GENMASK(25, 16)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

34

#define A2R10G10B10_FORMAT_MASK GENMASK(11, 8)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

37

#define LUM_BIT_DEPTH_MASK GENMASK(1, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

39

#define CHR_BIT_DEPTH_MASK GENMASK(5, 4)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

42

#define FORMAT_MASK GENMASK(1, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

48

#define WIDTH_MASK GENMASK(11, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

50

#define HEIGHT_MASK GENMASK(27, 16)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

52

#define V_START_MASK GENMASK(15, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

54

#define V_INC_MASK GENMASK(15, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

56

#define H_START_MASK GENMASK(18, 0)

drivers/gpu/drm/imx/dcss/dcss-scaler.c

58

#define H_INC_MASK GENMASK(15, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

15

#define LRC_X_MASK GENMASK(12, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

17

#define LRC_Y_MASK GENMASK(28, 16)

drivers/gpu/drm/imx/dcss/dcss-ss.c

21

#define SYNC_START_MASK GENMASK(12, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

23

#define SYNC_END_MASK GENMASK(28, 16)

drivers/gpu/drm/imx/dcss/dcss-ss.c

27

#define ULC_X_MASK GENMASK(12, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

29

#define ULC_Y_MASK GENMASK(28, 16)

drivers/gpu/drm/imx/dcss/dcss-ss.c

34

#define PIPE_MODE_MASK GENMASK(1, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

37

#define HORIZ_A_MASK GENMASK(3, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

39

#define HORIZ_B_MASK GENMASK(7, 4)

drivers/gpu/drm/imx/dcss/dcss-ss.c

41

#define HORIZ_C_MASK GENMASK(11, 8)

drivers/gpu/drm/imx/dcss/dcss-ss.c

43

#define HORIZ_H_NORM_MASK GENMASK(14, 12)

drivers/gpu/drm/imx/dcss/dcss-ss.c

45

#define VERT_A_MASK GENMASK(19, 16)

drivers/gpu/drm/imx/dcss/dcss-ss.c

47

#define VERT_B_MASK GENMASK(23, 20)

drivers/gpu/drm/imx/dcss/dcss-ss.c

49

#define VERT_C_MASK GENMASK(27, 24)

drivers/gpu/drm/imx/dcss/dcss-ss.c

51

#define VERT_H_NORM_MASK GENMASK(30, 28)

drivers/gpu/drm/imx/dcss/dcss-ss.c

55

#define CLIP_MIN_MASK GENMASK(9, 0)

drivers/gpu/drm/imx/dcss/dcss-ss.c

57

#define CLIP_MAX_MASK GENMASK(23, 16)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

61

#define IMX21LCDC_LHCR_HWIDTH GENMASK(31, 26)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

62

#define IMX21LCDC_LHCR_HFPORCH GENMASK(15, 8) /* H_WAIT_1 in the i.MX25 Reference manual */

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

63

#define IMX21LCDC_LHCR_HBPORCH GENMASK(7, 0) /* H_WAIT_2 in the i.MX25 Reference manual */

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

65

#define IMX21LCDC_LVCR_VWIDTH GENMASK(31, 26)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

66

#define IMX21LCDC_LVCR_VFPORCH GENMASK(15, 8) /* V_WAIT_1 in the i.MX25 Reference manual */

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

67

#define IMX21LCDC_LVCR_VBPORCH GENMASK(7, 0) /* V_WAIT_2 in the i.MX25 Reference manual */

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

69

#define IMX21LCDC_LSR_XMAX GENMASK(25, 20)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

70

#define IMX21LCDC_LSR_YMAX GENMASK(9, 0)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

73

#define IMX21LCDC_LPCR_PCD GENMASK(5, 0)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

76

#define IMX21LCDC_LPCR_ACD GENMASK(14, 8)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

87

#define IMX21LCDC_LPCR_BPIX GENMASK(27, 25)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

88

#define IMX21LCDC_LPCR_PBSIZ GENMASK(29, 28)

drivers/gpu/drm/ingenic/ingenic-drm.h

189

#define JZ_LCD_DESSIZE_HEIGHT_MASK GENMASK(23, 12)

drivers/gpu/drm/ingenic/ingenic-drm.h

190

#define JZ_LCD_DESSIZE_WIDTH_MASK GENMASK(11, 0)

drivers/gpu/drm/logicvc/logicvc_regs.h

57

#define LOGICVC_IP_VERSION_MAJOR_MASK GENMASK(16, 11)

drivers/gpu/drm/logicvc/logicvc_regs.h

58

#define LOGICVC_IP_VERSION_MINOR_MASK GENMASK(10, 5)

drivers/gpu/drm/logicvc/logicvc_regs.h

59

#define LOGICVC_IP_VERSION_LEVEL_MASK GENMASK(4, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

101

#define VSYNC_END_MASK GENMASK(27, 16)

drivers/gpu/drm/loongson/lsdc_regs.h

103

#define VSYNC_START_MASK GENMASK(11, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

159

#define SYNC_DEVIATION_NUM GENMASK(12, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

178

#define CURSOR_FORMAT_MASK GENMASK(1, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

273

#define INT_STATUS_MASK GENMASK(15, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

326

#define HDMI_VIDEO_PREAMBLE_MASK GENMASK(7, 4)

drivers/gpu/drm/loongson/lsdc_regs.h

350

#define HDMI_PLL_IDF_MASK GENMASK(5, 1)

drivers/gpu/drm/loongson/lsdc_regs.h

352

#define HDMI_PLL_LF_MASK GENMASK(12, 6)

drivers/gpu/drm/loongson/lsdc_regs.h

354

#define HDMI_PLL_ODF_MASK GENMASK(15, 13)

drivers/gpu/drm/loongson/lsdc_regs.h

43

#define CFG_PIX_FMT_MASK GENMASK(2, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

79

#define CFG_DMA_STEP_MASK GENMASK(17, 16)

drivers/gpu/drm/loongson/lsdc_regs.h

88

#define CFG_VALID_BITS_MASK GENMASK(20, 0)

drivers/gpu/drm/loongson/lsdc_regs.h

93

#define HSYNC_END_MASK GENMASK(28, 16)

drivers/gpu/drm/loongson/lsdc_regs.h

95

#define HSYNC_START_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

25

#define DISP_AAL_SIZE_HSIZE GENMASK(28, 16)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

26

#define DISP_AAL_SIZE_VSIZE GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

29

#define DISP_AAL_GAMMA_LUT_R GENMASK(29, 20)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

30

#define DISP_AAL_GAMMA_LUT_G GENMASK(19, 10)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

31

#define DISP_AAL_GAMMA_LUT_B GENMASK(9, 0)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

27

#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

28

#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

30

#define DISP_GAMMA_BANK_BANK GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

36

#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

37

#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

38

#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

41

#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

42

#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

43

#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

25

#define FLD_SWAP_MODE GENMASK(4, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

30

#define FLD_CFG_MERGE_MODE GENMASK(4, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

41

#define FLD_BUFFER_MODE GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

51

#define FLD_ULTRA_TH_LOW GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

52

#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

58

#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

59

#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

46

#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(n) (GENMASK(1, 0) << (4 * (n)))

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

500

unsigned int pitch_lsb = pending->pitch & GENMASK(15, 0);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

86

#define OVL_COLOR_ALPHA GENMASK(31, 24)

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

34

#define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

101

#define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

103

#define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

106

#define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

125

#define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

126

#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

132

#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK GENMASK(14, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

139

#define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

144

#define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

152

#define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

154

#define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

156

#define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

158

#define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

162

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

17

#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

177

#define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

178

#define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

180

#define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

182

#define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

184

#define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

186

#define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

188

#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

19

#define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

190

#define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

192

#define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

194

#define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

196

#define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

198

#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

201

#define PGEN_PATTERN_SEL_MASK GENMASK(6, 4)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

204

#define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

209

#define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

214

#define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

220

#define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

224

#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

226

#define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

232

#define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

241

#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

258

#define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

259

#define HPD_INT_THD_DP_TRANS_P0_MASK GENMASK(7, 4)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

262

#define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

263

#define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

267

#define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

268

#define IRQ_MASK_DP_TRANS_P0_MASK GENMASK(7, 4)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

272

#define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

275

#define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

277

#define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

280

#define LANE_NUM_DP_TRANS_P0_MASK GENMASK(3, 2)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

290

#define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

291

#define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

293

#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

296

#define DP_TRANS_DUMMY_RW_0_MASK GENMASK(3, 2)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

300

#define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

303

#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

307

#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

311

#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

313

#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

315

#define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

320

#define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

324

#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

342

#define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

344

#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

346

#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

348

#define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

38

#define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

39

#define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

41

#define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

42

#define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

44

#define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

45

#define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

47

#define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

48

#define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

56

#define DP_PWR_STATE_MASK GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

59

#define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

61

#define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

63

#define DP_TX0_PRE_EMPH_MASK GENMASK(3, 2)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

65

#define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

67

#define DP_TX1_PRE_EMPH_MASK GENMASK(11, 10)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

68

#define DP_TX2_VOLT_SWING_MASK GENMASK(17, 16)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

69

#define DP_TX2_PRE_EMPH_MASK GENMASK(19, 18)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

70

#define DP_TX3_VOLT_SWING_MASK GENMASK(25, 24)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

71

#define DP_TX3_PRE_EMPH_MASK GENMASK(27, 26)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

82

#define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

91

#define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

93

#define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

95

#define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

97

#define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dp_reg.h

99

#define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)

drivers/gpu/drm/mediatek/mtk_dpi_regs.h

239

#define INT_MATRIX_SEL_MASK GENMASK(4, 0)

drivers/gpu/drm/mediatek/mtk_dpi_regs.h

245

#define DPI_PAT_SEL GENMASK(6, 4)

drivers/gpu/drm/mediatek/mtk_dsi.c

120

#define LPX GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

121

#define HS_PREP GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dsi.c

122

#define HS_ZERO GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

123

#define HS_TRAIL GENMASK(31, 24)

drivers/gpu/drm/mediatek/mtk_dsi.c

126

#define TA_GO GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

127

#define TA_SURE GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dsi.c

128

#define TA_GET GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

129

#define DA_HS_EXIT GENMASK(31, 24)

drivers/gpu/drm/mediatek/mtk_dsi.c

132

#define CONT_DET GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

133

#define DA_HS_SYNC GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dsi.c

134

#define CLK_ZERO GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

135

#define CLK_TRAIL GENMASK(31, 24)

drivers/gpu/drm/mediatek/mtk_dsi.c

138

#define CLK_HS_PREP GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

139

#define CLK_HS_POST GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dsi.c

140

#define CLK_HS_EXIT GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

151

#define CONFIG GENMASK(7, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

156

#define DATA_ID GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_dsi.c

157

#define DATA_0 GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

158

#define DATA_1 GENMASK(31, 24)

drivers/gpu/drm/mediatek/mtk_dsi.c

63

#define LANE_NUM GENMASK(5, 2)

drivers/gpu/drm/mediatek/mtk_dsi.c

69

#define MAX_RTN_SIZE GENMASK(15, 12)

drivers/gpu/drm/mediatek/mtk_dsi.c

73

#define DSI_PS_WC GENMASK(13, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

74

#define DSI_PS_SEL GENMASK(17, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

84

#define VACT_NL GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

86

#define DSI_HEIGHT GENMASK(30, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

87

#define DSI_WIDTH GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_dsi.c

91

#define HFP_HS_VB_PS_WC GENMASK(30, 16)

drivers/gpu/drm/mediatek/mtk_dsi.c

99

#define HSTX_CKL_WC GENMASK(15, 2)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

133

#define I2S_EN GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

143

#define MAX_1UI_WRITE GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

144

#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

145

#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

147

#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

148

#define AUD_ERR_THRESH GENMASK(29, 24)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

151

#define FIFO0_MAP GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

152

#define FIFO1_MAP GENMASK(3, 2)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

153

#define FIFO2_MAP GENMASK(5, 4)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

154

#define FIFO3_MAP GENMASK(7, 6)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

17

#define TMDS_PACK_MODE GENMASK(9, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

198

#define HPD_DDC_DELAY_CNT GENMASK(31, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

202

#define DDC_CTRL_ADDR GENMASK(7, 1)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

203

#define DDC_CTRL_OFFSET GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

204

#define DDC_CTRL_DIN_CNT GENMASK(25, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

205

#define DDC_CTRL_CMD GENMASK(31, 28)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

207

#define SCDC_DDC_SEGMENT GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

209

#define HPD_STATE GENMASK(1, 0)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

214

#define DDC_DATA_OUT GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

219

#define SI2C_WDATA GENMASK(15, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

220

#define SI2C_ADDR GENMASK(23, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

23

#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

33

#define SD0_MAP GENMASK(2, 0)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

34

#define SD1_MAP GENMASK(6, 4)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

35

#define SD2_MAP GENMASK(10, 8)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

36

#define SD3_MAP GENMASK(14, 12)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

37

#define SD4_MAP GENMASK(18, 16)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

38

#define SD5_MAP GENMASK(22, 20)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

39

#define SD6_MAP GENMASK(26, 24)

drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h

40

#define SD7_MAP GENMASK(30, 28)

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

1475

regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

1476

regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

27

#define FLD_RD_REQ_TYPE GENMASK(7, 4)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

29

#define FLD_ULTRA_EN GENMASK(13, 12)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

31

#define FLD_PRE_ULTRA_EN GENMASK(17, 16)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

36

#define FLD_BIT_NUMBER GENMASK(19, 18)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

40

#define FLD_SRC_FORMAT GENMASK(3, 0)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

46

#define FLD_MF_BKGD_WB GENMASK(22, 0)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

48

#define FLD_MF_SRC_H GENMASK(30, 16)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

49

#define FLD_MF_SRC_W GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

51

#define FLD_MF_CLIP_H GENMASK(30, 16)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

52

#define FLD_MF_CLIP_W GENMASK(14, 0)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

54

#define FLD_SRC_OFFSET_0 GENMASK(31, 0)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

56

#define FLD_INT_MATRIX_SEL GENMASK(27, 23)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

59

#define FLD_SRC_BASE_0 GENMASK(31, 0)

drivers/gpu/drm/meson/meson_crtc.c

139

writel(FIELD_PREP(GENMASK(11, 0), 2303),

drivers/gpu/drm/meson/meson_crtc.c

99

writel(FIELD_PREP(GENMASK(11, 0), 2303),

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

113

#define MIPI_DSI_TOP_DPI_COLOR_MODE GENMASK(23, 20)

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

114

#define MIPI_DSI_TOP_IN_COLOR_MODE GENMASK(18, 16)

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

115

#define MIPI_DSI_TOP_CHROMA_SUBSAMPLE GENMASK(15, 14)

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

116

#define MIPI_DSI_TOP_COMP2_SEL GENMASK(13, 12)

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

117

#define MIPI_DSI_TOP_COMP1_SEL GENMASK(11, 10)

drivers/gpu/drm/meson/meson_dw_mipi_dsi.h

118

#define MIPI_DSI_TOP_COMP0_SEL GENMASK(9, 8)

drivers/gpu/drm/meson/meson_overlay.c

103

#define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

104

#define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

107

#define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value)

drivers/gpu/drm/meson/meson_overlay.c

108

#define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value)

drivers/gpu/drm/meson/meson_overlay.c

109

#define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

112

#define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

115

#define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

116

#define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

119

#define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

120

#define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

121

#define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

122

#define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

125

#define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

126

#define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

130

#define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)

drivers/gpu/drm/meson/meson_overlay.c

133

#define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)

drivers/gpu/drm/meson/meson_overlay.c

134

#define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)

drivers/gpu/drm/meson/meson_overlay.c

138

#define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

139

#define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

142

#define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

143

#define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

146

#define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

147

#define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

150

#define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \

drivers/gpu/drm/meson/meson_overlay.c

151

((value) & GENMASK(12, 0)))

drivers/gpu/drm/meson/meson_overlay.c

152

#define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

155

#define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

156

#define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

159

#define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

29

#define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)

drivers/gpu/drm/meson/meson_overlay.c

31

#define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)

drivers/gpu/drm/meson/meson_overlay.c

38

#define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)

drivers/gpu/drm/meson/meson_overlay.c

39

#define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)

drivers/gpu/drm/meson/meson_overlay.c

40

#define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)

drivers/gpu/drm/meson/meson_overlay.c

43

#define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

44

#define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

47

#define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

48

#define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

51

#define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

54

#define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)

drivers/gpu/drm/meson/meson_overlay.c

57

#define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)

drivers/gpu/drm/meson/meson_overlay.c

58

#define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)

drivers/gpu/drm/meson/meson_overlay.c

62

#define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

63

#define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \

drivers/gpu/drm/meson/meson_overlay.c

64

((value) & GENMASK(13, 0)))

drivers/gpu/drm/meson/meson_overlay.c

67

#define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

68

#define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

71

#define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

72

#define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

75

#define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

76

#define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

79

#define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

80

#define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

87

#define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value)

drivers/gpu/drm/meson/meson_overlay.c

88

#define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value)

drivers/gpu/drm/meson/meson_overlay.c

89

#define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value)

drivers/gpu/drm/meson/meson_overlay.c

90

#define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value)

drivers/gpu/drm/meson/meson_overlay.c

91

#define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value)

drivers/gpu/drm/meson/meson_overlay.c

94

#define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value)

drivers/gpu/drm/meson/meson_overlay.c

95

#define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value)

drivers/gpu/drm/meson/meson_overlay.c

96

#define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value)

drivers/gpu/drm/meson/meson_overlay.c

97

#define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value)

drivers/gpu/drm/meson/meson_plane.c

31

#define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)

drivers/gpu/drm/meson/meson_plane.c

32

#define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)

drivers/gpu/drm/meson/meson_plane.c

36

#define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)

drivers/gpu/drm/meson/meson_plane.c

37

#define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)

drivers/gpu/drm/meson/meson_plane.c

44

#define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)

drivers/gpu/drm/meson/meson_plane.c

45

#define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)

drivers/gpu/drm/meson/meson_plane.c

46

#define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)

drivers/gpu/drm/meson/meson_plane.c

47

#define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)

drivers/gpu/drm/meson/meson_plane.c

48

#define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)

drivers/gpu/drm/meson/meson_plane.c

53

#define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)

drivers/gpu/drm/meson/meson_plane.c

54

#define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top)

drivers/gpu/drm/meson/meson_plane.c

57

#define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value)

drivers/gpu/drm/meson/meson_plane.c

58

#define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value)

drivers/gpu/drm/meson/meson_plane.c

59

#define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value)

drivers/gpu/drm/meson/meson_plane.c

64

#define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value)

drivers/gpu/drm/meson/meson_registers.h

1255

#define RDMA_ACCESS_TRIGGER_CHAN3 GENMASK(31, 24)

drivers/gpu/drm/meson/meson_registers.h

1256

#define RDMA_ACCESS_TRIGGER_CHAN2 GENMASK(23, 16)

drivers/gpu/drm/meson/meson_registers.h

1257

#define RDMA_ACCESS_TRIGGER_CHAN1 GENMASK(15, 8)

drivers/gpu/drm/meson/meson_registers.h

1277

#define RDMA_ACCESS_TRIGGER_CHAN7 GENMASK(31, 24)

drivers/gpu/drm/meson/meson_registers.h

1278

#define RDMA_ACCESS_TRIGGER_CHAN6 GENMASK(23, 16)

drivers/gpu/drm/meson/meson_registers.h

1279

#define RDMA_ACCESS_TRIGGER_CHAN5 GENMASK(15, 8)

drivers/gpu/drm/meson/meson_registers.h

1280

#define RDMA_ACCESS_TRIGGER_CHAN4 GENMASK(7, 0)

drivers/gpu/drm/meson/meson_registers.h

1295

#define RDMA_CTRL_AHB_WR_BURST GENMASK(5, 4)

drivers/gpu/drm/meson/meson_registers.h

1296

#define RDMA_CTRL_AHB_RD_BURST GENMASK(3, 2)

drivers/gpu/drm/meson/meson_registers.h

1326

#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0)

drivers/gpu/drm/meson/meson_registers.h

149

#define MALI_AFBC_MISC GENMASK(15, 8)

drivers/gpu/drm/meson/meson_registers.h

1720

#define OSD1_AFBCD_ID_FIFO_THRD GENMASK(15, 9)

drivers/gpu/drm/meson/meson_registers.h

1726

#define OSD1_AFBCD_MIF_URGENT GENMASK(25, 24)

drivers/gpu/drm/meson/meson_registers.h

1727

#define OSD1_AFBCD_HOLD_LINE_NUM GENMASK(22, 16)

drivers/gpu/drm/meson/meson_registers.h

1728

#define OSD1_AFBCD_RGBA_EXCHAN_CTRL GENMASK(15, 8)

drivers/gpu/drm/meson/meson_registers.h

1731

#define OSD1_AFBCD_HREG_PIXEL_PACKING_FMT GENMASK(4, 0)

drivers/gpu/drm/meson/meson_registers.h

1733

#define OSD1_AFBCD_HREG_VSIZE_IN GENMASK(31, 16)

drivers/gpu/drm/meson/meson_registers.h

1734

#define OSD1_AFBCD_HREG_HSIZE_IN GENMASK(15, 0)

drivers/gpu/drm/meson/meson_registers.h

1739

#define OSD1_AFBCD_CONV_LBUF_LEN GENMASK(15, 0)

drivers/gpu/drm/meson/meson_registers.h

1742

#define OSD1_AFBCD_DEC_PIXEL_BGN_H GENMASK(31, 16)

drivers/gpu/drm/meson/meson_registers.h

1743

#define OSD1_AFBCD_DEC_PIXEL_END_H GENMASK(15, 0)

drivers/gpu/drm/meson/meson_registers.h

1745

#define OSD1_AFBCD_DEC_PIXEL_BGN_V GENMASK(31, 16)

drivers/gpu/drm/meson/meson_registers.h

1746

#define OSD1_AFBCD_DEC_PIXEL_END_V GENMASK(15, 0)

drivers/gpu/drm/meson/meson_registers.h

1782

#define VPU_MAFBC_SUPER_BLOCK_ASPECT GENMASK(17, 16)

drivers/gpu/drm/meson/meson_registers.h

1785

#define VPU_MAFBC_PIXEL_FORMAT GENMASK(3, 0)

drivers/gpu/drm/meson/meson_registers.h

197

#define VIU_OSD1_MALI_AFBCD_R_REORDER GENMASK(15, 12)

drivers/gpu/drm/meson/meson_registers.h

198

#define VIU_OSD1_MALI_AFBCD_G_REORDER GENMASK(11, 8)

drivers/gpu/drm/meson/meson_registers.h

199

#define VIU_OSD1_MALI_AFBCD_B_REORDER GENMASK(7, 4)

drivers/gpu/drm/meson/meson_registers.h

200

#define VIU_OSD1_MALI_AFBCD_A_REORDER GENMASK(3, 0)

drivers/gpu/drm/meson/meson_registers.h

459

#define VPP_OFIFO_SIZE_MASK GENMASK(13, 0)

drivers/gpu/drm/mgag200/mgag200_g200wb.c

112

xpixpllcp = ((pixpllcn & GENMASK(10, 9)) >> 3) | (pixpllcs << 3) | pixpllcp;

drivers/gpu/drm/mgag200/mgag200_mode.c

173

opmode &= ~(GENMASK(17, 16) | GENMASK(9, 8) | GENMASK(3, 2));

drivers/gpu/drm/mgag200/mgag200_mode.c

386

crtcext3 &= ~GENMASK(2, 0);

drivers/gpu/drm/mgag200/mgag200_reg.h

232

#define MGAREG_MISC_CLKSEL_MASK GENMASK(3, 2)

drivers/gpu/drm/mgag200/mgag200_reg.h

260

#define MGAREG_CRTCEXT0_OFFSET_MASK GENMASK(5, 4)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

954

FIELD_PREP(GENMASK(30, 18), fence_range_upper) |

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

955

FIELD_PREP(GENMASK(17, 0), fence_range_lower));

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

981

(gmu->log.iova & GENMASK(31, 12)) |

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

982

((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

986

(gmu->log.iova & GENMASK(31, 12)) |

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

987

((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1405

FIELD_PREP(GENMASK(7, 0), 0x4));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1470

FIELD_PREP(GENMASK(19, 16), 6) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1471

FIELD_PREP(GENMASK(15, 12), 6) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1472

FIELD_PREP(GENMASK(11, 8), 9) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1474

FIELD_PREP(GENMASK(1, 0), 2));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1745

val &= GENMASK(6, 0);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1779

val &= GENMASK(6, 0);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2059

cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2083

gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2097

gpu_scid &= GENMASK(4, 0);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2100

FIELD_PREP(GENMASK(29, 25), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2101

FIELD_PREP(GENMASK(24, 20), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2102

FIELD_PREP(GENMASK(19, 15), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2103

FIELD_PREP(GENMASK(14, 10), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2104

FIELD_PREP(GENMASK(9, 5), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2105

FIELD_PREP(GENMASK(4, 0), gpu_scid));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2108

FIELD_PREP(GENMASK(14, 10), gpu_scid) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2207

#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

857

FIELD_PREP(GENMASK(8, 5), hbb_lo));

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

917

gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

947

gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0);

drivers/gpu/drm/msm/adreno/a6xx_hfi.h

214

#define AB_VOTE_MASK GENMASK(31, 16)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

112

adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1128

gpu_scid &= GENMASK(5, 0);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1131

FIELD_PREP(GENMASK(29, 24), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1132

FIELD_PREP(GENMASK(23, 18), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1133

FIELD_PREP(GENMASK(17, 12), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1134

FIELD_PREP(GENMASK(11, 6), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1135

FIELD_PREP(GENMASK(5, 0), gpu_scid));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1138

FIELD_PREP(GENMASK(27, 22), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1139

FIELD_PREP(GENMASK(21, 16), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1140

FIELD_PREP(GENMASK(15, 10), gpu_scid) |

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1149

#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

560

FIELD_PREP(GENMASK(7, 0), 0x4));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

817

val &= GENMASK(6, 0);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

890

u32 hw_fault_mask = GENMASK(6, 0);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

891

u32 sw_fault_mask = GENMASK(22, 16);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

98

slice_mask = GENMASK(info->max_slices - 1, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

43

#define CDM_CDWN2_V_PIXEL_METHOD_MASK GENMASK(6, 5)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

44

#define CDM_CDWN2_H_PIXEL_METHOD_MASK GENMASK(4, 3)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

15

#define CWB_MUX_MASK GENMASK(3, 0)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

16

#define CWB_MODE_MASK GENMASK(2, 0)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

93

#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

95

#define QOS_QOS_CTRL_CREQ_VBLANK_MASK GENMASK(21, 20)

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

64

#define MDP_DP_PHY_INTF_SEL_INTF0 GENMASK(2, 0)

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

65

#define MDP_DP_PHY_INTF_SEL_INTF1 GENMASK(5, 3)

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

66

#define MDP_DP_PHY_INTF_SEL_PHY0 GENMASK(8, 6)

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

67

#define MDP_DP_PHY_INTF_SEL_PHY1 GENMASK(11, 9)

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

68

#define MDP_DP_PHY_INTF_SEL_PHY2 GENMASK(14, 12)

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

292

.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

544

.reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */

drivers/gpu/drm/msm/dp/dp_reg.h

127

#define DP_MAINLINK_CTRL_FLUSH_MODE_MASK GENMASK(24, 23)

drivers/gpu/drm/msm/dp/dp_utils.h

22

#define HEADER_0_MASK GENMASK(7, 0)

drivers/gpu/drm/msm/dp/dp_utils.h

23

#define PARITY_0_MASK GENMASK(15, 8)

drivers/gpu/drm/msm/dp/dp_utils.h

24

#define HEADER_1_MASK GENMASK(23, 16)

drivers/gpu/drm/msm/dp/dp_utils.h

25

#define PARITY_1_MASK GENMASK(31, 24)

drivers/gpu/drm/msm/dp/dp_utils.h

26

#define HEADER_2_MASK GENMASK(7, 0)

drivers/gpu/drm/msm/dp/dp_utils.h

27

#define PARITY_2_MASK GENMASK(15, 8)

drivers/gpu/drm/msm/dp/dp_utils.h

28

#define HEADER_3_MASK GENMASK(23, 16)

drivers/gpu/drm/msm/dp/dp_utils.h

29

#define PARITY_3_MASK GENMASK(31, 24)

drivers/gpu/drm/msm/msm_iommu.c

56

pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0);

drivers/gpu/drm/msm/msm_iommu.c

60

pgsizes &= GENMASK(__ffs(addr_merge), 0);

drivers/gpu/drm/msm/msm_iommu.c

72

pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0);

drivers/gpu/drm/mxsfb/lcdif_regs.h

131

#define CTRL_FETCH_START_OPTION_RESV GENMASK(9, 8)

drivers/gpu/drm/mxsfb/lcdif_regs.h

132

#define CTRL_FETCH_START_OPTION_MASK GENMASK(9, 8)

drivers/gpu/drm/mxsfb/lcdif_regs.h

144

#define DISP_PARA_LINE_PATTERN_MASK GENMASK(29, 26)

drivers/gpu/drm/mxsfb/lcdif_regs.h

145

#define DISP_PARA_DISP_MODE_MASK GENMASK(25, 24)

drivers/gpu/drm/mxsfb/lcdif_regs.h

146

#define DISP_PARA_BGND_R_MASK GENMASK(23, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

147

#define DISP_PARA_BGND_G_MASK GENMASK(15, 8)

drivers/gpu/drm/mxsfb/lcdif_regs.h

148

#define DISP_PARA_BGND_B_MASK GENMASK(7, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

151

#define DISP_SIZE_DELTA_Y_MASK GENMASK(31, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

153

#define DISP_SIZE_DELTA_X_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

156

#define HSYN_PARA_BP_H_MASK GENMASK(31, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

158

#define HSYN_PARA_FP_H_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

161

#define VSYN_PARA_BP_V_MASK GENMASK(31, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

163

#define VSYN_PARA_FP_V_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

166

#define VSYN_HSYN_WIDTH_PW_V_MASK GENMASK(31, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

168

#define VSYN_HSYN_WIDTH_PW_H_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

189

#define CTRLDESCL0_1_HEIGHT_MASK GENMASK(31, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

191

#define CTRLDESCL0_1_WIDTH_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

194

#define CTRLDESCL0_3_P_SIZE_MASK GENMASK(22, 20)

drivers/gpu/drm/mxsfb/lcdif_regs.h

196

#define CTRLDESCL0_3_T_SIZE_MASK GENMASK(17, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

198

#define CTRLDESCL0_3_PITCH_MASK GENMASK(15, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

201

#define CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK GENMASK(3, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

212

#define CTRLDESCL0_5_BPP_MASK GENMASK(27, 24)

drivers/gpu/drm/mxsfb/lcdif_regs.h

217

#define CTRLDESCL0_5_YUV_FORMAT_MASK GENMASK(15, 14)

drivers/gpu/drm/mxsfb/lcdif_regs.h

223

#define CSC0_CTRL_CSC_MODE_MASK GENMASK(2, 1)

drivers/gpu/drm/mxsfb/lcdif_regs.h

227

#define CSC0_COEF0_A2_MASK GENMASK(26, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

229

#define CSC0_COEF0_A1_MASK GENMASK(10, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

232

#define CSC0_COEF1_B1_MASK GENMASK(26, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

234

#define CSC0_COEF1_A3_MASK GENMASK(10, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

237

#define CSC0_COEF2_B3_MASK GENMASK(26, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

239

#define CSC0_COEF2_B2_MASK GENMASK(10, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

242

#define CSC0_COEF3_C2_MASK GENMASK(26, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

244

#define CSC0_COEF3_C1_MASK GENMASK(10, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

247

#define CSC0_COEF4_D1_MASK GENMASK(24, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

249

#define CSC0_COEF4_C3_MASK GENMASK(10, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

252

#define CSC0_COEF5_D3_MASK GENMASK(24, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

254

#define CSC0_COEF5_D2_MASK GENMASK(8, 0)

drivers/gpu/drm/mxsfb/lcdif_regs.h

256

#define PANIC0_THRES_LOW_MASK GENMASK(24, 16)

drivers/gpu/drm/mxsfb/lcdif_regs.h

257

#define PANIC0_THRES_HIGH_MASK GENMASK(8, 0)

drivers/gpu/drm/nouveau/dispnv50/base907c.c

132

return ret & GENMASK(18, 0);

drivers/gpu/drm/panel/panel-auo-a030jtn01.c

28

#define REG06_VBLK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-auo-a030jtn01.c

29

#define REG07_HBLK GENMASK(7, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

100

#define HX8279_P6_VOLT_ADJ_VCCS GENMASK(1, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

105

#define HX8279_DGAMMA_DGMA1_HI GENMASK(7, 6)

drivers/gpu/drm/panel/panel-himax-hx8279.c

106

#define HX8279_DGAMMA_DGMA2_HI GENMASK(5, 4)

drivers/gpu/drm/panel/panel-himax-hx8279.c

107

#define HX8279_DGAMMA_DGMA3_HI GENMASK(3, 2)

drivers/gpu/drm/panel/panel-himax-hx8279.c

108

#define HX8279_DGAMMA_DGMA4_HI GENMASK(1, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

25

#define HX8279_PAGE_SEL GENMASK(3, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

32

#define HX8279_P0_VG_SEL GENMASK(4, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

48

#define HX8279_GOUT_STB GENMASK(7, 6)

drivers/gpu/drm/panel/panel-himax-hx8279.c

49

#define HX8279_GOUT_SEL GENMASK(5, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

62

#define HX8279_P3_GOA_STV_LEAD GENMASK(4, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

64

#define HX8279_P3_GOA_CKV_LEAD GENMASK(4, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

68

#define HX8279_P3_GOA_CKV_DUMMY GENMASK(5, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

75

#define HX8279_P3_GOA_CLR_CFG_STARTPOS GENMASK(6, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

83

#define HX8279_P5_TIMING_THS_SETTLE GENMASK(7, 5)

drivers/gpu/drm/panel/panel-himax-hx8279.c

85

#define HX8279_P5_TIMING_TLPX GENMASK(3, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

95

#define HX8279_P6_GAMMA_POCGM_CTL GENMASK(6, 4)

drivers/gpu/drm/panel/panel-himax-hx8279.c

96

#define HX8279_P6_GAMMA_POGCMD_CTL GENMASK(2, 0)

drivers/gpu/drm/panel/panel-himax-hx8279.c

99

#define HX8279_P6_VOLT_ADJ_VCCIFS GENMASK(3, 2)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

26

#define ST7701_CMD2BK_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

48

#define ST7701_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

49

#define ST7701_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

50

#define ST7701_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

51

#define ST7701_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

52

#define ST7701_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

53

#define ST7701_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

54

#define ST7701_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

55

#define ST7701_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

56

#define ST7701_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

57

#define ST7701_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

58

#define ST7701_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

59

#define ST7701_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

60

#define ST7701_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

61

#define ST7701_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

62

#define ST7701_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

63

#define ST7701_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

64

#define ST7701_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

65

#define ST7701_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

67

#define ST7701_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

68

#define ST7701_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

69

#define ST7701_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

70

#define ST7701_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

71

#define ST7701_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

72

#define ST7701_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

75

#define ST7701_CMD2_BK1_VRHA_MASK GENMASK(7, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

76

#define ST7701_CMD2_BK1_VCOM_MASK GENMASK(7, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

77

#define ST7701_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

80

#define ST7701_CMD2_BK1_VGLS_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

81

#define ST7701_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

82

#define ST7701_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

83

#define ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

84

#define ST7701_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

85

#define ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

86

#define ST7701_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

87

#define ST7701_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

88

#define ST7701_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4)

drivers/gpu/drm/panel/panel-sitronix-st7701.c

89

#define ST7701_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)

drivers/gpu/drm/panel/panel-sitronix-st7789v.c

203

bit9 = rxbuf[i] & GENMASK(i - 1, 0);

drivers/gpu/drm/panel/panel-tpo-tpg110.c

29

#define TPG110_RES_MASK GENMASK(2, 0)

drivers/gpu/drm/panfrost/panfrost_device.h

30

(GENMASK(16 + NUM_JOB_SLOTS - 1, 16) | \

drivers/gpu/drm/panfrost/panfrost_device.h

31

GENMASK(NUM_JOB_SLOTS - 1, 0))

drivers/gpu/drm/panfrost/panfrost_perfcnt.c

306

nl2c = ((pfdev->features.mem_features >> 8) & GENMASK(3, 0)) + 1;

drivers/gpu/drm/panfrost/panfrost_regs.h

19

#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0))

drivers/gpu/drm/panfrost/panfrost_regs.h

20

#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0))

drivers/gpu/drm/panthor/panthor_drv.c

1203

ret = panthor_heap_destroy(pool, args->handle & GENMASK(15, 0));

drivers/gpu/drm/panthor/panthor_fw.c

105

#define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_MASK GENMASK(4, 3)

drivers/gpu/drm/panthor/panthor_fw.h

108

#define CS_STATUS_BLOCKED_REASON_MASK GENMASK(3, 0)

drivers/gpu/drm/panthor/panthor_fw.h

113

#define CS_EXCEPTION_TYPE(x) ((x) & GENMASK(7, 0))

drivers/gpu/drm/panthor/panthor_fw.h

114

#define CS_EXCEPTION_DATA(x) (((x) >> 8) & GENMASK(23, 0))

drivers/gpu/drm/panthor/panthor_fw.h

138

#define CSG_STATE_MASK GENMASK(2, 0)

drivers/gpu/drm/panthor/panthor_fw.h

165

#define CSG_EP_REQ_COMPUTE(x) ((x) & GENMASK(7, 0))

drivers/gpu/drm/panthor/panthor_fw.h

166

#define CSG_EP_REQ_FRAGMENT(x) (((x) << 8) & GENMASK(15, 8))

drivers/gpu/drm/panthor/panthor_fw.h

167

#define CSG_EP_REQ_TILER(x) (((x) << 16) & GENMASK(19, 16))

drivers/gpu/drm/panthor/panthor_fw.h

170

#define CSG_EP_REQ_PRIORITY_MASK GENMASK(31, 28)

drivers/gpu/drm/panthor/panthor_fw.h

218

#define GLB_STATE_MASK GENMASK(14, 12)

drivers/gpu/drm/panthor/panthor_fw.h

234

#define GLB_REQ_MASK GENMASK(10, 0)

drivers/gpu/drm/panthor/panthor_fw.h

235

#define GLB_EVT_MASK GENMASK(26, 20)

drivers/gpu/drm/panthor/panthor_fw.h

242

#define GLB_TIMER_VAL(x) ((x) & GENMASK(30, 0))

drivers/gpu/drm/panthor/panthor_fw.h

26

#define CS_FEATURES_WORK_REGS(x) (((x) & GENMASK(7, 0)) + 1)

drivers/gpu/drm/panthor/panthor_fw.h

27

#define CS_FEATURES_SCOREBOARDS(x) (((x) & GENMASK(15, 8)) >> 8)

drivers/gpu/drm/panthor/panthor_fw.h

37

#define CS_STATE_MASK GENMASK(2, 0)

drivers/gpu/drm/panthor/panthor_fw.h

61

#define CS_CONFIG_PRIORITY(x) ((x) & GENMASK(3, 0))

drivers/gpu/drm/panthor/panthor_fw.h

62

#define CS_CONFIG_DOORBELL(x) (((x) << 8) & GENMASK(15, 8))

drivers/gpu/drm/panthor/panthor_fw.h

84

#define CS_STATUS_WAIT_SB_MASK GENMASK(15, 0)

drivers/gpu/drm/panthor/panthor_fw.h

85

#define CS_STATUS_WAIT_SB_SRC_MASK GENMASK(19, 16)

drivers/gpu/drm/panthor/panthor_fw.h

90

#define CS_STATUS_WAIT_SYNC_COND_MASK GENMASK(27, 24)

drivers/gpu/drm/panthor/panthor_mmu.c

2884

ptdev->gpu_info.mmu_features &= ~GENMASK(7, 0);

drivers/gpu/drm/panthor/panthor_mmu.c

612

return value & GENMASK(15, 0);

drivers/gpu/drm/panthor/panthor_regs.h

15

#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24)

drivers/gpu/drm/panthor/panthor_regs.h

16

#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20)

drivers/gpu/drm/panthor/panthor_regs.h

17

#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16)

drivers/gpu/drm/panthor/panthor_regs.h

18

#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12)

drivers/gpu/drm/panthor/panthor_regs.h

19

#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4)

drivers/gpu/drm/panthor/panthor_regs.h

20

#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0))

drivers/gpu/drm/panthor/panthor_regs.h

23

#define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))

drivers/gpu/drm/panthor/panthor_regs.h

32

#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0))

drivers/gpu/drm/panthor/panthor_regs.h

33

#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0))

drivers/gpu/drm/panthor/panthor_sched.c

2141

group->fatal_queues |= GENMASK(group->queue_count - 1, 0);

drivers/gpu/drm/panthor/panthor_sched.c

3185

params->waitall_mask = GENMASK(sched->sb_slot_count - 1, 0);

drivers/gpu/drm/panthor/panthor_sched.c

3745

group->idle_queues = GENMASK(group->queue_count - 1, 0);

drivers/gpu/drm/panthor/panthor_sched.c

391

#define CSF_MAX_QUEUE_PRIO GENMASK(3, 0)

drivers/gpu/drm/panthor/panthor_sched.c

3980

if (qsubmit->latest_flush & GENMASK(30, 24))

drivers/gpu/drm/panthor/panthor_sched.c

4119

gpu_as_count = hweight32(ptdev->gpu_info.as_present & GENMASK(31, 1));

drivers/gpu/drm/pl111/pl111_drm.h

54

#define TIM2_PCD_LO_MASK GENMASK(4, 0)

drivers/gpu/drm/pl111/pl111_drm.h

57

#define TIM2_ACB_MASK GENMASK(10, 6)

drivers/gpu/drm/pl111/pl111_drm.h

63

#define TIM2_PCD_HI_MASK GENMASK(31, 27)

drivers/gpu/drm/pl111/pl111_versatile.c

114

#define INTEGRATOR_CLCD_MASK GENMASK(19, 8)

drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c

910

& GENMASK(1, 0);

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

682

phycr = rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0);

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

117

#define DSISETR_MRPSZ GENMASK(15, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

124

#define RXRSS0R_DT GENMASK(21, 16)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

125

#define RXRSS0R_DATA1 GENMASK(15, 8)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

126

#define RXRSS0R_DATA0 GENMASK(7, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

127

#define RXRSS0R_WC GENMASK(15, 0) /* Word count for long packet. */

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

212

#define SQCH0DSC0AR_BTA GENMASK(27, 26)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

221

#define SQCH0DSC0AR_DT GENMASK(21, 16)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

222

#define SQCH0DSC0AR_DATA1 GENMASK(15, 8)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

223

#define SQCH0DSC0AR_DATA0 GENMASK(7, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

51

#define PLLCLKSET0R_PLL_S GENMASK(2, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

52

#define PLLCLKSET0R_PLL_P GENMASK(13, 8)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

53

#define PLLCLKSET0R_PLL_M GENMASK(25, 16)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

56

#define PLLCLKSET1R_PLL_K GENMASK(15, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

59

#define PHYTCLKSETR_TCLKTRAILCTL GENMASK(7, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

60

#define PHYTCLKSETR_TCLKPOSTCTL GENMASK(15, 8)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

61

#define PHYTCLKSETR_TCLKZEROCTL GENMASK(23, 16)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

62

#define PHYTCLKSETR_TCLKPRPRCTL GENMASK(31, 24)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

65

#define PHYTHSSETR_THSEXITCTL GENMASK(7, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

66

#define PHYTHSSETR_THSTRAILCTL GENMASK(15, 8)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

67

#define PHYTHSSETR_THSZEROCTL GENMASK(23, 16)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

68

#define PHYTHSSETR_THSPRPRCTL GENMASK(31, 24)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

71

#define PHYTLPXSETR_TLPXCTL GENMASK(7, 0)

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

74

#define PHYCR_ULPSEXIT GENMASK(9, 0)

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

111

mask = GENMASK(field->msb, field->lsb);

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

159

#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10)

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

1605

GENMASK(dsi->dphy_config.lanes - 1, 0)));

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

193

#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)

drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c

94

(val << field->lsb) | (GENMASK(field->msb, field->lsb) << 16));

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

42

#define RK3576_COLOR_DEPTH_MASK GENMASK(11, 8)

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

45

#define RK3576_COLOR_FORMAT_MASK GENMASK(7, 4)

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

73

#define RK3588_COLOR_DEPTH_MASK GENMASK(7, 4)

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

76

#define RK3588_COLOR_FORMAT_MASK GENMASK(3, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

494

#define TRANSFORM_XOFFSET GENMASK(7, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

495

#define TRANSFORM_YOFFSET GENMASK(23, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

643

#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

654

#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

658

#define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

659

#define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

664

#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

666

#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

668

#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

669

#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

670

#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

671

#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

672

#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

679

#define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

680

#define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

681

#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

682

#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

683

#define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

684

#define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

685

#define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

695

#define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

696

#define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

697

#define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

698

#define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

699

#define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

700

#define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

702

#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

703

#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

704

#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

705

#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

707

#define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

708

#define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

710

#define RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL GENMASK(13, 12)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

725

#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL GENMASK(31, 30)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

729

#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

731

#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

732

#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

733

#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

734

#define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

735

#define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

736

#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

737

#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

738

#define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

739

#define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

740

#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

741

#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

742

#define RK3588_OVL_PORT_SET__PORT3_MUX GENMASK(15, 12)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

743

#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

744

#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

745

#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

748

#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

749

#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

750

#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

751

#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

757

#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

758

#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

759

#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

760

#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

773

#define RK3576_OVL_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

778

#define RK3576_DSP_IF_PIN_POL GENMASK(5, 4)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

779

#define RK3576_DSP_IF_MUX GENMASK(3, 2)

drivers/gpu/drm/rockchip/rockchip_lvds.h

118

#define PX30_LVDS_FORMAT(val) FIELD_PREP_WM16(GENMASK(14, 13), (val))

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1720

FIELD_PREP_WM16(GENMASK(6, 5), val));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1733

FIELD_PREP_WM16(GENMASK(8, 7), val));

drivers/gpu/drm/sitronix/st7571.c

47

#define ST7571_SET_COLUMN_LSB(c) (0x00 | FIELD_PREP(GENMASK(3, 0), (c)))

drivers/gpu/drm/sitronix/st7571.c

48

#define ST7571_SET_COLUMN_MSB(c) (0x10 | FIELD_PREP(GENMASK(2, 0), (c) >> 4))

drivers/gpu/drm/sitronix/st7571.c

49

#define ST7571_SET_COM0_LSB(x) (FIELD_PREP(GENMASK(6, 0), (x)))

drivers/gpu/drm/sitronix/st7571.c

51

#define ST7571_SET_COM_SCAN_DIR(d) (0xc0 | FIELD_PREP(GENMASK(3, 3), (d)))

drivers/gpu/drm/sitronix/st7571.c

52

#define ST7571_SET_CONTRAST_LSB(c) (FIELD_PREP(GENMASK(5, 0), (c)))

drivers/gpu/drm/sitronix/st7571.c

54

#define ST7571_SET_DISPLAY_DUTY_LSB(d) (FIELD_PREP(GENMASK(7, 0), (d)))

drivers/gpu/drm/sitronix/st7571.c

56

#define ST7571_SET_ENTIRE_DISPLAY_ON(p) (0xa4 | FIELD_PREP(GENMASK(0, 0), (p)))

drivers/gpu/drm/sitronix/st7571.c

57

#define ST7571_SET_LCD_BIAS(b) (0x50 | FIELD_PREP(GENMASK(2, 0), (b)))

drivers/gpu/drm/sitronix/st7571.c

58

#define ST7571_SET_MODE_LSB(m) (FIELD_PREP(GENMASK(7, 2), (m)))

drivers/gpu/drm/sitronix/st7571.c

60

#define ST7571_SET_PAGE(p) (0xb0 | FIELD_PREP(GENMASK(3, 0), (p)))

drivers/gpu/drm/sitronix/st7571.c

61

#define ST7571_SET_POWER(p) (0x28 | FIELD_PREP(GENMASK(2, 0), (p)))

drivers/gpu/drm/sitronix/st7571.c

62

#define ST7571_SET_REGULATOR_REG(r) (0x20 | FIELD_PREP(GENMASK(2, 0), (r)))

drivers/gpu/drm/sitronix/st7571.c

63

#define ST7571_SET_REVERSE(r) (0xa6 | FIELD_PREP(GENMASK(0, 0), (r)))

drivers/gpu/drm/sitronix/st7571.c

64

#define ST7571_SET_SEG_SCAN_DIR(d) (0xa0 | FIELD_PREP(GENMASK(0, 0), (d)))

drivers/gpu/drm/sitronix/st7571.c

65

#define ST7571_SET_START_LINE_LSB(l) (FIELD_PREP(GENMASK(6, 0), (l)))

drivers/gpu/drm/sitronix/st7571.c

70

#define ST7571_SET_COLOR_MODE(c) (0x10 | FIELD_PREP(GENMASK(0, 0), (c)))

drivers/gpu/drm/sitronix/st7571.c

74

#define ST7567_SET_LCD_BIAS(m) (0xa2 | FIELD_PREP(GENMASK(0, 0), (m)))

drivers/gpu/drm/solomon/ssd130x.c

57

#define SSD13XX_SET_SEG_REMAP_MASK GENMASK(0, 0)

drivers/gpu/drm/solomon/ssd130x.c

78

#define SSD130X_PAGE_COL_START_MASK GENMASK(3, 0)

drivers/gpu/drm/solomon/ssd130x.c

81

#define SSD130X_START_PAGE_ADDRESS_MASK GENMASK(2, 0)

drivers/gpu/drm/solomon/ssd130x.c

83

#define SSD130X_SET_COM_SCAN_DIR_MASK GENMASK(3, 3)

drivers/gpu/drm/solomon/ssd130x.c

85

#define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0)

drivers/gpu/drm/solomon/ssd130x.c

87

#define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4)

drivers/gpu/drm/solomon/ssd130x.c

89

#define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0)

drivers/gpu/drm/solomon/ssd130x.c

91

#define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4)

drivers/gpu/drm/solomon/ssd130x.c

93

#define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4)

drivers/gpu/drm/solomon/ssd130x.c

95

#define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5)

drivers/gpu/drm/sprd/sprd_dsi.c

102

#define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

103

#define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16)

drivers/gpu/drm/sprd/sprd_dsi.c

121

#define VIDEO_SIG_DELAY GENMASK(23, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

128

#define PHY_TESTDIN GENMASK(7, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

129

#define PHY_TESTDOUT GENMASK(15, 8)

drivers/gpu/drm/sprd/sprd_dsi.c

27

#define GEN_RX_VCID GENMASK(1, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

28

#define VIDEO_PKT_VCID GENMASK(3, 2)

drivers/gpu/drm/sprd/sprd_dsi.c

31

#define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

35

#define VIDEO_PKT_SIZE GENMASK(15, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

36

#define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16)

drivers/gpu/drm/sprd/sprd_dsi.c

39

#define VIDEO_LINE_HBP_TIME GENMASK(15, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

40

#define VIDEO_LINE_HSA_TIME GENMASK(31, 16)

drivers/gpu/drm/sprd/sprd_dsi.c

45

#define VFP_LINES GENMASK(9, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

46

#define VBP_LINES GENMASK(19, 10)

drivers/gpu/drm/sprd/sprd_dsi.c

47

#define VSA_LINES GENMASK(29, 20)

drivers/gpu/drm/sprd/sprd_dsi.c

52

#define VID_MODE_TYPE GENMASK(1, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

71

#define GEN_DT GENMASK(5, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

72

#define GEN_VC GENMASK(7, 6)

drivers/gpu/drm/sprd/sprd_dsi.c

98

#define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0)

drivers/gpu/drm/sprd/sprd_dsi.c

99

#define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16)

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

30

#define VERSION GENMASK(31, 8)

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

36

#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

46

#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

51

#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

52

#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

53

#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */

drivers/gpu/drm/stm/ltdc.c

117

#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */

drivers/gpu/drm/stm/ltdc.c

118

#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */

drivers/gpu/drm/stm/ltdc.c

120

#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */

drivers/gpu/drm/stm/ltdc.c

121

#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */

drivers/gpu/drm/stm/ltdc.c

123

#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */

drivers/gpu/drm/stm/ltdc.c

124

#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */

drivers/gpu/drm/stm/ltdc.c

126

#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */

drivers/gpu/drm/stm/ltdc.c

127

#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */

drivers/gpu/drm/stm/ltdc.c

137

#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */

drivers/gpu/drm/stm/ltdc.c

138

#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */

drivers/gpu/drm/stm/ltdc.c

139

#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */

drivers/gpu/drm/stm/ltdc.c

141

#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */

drivers/gpu/drm/stm/ltdc.c

142

#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */

drivers/gpu/drm/stm/ltdc.c

158

#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */

drivers/gpu/drm/stm/ltdc.c

165

#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */

drivers/gpu/drm/stm/ltdc.c

166

#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */

drivers/gpu/drm/stm/ltdc.c

167

#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */

drivers/gpu/drm/stm/ltdc.c

168

#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */

drivers/gpu/drm/stm/ltdc.c

178

#define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */

drivers/gpu/drm/stm/ltdc.c

197

#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */

drivers/gpu/drm/stm/ltdc.c

198

#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */

drivers/gpu/drm/stm/ltdc.c

200

#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */

drivers/gpu/drm/stm/ltdc.c

201

#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */

drivers/gpu/drm/stm/ltdc.c

203

#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */

drivers/gpu/drm/stm/ltdc.c

206

#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */

drivers/gpu/drm/stm/ltdc.c

208

#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */

drivers/gpu/drm/stm/ltdc.c

209

#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */

drivers/gpu/drm/stm/ltdc.c

210

#define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */

drivers/gpu/drm/stm/ltdc.c

212

#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */

drivers/gpu/drm/stm/ltdc.c

213

#define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */

drivers/gpu/drm/stm/ltdc.c

215

#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */

drivers/gpu/drm/stm/ltdc.c

226

#define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */

drivers/gpu/drm/stm/ltdc.c

48

#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)

drivers/gpu/drm/stm/lvds.c

100

#define PHY_PLLCR2_BDIV GENMASK(9, 0) /* BDIV mask value */

drivers/gpu/drm/stm/lvds.c

102

#define PHY_PLLSDCR1_MDIV GENMASK(9, 0) /* MDIV mask value */

drivers/gpu/drm/stm/lvds.c

103

#define PHY_PLLTESTCR_TDIV GENMASK(25, 16) /* TDIV mask value */

drivers/gpu/drm/stm/lvds.c

62

#define CR_LK1POL GENMASK(20, 16) /* Link-1 output Polarity */

drivers/gpu/drm/stm/lvds.c

63

#define CR_LK2POL GENMASK(25, 21) /* Link-2 output Polarity */

drivers/gpu/drm/stm/lvds.c

65

#define DMMCR_MAP0 GENMASK(4, 0) /* Mapping for bit 0 of datalane x */

drivers/gpu/drm/stm/lvds.c

66

#define DMMCR_MAP1 GENMASK(9, 5) /* Mapping for bit 1 of datalane x */

drivers/gpu/drm/stm/lvds.c

67

#define DMMCR_MAP2 GENMASK(14, 10) /* Mapping for bit 2 of datalane x */

drivers/gpu/drm/stm/lvds.c

68

#define DMMCR_MAP3 GENMASK(19, 15) /* Mapping for bit 3 of datalane x */

drivers/gpu/drm/stm/lvds.c

69

#define DMLCR_MAP4 GENMASK(4, 0) /* Mapping for bit 4 of datalane x */

drivers/gpu/drm/stm/lvds.c

70

#define DMLCR_MAP5 GENMASK(9, 5) /* Mapping for bit 5 of datalane x */

drivers/gpu/drm/stm/lvds.c

71

#define DMLCR_MAP6 GENMASK(14, 10) /* Mapping for bit 6 of datalane x */

drivers/gpu/drm/stm/lvds.c

73

#define CDLCR_DISTR0 GENMASK(3, 0) /* Channel distribution for lane 0 */

drivers/gpu/drm/stm/lvds.c

74

#define CDLCR_DISTR1 GENMASK(7, 4) /* Channel distribution for lane 1 */

drivers/gpu/drm/stm/lvds.c

75

#define CDLCR_DISTR2 GENMASK(11, 8) /* Channel distribution for lane 2 */

drivers/gpu/drm/stm/lvds.c

76

#define CDLCR_DISTR3 GENMASK(15, 12) /* Channel distribution for lane 3 */

drivers/gpu/drm/stm/lvds.c

77

#define CDLCR_DISTR4 GENMASK(19, 16) /* Channel distribution for lane 4 */

drivers/gpu/drm/stm/lvds.c

94

#define PHY_CFGCR_EN_DIG_DL GENMASK(4, 0) /* LVDS PHY digital lane enable */

drivers/gpu/drm/stm/lvds.c

99

#define PHY_PLLCR2_NDIV GENMASK(25, 16) /* NDIV mask value */

drivers/gpu/drm/sun4i/sun4i_backend.h

115

#define SUN4I_BACKEND_IYUVCTL_FBFMT_MASK GENMASK(14, 12)

drivers/gpu/drm/sun4i/sun4i_backend.h

121

#define SUN4I_BACKEND_IYUVCTL_FBPS_MASK GENMASK(9, 8)

drivers/gpu/drm/sun4i/sun4i_backend.h

23

#define SUN4I_BACKEND_MODCTL_OUT_SEL GENMASK(22, 20)

drivers/gpu/drm/sun4i/sun4i_backend.h

56

#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l) GENMASK(3 + ((l) * 8), (l) * 8)

drivers/gpu/drm/sun4i/sun4i_backend.h

67

#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK GENMASK(31, 24)

drivers/gpu/drm/sun4i/sun4i_backend.h

71

#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK GENMASK(11, 10)

drivers/gpu/drm/sun4i/sun4i_backend.h

78

#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT GENMASK(15, 14)

drivers/gpu/drm/sun4i/sun4i_backend.h

79

#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT GENMASK(13, 12)

drivers/gpu/drm/sun4i/sun4i_backend.h

80

#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT GENMASK(11, 8)

drivers/gpu/drm/sun4i/sun4i_hdmi.h

134

#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4)

drivers/gpu/drm/sun4i/sun4i_hdmi.h

137

#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)

drivers/gpu/drm/sun4i/sun4i_hdmi.h

37

#define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))

drivers/gpu/drm/sun4i/sun4i_hdmi.h

38

#define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)

drivers/gpu/drm/sun4i/sun4i_hdmi.h

88

#define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4)

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

333

#define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

334

#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))

drivers/gpu/drm/sun4i/sun4i_tcon.c

394

tcon_div &= GENMASK(6, 0);

drivers/gpu/drm/sun4i/sun4i_tcon.h

110

#define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0)

drivers/gpu/drm/sun4i/sun4i_tcon.h

124

#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0)

drivers/gpu/drm/sun4i/sun4i_tcon.h

129

#define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4)

drivers/gpu/drm/sun4i/sun4i_tcon.h

131

#define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0)

drivers/gpu/drm/sun4i/sun4i_tcon.h

55

#define SUN4I_TCON0_CTL_IF_MASK GENMASK(25, 24)

drivers/gpu/drm/sun4i/sun4i_tcon.h

57

#define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4)

drivers/gpu/drm/sun4i/sun4i_tcon.h

59

#define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0)

drivers/gpu/drm/sun4i/sun4i_tcon.h

85

#define SUN4I_TCON0_CPU_IF_MODE_MASK GENMASK(31, 28)

drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c

124

GENMASK(6, 0), div);

drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c

148

GENMASK(29, 28),

drivers/gpu/drm/sun4i/sun4i_tv.c

30

#define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)

drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c

332

u8 lanes_mask = GENMASK(device->lanes - 1, 0);

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

112

#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

133

#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

142

#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

144

#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

18

#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

21

#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

48

#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12)

drivers/gpu/drm/sun4i/sun8i_mixer.h

63

#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)

drivers/gpu/drm/sun4i/sun8i_tcon_top.h

15

#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)

drivers/gpu/drm/sun4i/sun8i_tcon_top.h

16

#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)

drivers/gpu/drm/sun4i/sun8i_tcon_top.h

19

#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)

drivers/gpu/drm/sun4i/sun8i_ui_layer.h

39

#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)

drivers/gpu/drm/sun4i/sun8i_ui_layer.h

40

#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)

drivers/gpu/drm/sun4i/sun8i_ui_layer.h

42

#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)

drivers/gpu/drm/sun4i/sun8i_vi_layer.h

36

#define SUN8I_MIXER_FCC_GLOBAL_ALPHA_MASK GENMASK(31, 24)

drivers/gpu/drm/sun4i/sun8i_vi_layer.h

42

#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)

drivers/gpu/drm/sun4i/sun8i_vi_layer.h

43

#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)

drivers/gpu/drm/sun4i/sun8i_vi_layer.h

44

#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)

drivers/gpu/drm/tidss/tidss_dispc.c

1543

#define OVAL(x, y) (FIELD_PREP(GENMASK(15, 3), x) | FIELD_PREP(GENMASK(31, 19), y))

drivers/gpu/drm/tidss/tidss_dispc.c

1550

#define CVAL(x, y) (FIELD_PREP(GENMASK(10, 0), x) | FIELD_PREP(GENMASK(26, 16), y))

drivers/gpu/drm/tidss/tidss_dispc.c

1790

c12 = FIELD_PREP(GENMASK(19, 10), c1) | FIELD_PREP(GENMASK(29, 20),

drivers/gpu/drm/tidss/tidss_dispc.c

2631

#define CVAL(xR, xG, xB) (FIELD_PREP(GENMASK(9, 0), xR) | FIELD_PREP(GENMASK(20, 11), xG) | \

drivers/gpu/drm/tidss/tidss_dispc.c

2632

FIELD_PREP(GENMASK(31, 22), xB))

drivers/gpu/drm/tidss/tidss_dispc.c

2803

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(1, 1)),

drivers/gpu/drm/tidss/tidss_dispc.c

2804

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(2, 2)),

drivers/gpu/drm/tidss/tidss_dispc.c

2805

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(3, 3)));

drivers/gpu/drm/tidss/tidss_dispc.c

2810

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)),

drivers/gpu/drm/tidss/tidss_dispc.c

2811

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)),

drivers/gpu/drm/tidss/tidss_dispc.c

2812

REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7)));

drivers/gpu/drm/tidss/tidss_dispc_regs.h

102

#define DISPC_CONNECTIONS_DPI_1_CONN_MASK GENMASK(7, 4)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

103

#define DISPC_CONNECTIONS_DPI_0_CONN_MASK GENMASK(3, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

119

#define DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK GENMASK(28, 28)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

120

#define DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK GENMASK(21, 21)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

121

#define DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK GENMASK(19, 19)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

122

#define DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK GENMASK(9, 9)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

123

#define DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK GENMASK(8, 8)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

124

#define DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK GENMASK(7, 7)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

125

#define DISPC_VID_ATTRIBUTES_FORMAT_MASK GENMASK(6, 1)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

126

#define DISPC_VID_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

134

#define DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK GENMASK(15, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

137

#define DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK GENMASK(31, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

138

#define DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK GENMASK(15, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

168

#define DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK GENMASK(7, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

173

#define DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK GENMASK(31, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

174

#define DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK GENMASK(15, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

177

#define DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK GENMASK(27, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

178

#define DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK GENMASK(11, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

185

#define DISPC_VID_SIZE_SIZEY_MASK GENMASK(27, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

186

#define DISPC_VID_SIZE_SIZEX_MASK GENMASK(11, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

215

#define DISPC_OVR_ATTRIBUTES_POSY_MASK GENMASK(30, 19)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

216

#define DISPC_OVR_ATTRIBUTES_POSX_MASK GENMASK(17, 6)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

217

#define DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK GENMASK(4, 1)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

218

#define DISPC_OVR_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

221

#define DISPC_OVR_ATTRIBUTES2_POSY_MASK GENMASK(29, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

222

#define DISPC_OVR_ATTRIBUTES2_POSX_MASK GENMASK(13, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

227

#define DISPC_VP_CONFIG_COLORCONVENABLE_MASK GENMASK(24, 24)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

228

#define DISPC_VP_CONFIG_CPR_MASK GENMASK(15, 15)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

229

#define DISPC_VP_CONFIG_GAMMAENABLE_MASK GENMASK(2, 2)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

232

#define DISPC_VP_CONTROL_DATALINES_MASK GENMASK(10, 8)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

233

#define DISPC_VP_CONTROL_GOBIT_MASK GENMASK(5, 5)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

234

#define DISPC_VP_CONTROL_ENABLE_MASK GENMASK(0, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

247

#define DISPC_VP_POL_FREQ_ALIGN_MASK GENMASK(18, 18)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

248

#define DISPC_VP_POL_FREQ_ONOFF_MASK GENMASK(17, 17)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

249

#define DISPC_VP_POL_FREQ_RF_MASK GENMASK(16, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

250

#define DISPC_VP_POL_FREQ_IEO_MASK GENMASK(15, 15)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

251

#define DISPC_VP_POL_FREQ_IPC_MASK GENMASK(14, 14)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

252

#define DISPC_VP_POL_FREQ_IHS_MASK GENMASK(13, 13)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

253

#define DISPC_VP_POL_FREQ_IVS_MASK GENMASK(12, 12)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

256

#define DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK GENMASK(11, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

257

#define DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK GENMASK(27, 16)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

260

#define DISPC_VP_TIMING_H_SYNC_PULSE_MASK GENMASK(7, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

261

#define DISPC_VP_TIMING_H_FRONT_PORCH_MASK GENMASK(19, 8)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

262

#define DISPC_VP_TIMING_H_BACK_PORCH_MASK GENMASK(31, 20)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

265

#define DISPC_VP_TIMING_V_SYNC_PULSE_MASK GENMASK(7, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

266

#define DISPC_VP_TIMING_V_FRONT_PORCH_MASK GENMASK(19, 8)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

267

#define DISPC_VP_TIMING_V_BACK_PORCH_MASK GENMASK(31, 20)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

297

#define DISPC_VP_DSS_OLDI_CFG_MAP_MASK GENMASK(3, 1)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

59

#define DSS_SYSCONFIG_SOFTRESET_MASK GENMASK(1, 1)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

62

#define DSS_SYSSTATUS_DISPC_IDLE_STATUS GENMASK(9, 9)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

63

#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE GENMASK(0, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

78

#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK GENMASK(6, 6)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

79

#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK GENMASK(1, 0)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

84

#define DSS_CBA_CFG_PRI_HI_MASK GENMASK(5, 3)

drivers/gpu/drm/tidss/tidss_dispc_regs.h

85

#define DSS_CBA_CFG_PRI_LO_MASK GENMASK(2, 0)

drivers/gpu/drm/tidss/tidss_irq.h

32

#define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1)

drivers/gpu/drm/tidss/tidss_irq.h

44

return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0));

drivers/gpu/drm/tidss/tidss_irq.h

49

return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0),

drivers/gpu/drm/tve200/tve200_drm.h

66

#define TVE200_CTRL_RETRYCNT_MASK GENMASK(23, 16)

drivers/gpu/drm/udl/udl_proto.h

59

#define UDL_BASE_ADDR0_MASK GENMASK(7, 0)

drivers/gpu/drm/udl/udl_proto.h

60

#define UDL_BASE_ADDR1_MASK GENMASK(15, 8)

drivers/gpu/drm/udl/udl_proto.h

61

#define UDL_BASE_ADDR2_MASK GENMASK(23, 16)

drivers/gpu/drm/v3d/v3d_perfmon.c

239

mask = GENMASK(ncounters - 1, 0);

drivers/gpu/drm/v3d/v3d_regs.h

9

#define V3D_MASK(high, low) ((u32)GENMASK(high, low))

drivers/gpu/drm/vc4/vc4_hdmi.c

2170

channel_mask = GENMASK(channels - 1, 0);

drivers/gpu/drm/vc4/vc4_kms.c

126

r |= GENMASK(8, 0);

drivers/gpu/drm/vc4/vc4_kms.c

129

r |= (in >> 23) & GENMASK(8, 0);

drivers/gpu/drm/vc4/vc4_perfmon.c

63

mask = GENMASK(perfmon->ncounters - 1, 0);

drivers/gpu/drm/vc4/vc4_plane.c

2592

GENMASK(drm->mode_config.num_crtc - 1, 0));

drivers/gpu/drm/vc4/vc4_regs.h

12

#define VC4_MASK(high, low) ((u32)GENMASK(high, low))

drivers/gpu/drm/vc4/vc4_txp.c

107

# define TXP_FORMAT_MASK GENMASK(11, 8)

drivers/gpu/drm/vc4/vc4_txp.c

279

if (fb->pitches[0] & GENMASK(3, 0))

drivers/gpu/drm/vc4/vc4_txp.c

62

# define TXP_HEIGHT_MASK GENMASK(31, 16)

drivers/gpu/drm/vc4/vc4_txp.c

64

# define TXP_WIDTH_MASK GENMASK(15, 0)

drivers/gpu/drm/vc4/vc4_txp.c

69

#define TXP_PILOT_MASK GENMASK(31, 24)

drivers/gpu/drm/vc4/vc4_txp.c

72

#define TXP_VERSION_MASK GENMASK(23, 22)

drivers/gpu/drm/vc4/vc4_txp.c

86

# define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)

drivers/gpu/drm/vc4/vc4_vec.c

110

#define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)

drivers/gpu/drm/vc4/vc4_vec.c

131

#define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)

drivers/gpu/drm/vc4/vc4_vec.c

136

#define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)

drivers/gpu/drm/vc4/vc4_vec.c

164

#define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)

drivers/gpu/drm/vc4/vc4_vec.c

180

#define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)

drivers/gpu/drm/vc4/vc4_vec.c

46

#define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)

drivers/gpu/drm/vc4/vc4_vec.c

48

#define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)

drivers/gpu/drm/vc4/vc4_vec.c

52

#define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)

drivers/gpu/drm/vc4/vc4_vec.c

57

#define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)

drivers/gpu/drm/vc4/vc4_vec.c

71

#define VEC_CONFIG0_STD_MASK GENMASK(1, 0)

drivers/gpu/drm/xe/abi/gsc_proxy_commands_abi.h

23

#define GSC_PROXY_TYPE GENMASK(7, 0)

drivers/gpu/drm/xe/abi/gsc_proxy_commands_abi.h

24

#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)

drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h

45

#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)

drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h

46

#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)

drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h

47

#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)

drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h

75

#define PXP43_INIT_SESSION_APPID GENMASK(17, 2)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

118

#define GUC_STATE_CAPTURE_HEADER_VFID GENMASK(7, 0)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

121

#define GUC_STATE_CAPTURE_HEADER_CAPTURE_TYPE GENMASK(3, 0) /* see guc_state_capture_type */

drivers/gpu/drm/xe/abi/guc_capture_abi.h

122

#define GUC_STATE_CAPTURE_HEADER_ENGINE_CLASS GENMASK(7, 4) /* see guc_capture_list_class_type */

drivers/gpu/drm/xe/abi/guc_capture_abi.h

123

#define GUC_STATE_CAPTURE_HEADER_ENGINE_INSTANCE GENMASK(11, 8)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

136

#define GUC_STATE_CAPTURE_HEADER_NUM_MMIO_ENTRIES GENMASK(9, 0)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

167

#define GUC_STATE_CAPTURE_GROUP_HEADER_VFID GENMASK(7, 0)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

170

#define GUC_STATE_CAPTURE_GROUP_HEADER_NUM_CAPTURES GENMASK(7, 0)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

171

#define GUC_STATE_CAPTURE_GROUP_HEADER_CAPTURE_GROUP_TYPE GENMASK(15, 8)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

57

#define GUC_REGSET_STEERING_GROUP GENMASK(16, 12)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

58

#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)

drivers/gpu/drm/xe/abi/guc_capture_abi.h

83

#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)

drivers/gpu/drm/xe/abi/guc_lfd_abi.h

109

#define GUC_LFD_DATA_HEADER_MASK_TYPE GENMASK(31, 16)

drivers/gpu/drm/xe/abi/guc_lfd_abi.h

110

#define GUC_LFD_DATA_HEADER_MASK_MAGIC GENMASK(15, 0)

drivers/gpu/drm/xe/abi/guc_lfd_abi.h

163

#define GUC_LFD_FILE_HEADER_VERSION_MASK_MAJOR GENMASK(31, 16)

drivers/gpu/drm/xe/abi/guc_lfd_abi.h

164

#define GUC_LFD_FILE_HEADER_VERSION_MASK_MINOR GENMASK(15, 0)

drivers/gpu/drm/xe/abi/guc_lic_abi.h

62

#define GUC_LIC_VERSION_MASK_MAJOR GENMASK(31, 16)

drivers/gpu/drm/xe/abi/guc_lic_abi.h

63

#define GUC_LIC_VERSION_MASK_MINOR GENMASK(15, 0)

drivers/gpu/drm/xe/abi/guc_log_abi.h

103

#define GUC_LOG_BUFFER_STATE_FLUSH_TO_FILE GENMASK(0, 0)

drivers/gpu/drm/xe/abi/guc_log_abi.h

104

#define GUC_LOG_BUFFER_STATE_BUFFER_FULL_CNT GENMASK(4, 1)

drivers/gpu/drm/xe/abi/guc_scheduler_abi.h

40

#define CONTEXT_REGISTRATION_FLAG_TYPE GENMASK(2, 1)

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

33

#define CS_ALU_OPERAND_REG(n) REG_FIELD_PREP(GENMASK(3, 0), (n))

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

58

#define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

59

REG_FIELD_PREP(GENMASK(19, 10), (op1)) | \

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

60

REG_FIELD_PREP(GENMASK(9, 0), (op2)))

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

14

#define CCS_SIZE_MASK GENMASK(17, 8)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

15

#define XE2_CCS_SIZE_MASK GENMASK(18, 9)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

16

#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

17

#define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

24

#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

25

#define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

32

#define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

37

#define MEM_COPY_SRC_MOCS_INDEX_MASK GENMASK(31, 28)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

38

#define MEM_COPY_DST_MOCS_INDEX_MASK GENMASK(6, 3)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

43

#define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

45

#define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1)

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

46

#define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3)

drivers/gpu/drm/xe/instructions/xe_instr_defs.h

16

#define XE_INSTR_CMD_TYPE GENMASK(31, 29)

drivers/gpu/drm/xe/instructions/xe_instr_defs.h

32

#define XE_INSTR_LEN_MASK GENMASK(7, 0)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

39

#define MI_SDI_LEN_DW GENMASK(9, 0)

drivers/gpu/drm/xe/regs/xe_irq_regs.h

56

#define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)

drivers/gpu/drm/xe/regs/xe_irq_regs.h

57

#define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)

drivers/gpu/drm/xe/regs/xe_irq_regs.h

58

#define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)

drivers/gpu/drm/xe/xe_guc_ct.c

878

#define CT_SEQNO_MASK GENMASK(14, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

192

#define ACCESS_COUNTER_SUBG_LO GENMASK(31, 1)

drivers/gpu/drm/xe/xe_guc_fwif.h

196

#define ACCESS_COUNTER_RSVD0 GENMASK(2, 1)

drivers/gpu/drm/xe/xe_guc_fwif.h

197

#define ACCESS_COUNTER_ENG_INSTANCE GENMASK(8, 3)

drivers/gpu/drm/xe/xe_guc_fwif.h

198

#define ACCESS_COUNTER_ENG_CLASS GENMASK(11, 9)

drivers/gpu/drm/xe/xe_guc_fwif.h

199

#define ACCESS_COUNTER_ASID GENMASK(31, 12)

drivers/gpu/drm/xe/xe_guc_fwif.h

202

#define ACCESS_COUNTER_VFID GENMASK(5, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

203

#define ACCESS_COUNTER_RSVD1 GENMASK(7, 6)

drivers/gpu/drm/xe/xe_guc_fwif.h

204

#define ACCESS_COUNTER_GRANULARITY GENMASK(10, 8)

drivers/gpu/drm/xe/xe_guc_fwif.h

205

#define ACCESS_COUNTER_RSVD2 GENMASK(16, 11)

drivers/gpu/drm/xe/xe_guc_fwif.h

206

#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)

drivers/gpu/drm/xe/xe_guc_fwif.h

209

#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

247

#define PFD_FAULT_LEVEL GENMASK(2, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

248

#define PFD_SRC_ID GENMASK(10, 3)

drivers/gpu/drm/xe/xe_guc_fwif.h

249

#define PFD_RSVD_0 GENMASK(17, 11)

drivers/gpu/drm/xe/xe_guc_fwif.h

251

#define PFD_ENG_INSTANCE GENMASK(24, 19)

drivers/gpu/drm/xe/xe_guc_fwif.h

252

#define PFD_ENG_CLASS GENMASK(27, 25)

drivers/gpu/drm/xe/xe_guc_fwif.h

253

#define PFD_PDATA_LO GENMASK(31, 28)

drivers/gpu/drm/xe/xe_guc_fwif.h

256

#define PFD_PDATA_HI GENMASK(11, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

258

#define PFD_ASID GENMASK(31, 12)

drivers/gpu/drm/xe/xe_guc_fwif.h

261

#define PFD_ACCESS_TYPE GENMASK(1, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

262

#define PFD_FAULT_TYPE GENMASK(3, 2)

drivers/gpu/drm/xe/xe_guc_fwif.h

263

#define PFD_VFID GENMASK(9, 4)

drivers/gpu/drm/xe/xe_guc_fwif.h

264

#define PFD_RSVD_1 GENMASK(11, 10)

drivers/gpu/drm/xe/xe_guc_fwif.h

265

#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)

drivers/gpu/drm/xe/xe_guc_fwif.h

269

#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

277

#define PFR_REPLY GENMASK(4, 2)

drivers/gpu/drm/xe/xe_guc_fwif.h

278

#define PFR_RSVD_0 GENMASK(9, 5)

drivers/gpu/drm/xe/xe_guc_fwif.h

279

#define PFR_DESC_TYPE GENMASK(11, 10)

drivers/gpu/drm/xe/xe_guc_fwif.h

280

#define PFR_ASID GENMASK(31, 12)

drivers/gpu/drm/xe/xe_guc_fwif.h

283

#define PFR_VFID GENMASK(5, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

285

#define PFR_ENG_INSTANCE GENMASK(12, 7)

drivers/gpu/drm/xe/xe_guc_fwif.h

286

#define PFR_ENG_CLASS GENMASK(15, 13)

drivers/gpu/drm/xe/xe_guc_fwif.h

287

#define PFR_PDATA GENMASK(31, 16)

drivers/gpu/drm/xe/xe_guc_fwif.h

290

#define PFR_RSVD_2 GENMASK(31, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

298

#define ACC_SUBG_LO GENMASK(31, 1)

drivers/gpu/drm/xe/xe_guc_fwif.h

302

#define ACC_RSVD0 GENMASK(2, 1)

drivers/gpu/drm/xe/xe_guc_fwif.h

303

#define ACC_ENG_INSTANCE GENMASK(8, 3)

drivers/gpu/drm/xe/xe_guc_fwif.h

304

#define ACC_ENG_CLASS GENMASK(11, 9)

drivers/gpu/drm/xe/xe_guc_fwif.h

305

#define ACC_ASID GENMASK(31, 12)

drivers/gpu/drm/xe/xe_guc_fwif.h

308

#define ACC_VFID GENMASK(5, 0)

drivers/gpu/drm/xe/xe_guc_fwif.h

309

#define ACC_RSVD1 GENMASK(7, 6)

drivers/gpu/drm/xe/xe_guc_fwif.h

310

#define ACC_GRANULARITY GENMASK(10, 8)

drivers/gpu/drm/xe/xe_guc_fwif.h

311

#define ACC_RSVD2 GENMASK(16, 11)

drivers/gpu/drm/xe/xe_guc_fwif.h

312

#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)

drivers/gpu/drm/xe/xe_guc_fwif.h

315

#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)

drivers/gpu/drm/xe/xe_guc_submit_types.h

19

#define WQ_TYPE_MASK GENMASK(7, 0)

drivers/gpu/drm/xe/xe_guc_submit_types.h

20

#define WQ_LEN_MASK GENMASK(26, 16)

drivers/gpu/drm/xe/xe_guc_submit_types.h

22

#define WQ_GUC_ID_MASK GENMASK(15, 0)

drivers/gpu/drm/xe/xe_guc_submit_types.h

23

#define WQ_RING_TAIL_MASK GENMASK(28, 18)

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

173

xe_gt_assert(gt, !(length & GENMASK(ilog2(SZ_16M) - 1,

drivers/gpu/drm/xe/xe_lmtt_2l.c

64

#define LMTT_2L_PDE_LMTT_PTR GENMASK(LMTT_2L_HAW - 13, 4)

drivers/gpu/drm/xe/xe_lmtt_2l.c

68

#define LMTT_2L_PTE_LMEM_PAGE GENMASK(LMTT_2L_HAW - 17, 5)

drivers/gpu/drm/xe/xe_lmtt_ml.c

68

#define LMTT_ML_PTE_LMEM_PAGE GENMASK(LMTT_ML_HAW - 17, 5)

drivers/gpu/drm/xe/xe_memirq.c

215

iosys_map_wr(&memirq->mask, 0, u32, enable ? GENMASK(15, 0) : 0);

drivers/gpu/drm/xe/xe_migrate.c

1463

return gt->info.engine_mask & GENMASK(XE_HW_ENGINE_BCS8,

drivers/gpu/drm/xe/xe_pci.c

103

GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)

drivers/gpu/drm/xe/xe_pci.c

113

GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |

drivers/gpu/drm/xe/xe_pci.c

114

GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),

drivers/gpu/drm/xe/xe_pci.c

119

GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |

drivers/gpu/drm/xe/xe_pci.c

120

GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),

drivers/gpu/drm/xe/xe_pci.c

125

GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |

drivers/gpu/drm/xe/xe_pci.c

126

GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |

drivers/gpu/drm/xe/xe_step.c

129

baseid = FIELD_GET(GENMASK(5, 3), xe->info.revid);

drivers/gpu/drm/xe/xe_step.c

130

revid = FIELD_GET(GENMASK(2, 0), xe->info.revid);

drivers/gpu/drm/xe/xe_uc_fw_abi.h

276

#define GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)

drivers/gpu/drm/xe/xe_uc_fw_abi.h

306

#define GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)

drivers/gpu/drm/xe/xe_vm_types.h

232

#define XE_VM_FLAG_TILE_ID(flags) FIELD_GET(GENMASK(7, 6), flags)

drivers/gpu/drm/xe/xe_vm_types.h

233

#define XE_VM_FLAG_SET_TILE_ID(tile) FIELD_PREP(GENMASK(7, 6), (tile)->id)

drivers/gpu/drm/xe/xe_vram.c

156

*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;

drivers/gpu/drm/xe/xe_vram.c

157

*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;

drivers/gpu/drm/xe/xe_vsec.c

73

#define GUID_TELEM_ITERATION GENMASK(3, 0)

drivers/gpu/drm/xe/xe_vsec.c

74

#define GUID_SEGMENT GENMASK(7, 4)

drivers/gpu/drm/xe/xe_vsec.c

75

#define GUID_SOC_SKU GENMASK(11, 8)

drivers/gpu/drm/xe/xe_vsec.c

76

#define GUID_DEVICE_ID GENMASK(27, 12)

drivers/gpu/drm/xe/xe_vsec.c

77

#define GUID_CAP_TYPE GENMASK(29, 28)

drivers/gpu/drm/xe/xe_vsec.c

78

#define GUID_RECORD_ID GENMASK(31, 30)

drivers/gpu/drm/xlnx/zynqmp_disp_regs.h

167

#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0)

drivers/gpu/drm/xlnx/zynqmp_disp_regs.h

172

#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4)

drivers/gpu/drm/xlnx/zynqmp_dp.c

79

#define ZYNQMP_DP_VERSION_MAJOR_MASK GENMASK(31, 24)

drivers/gpu/drm/xlnx/zynqmp_dp.c

81

#define ZYNQMP_DP_VERSION_MINOR_MASK GENMASK(23, 16)

drivers/gpu/drm/xlnx/zynqmp_dp.c

83

#define ZYNQMP_DP_VERSION_REVISION_MASK GENMASK(15, 12)

drivers/gpu/drm/xlnx/zynqmp_dp.c

85

#define ZYNQMP_DP_VERSION_PATCH_MASK GENMASK(11, 8)

drivers/gpu/drm/xlnx/zynqmp_dp.c

87

#define ZYNQMP_DP_VERSION_INTERNAL_MASK GENMASK(7, 0)

drivers/gpu/drm/xlnx/zynqmp_dp.c

92

#define ZYNQMP_DP_CORE_ID_MAJOR_MASK GENMASK(31, 24)

drivers/gpu/drm/xlnx/zynqmp_dp.c

94

#define ZYNQMP_DP_CORE_ID_MINOR_MASK GENMASK(23, 16)

drivers/gpu/drm/xlnx/zynqmp_dp.c

96

#define ZYNQMP_DP_CORE_ID_REVISION_MASK GENMASK(15, 8)

drivers/gpu/drm/xlnx/zynqmp_dp.c

98

#define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1)

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c

283

acs = privdata->mp2_acs & GENMASK(3, 0);

drivers/hid/amd-sfh-hid/amd_sfh_pcie.h

28

#define SENSOR_DISCOVERY_STATUS_MASK GENMASK(5, 3)

drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c

212

u8 supported_input = privdata->mp2_acs & GENMASK(3, 0);

drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c

30

#define ILLUMINANCE_MASK GENMASK(14, 0)

drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c

139

mantissa = flt32_val & GENMASK(22, 0);

drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c

171

fraction = (shift == 0) ? 0 : mantissa & GENMASK(shift - 1, 0);

drivers/hid/hid-corsair-void.c

100

#define CORSAIR_VOID_MIC_MASK GENMASK(7, 7)

drivers/hid/hid-corsair-void.c

101

#define CORSAIR_VOID_CAPACITY_MASK GENMASK(6, 0)

drivers/hid/hid-cp2112.c

37

#define CP2112_GPIO_ALL_GPIO_MASK GENMASK(7, 0)

drivers/hid/hid-logitech-dj.c

100

#define HIDPP_DEVICE_TYPE_MASK GENMASK(3, 0)

drivers/hid/hid-mcp2221.c

1003

tmp = FIELD_GET(GENMASK(7, 6), data[6]);

drivers/hid/hid-mcp2221.c

1010

tmp = FIELD_GET(GENMASK(4, 3), data[7]);

drivers/hid/hid-mcp2221.c

978

mcp->dac_value = data[6] & GENMASK(4, 0);

drivers/hid/hid-multitouch.c

100

#define MT_IO_SLOTS_MASK GENMASK(7, 0) /* reserve first 8 bits for slot tracking */

drivers/hid/hid-playstation.c

116

#define DS_STATUS0_BATTERY_CAPACITY GENMASK(3, 0)

drivers/hid/hid-playstation.c

117

#define DS_STATUS0_CHARGING GENMASK(7, 4)

drivers/hid/hid-playstation.c

124

#define DS_FEATURE_VERSION_MINOR GENMASK(7, 0)

drivers/hid/hid-playstation.c

125

#define DS_FEATURE_VERSION_MAJOR GENMASK(15, 8)

drivers/hid/hid-playstation.c

134

#define DS_TOUCH_POINT_X_LO GENMASK(7, 0)

drivers/hid/hid-playstation.c

135

#define DS_TOUCH_POINT_X_HI GENMASK(11, 8)

drivers/hid/hid-playstation.c

138

#define DS_TOUCH_POINT_Y_LO GENMASK(3, 0)

drivers/hid/hid-playstation.c

139

#define DS_TOUCH_POINT_Y_HI GENMASK(11, 4)

drivers/hid/hid-playstation.c

145

#define DS_OUTPUT_SEQ_TAG GENMASK(3, 0)

drivers/hid/hid-playstation.c

146

#define DS_OUTPUT_SEQ_NO GENMASK(7, 4)

drivers/hid/hid-playstation.c

161

#define DS_OUTPUT_AUDIO_FLAGS_OUTPUT_PATH_SEL GENMASK(5, 4)

drivers/hid/hid-playstation.c

162

#define DS_OUTPUT_AUDIO_FLAGS2_SP_PREAMP_GAIN GENMASK(2, 0)

drivers/hid/hid-playstation.c

356

#define DS4_STATUS0_BATTERY_CAPACITY GENMASK(3, 0)

drivers/hid/hid-playstation.c

98

#define DS_BUTTONS0_HAT_SWITCH GENMASK(3, 0)

drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

109

#define IPC_ISH_FWSTS_MASK GENMASK(15, 12)

drivers/hid/intel-ish-hid/ishtp-fw-loader.c

49

#define CMD_MASK GENMASK(6, 0)

drivers/hid/intel-thc-hid/intel-quickspi/quickspi-dev.h

48

#define SPI_IO_MODE_OPCODE GENMASK(15, 14)

drivers/hid/intel-thc-hid/intel-quickspi/quickspi-dev.h

49

#define PERFORMANCE_LIMITATION GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-quickspi/quickspi-protocol.c

21

#define HIDSPI_IN_REP_BDY_HDR_REP_TYPE GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.h

13

#define THC_POINTER_MASK GENMASK(6, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

246

#define THC_CFG_DID_VID_VID GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

247

#define THC_CFG_DID_VID_DID GENMASK(31, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

264

#define THC_CFG_STS_CMD_DEVT GENMASK(26, 25)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

271

#define THC_CFG_CC_RID_RID GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

272

#define THC_CFG_CC_RID_PI GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

273

#define THC_CFG_CC_RID_SCC GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

274

#define THC_CFG_CC_RID_BCC GENMASK(31, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

276

#define THC_CFG_BIST_HTYPE_LT_CLS_CLSZ GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

277

#define THC_CFG_BIST_HTYPE_LT_CLS_LT GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

278

#define THC_CFG_BIST_HTYPE_LT_CLS_HTYPE GENMASK(22, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

282

#define THC_CFG_BAR0_LOW_TYP GENMASK(2, 1)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

284

#define THC_CFG_BAR0_LOW_MEMSIZE GENMASK(14, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

285

#define THC_CFG_BAR0_LOW_MEMBAR GENMASK(31, 15)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

286

#define THC_CFG_BAR0_HI_MEMBAR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

288

#define THC_CFG_SID_SVID_SSVID GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

289

#define THC_CFG_SID_SVID_SSID GENMASK(31, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

291

#define THC_CFG_CAPP_CP GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

293

#define THC_CFG_INT_ILINE GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

294

#define THC_CFG_INT_IPIN GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

300

#define THC_CFG_MSIMC_MSINP_MSICID_CAPID GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

301

#define THC_CFG_MSIMC_MSINP_MSICID_NXTP GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

303

#define THC_CFG_MSIMC_MSINP_MSICID_MMC GENMASK(19, 17)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

304

#define THC_CFG_MSIMC_MSINP_MSICID_MMEN GENMASK(22, 20)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

307

#define THC_CFG_MSIMA_MADDR GENMASK(31, 2)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

308

#define THC_CFG_MSIMUA_MAUDDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

309

#define THC_CFG_MSIMD_MDAT GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

311

#define THC_CFG_PMCAP_PMNP_PMCID_CAPP GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

312

#define THC_CFG_PMCAP_PMNP_PMCID_NXTP GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

313

#define THC_CFG_PMCAP_PMNP_PMCID_VER GENMASK(18, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

316

#define THC_CFG_PMCAP_PMNP_PMCID_AUXC GENMASK(24, 22)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

319

#define THC_CFG_PMCAP_PMNP_PMCID_PMES GENMASK(31, 27)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

321

#define THC_CFG_PMD_PMCSRBSE_PMCSR_PWRST GENMASK(1, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

324

#define THC_CFG_PMD_PMCSRBSE_PMCSR_DSEL GENMASK(12, 9)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

325

#define THC_CFG_PMD_PMCSRBSE_PMCSR_DS GENMASK(14, 13)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

328

#define THC_CFG_DEVIDLE_CAPPID GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

329

#define THC_CFG_DEVIDLE_NCAPPP GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

330

#define THC_CFG_DEVIDLE_LENGTH GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

331

#define THC_CFG_DEVIDLE_REV GENMASK(27, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

332

#define THC_CFG_DEVIDLE_VID GENMASK(31, 28)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

334

#define THC_CFG_VSHDR_VSECID GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

335

#define THC_CFG_VSHDR_VSECR GENMASK(19, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

336

#define THC_CFG_VSHDR_VSECL GENMASK(31, 20)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

339

#define THC_CFG_SWLTRPTR_BARNUM GENMASK(3, 1)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

340

#define THC_CFG_SWLTRPTR_SWLTRLOC GENMASK(31, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

343

#define THC_CFG_DEVIDLEPTR_BARNUM GENMASK(3, 1)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

344

#define THC_CFG_DEVIDLEPTR_DEVIDLELOC GENMASK(31, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

345

#define THC_CFG_DEVIDLEPOL_POLV GENMASK(9, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

346

#define THC_CFG_DEVIDLEPOL_POLS GENMASK(12, 10)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

354

#define THC_CFG_MANID_PROC GENMASK(7, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

355

#define THC_CFG_MANID_MID GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

356

#define THC_CFG_MANID_MSID GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

357

#define THC_CFG_MANID_DOT GENMASK(27, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

370

#define THC_M_CMN_LTR_CTRL_LP_LTR_SCALE GENMASK(6, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

371

#define THC_M_CMN_LTR_CTRL_LP_LTR_VAL GENMASK(16, 7)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

372

#define THC_M_CMN_LTR_CTRL_ACT_LTR_SCALE GENMASK(19, 17)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

373

#define THC_M_CMN_LTR_CTRL_ACT_LTR_VAL GENMASK(29, 20)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

374

#define THC_M_CMN_LTR_CTRL_LAST_LTR_SENT GENMASK(31, 30)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

381

#define THC_M_PRT_CONTROL_THC_INSTANCE_INDEX GENMASK(18, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

382

#define THC_M_PRT_CONTROL_PORT_INDEX GENMASK(22, 20)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

383

#define THC_M_PRT_CONTROL_THC_ARB_POLICY GENMASK(25, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

387

#define THC_M_PRT_CONTROL_PORT_TYPE GENMASK(31, 30)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

389

#define THC_M_PRT_SPI_CFG_SPI_TRDC GENMASK(1, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

390

#define THC_M_PRT_SPI_CFG_SPI_TRMODE GENMASK(3, 2)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

391

#define THC_M_PRT_SPI_CFG_SPI_TCRF GENMASK(6, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

392

#define THC_M_PRT_SPI_CFG_SPI_RD_MPS GENMASK(15, 7)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

393

#define THC_M_PRT_SPI_CFG_SPI_TWMODE GENMASK(19, 18)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

394

#define THC_M_PRT_SPI_CFG_SPI_TCWF GENMASK(22, 20)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

396

#define THC_M_PRT_SPI_CFG_SPI_WR_MPS GENMASK(31, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

398

#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_SIO GENMASK(31, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

399

#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_DIO GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

400

#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_QIO GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

402

#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE GENMASK(15, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

403

#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

451

#define THC_M_PRT_ERR_CAUSE_FATAL_ERR_CAUSE GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

455

#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CMD GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

456

#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_BC GENMASK(31, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

460

#define THC_M_PRT_SW_SEQ_DATA0_ADDR_THC_SW_SEQ_DATA0_ADDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

461

#define THC_M_PRT_SW_SEQ_DATA1_THC_SW_SEQ_DATA1 GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

463

#define THC_M_PRT_WPRD_BA_LOW_THC_M_PRT_WPRD_BA_LOW GENMASK(31, 12)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

464

#define THC_M_PRT_WPRD_BA_HI_THC_M_PRT_WPRD_BA_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

471

#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_PTEC GENMASK(31, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

478

#define THC_M_PRT_WR_BULK_ADDR_THC_M_PRT_WR_BULK_ADDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

480

#define THC_M_PRT_DEV_INT_CAUSE_ADDR_THC_M_PRT_DEV_INT_CAUSE_ADDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

481

#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_INTERRUPT_TYPE GENMASK(3, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

482

#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_MICRO_FRAME_SIZE GENMASK(23, 4)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

487

#define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

490

#define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

493

#define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

496

#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_OFFSET GENMASK(4, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

497

#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_LEN GENMASK(9, 5)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

498

#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_EOF_OFFSET GENMASK(14, 10)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

500

#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_DATA_VAL GENMASK(31, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

502

#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_OFFSET GENMASK(4, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

503

#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_LEN GENMASK(9, 5)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

504

#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_UNIT GENMASK(15, 12)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

513

#define THC_M_PRT_RPRD_BA_LOW_1_THC_M_PRT_RPRD_BA_LOW GENMASK(31, 12)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

514

#define THC_M_PRT_RPRD_BA_HI_1_THC_M_PRT_RPRD_BA_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

516

#define THC_M_PRT_RPRD_CNTRL_PCD GENMASK(6, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

517

#define THC_M_PRT_RPRD_CNTRL_PTEC GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

518

#define THC_M_PRT_RPRD_CNTRL_PREFETCH_WM GENMASK(19, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

527

#define THC_M_PRT_READ_DMA_CNTRL_TPCRP GENMASK(15, 8)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

528

#define THC_M_PRT_READ_DMA_CNTRL_TPCWP GENMASK(23, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

544

#define THC_M_PRT_GUC_OFFSET_LOW_1_THC_M_PRT_GUC_OFFSET_LOW GENMASK(31, 3)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

545

#define THC_M_PRT_GUC_OFFSET_HI_1_THC_M_PRT_GUC_OFFSET_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

546

#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_1_WORKQ_ITEM_SZ GENMASK(23, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

547

#define THC_M_PRT_GUC_WORKQ_SZ_1_WORKQ_SZ GENMASK(23, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

548

#define THC_M_PRT_GUC_WORKQ_SZ_1_FCD GENMASK(27, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

549

#define THC_M_PRT_GUC_WORKQ_SZ_1_GIC GENMASK(31, 28)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

556

#define THC_M_PRT_TSEQ_CNTRL_1_RX_DATA_FIFO_WR_WM GENMASK(25, 16)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

560

#define THC_M_PRT_GUC_DB_ADDR_LOW_1_GUC_DB_ADDR_LOW GENMASK(31, 2)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

561

#define THC_M_PRT_GUC_DB_ADDR_HI_1_GUC_DB_ADDR_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

562

#define THC_M_PRT_GUC_DB_DATA_1_GUC_DB_DATA GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

563

#define THC_M_PRT_GUC_OFFSET_INITVAL_1_THC_M_PRT_GUC_OFFSET_INITVAL GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

565

#define THC_M_PRT_RD_BULK_ADDR_1_THC_M_PRT_RD_BULK_ADDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

567

#define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

570

#define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

573

#define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

576

#define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

579

#define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

582

#define THC_M_PRT_FRAME_DROP_CNT_1_NOFD GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

585

#define THC_M_PRT_COALESCE_1_COALESCE_TIMEOUT GENMASK(6, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

587

#define THC_M_PRT_RPRD_BA_LOW_2_THC_M_PRT_RPRD_BA_LOW GENMASK(31, 12)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

588

#define THC_M_PRT_RPRD_BA_HI_2_THC_M_PRT_RPRD_BA_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

592

#define THC_M_PRT_GUC_OFFSET_LOW_2_THC_M_PRT_GUC_OFFSET_LOW GENMASK(31, 3)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

593

#define THC_M_PRT_GUC_OFFSET_HI_2_THC_M_PRT_GUC_OFFSET_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

595

#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_2_WORKQ_ITEM_SZ GENMASK(23, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

596

#define THC_M_PRT_GUC_WORKQ_SZ_2_WORKQ_SZ GENMASK(23, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

597

#define THC_M_PRT_GUC_WORKQ_SZ_2_FCD GENMASK(27, 24)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

598

#define THC_M_PRT_GUC_WORKQ_SZ_2_GIC GENMASK(31, 28)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

604

#define THC_M_PRT_GUC_DB_ADDR_LOW_2_GUC_DB_ADDR_LOW GENMASK(31, 2)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

605

#define THC_M_PRT_GUC_DB_ADDR_HI_2_GUC_DB_ADDR_HI GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

607

#define THC_M_PRT_GUC_DB_DATA_2_GUC_DB_DATA GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

609

#define THC_M_PRT_GUC_OFFSET_INITVAL_2_THC_M_PRT_GUC_OFFSET_INITVAL GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

611

#define THC_M_PRT_RD_BULK_ADDR_2_THC_M_PRT_RD_BULK_ADDR GENMASK(31, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

613

#define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

616

#define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

619

#define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

622

#define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

625

#define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

628

#define THC_M_PRT_FRAME_DROP_CNT_2_NOFD GENMASK(30, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

631

#define THC_M_PRT_COALESCE_2_COALESCE_TIMEOUT GENMASK(6, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

634

#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_PIO_I2C_WBC GENMASK(31, 26)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

637

#define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_WBC GENMASK(31, 26)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

642

#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_THC_M_PRT_SW_DMA_PRD_TABLE_LEN GENMASK(23, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

644

#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL GENMASK(3, 0)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

845

#define THC_I2C_IC_CON_SPEED GENMASK(2, 1)

drivers/hid/intel-thc-hid/intel-thc/intel-thc-hw.h

860

#define THC_I2C_IC_TAR_IC_TAR GENMASK(9, 0)

drivers/hwmon/amc6821.c

120

#define AMC6821_TEMP_SLOPE_MASK GENMASK(2, 0)

drivers/hwmon/amc6821.c

121

#define AMC6821_TEMP_LIMIT_MASK GENMASK(7, 3)

drivers/hwmon/amc6821.c

98

#define AMC6821_CONF3_REV_MASK GENMASK(3, 0)

drivers/hwmon/as370-hwmon.c

25

#define BN_MASK GENMASK(11, 0)

drivers/hwmon/aspeed-g6-pwm-tach.c

101

#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0)

drivers/hwmon/aspeed-g6-pwm-tach.c

127

#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0)

drivers/hwmon/aspeed-g6-pwm-tach.c

74

#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)

drivers/hwmon/aspeed-g6-pwm-tach.c

75

#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)

drivers/hwmon/aspeed-g6-pwm-tach.c

79

#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)

drivers/hwmon/aspeed-g6-pwm-tach.c

80

#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)

drivers/hwmon/aspeed-g6-pwm-tach.c

81

#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)

drivers/hwmon/aspeed-g6-pwm-tach.c

82

#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)

drivers/hwmon/aspeed-g6-pwm-tach.c

95

#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26)

drivers/hwmon/aspeed-g6-pwm-tach.c

97

#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24)

drivers/hwmon/aspeed-g6-pwm-tach.c

99

#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20)

drivers/hwmon/aspeed-pwm-tacho.c

140

#define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0)

drivers/hwmon/aspeed-pwm-tacho.c

76

#define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16)

drivers/hwmon/aspeed-pwm-tacho.c

81

#define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0)

drivers/hwmon/aspeed-pwm-tacho.c

92

#define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16)

drivers/hwmon/aspeed-pwm-tacho.c

95

#define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0)

drivers/hwmon/aspeed-pwm-tacho.c

98

#define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16))

drivers/hwmon/aspeed-pwm-tacho.c

99

#define TYPE_CTRL_FAN1_MASK GENMASK(31, 0)

drivers/hwmon/axi-fan-control.c

46

#define ADI_IRQ_SRC_MASK GENMASK(3, 0)

drivers/hwmon/bt1-pvt.h

21

#define PVT_CTRL_MODE_MASK GENMASK(3, PVT_CTRL_MODE_FLD)

drivers/hwmon/bt1-pvt.h

28

#define PVT_CTRL_TRIM_MASK GENMASK(8, PVT_CTRL_TRIM_FLD)

drivers/hwmon/bt1-pvt.h

32

#define PVT_DATA_DATA_MASK GENMASK(9, PVT_DATA_DATA_FLD)

drivers/hwmon/bt1-pvt.h

39

#define PVT_THRES_LO_MASK GENMASK(9, PVT_THRES_LO_FLD)

drivers/hwmon/bt1-pvt.h

41

#define PVT_THRES_HI_MASK GENMASK(19, PVT_THRES_HI_FLD)

drivers/hwmon/bt1-pvt.h

57

#define PVT_INTR_ALL GENMASK(10, 0)

drivers/hwmon/cgbc-hwmon.c

18

#define CGBC_HWMON_TYPE_MASK GENMASK(6, 5)

drivers/hwmon/cgbc-hwmon.c

19

#define CGBC_HWMON_ID_MASK GENMASK(4, 0)

drivers/hwmon/chipcap2.c

38

#define CC2_STATUS_FIELD GENMASK(7, 6)

drivers/hwmon/chipcap2.c

43

#define CC2_RESPONSE_FIELD GENMASK(1, 0)

drivers/hwmon/chipcap2.c

57

#define CC2_RH_DATA_FIELD GENMASK(13, 0)

drivers/hwmon/hs3001.c

36

#define HS3001_MASK_HUMIDITY_0X3FFF GENMASK(13, 0)

drivers/hwmon/hs3001.c

37

#define HS3001_MASK_STATUS_0XC0 GENMASK(7, 6)

drivers/hwmon/ina2xx.c

76

#define INA226_AVG_RD_MASK GENMASK(11, 9)

drivers/hwmon/ina2xx.c

91

#define INA226_ALERT_CONFIG_MASK GENMASK(15, 10)

drivers/hwmon/ina3221.c

38

#define INA3221_CONFIG_MODE_MASK GENMASK(2, 0)

drivers/hwmon/ina3221.c

44

#define INA3221_CONFIG_VSH_CT_MASK GENMASK(5, 3)

drivers/hwmon/ina3221.c

45

#define INA3221_CONFIG_VSH_CT(x) (((x) & GENMASK(5, 3)) >> 3)

drivers/hwmon/ina3221.c

47

#define INA3221_CONFIG_VBUS_CT_MASK GENMASK(8, 6)

drivers/hwmon/ina3221.c

48

#define INA3221_CONFIG_VBUS_CT(x) (((x) & GENMASK(8, 6)) >> 6)

drivers/hwmon/ina3221.c

50

#define INA3221_CONFIG_AVG_MASK GENMASK(11, 9)

drivers/hwmon/ina3221.c

51

#define INA3221_CONFIG_AVG(x) (((x) & GENMASK(11, 9)) >> 9)

drivers/hwmon/ina3221.c

52

#define INA3221_CONFIG_CHs_EN_MASK GENMASK(14, 12)

drivers/hwmon/ina3221.c

55

#define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12)

drivers/hwmon/jc42.c

49

#define JC42_CFG_HYST_MASK GENMASK(10, 9)

drivers/hwmon/k10temp.c

39

#define CPUID_PKGTYPE_MASK GENMASK(31, 28)

drivers/hwmon/k10temp.c

71

#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)

drivers/hwmon/k10temp.c

75

#define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)

drivers/hwmon/lan966x-hwmon.c

47

#define SENSOR_CFG_CLK_CFG GENMASK(27, 20)

drivers/hwmon/lan966x-hwmon.c

48

#define SENSOR_CFG_TRIM_VAL GENMASK(13, 9)

drivers/hwmon/lan966x-hwmon.c

52

#define SENSOR_CFG_PSAMPLE_ENA GENMASK(1, 0)

drivers/hwmon/lan966x-hwmon.c

55

#define SENSOR_STAT_DATA GENMASK(9, 0)

drivers/hwmon/lan966x-hwmon.c

58

#define FAN_CFG_DUTY_CYCLE GENMASK(23, 16)

drivers/hwmon/lan966x-hwmon.c

64

#define FAN_PWM_CYC_10US GENMASK(25, 15)

drivers/hwmon/lan966x-hwmon.c

65

#define FAN_PWM_FREQ_FREQ GENMASK(14, 0)

drivers/hwmon/lan966x-hwmon.c

67

#define FAN_CNT_DATA GENMASK(15, 0)

drivers/hwmon/lenovo-ec-sensors.c

53

m_index = phy_index & GENMASK(14, 2);

drivers/hwmon/lenovo-ec-sensors.c

56

onebyte = inb_p(MCHP_EMI0_EC_DATA_BYTE0 + (phy_index & GENMASK(1, 0)));

drivers/hwmon/ltc2947-core.c

26

#define LTC2947_PRE_MASK GENMASK(2, 0)

drivers/hwmon/ltc2947-core.c

28

#define LTC2947_DIV_MASK GENMASK(7, 3)

drivers/hwmon/ltc2947-core.c

32

#define LTC2947_ACCUM_POL_1_MASK GENMASK(1, 0)

drivers/hwmon/ltc2947-core.c

34

#define LTC2947_ACCUM_POL_2_MASK GENMASK(3, 2)

drivers/hwmon/ltc2990.c

39

#define LTC2990_ALL GENMASK(9, 0)

drivers/hwmon/ltc2990.c

42

#define LTC2990_MODE0_MASK GENMASK(2, 0)

drivers/hwmon/ltc2990.c

44

#define LTC2990_MODE1_MASK GENMASK(1, 0)

drivers/hwmon/ltc4282.c

33

#define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0)

drivers/hwmon/ltc4282.c

34

#define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2)

drivers/hwmon/ltc4282.c

35

#define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4)

drivers/hwmon/ltc4282.c

60

#define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4)

drivers/hwmon/ltc4282.c

70

#define LTC4282_CLK_DIV_MASK GENMASK(4, 0)

drivers/hwmon/ltc4282.c

71

#define LTC4282_CLKOUT_MASK GENMASK(6, 5)

drivers/hwmon/ltc4282.c

75

#define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3)

drivers/hwmon/ltc4282.c

76

#define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5)

drivers/hwmon/ltc4282.c

93

#define LTC4282_FET_FAILURE_MASK GENMASK(6, 5)

drivers/hwmon/macsmc-hwmon.c

37

#define FLT_EXP_MASK GENMASK(30, 23)

drivers/hwmon/macsmc-hwmon.c

39

#define FLT_MANT_MASK GENMASK(22, 0)

drivers/hwmon/max31760.c

14

#define CR1_DRV GENMASK(4, 3)

drivers/hwmon/max31760.c

15

#define CR1_TEMP_SRC GENMASK(1, 0)

drivers/hwmon/max31827.c

25

#define MAX31827_CONFIGURATION_CNV_RATE_MASK GENMASK(3, 1)

drivers/hwmon/max31827.c

28

#define MAX31827_CONFIGURATION_RESOLUTION_MASK GENMASK(7, 6)

drivers/hwmon/max31827.c

31

#define MAX31827_CONFIGURATION_FLT_Q_MASK GENMASK(11, 10)

drivers/hwmon/max6621.c

53

#define MAX6621_ENABLE_TEMP_ALL GENMASK(MAX6621_ENABLE_S3D1_BIT, \

drivers/hwmon/max6697.c

40

#define MAX6697_EXTERNAL_MASK_DT GENMASK(7, 1)

drivers/hwmon/max6697.c

42

#define MAX6697_EXTERNAL_MASK_CHIP GENMASK(6, 0)

drivers/hwmon/mc33xs2410_hwmon.c

16

#define MC33XS2410_TEMP_WT_MASK GENMASK(7, 0)

drivers/hwmon/mc33xs2410_hwmon.c

25

#define MC33XS2410_TS_TEMP_MASK GENMASK(9, 0)

drivers/hwmon/mr75203.c

26

#define TS_NUM_MSK GENMASK(4, 0)

drivers/hwmon/mr75203.c

28

#define PD_NUM_MSK GENMASK(12, 8)

drivers/hwmon/mr75203.c

30

#define VM_NUM_MSK GENMASK(20, 16)

drivers/hwmon/mr75203.c

32

#define CH_NUM_MSK GENMASK(31, 24)

drivers/hwmon/mr75203.c

69

#define SAMPLE_DATA_MSK GENMASK(15, 0)

drivers/hwmon/nct6694-hwmon.c

71

#define NCT6694_LSB_REG_MASK GENMASK(7, 5)

drivers/hwmon/nct6694-hwmon.c

72

#define NCT6694_TIN_HYST_MASK GENMASK(7, 5)

drivers/hwmon/nct6775-i2c.c

143

data->have_tsi_temp |= tsi_channel_mask & GENMASK(NUM_TSI_TEMP - 1, 0);

drivers/hwmon/nct7363.c

34

#define NCT7363_FANINX_LVAL_MASK GENMASK(4, 0)

drivers/hwmon/nct7363.c

35

#define NCT7363_FANIN_MASK GENMASK(12, 0)

drivers/hwmon/npcm750-pwm-fan.c

107

#define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)

drivers/hwmon/npcm750-pwm-fan.c

115

#define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)

drivers/hwmon/occ/sysfs.c

23

#define OCC_EXT_STAT_GPU_THROTTLE GENMASK(2, 0)

drivers/hwmon/peci/cputemp.c

21

#define TEMP_TARGET_FAN_TEMP_MASK GENMASK(15, 8)

drivers/hwmon/peci/cputemp.c

22

#define TEMP_TARGET_REF_TEMP_MASK GENMASK(23, 16)

drivers/hwmon/peci/cputemp.c

23

#define TEMP_TARGET_TJ_OFFSET_MASK GENMASK(29, 24)

drivers/hwmon/peci/cputemp.c

25

#define DTS_MARGIN_MASK GENMASK(15, 0)

drivers/hwmon/peci/cputemp.c

26

#define PCS_MODULE_TEMP_MASK GENMASK(15, 0)

drivers/hwmon/peci/dimmtemp.c

42

#define CPU_SEG_MASK GENMASK(23, 16)

drivers/hwmon/peci/dimmtemp.c

44

#define CPU_BUS_MASK GENMASK(7, 0)

drivers/hwmon/peci/dimmtemp.c

47

#define DIMM_TEMP_MAX GENMASK(15, 8)

drivers/hwmon/peci/dimmtemp.c

48

#define DIMM_TEMP_CRIT GENMASK(23, 16)

drivers/hwmon/pmbus/adm1266.c

43

#define ADM1266_PDIO_PIN_CFG(x) FIELD_GET(GENMASK(15, 13), x)

drivers/hwmon/pmbus/adm1266.c

44

#define ADM1266_PDIO_GLITCH_FILT(x) FIELD_GET(GENMASK(12, 9), x)

drivers/hwmon/pmbus/adm1266.c

45

#define ADM1266_PDIO_OUT_CFG(x) FIELD_GET(GENMASK(2, 0), x)

drivers/hwmon/pmbus/adm1275.c

82

#define ADM1275_VI_AVG_MASK GENMASK(ADM1275_VI_AVG_SHIFT + 2, \

drivers/hwmon/pmbus/adm1275.c

87

#define ADM1278_PWR_AVG_MASK GENMASK(ADM1278_PWR_AVG_SHIFT + 2, \

drivers/hwmon/pmbus/adm1275.c

90

#define ADM1278_VI_AVG_MASK GENMASK(ADM1278_VI_AVG_SHIFT + 2, \

drivers/hwmon/pmbus/hac300s.c

26

#define LINEAR11_EXPONENT_MASK GENMASK(15, 11)

drivers/hwmon/pmbus/hac300s.c

27

#define LINEAR11_MANTISSA_MASK GENMASK(10, 0)

drivers/hwmon/pmbus/ibm-cffps.c

31

#define CFFPS_CCIN_REVISION GENMASK(7, 0)

drivers/hwmon/pmbus/ibm-cffps.c

33

#define CFFPS_CCIN_VERSION GENMASK(15, 8)

drivers/hwmon/pmbus/max20730.c

69

#define MAX20730_MFR_VOUT_MIN_MASK GENMASK(9, 0)

drivers/hwmon/pmbus/max20730.c

76

#define MAX20730_MFR_DEVSET1_FSW_MASK GENMASK(4, 2)

drivers/hwmon/pmbus/max20730.c

86

#define MAX20730_MFR_DEVSET2_IMAX_MASK GENMASK(10, 8)

drivers/hwmon/pmbus/mp2856.c

127

GENMASK(9, 0));

drivers/hwmon/pmbus/mp2856.c

267

MP2856_MAX_PHASE_RAIL1, GENMASK(3, 0));

drivers/hwmon/pmbus/mp2856.c

28

#define MP2856_DRMOS_KCS GENMASK(13, 12)

drivers/hwmon/pmbus/mp2856.c

287

MP2856_MAX_PHASE_RAIL2, GENMASK(2, 0));

drivers/hwmon/pmbus/mp2869.c

101

data->mfr_thwn_flt_en = FIELD_GET(GENMASK(13, 13), ret);

drivers/hwmon/pmbus/mp2869.c

130

data->vout_scale[page] = mp2869_vout_sacle[FIELD_GET(GENMASK(12, 10), ret)];

drivers/hwmon/pmbus/mp2869.c

159

data->iout_scale[page] = mp2869_iout_sacle[FIELD_GET(GENMASK(2, 0), ret)];

drivers/hwmon/pmbus/mp2869.c

196

ret = (ret & ~GENMASK(2, 2)) |

drivers/hwmon/pmbus/mp2869.c

197

FIELD_PREP(GENMASK(2, 2),

drivers/hwmon/pmbus/mp2869.c

198

FIELD_GET(GENMASK(1, 1), mfr));

drivers/hwmon/pmbus/mp2869.c

218

ret = (ret & ~GENMASK(7, 6)) |

drivers/hwmon/pmbus/mp2869.c

219

FIELD_PREP(GENMASK(6, 6),

drivers/hwmon/pmbus/mp2869.c

220

FIELD_GET(GENMASK(1, 1), mfr)) |

drivers/hwmon/pmbus/mp2869.c

221

FIELD_PREP(GENMASK(7, 7),

drivers/hwmon/pmbus/mp2869.c

222

FIELD_GET(GENMASK(1, 1), mfr));

drivers/hwmon/pmbus/mp2869.c

258

ret = (ret & ~GENMASK(2, 2)) |

drivers/hwmon/pmbus/mp2869.c

259

FIELD_PREP(GENMASK(2, 2),

drivers/hwmon/pmbus/mp2869.c

260

FIELD_GET(GENMASK(1, 1), mfr));

drivers/hwmon/pmbus/mp2869.c

273

ret = FIELD_GET(GENMASK(10, 0), ret);

drivers/hwmon/pmbus/mp2869.c

304

ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) * data->vout_scale[page],

drivers/hwmon/pmbus/mp2869.c

312

ret = DIV_ROUND_CLOSEST((ret & GENMASK(10, 0)) * data->iout_scale[page],

drivers/hwmon/pmbus/mp2869.c

333

ret = FIELD_GET(GENMASK(10, 0), ret);

drivers/hwmon/pmbus/mp2869.c

340

if (FIELD_GET(GENMASK(12, 9), ret))

drivers/hwmon/pmbus/mp2869.c

341

ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE +

drivers/hwmon/pmbus/mp2869.c

342

(FIELD_GET(GENMASK(12, 9), ret) + 1) * MP2869_OVUV_DELTA_SCALE;

drivers/hwmon/pmbus/mp2869.c

344

ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE;

drivers/hwmon/pmbus/mp2869.c

351

if (FIELD_GET(GENMASK(12, 9), ret))

drivers/hwmon/pmbus/mp2869.c

352

ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE -

drivers/hwmon/pmbus/mp2869.c

353

(FIELD_GET(GENMASK(12, 9), ret) + 1) * MP2869_OVUV_DELTA_SCALE;

drivers/hwmon/pmbus/mp2869.c

355

ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE;

drivers/hwmon/pmbus/mp2869.c

367

ret = (ret & GENMASK(7, 0)) - MP2869_TEMP_LIMIT_OFFSET;

drivers/hwmon/pmbus/mp2869.c

374

ret = (ret & GENMASK(7, 0)) * MP2869_VIN_OV_FAULT_GAIN;

drivers/hwmon/pmbus/mp2869.c

382

ret = FIELD_GET(GENMASK(9, 0), ret);

drivers/hwmon/pmbus/mp2869.c

390

ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * data->iout_scale[page] *

drivers/hwmon/pmbus/mp2869.c

398

ret = (ret & GENMASK(7, 0)) * MP2869_POUT_OP_GAIN;

drivers/hwmon/pmbus/mp2869.c

425

if (FIELD_GET(GENMASK(12, 9), ret))

drivers/hwmon/pmbus/mp2869.c

427

(ret & ~GENMASK(8, 0)) |

drivers/hwmon/pmbus/mp2869.c

428

FIELD_PREP(GENMASK(8, 0),

drivers/hwmon/pmbus/mp2869.c

430

(FIELD_GET(GENMASK(12, 9),

drivers/hwmon/pmbus/mp2869.c

436

(ret & ~GENMASK(8, 0)) |

drivers/hwmon/pmbus/mp2869.c

437

FIELD_PREP(GENMASK(8, 0),

drivers/hwmon/pmbus/mp2869.c

450

if (FIELD_GET(GENMASK(12, 9), ret))

drivers/hwmon/pmbus/mp2869.c

452

(ret & ~GENMASK(8, 0)) |

drivers/hwmon/pmbus/mp2869.c

453

FIELD_PREP(GENMASK(8, 0),

drivers/hwmon/pmbus/mp2869.c

455

(FIELD_GET(GENMASK(12, 9),

drivers/hwmon/pmbus/mp2869.c

461

(ret & ~GENMASK(8, 0)) |

drivers/hwmon/pmbus/mp2869.c

462

FIELD_PREP(GENMASK(8, 0),

drivers/hwmon/pmbus/mp2869.c

485

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2869.c

486

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2869.c

501

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2869.c

502

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2869.c

519

(ret & ~GENMASK(9, 0)) |

drivers/hwmon/pmbus/mp2869.c

520

FIELD_PREP(GENMASK(9, 0),

drivers/hwmon/pmbus/mp2869.c

540

(ret & ~GENMASK(11, 0)) |

drivers/hwmon/pmbus/mp2869.c

541

FIELD_PREP(GENMASK(11, 0),

drivers/hwmon/pmbus/mp2888.c

171

ret = (ret & GENMASK(9, 0)) | ((ret & GENMASK(31, 10)) << 1);

drivers/hwmon/pmbus/mp2888.c

194

ret &= GENMASK(11, 0);

drivers/hwmon/pmbus/mp2888.c

201

ret &= GENMASK(9, 0);

drivers/hwmon/pmbus/mp2888.c

26

#define MP2888_DRMOS_KCS GENMASK(2, 0)

drivers/hwmon/pmbus/mp2888.c

272

word = clamp_val(word, 0, GENMASK(7, 0));

drivers/hwmon/pmbus/mp2888.c

279

word = clamp_val(word, 0, GENMASK(9, 0));

drivers/hwmon/pmbus/mp2888.c

286

word = clamp_val(word, 0, GENMASK(9, 0));

drivers/hwmon/pmbus/mp2888.c

309

info->phases[0] = ret & GENMASK(3, 0);

drivers/hwmon/pmbus/mp2891.c

106

if (ret & GENMASK(13, 13)) {

drivers/hwmon/pmbus/mp2891.c

109

ret = FIELD_GET(GENMASK(15, 14), ret);

drivers/hwmon/pmbus/mp2891.c

147

switch (ret & GENMASK(2, 0)) {

drivers/hwmon/pmbus/mp2891.c

234

ret = ret & GENMASK(9, 0);

drivers/hwmon/pmbus/mp2891.c

293

ret = DIV_ROUND_CLOSEST((ret & GENMASK(10, 0)) * data->iout_scale[page],

drivers/hwmon/pmbus/mp2891.c

306

ret = (ret & GENMASK(7, 0)) - MP2891_TEMP_LIMIT_OFFSET;

drivers/hwmon/pmbus/mp2891.c

318

ret = (ret & GENMASK(7, 0)) * 4;

drivers/hwmon/pmbus/mp2891.c

325

if (FIELD_GET(GENMASK(11, 8), ret))

drivers/hwmon/pmbus/mp2891.c

326

ret = FIELD_GET(GENMASK(7, 0), ret) * MP2891_UV_LIMIT_SCALE -

drivers/hwmon/pmbus/mp2891.c

327

(FIELD_GET(GENMASK(11, 8), ret) + 1) * MP2891_OVUV_DELTA_SCALE;

drivers/hwmon/pmbus/mp2891.c

329

ret = FIELD_GET(GENMASK(7, 0), ret) * MP2891_UV_LIMIT_SCALE;

drivers/hwmon/pmbus/mp2891.c

338

if (FIELD_GET(GENMASK(11, 8), ret))

drivers/hwmon/pmbus/mp2891.c

339

ret = FIELD_GET(GENMASK(7, 0), ret) * MP2891_OV_LIMIT_SCALE +

drivers/hwmon/pmbus/mp2891.c

340

(FIELD_GET(GENMASK(11, 8), ret) + 1) * MP2891_OVUV_DELTA_SCALE;

drivers/hwmon/pmbus/mp2891.c

342

ret = FIELD_GET(GENMASK(7, 0), ret) * MP2891_OV_LIMIT_SCALE;

drivers/hwmon/pmbus/mp2891.c

350

ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * data->iout_scale[page] *

drivers/hwmon/pmbus/mp2891.c

363

ret = DIV_ROUND_CLOSEST((ret & GENMASK(9, 0)), 2);

drivers/hwmon/pmbus/mp2891.c

375

ret = (ret & GENMASK(9, 0)) * MP2891_PIN_LIMIT_UINT;

drivers/hwmon/pmbus/mp2891.c

412

if (FIELD_GET(GENMASK(11, 8), ret))

drivers/hwmon/pmbus/mp2891.c

414

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

415

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2891.c

417

(FIELD_GET(GENMASK(11, 8), ret) + 1) *

drivers/hwmon/pmbus/mp2891.c

422

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

423

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2891.c

436

if (FIELD_GET(GENMASK(11, 8), ret))

drivers/hwmon/pmbus/mp2891.c

438

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

439

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2891.c

441

(FIELD_GET(GENMASK(11, 8), ret) + 1) *

drivers/hwmon/pmbus/mp2891.c

446

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

447

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2891.c

463

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

464

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp2891.c

479

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp2891.c

480

FIELD_PREP(GENMASK(7, 0), word + MP2891_TEMP_LIMIT_OFFSET));

drivers/hwmon/pmbus/mp2925.c

105

ret = DIV_ROUND_CLOSEST(((ret & GENMASK(11, 0)) + data->vid_offset[page]) *

drivers/hwmon/pmbus/mp2925.c

114

ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) * MP2925_VOUT_OVUV_UINT,

drivers/hwmon/pmbus/mp2925.c

173

(ret & ~GENMASK(11, 0)) |

drivers/hwmon/pmbus/mp2925.c

174

FIELD_PREP(GENMASK(11, 0),

drivers/hwmon/pmbus/mp2925.c

202

FIELD_GET(GENMASK(15, 11),

drivers/hwmon/pmbus/mp2925.c

228

if (FIELD_GET(GENMASK(5, 5), ret)) {

drivers/hwmon/pmbus/mp2925.c

238

if (FIELD_GET(GENMASK(5, 5), ret))

drivers/hwmon/pmbus/mp2925.c

251

} else if (FIELD_GET(GENMASK(4, 4), ret)) {

drivers/hwmon/pmbus/mp29502.c

136

data->vout_bottom_div = FIELD_GET(GENMASK(11, 0), ret);

drivers/hwmon/pmbus/mp29502.c

142

data->vout_top_div = FIELD_GET(GENMASK(14, 0), ret);

drivers/hwmon/pmbus/mp29502.c

162

data->ovp_div = FIELD_GET(GENMASK(9, 0), ret);

drivers/hwmon/pmbus/mp29502.c

182

switch (ret & GENMASK(2, 0)) {

drivers/hwmon/pmbus/mp29502.c

229

ov_value = DIV_ROUND_CLOSEST(FIELD_GET(GENMASK(12, 7), ret) *

drivers/hwmon/pmbus/mp29502.c

260

(ret & ~GENMASK(12, 7)) |

drivers/hwmon/pmbus/mp29502.c

261

FIELD_PREP(GENMASK(12, 7),

drivers/hwmon/pmbus/mp29502.c

310

ret = FIELD_GET(GENMASK(10, 0), ret);

drivers/hwmon/pmbus/mp29502.c

321

ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) *

drivers/hwmon/pmbus/mp29502.c

377

ret = DIV_ROUND_CLOSEST((ret & GENMASK(10, 0)) * data->iout_scale,

drivers/hwmon/pmbus/mp29502.c

385

ret = FIELD_GET(GENMASK(10, 0), ret);

drivers/hwmon/pmbus/mp29502.c

397

ret = FIELD_GET(GENMASK(7, 0), ret) * MP29502_VIN_OV_GAIN;

drivers/hwmon/pmbus/mp29502.c

411

ret = FIELD_GET(GENMASK(9, 0), ret);

drivers/hwmon/pmbus/mp29502.c

428

ret = DIV_ROUND_CLOSEST((FIELD_GET(GENMASK(8, 0), ret) *

drivers/hwmon/pmbus/mp29502.c

441

ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) *

drivers/hwmon/pmbus/mp29502.c

456

ret = (ret & GENMASK(7, 0)) - MP29502_TEMP_LIMIT_OFFSET;

drivers/hwmon/pmbus/mp29502.c

491

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp29502.c

492

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp29502.c

507

(ret & ~GENMASK(9, 0)) |

drivers/hwmon/pmbus/mp29502.c

508

FIELD_PREP(GENMASK(9, 0),

drivers/hwmon/pmbus/mp29502.c

523

(ret & ~GENMASK(8, 0)) |

drivers/hwmon/pmbus/mp29502.c

524

FIELD_PREP(GENMASK(8, 0),

drivers/hwmon/pmbus/mp29502.c

553

(ret & ~GENMASK(7, 0)) |

drivers/hwmon/pmbus/mp29502.c

554

FIELD_PREP(GENMASK(7, 0),

drivers/hwmon/pmbus/mp29502.c

88

switch (FIELD_GET(GENMASK(12, 10), ret)) {

drivers/hwmon/pmbus/mp2975.c

322

GENMASK(7, 0));

drivers/hwmon/pmbus/mp2975.c

326

GENMASK(7, 0));

drivers/hwmon/pmbus/mp2975.c

338

GENMASK(2, 0));

drivers/hwmon/pmbus/mp2975.c

346

GENMASK(8, 0));

drivers/hwmon/pmbus/mp2975.c

362

GENMASK(15, 0));

drivers/hwmon/pmbus/mp2975.c

479

GENMASK(7, 0));

drivers/hwmon/pmbus/mp2975.c

48

#define MP2975_DRMOS_KCS GENMASK(13, 12)

drivers/hwmon/pmbus/mp2975.c

483

GENMASK(7, 0));

drivers/hwmon/pmbus/mp2975.c

498

GENMASK(2, 0));

drivers/hwmon/pmbus/mp2975.c

508

GENMASK(2, 0));

drivers/hwmon/pmbus/mp2975.c

518

GENMASK(12, 0));

drivers/hwmon/pmbus/mp2975.c

527

GENMASK(12, 0));

drivers/hwmon/pmbus/mp2975.c

56

#define MP2973_VOUT_FORMAT_R1 GENMASK(7, 6)

drivers/hwmon/pmbus/mp2975.c

57

#define MP2973_VOUT_FORMAT_R2 GENMASK(4, 3)

drivers/hwmon/pmbus/mp2975.c

580

ret &= GENMASK(2, 0);

drivers/hwmon/pmbus/mp2975.c

617

info->phases[0] = ret & GENMASK(3, 0);

drivers/hwmon/pmbus/mp2975.c

71

#define MP2973_OCP_TOTAL_CUR_MASK GENMASK(6, 0)

drivers/hwmon/pmbus/mp2975.c

800

switch ((ret & GENMASK(5, 3)) >> 3) {

drivers/hwmon/pmbus/mp2975.c

828

GENMASK(8, 0));

drivers/hwmon/pmbus/mp2993.c

108

ret = DIV_ROUND_CLOSEST((ret & GENMASK(9, 0)) * MP2993_READ_VIN_UINT,

drivers/hwmon/pmbus/mp2993.c

120

ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * MP2993_VIN_LIMIT_UINT,

drivers/hwmon/pmbus/mp9941.c

106

ret = (ret & ~GENMASK(3, 2)) | FIELD_PREP(GENMASK(3, 2), 0);

drivers/hwmon/pmbus/mp9941.c

124

ret = (ret & ~GENMASK(15, 13)) | FIELD_PREP(GENMASK(15, 13), 0);

drivers/hwmon/pmbus/mp9941.c

158

ret = DIV_ROUND_CLOSEST((ret & GENMASK(9, 0)) * MP9941_READ_VIN_UINT,

drivers/hwmon/pmbus/mp9941.c

166

ret = ret & GENMASK(10, 0);

drivers/hwmon/pmbus/mp9941.c

174

ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * MP9941_VIN_LIMIT_UINT,

drivers/hwmon/pmbus/mp9941.c

182

ret = ret & GENMASK(7, 0);

drivers/hwmon/pmbus/mp9941.c

62

ret = (ret & ~GENMASK(7, 6)) | FIELD_PREP(GENMASK(7, 6), 3);

drivers/hwmon/pmbus/mp9941.c

86

if (FIELD_GET(GENMASK(4, 4), ret))

drivers/hwmon/pmbus/mp9945.c

116

ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) * 39, 20);

drivers/hwmon/pmbus/mp9945.c

123

ret &= GENMASK(9, 0);

drivers/hwmon/pmbus/mp9945.c

54

ret &= GENMASK(11, 0);

drivers/hwmon/pmbus/mpq7932.c

29

#define MPQ7932_VOUT_SLEW_MASK GENMASK(1, 0)

drivers/hwmon/pmbus/mpq7932.c

30

#define MPQ7932_TON_DELAY_MASK GENMASK(4, 0)

drivers/hwmon/pmbus/mpq8785.c

18

[mpm3695] = GENMASK(9, 0),

drivers/hwmon/pmbus/mpq8785.c

19

[mpm3695_25] = GENMASK(11, 0),

drivers/hwmon/pmbus/mpq8785.c

20

[mpm82504] = GENMASK(9, 0),

drivers/hwmon/pmbus/mpq8785.c

21

[mpq8785] = GENMASK(10, 0),

drivers/hwmon/pmbus/pxe1610.c

34

vout_mode = ret & GENMASK(4, 0);

drivers/hwmon/pmbus/tps25990.c

34

#define PK_MIN_AVG_AVG_CNT GENMASK(2, 0)

drivers/hwmon/pmbus/tps53679.c

55

vout_params = ret & GENMASK(4, 0);

drivers/hwmon/pmbus/xdp710.c

78

cs_rng = (ret >> 6) & GENMASK(1, 0);

drivers/hwmon/pmbus/xdp710.c

85

vtlm_rng = ret & GENMASK(1, 0);

drivers/hwmon/pmbus/xdp710.c

92

ret &= GENMASK(5, 0);

drivers/hwmon/pmbus/xdpe12284.c

104

vout_params = ret & GENMASK(4, 0);

drivers/hwmon/pmbus/xdpe12284.c

41

mantissa = ((s16)((ret & GENMASK(10, 0)) << 5)) >> 5;

drivers/hwmon/sfctemp.c

43

#define SFCTEMP_DOUT_MSK GENMASK(27, 16)

drivers/hwmon/sl28cpld-hwmon.c

19

#define FAN_VALUE_MASK GENMASK(6, 0)

drivers/hwmon/sparx5-temp.c

18

#define TEMP_CFG_CYCLES GENMASK(24, 15)

drivers/hwmon/sparx5-temp.c

22

#define TEMP_STAT_TEMP GENMASK(11, 0)

drivers/hwmon/spd5118.c

59

#define SPD5118_LEGACY_PAGE_MASK GENMASK(2, 0)

drivers/hwmon/spd5118.c

65

#define SPD5118_PAGE_MASK GENMASK(6, 0)

drivers/hwmon/spd5118.c

70

#define PAGE_ADDR1_4(page) (((page) & GENMASK(4, 1)) >> 1)

drivers/hwmon/tmp108.c

77

#define TMP108_CONF_CONVRATE_FLD GENMASK(TMP108_CONF_CR1_POS, TMP108_CONF_CR0_POS)

drivers/hwmon/tmp421.c

37

#define TMP421_CONFIG_REG_REN_MASK GENMASK(6, 3)

drivers/hwmon/tmp464.c

52

#define TMP464_CONFIG_REG_REN_MASK GENMASK(15, 7)

drivers/hwmon/tmp464.c

55

#define TMP464_CONFIG_CONVERSION_RATE_MASK GENMASK(TMP464_CONFIG_CONVERSION_RATE_B2, \

drivers/hwmon/tmp513.c

121

#define TMP51X_TEMP_CONFIG_CONV_RATE GENMASK(9, 7)

drivers/hwmon/tmp513.c

123

#define TMP51X_TEMP_CHANNEL_MASK(n) (GENMASK((n) - 1, 0) << 11)

drivers/hwmon/tps23861.c

41

#define VOLTAGE_CURRENT_MASK GENMASK(13, 0)

drivers/hwmon/tps23861.c

51

#define PORT_RESISTANCE_MASK GENMASK(13, 0)

drivers/hwmon/tps23861.c

52

#define PORT_RESISTANCE_RSN_MASK GENMASK(15, 14)

drivers/hwmon/tps23861.c

61

#define PORT_STATUS_CLASS_MASK GENMASK(7, 4)

drivers/hwmon/tps23861.c

62

#define PORT_STATUS_DETECT_MASK GENMASK(3, 0)

drivers/hwmon/tps23861.c

93

#define OPERATING_MODE_PORT_1_MASK GENMASK(1, 0)

drivers/hwmon/tps23861.c

94

#define OPERATING_MODE_PORT_2_MASK GENMASK(3, 2)

drivers/hwmon/tps23861.c

95

#define OPERATING_MODE_PORT_3_MASK GENMASK(5, 4)

drivers/hwmon/tps23861.c

96

#define OPERATING_MODE_PORT_4_MASK GENMASK(7, 6)

drivers/hwmon/tsc1641.c

47

#define TSC1641_CONV_TIME_MASK GENMASK(7, 4)

drivers/hwtracing/coresight/coresight-cpu-debug.c

45

#define EDPCSR_ARM_INST_MASK GENMASK(31, 2)

drivers/hwtracing/coresight/coresight-cpu-debug.c

46

#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)

drivers/hwtracing/coresight/coresight-cpu-debug.c

61

#define EDVIDSR_VMID GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-cpu-debug.c

75

#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)

drivers/hwtracing/coresight/coresight-cpu-debug.c

80

#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)

drivers/hwtracing/coresight/coresight-cti-core.c

241

config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0);

drivers/hwtracing/coresight/coresight-cti-core.c

317

u32 n_trig_mask = GENMASK(n_trigs - 1, 0);

drivers/hwtracing/coresight/coresight-cti-sysfs.c

740

config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0);

drivers/hwtracing/coresight/coresight-cti-sysfs.c

853

chan_mask = GENMASK(config->nr_ctm_channels - 1, 0);

drivers/hwtracing/coresight/coresight-etm.h

125

#define PORT_SIZE_MASK (GENMASK(21, 21) | GENMASK(6, 4))

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

103

idx = (offset & GENMASK(6, 0)) / 4;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

111

idx = (offset & GENMASK(6, 0)) / 8;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

112

off_mask = offset & GENMASK(11, 7);

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

120

idx = (offset & GENMASK(3, 0)) / 4;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

121

off_mask = offset & GENMASK(11, 4);

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

76

} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

78

idx = (offset & GENMASK(3, 0)) / 4;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

85

idx = (offset & GENMASK(4, 0)) / 4;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

86

off_mask = (offset & GENMASK(11, 5));

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

94

idx = (offset & GENMASK(5, 0)) / 8;

drivers/hwtracing/coresight/coresight-etm4x-cfg.c

95

off_mask = (offset & GENMASK(11, 6));

drivers/hwtracing/coresight/coresight-etm4x-core.c

118

val &= GENMASK(31, 0);

drivers/hwtracing/coresight/coresight-etm4x-core.c

150

val &= GENMASK(31, 0);

drivers/hwtracing/coresight/coresight-etm4x.h

132

#define TRCIDR0_INSTP0_MASK GENMASK(2, 1)

drivers/hwtracing/coresight/coresight-etm4x.h

137

#define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10)

drivers/hwtracing/coresight/coresight-etm4x.h

139

#define TRCIDR0_QSUPP_MASK GENMASK(16, 15)

drivers/hwtracing/coresight/coresight-etm4x.h

140

#define TRCIDR0_TSSIZE_MASK GENMASK(28, 24)

drivers/hwtracing/coresight/coresight-etm4x.h

142

#define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5)

drivers/hwtracing/coresight/coresight-etm4x.h

143

#define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10)

drivers/hwtracing/coresight/coresight-etm4x.h

144

#define TRCIDR2_CCSIZE_MASK GENMASK(28, 25)

drivers/hwtracing/coresight/coresight-etm4x.h

146

#define TRCIDR3_CCITMIN_MASK GENMASK(11, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

147

#define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

148

#define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20)

drivers/hwtracing/coresight/coresight-etm4x.h

153

#define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28)

drivers/hwtracing/coresight/coresight-etm4x.h

154

#define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12)

drivers/hwtracing/coresight/coresight-etm4x.h

157

#define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

158

#define TRCIDR4_NUMPC_MASK GENMASK(15, 12)

drivers/hwtracing/coresight/coresight-etm4x.h

159

#define TRCIDR4_NUMRSPAIR_MASK GENMASK(19, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

160

#define TRCIDR4_NUMSSCC_MASK GENMASK(23, 20)

drivers/hwtracing/coresight/coresight-etm4x.h

161

#define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24)

drivers/hwtracing/coresight/coresight-etm4x.h

162

#define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28)

drivers/hwtracing/coresight/coresight-etm4x.h

164

#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

165

#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9)

drivers/hwtracing/coresight/coresight-etm4x.h

166

#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

169

#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25)

drivers/hwtracing/coresight/coresight-etm4x.h

170

#define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28)

drivers/hwtracing/coresight/coresight-etm4x.h

179

#define TRCCONFIGR_COND_MASK GENMASK(10, 8)

drivers/hwtracing/coresight/coresight-etm4x.h

188

#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

200

#define TRCVICTLR_EVENT_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

204

#define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

205

#define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

206

#define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20)

drivers/hwtracing/coresight/coresight-etm4x.h

208

#define TRCACATRn_TYPE_MASK GENMASK(1, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

209

#define TRCACATRn_CONTEXTTYPE_MASK GENMASK(3, 2)

drivers/hwtracing/coresight/coresight-etm4x.h

212

#define TRCACATRn_CONTEXT_MASK GENMASK(6, 4)

drivers/hwtracing/coresight/coresight-etm4x.h

213

#define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)

drivers/hwtracing/coresight/coresight-etm4x.h

216

#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

218

#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

221

#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

225

#define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

226

#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

230

#define TRCCNTCTLRn_RLDEVENT_MASK GENMASK(15, 8)

drivers/hwtracing/coresight/coresight-etm4x.h

231

#define TRCCNTCTLRn_CNTEVENT_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

233

#define TRCTSCTLR_EVENT_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

238

#define ETM4_RES_SEL_SINGLE_MASK GENMASK(4, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

239

#define ETM4_RES_SEL_PAIR_MASK GENMASK(3, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

662

#define ETMv4_MODE_ALL (GENMASK(27, 0) | \

drivers/hwtracing/coresight/coresight-etm4x.h

678

#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))

drivers/hwtracing/coresight/coresight-etm4x.h

694

#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)

drivers/hwtracing/coresight/coresight-etm4x.h

698

#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)

drivers/hwtracing/coresight/coresight-etm4x.h

701

#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)

drivers/hwtracing/coresight/coresight-etm4x.h

703

#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)

drivers/hwtracing/coresight/coresight-priv.h

38

#define CORESIGHT_CLAIM_MASK GENMASK(1, 0)

drivers/hwtracing/coresight/coresight-priv.h

45

#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)

drivers/hwtracing/coresight/coresight-tmc-core.c

102

mask = GENMASK(31, 5);

drivers/hwtracing/coresight/coresight-tmc-core.c

99

mask = GENMASK(31, 4);

drivers/hwtracing/coresight/coresight-tmc.h

99

#define TMC_AUTH_NSID_MASK GENMASK(1, 0)

drivers/hwtracing/coresight/coresight-tpda.h

26

#define TPDA_CR_ATID GENMASK(12, 6)

drivers/hwtracing/coresight/coresight-tpda.h

37

#define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6)

drivers/hwtracing/coresight/coresight-tpda.h

42

#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0)

drivers/hwtracing/coresight/coresight-tpda.h

44

#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12)

drivers/hwtracing/coresight/coresight-tpdm.c

583

drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);

drivers/hwtracing/coresight/coresight-tpdm.h

32

#define TPDM_CMB_CR_XTRIG_LNSEL GENMASK(20, 18)

drivers/hwtracing/coresight/coresight-tpdm.h

34

#define TPDM_CMB_CR_E_LN GENMASK(17, 10)

drivers/hwtracing/coresight/coresight-tpdm.h

52

#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0)

drivers/hwtracing/coresight/coresight-tpdm.h

72

#define TPDM_DSB_CR_HPSEL GENMASK(6, 2)

drivers/hwtracing/coresight/coresight-tpdm.h

74

#define TPDM_DSB_CR_TEST_MODE GENMASK(10, 9)

drivers/hwtracing/coresight/coresight-tpdm.h

85

#define TPDM_DSB_MODE_MASK GENMASK(8, 0)

drivers/hwtracing/coresight/coresight-tpdm.h

87

#define TPDM_DSB_MODE_TEST(val) (val & GENMASK(1, 0))

drivers/hwtracing/coresight/coresight-tpdm.h

91

#define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4))

drivers/hwtracing/coresight/ultrasoc-smb.h

29

#define SMB_GLB_CFG_BURST_LEN_MSK GENMASK(11, 4)

drivers/hwtracing/coresight/ultrasoc-smb.h

30

#define SMB_GLB_CFG_IDLE_PRD_MSK GENMASK(15, 12)

drivers/hwtracing/coresight/ultrasoc-smb.h

31

#define SMB_GLB_CFG_MEM_WR_MSK GENMASK(21, 16)

drivers/hwtracing/coresight/ultrasoc-smb.h

32

#define SMB_GLB_CFG_MEM_RD_MSK GENMASK(27, 22)

drivers/hwtracing/coresight/ultrasoc-smb.h

52

#define SMB_LB_CFG_LO_FLOW_MSK GENMASK(19, 16)

drivers/hwtracing/coresight/ultrasoc-smb.h

58

#define SMB_LB_CFG_HI_RANGE_UP_MSK GENMASK(15, 8)

drivers/hwtracing/coresight/ultrasoc-smb.h

72

#define SMB_LB_INT_CTRL_BUF_NOTE_MSK GENMASK(11, 8)

drivers/hwtracing/coresight/ultrasoc-smb.h

78

#define SMB_LB_INT_STS_BUF_RESET_MSK GENMASK(3, 0)

drivers/hwtracing/coresight/ultrasoc-smb.h

85

#define SMB_BUF_ADDR_LO_MSK GENMASK(31, 0)

drivers/hwtracing/ptt/hisi_ptt.h

31

#define HISI_PTT_TUNING_CTRL_CODE GENMASK(15, 0)

drivers/hwtracing/ptt/hisi_ptt.h

32

#define HISI_PTT_TUNING_CTRL_SUB GENMASK(23, 16)

drivers/hwtracing/ptt/hisi_ptt.h

34

#define HISI_PTT_TUNING_DATA_VAL_MASK GENMASK(15, 0)

drivers/hwtracing/ptt/hisi_ptt.h

42

#define HISI_PTT_TRACE_CTRL_RXTX_SEL GENMASK(3, 2)

drivers/hwtracing/ptt/hisi_ptt.h

43

#define HISI_PTT_TRACE_CTRL_TYPE_SEL GENMASK(7, 4)

drivers/hwtracing/ptt/hisi_ptt.h

46

#define HISI_PTT_TRACE_CTRL_TARGET_SEL GENMASK(31, 16)

drivers/hwtracing/ptt/hisi_ptt.h

48

#define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0)

drivers/hwtracing/ptt/hisi_ptt.h

50

#define HISI_PTT_TRACE_INT_MASK_ALL GENMASK(3, 0)

drivers/hwtracing/ptt/hisi_ptt.h

54

#define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0)

drivers/hwtracing/ptt/hisi_ptt.h

55

#define HISI_PTT_TRACE_WR_STS_BUFFER GENMASK(29, 28)

drivers/hwtracing/ptt/hisi_ptt.h

59

#define HISI_PTT_DEVICE_RANGE_UPPER GENMASK(31, 16)

drivers/hwtracing/ptt/hisi_ptt.h

60

#define HISI_PTT_DEVICE_RANGE_LOWER GENMASK(15, 0)

drivers/hwtracing/ptt/hisi_ptt.h

62

#define HISI_PTT_CORE_ID GENMASK(15, 0)

drivers/hwtracing/ptt/hisi_ptt.h

63

#define HISI_PTT_SICL_ID GENMASK(31, 16)

drivers/hwtracing/ptt/hisi_ptt.h

88

#define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0)

drivers/hwtracing/ptt/hisi_ptt.h

89

#define HISI_PTT_PMU_DIRECTION_MASK GENMASK(23, 20)

drivers/hwtracing/ptt/hisi_ptt.h

90

#define HISI_PTT_PMU_TYPE_MASK GENMASK(31, 24)

drivers/hwtracing/ptt/hisi_ptt.h

91

#define HISI_PTT_PMU_FORMAT_MASK GENMASK(35, 32)

drivers/i2c/busses/i2c-amd-asf-plat.c

47

#define ASF_ERROR_STATUS GENMASK(3, 1)

drivers/i2c/busses/i2c-amd-asf-plat.c

73

reg |= GENMASK(3, 2);

drivers/i2c/busses/i2c-aspeed.c

118

#define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)

drivers/i2c/busses/i2c-aspeed.c

52

#define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)

drivers/i2c/busses/i2c-aspeed.c

53

#define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)

drivers/i2c/busses/i2c-aspeed.c

54

#define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)

drivers/i2c/busses/i2c-aspeed.c

56

#define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)

drivers/i2c/busses/i2c-aspeed.c

58

#define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)

drivers/i2c/busses/i2c-aspeed.c

59

#define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)

drivers/i2c/busses/i2c-aspeed.c

60

#define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)

drivers/i2c/busses/i2c-aspeed.c

898

return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);

drivers/i2c/busses/i2c-aspeed.c

907

return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);

drivers/i2c/busses/i2c-at91.h

86

#define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0)

drivers/i2c/busses/i2c-at91.h

95

#define AT91_TWI_FILTR_THRES_MASK GENMASK(10, 8)

drivers/i2c/busses/i2c-brcmstb.c

25

#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))

drivers/i2c/busses/i2c-cht-wc.c

37

#define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1))

drivers/i2c/busses/i2c-designware-core.h

137

#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)

drivers/i2c/busses/i2c-designware-core.h

144

#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)

drivers/i2c/busses/i2c-designware-core.h

152

#define STATUS_MASK GENMASK(2, 0)

drivers/i2c/busses/i2c-designware-core.h

32

#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)

drivers/i2c/busses/i2c-designware-core.h

333

#define MODEL_MASK GENMASK(11, 8)

drivers/i2c/busses/i2c-designware-core.h

42

#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)

drivers/i2c/busses/i2c-designware-core.h

54

#define DW_IC_FIFO_TX_FIELD GENMASK(23, 16)

drivers/i2c/busses/i2c-designware-core.h

55

#define DW_IC_FIFO_RX_FIELD GENMASK(15, 8)

drivers/i2c/busses/i2c-designware-master.c

32

#define AMD_MASTERCFG_MASK GENMASK(15, 0)

drivers/i2c/busses/i2c-designware-master.c

693

if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0))

drivers/i2c/busses/i2c-fsi.c

101

#define I2C_STAT_MAX_PORT GENMASK(22, 16)

drivers/i2c/busses/i2c-fsi.c

107

#define I2C_STAT_FIFO_COUNT GENMASK(7, 0)

drivers/i2c/busses/i2c-fsi.c

121

#define I2C_ESTAT_FIFO_SZ GENMASK(31, 24)

drivers/i2c/busses/i2c-fsi.c

132

#define I2C_ESTAT_VERSION GENMASK(4, 0)

drivers/i2c/busses/i2c-fsi.c

59

#define I2C_CMD_ADDR GENMASK(23, 17)

drivers/i2c/busses/i2c-fsi.c

61

#define I2C_CMD_LEN GENMASK(15, 0)

drivers/i2c/busses/i2c-fsi.c

64

#define I2C_MODE_CLKDIV GENMASK(31, 16)

drivers/i2c/busses/i2c-fsi.c

65

#define I2C_MODE_PORT GENMASK(15, 10)

drivers/i2c/busses/i2c-fsi.c

72

#define I2C_WATERMARK_HI GENMASK(15, 12)

drivers/i2c/busses/i2c-fsi.c

73

#define I2C_WATERMARK_LO GENMASK(7, 4)

drivers/i2c/busses/i2c-hisi.c

22

#define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0)

drivers/i2c/busses/i2c-hisi.c

25

#define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0)

drivers/i2c/busses/i2c-hisi.c

29

#define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0)

drivers/i2c/busses/i2c-hisi.c

34

#define HISI_I2C_RXDATA_DATA GENMASK(7, 0)

drivers/i2c/busses/i2c-hisi.c

44

#define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2)

drivers/i2c/busses/i2c-hisi.c

45

#define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8)

drivers/i2c/busses/i2c-hisi.c

54

#define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0)

drivers/i2c/busses/i2c-hisi.c

55

#define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16)

drivers/i2c/busses/i2c-hisi.c

57

#define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0)

drivers/i2c/busses/i2c-hisi.c

59

#define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0)

drivers/i2c/busses/i2c-hisi.c

69

#define HISI_I2C_INT_ALL GENMASK(4, 0)

drivers/i2c/busses/i2c-k1.c

85

#define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0)

drivers/i2c/busses/i2c-ljca.c

24

#define LJCA_I2C_INIT_FLAG_FREQ GENMASK(2, 1)

drivers/i2c/busses/i2c-ls2x.c

116

writeb(FIELD_GET(GENMASK(7, 0), val), priv->base + I2C_LS2X_PRER_LO);

drivers/i2c/busses/i2c-ls2x.c

117

writeb(FIELD_GET(GENMASK(15, 8), val), priv->base + I2C_LS2X_PRER_HI);

drivers/i2c/busses/i2c-ls2x.c

57

#define CTR_FREQ_MASK GENMASK(7, 6)

drivers/i2c/busses/i2c-ls2x.c

58

#define CTR_READY_MASK GENMASK(7, 5)

drivers/i2c/busses/i2c-meson.c

161

if (div_h > GENMASK(11, 0)) {

drivers/i2c/busses/i2c-meson.c

163

div_h = GENMASK(11, 0);

drivers/i2c/busses/i2c-meson.c

165

if (div_l > GENMASK(11, 0)) {

drivers/i2c/busses/i2c-meson.c

167

div_l = GENMASK(11, 0);

drivers/i2c/busses/i2c-meson.c

171

FIELD_PREP(REG_CTRL_CLKDIV_MASK, div_h & GENMASK(9, 0)));

drivers/i2c/busses/i2c-meson.c

197

if (div > GENMASK(11, 0)) {

drivers/i2c/busses/i2c-meson.c

199

div = GENMASK(11, 0);

drivers/i2c/busses/i2c-meson.c

203

FIELD_PREP(REG_CTRL_CLKDIV_MASK, div & GENMASK(9, 0)));

drivers/i2c/busses/i2c-meson.c

37

#define REG_CTRL_CLKDIV_MASK GENMASK(21, REG_CTRL_CLKDIV_SHIFT)

drivers/i2c/busses/i2c-meson.c

39

#define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, REG_CTRL_CLKDIVEXT_SHIFT)

drivers/i2c/busses/i2c-meson.c

41

#define REG_SLV_ADDR_MASK GENMASK(7, 0)

drivers/i2c/busses/i2c-meson.c

42

#define REG_SLV_SDA_FILTER_MASK GENMASK(10, 8)

drivers/i2c/busses/i2c-meson.c

43

#define REG_SLV_SCL_FILTER_MASK GENMASK(13, 11)

drivers/i2c/busses/i2c-meson.c

45

#define REG_SLV_SCL_LOW_MASK GENMASK(27, REG_SLV_SCL_LOW_SHIFT)

drivers/i2c/busses/i2c-mlxbf.c

113

#define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)

drivers/i2c/busses/i2c-mlxbf.c

1563

addr_tmp = slave_reg_tmp & GENMASK(7, 0);

drivers/i2c/busses/i2c-mlxbf.c

1631

slave_reg &= ~(GENMASK(7, 0) << (byte * 8));

drivers/i2c/busses/i2c-mlxbf.c

175

#define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3)

drivers/i2c/busses/i2c-mlxbf.c

176

#define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16)

drivers/i2c/busses/i2c-mlxbf.c

177

#define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20)

drivers/i2c/busses/i2c-mlxbf.c

180

#define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)

drivers/i2c/busses/i2c-mlxbf.c

181

#define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)

drivers/i2c/busses/i2c-mlxbf.c

182

#define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26)

drivers/i2c/busses/i2c-mlxbf.c

1831

addr = (data32 & GENMASK(7, 0)) >> 1;

drivers/i2c/busses/i2c-mlxbf.c

1853

value = (data32 >> 8) & GENMASK(7, 0);

drivers/i2c/busses/i2c-mlxbf.c

198

#define MLXBF_I2C_MASK_8 GENMASK(7, 0)

drivers/i2c/busses/i2c-mlxbf.c

199

#define MLXBF_I2C_MASK_16 GENMASK(15, 0)

drivers/i2c/busses/i2c-mlxbf.c

1999

recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);

drivers/i2c/busses/i2c-mlxbf.c

200

#define MLXBF_I2C_MASK_32 GENMASK(31, 0)

drivers/i2c/busses/i2c-mlxbf.c

258

#define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)

drivers/i2c/busses/i2c-mlxbf.c

302

#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)

drivers/i2c/busses/i2c-mlxbf.c

630

data[offset + byte] = data32 & GENMASK(7, 0);

drivers/i2c/busses/i2c-mlxbf.c

701

slave = request->slave & GENMASK(6, 0);

drivers/i2c/busses/i2c-mlxcpld.c

26

#define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5)

drivers/i2c/busses/i2c-mt65xx.c

755

i2c->ac_timing.ltiming &= ~GENMASK(15, 9);

drivers/i2c/busses/i2c-mt65xx.c

758

i2c->ac_timing.ext &= ~GENMASK(7, 1);

drivers/i2c/busses/i2c-mt65xx.c

766

i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);

drivers/i2c/busses/i2c-nomadik.c

1032

GENMASK(5, 4),

drivers/i2c/busses/i2c-nomadik.c

1033

GENMASK(7, 6),

drivers/i2c/busses/i2c-nomadik.c

1034

GENMASK(9, 8),

drivers/i2c/busses/i2c-nomadik.c

1035

GENMASK(11, 10),

drivers/i2c/busses/i2c-nomadik.c

1036

GENMASK(13, 12),

drivers/i2c/busses/i2c-nomadik.c

343

#define ADR_3MSB_BITS GENMASK(9, 7)

drivers/i2c/busses/i2c-nomadik.c

57

#define I2C_CR_OM GENMASK(2, 1) /* Operating mode */

drivers/i2c/busses/i2c-nomadik.c

59

#define I2C_CR_SM GENMASK(5, 4) /* Speed mode */

drivers/i2c/busses/i2c-nomadik.c

67

#define I2C_CR_FON GENMASK(14, 13) /* Filtering on */

drivers/i2c/busses/i2c-nomadik.c

68

#define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */

drivers/i2c/busses/i2c-nomadik.c

71

#define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */

drivers/i2c/busses/i2c-nomadik.c

75

#define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */

drivers/i2c/busses/i2c-nomadik.c

76

#define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */

drivers/i2c/busses/i2c-nomadik.c

78

#define I2C_MCR_AM GENMASK(13, 12) /* Address type */

drivers/i2c/busses/i2c-nomadik.c

80

#define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */

drivers/i2c/busses/i2c-nomadik.c

83

#define I2C_SR_OP GENMASK(1, 0) /* Operation */

drivers/i2c/busses/i2c-nomadik.c

84

#define I2C_SR_STATUS GENMASK(3, 2) /* controller status */

drivers/i2c/busses/i2c-nomadik.c

85

#define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */

drivers/i2c/busses/i2c-nomadik.c

86

#define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */

drivers/i2c/busses/i2c-nomadik.c

87

#define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */

drivers/i2c/busses/i2c-nomadik.c

90

#define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */

drivers/i2c/busses/i2c-nomadik.c

91

#define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */

drivers/i2c/busses/i2c-npcm7xx.c

184

#define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */

drivers/i2c/busses/i2c-npcm7xx.c

189

#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */

drivers/i2c/busses/i2c-npcm7xx.c

192

#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */

drivers/i2c/busses/i2c-npcm7xx.c

217

#define I2CCTL4_HLDT GENMASK(5, 0)

drivers/i2c/busses/i2c-npcm7xx.c

221

#define I2CCTL5_DBNCT GENMASK(3, 0)

drivers/i2c/busses/i2c-npcm7xx.c

233

#define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)

drivers/i2c/busses/i2c-npcm7xx.c

252

#define I2C_VER_VERSION GENMASK(6, 0)

drivers/i2c/busses/i2c-npcm7xx.c

259

#define SCLFRQ_0_TO_6 GENMASK(6, 0)

drivers/i2c/busses/i2c-npcm7xx.c

260

#define SCLFRQ_7_TO_8 GENMASK(8, 7)

drivers/i2c/busses/i2c-npcm7xx.c

536

.txf_sts_tx_bytes = GENMASK(4, 0),

drivers/i2c/busses/i2c-npcm7xx.c

537

.rxf_sts_rx_bytes = GENMASK(4, 0),

drivers/i2c/busses/i2c-npcm7xx.c

544

.txf_sts_tx_bytes = GENMASK(5, 0),

drivers/i2c/busses/i2c-npcm7xx.c

545

.rxf_sts_rx_bytes = GENMASK(5, 0),

drivers/i2c/busses/i2c-nvidia-gpu.c

31

#define I2C_MST_CNTL_STATUS GENMASK(30, 29)

drivers/i2c/busses/i2c-octeon-core.h

240

#define PCI_SUBSYS_MASK GENMASK(15, 12)

drivers/i2c/busses/i2c-owl.c

85

#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)

drivers/i2c/busses/i2c-owl.c

86

#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)

drivers/i2c/busses/i2c-pasemi-core.c

35

#define MTXFIFO_DATA_M GENMASK(7, 0)

drivers/i2c/busses/i2c-pasemi-core.c

38

#define MRXFIFO_DATA_M GENMASK(7, 0)

drivers/i2c/busses/i2c-pasemi-core.c

55

#define CTL_CLK_M GENMASK(7, 0)

drivers/i2c/busses/i2c-qcom-geni.c

45

#define SLV_ADDR_MSK GENMASK(15, 9)

drivers/i2c/busses/i2c-qcom-geni.c

48

#define HIGH_COUNTER_MSK GENMASK(29, 20)

drivers/i2c/busses/i2c-qcom-geni.c

50

#define LOW_COUNTER_MSK GENMASK(19, 10)

drivers/i2c/busses/i2c-qcom-geni.c

52

#define CYCLE_COUNTER_MSK GENMASK(9, 0)

drivers/i2c/busses/i2c-rcar.c

131

#define ID_P_MASK GENMASK(31, 27)

drivers/i2c/busses/i2c-riic.c

65

#define ICMR1_CKS_MASK GENMASK(6, 4)

drivers/i2c/busses/i2c-riic.c

84

#define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */

drivers/i2c/busses/i2c-sprd.c

35

#define FIFO_AF_LVL_MASK GENMASK(19, 16)

drivers/i2c/busses/i2c-sprd.c

37

#define FIFO_AE_LVL_MASK GENMASK(15, 12)

drivers/i2c/busses/i2c-sprd.c

68

((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))

drivers/i2c/busses/i2c-sprd.c

70

(((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))

drivers/i2c/busses/i2c-stm32f4.c

51

#define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0)

drivers/i2c/busses/i2c-stm32f4.c

82

#define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0)

drivers/i2c/busses/i2c-stm32f4.c

88

#define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0)

drivers/i2c/busses/i2c-stm32f7.c

105

#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)

drivers/i2c/busses/i2c-stm32f7.c

108

#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)

drivers/i2c/busses/i2c-stm32f7.c

117

#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)

drivers/i2c/busses/i2c-stm32f7.c

119

#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)

drivers/i2c/busses/i2c-stm32f7.c

126

#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)

drivers/i2c/busses/i2c-stm32f7.c

63

#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)

drivers/i2c/busses/i2c-stm32f7.c

88

#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)

drivers/i2c/busses/i2c-stm32f7.c

96

#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)

drivers/i2c/busses/i2c-stm32f7.c

99

#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)

drivers/i2c/busses/i2c-tegra.c

112

#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)

drivers/i2c/busses/i2c-tegra.c

113

#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)

drivers/i2c/busses/i2c-tegra.c

115

#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)

drivers/i2c/busses/i2c-tegra.c

116

#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)

drivers/i2c/busses/i2c-tegra.c

117

#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)

drivers/i2c/busses/i2c-tegra.c

118

#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)

drivers/i2c/busses/i2c-tegra.c

121

#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)

drivers/i2c/busses/i2c-tegra.c

122

#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)

drivers/i2c/busses/i2c-tegra.c

124

#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)

drivers/i2c/busses/i2c-tegra.c

125

#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)

drivers/i2c/busses/i2c-tegra.c

126

#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)

drivers/i2c/busses/i2c-tegra.c

135

#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)

drivers/i2c/busses/i2c-tegra.c

136

#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)

drivers/i2c/busses/i2c-tegra.c

141

#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)

drivers/i2c/busses/i2c-tegra.c

142

#define I2C_SW_MUTEX_GRANT GENMASK(7, 4)

drivers/i2c/busses/i2c-tegra.c

34

#define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)

drivers/i2c/busses/i2c-tegra.c

54

#define I2C_FIFO_STATUS_TX GENMASK(7, 4)

drivers/i2c/busses/i2c-tegra.c

55

#define I2C_FIFO_STATUS_RX GENMASK(3, 0)

drivers/i2c/busses/i2c-tegra.c

65

#define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)

drivers/i2c/busses/i2c-tegra.c

66

#define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)

drivers/i2c/busses/i2c-tegra.c

82

#define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)

drivers/i2c/busses/i2c-tegra.c

83

#define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)

drivers/i2c/busses/i2c-tegra.c

84

#define PACKET_HEADER0_CONT_ID GENMASK(15, 12)

drivers/i2c/busses/i2c-tegra.c

85

#define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)

drivers/i2c/busses/i2c-tegra.c

98

#define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)

drivers/i2c/busses/i2c-viai2c-common.h

20

#define VIAI2C_CR_END_MASK GENMASK(2, 1)

drivers/i2c/busses/i2c-viai2c-common.h

27

#define VIAI2C_TCR_ADDR_MASK GENMASK(6, 0)

drivers/i2c/busses/i2c-viai2c-common.h

40

#define VIAI2C_ISR_MASK_ALL GENMASK(2, 0)

drivers/i2c/busses/i2c-viai2c-common.h

45

#define VIAI2C_IMR_ENABLE_ALL GENMASK(2, 0)

drivers/i2c/busses/i2c-viai2c-zhaoxin.c

28

#define ZXI2C_HCR_RST_FIFO GENMASK(1, 0)

drivers/i2c/i2c-slave-eeprom.c

40

#define I2C_SLAVE_BYTELEN GENMASK(15, 0)

drivers/i3c/master/adi-i3c-master.c

31

#define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x))

drivers/i3c/master/adi-i3c-master.c

32

#define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x))

drivers/i3c/master/adi-i3c-master.c

33

#define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x))

drivers/i3c/master/adi-i3c-master.c

45

#define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l))

drivers/i3c/master/adi-i3c-master.c

46

#define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a))

drivers/i3c/master/adi-i3c-master.c

48

#define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id))

drivers/i3c/master/adi-i3c-master.c

57

#define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x))

drivers/i3c/master/adi-i3c-master.c

58

#define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x))

drivers/i3c/master/adi-i3c-master.c

69

#define REG_OPS_PP_SG_MASK GENMASK(6, 5)

drivers/i3c/master/adi-i3c-master.c

705

da = FIELD_GET(GENMASK(23, 17), raw);

drivers/i3c/master/adi-i3c-master.c

706

mdb = FIELD_GET(GENMASK(15, 8), raw);

drivers/i3c/master/adi-i3c-master.c

79

#define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x))

drivers/i3c/master/adi-i3c-master.c

81

#define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x))

drivers/i3c/master/adi-i3c-master.c

975

master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1);

drivers/i3c/master/ast2600-i3c-master.c

20

#define AST2600_I3CG_REG0_SDA_PULLUP_EN_MASK GENMASK(29, 28)

drivers/i3c/master/ast2600-i3c-master.c

27

#define AST2600_I3CG_REG1_ACT_MODE_MASK GENMASK(3, 2)

drivers/i3c/master/ast2600-i3c-master.c

29

#define AST2600_I3CG_REG1_PENDING_INT_MASK GENMASK(7, 4)

drivers/i3c/master/ast2600-i3c-master.c

31

#define AST2600_I3CG_REG1_SA_MASK GENMASK(14, 8)

drivers/i3c/master/ast2600-i3c-master.c

34

#define AST2600_I3CG_REG1_INST_ID_MASK GENMASK(19, 16)

drivers/i3c/master/dw-i3c-master.c

103

#define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)

drivers/i3c/master/dw-i3c-master.c

108

#define IBI_REQ_REJECT_ALL GENMASK(31, 0)

drivers/i3c/master/dw-i3c-master.c

154

#define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)

drivers/i3c/master/dw-i3c-master.c

155

#define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)

drivers/i3c/master/dw-i3c-master.c

156

#define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8)

drivers/i3c/master/dw-i3c-master.c

157

#define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

160

#define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

1646

master->free_pos = GENMASK(master->maxdevs - 1, 0);

drivers/i3c/master/dw-i3c-master.c

165

#define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)

drivers/i3c/master/dw-i3c-master.c

166

#define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

180

#define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))

drivers/i3c/master/dw-i3c-master.c

181

#define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

185

#define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))

drivers/i3c/master/dw-i3c-master.c

186

#define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))

drivers/i3c/master/dw-i3c-master.c

189

#define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))

drivers/i3c/master/dw-i3c-master.c

190

#define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))

drivers/i3c/master/dw-i3c-master.c

193

#define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24))

drivers/i3c/master/dw-i3c-master.c

194

#define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16))

drivers/i3c/master/dw-i3c-master.c

195

#define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8))

drivers/i3c/master/dw-i3c-master.c

196

#define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

200

#define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0))

drivers/i3c/master/dw-i3c-master.c

208

#define DYN_ADDR_LO_MASK GENMASK(4, 0)

drivers/i3c/master/dw-i3c-master.c

209

#define DYN_ADDR_HI_MASK GENMASK(6, 5)

drivers/i3c/master/dw-i3c-master.c

213

#define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29)

drivers/i3c/master/dw-i3c-master.c

214

#define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16)

drivers/i3c/master/dw-i3c-master.c

215

#define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0)

drivers/i3c/master/dw-i3c-master.c

356

if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))

drivers/i3c/master/dw-i3c-master.c

38

#define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16))

drivers/i3c/master/dw-i3c-master.c

46

#define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21))

drivers/i3c/master/dw-i3c-master.c

47

#define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16))

drivers/i3c/master/dw-i3c-master.c

49

#define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7))

drivers/i3c/master/dw-i3c-master.c

50

#define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3))

drivers/i3c/master/dw-i3c-master.c

52

#define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16))

drivers/i3c/master/dw-i3c-master.c

56

#define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))

drivers/i3c/master/dw-i3c-master.c

57

#define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))

drivers/i3c/master/dw-i3c-master.c

58

#define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))

drivers/i3c/master/dw-i3c-master.c

64

#define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21))

drivers/i3c/master/dw-i3c-master.c

68

#define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)

drivers/i3c/master/dw-i3c-master.c

78

#define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24)

drivers/i3c/master/dw-i3c-master.c

79

#define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0))

drivers/i3c/master/dw-i3c-master.c

83

#define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8)

drivers/i3c/master/dw-i3c-master.c

84

#define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/dw-i3c-master.c

904

newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);

drivers/i3c/master/dw-i3c-master.c

95

#define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24)

drivers/i3c/master/dw-i3c-master.c

97

#define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16)

drivers/i3c/master/dw-i3c-master.c

99

#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)

drivers/i3c/master/i3c-master-cdns.c

144

#define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)

drivers/i3c/master/i3c-master-cdns.c

145

#define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)

drivers/i3c/master/i3c-master-cdns.c

148

#define CMDR_CMDID(x) ((x) & GENMASK(7, 0))

drivers/i3c/master/i3c-master-cdns.c

152

#define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)

drivers/i3c/master/i3c-master-cdns.c

154

#define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)

drivers/i3c/master/i3c-master-cdns.c

158

#define IBIR_TYPE(x) ((x) & GENMASK(1, 0))

drivers/i3c/master/i3c-master-cdns.c

1601

master->free_rr_slots = GENMASK(master->maxdevs, 1);

drivers/i3c/master/i3c-master-cdns.c

188

#define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)

drivers/i3c/master/i3c-master-cdns.c

189

#define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))

drivers/i3c/master/i3c-master-cdns.c

192

#define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)

drivers/i3c/master/i3c-master-cdns.c

197

#define SLV_STATUS1_DA(s) (((s) & GENMASK(15, 9)) >> 9)

drivers/i3c/master/i3c-master-cdns.c

281

#define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)

drivers/i3c/master/i3c-master-cdns.c

284

#define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)

drivers/i3c/master/i3c-master-cdns.c

291

#define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))

drivers/i3c/master/i3c-master-cdns.c

292

#define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \

drivers/i3c/master/i3c-master-cdns.c

293

(((a) & GENMASK(9, 7)) << 6))

drivers/i3c/master/i3c-master-cdns.c

294

#define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \

drivers/i3c/master/i3c-master-cdns.c

295

(((x) >> 6) & GENMASK(9, 7)))

drivers/i3c/master/i3c-master-cdns.c

309

#define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))

drivers/i3c/master/i3c-master-cdns.c

316

#define SIR_MAP_PL_MAX GENMASK(4, 0)

drivers/i3c/master/i3c-master-cdns.c

32

#define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))

drivers/i3c/master/i3c-master-cdns.c

322

(((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))

drivers/i3c/master/i3c-master-cdns.c

326

(((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))

drivers/i3c/master/i3c-master-cdns.c

344

#define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))

drivers/i3c/master/i3c-master-cdns.c

348

#define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))

drivers/i3c/master/i3c-master-cdns.c

38

#define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)

drivers/i3c/master/i3c-master-cdns.c

39

#define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)

drivers/i3c/master/i3c-master-cdns.c

40

#define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))

drivers/i3c/master/i3c-master-cdns.c

43

#define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))

drivers/i3c/master/i3c-master-cdns.c

46

#define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)

drivers/i3c/master/i3c-master-cdns.c

47

#define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))

drivers/i3c/master/i3c-master-cdns.c

48

#define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))

drivers/i3c/master/i3c-master-cdns.c

49

#define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))

drivers/i3c/master/i3c-master-cdns.c

50

#define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))

drivers/i3c/master/i3c-master-cdns.c

51

#define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))

drivers/i3c/master/i3c-master-cdns.c

52

#define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))

drivers/i3c/master/i3c-master-cdns.c

55

#define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)

drivers/i3c/master/i3c-master-cdns.c

56

#define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)

drivers/i3c/master/i3c-master-cdns.c

57

#define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)

drivers/i3c/master/i3c-master-cdns.c

58

#define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))

drivers/i3c/master/i3c-master-cdns.c

65

#define CTRL_THD_DELAY(x) (((x) << 24) & GENMASK(25, 24))

drivers/i3c/master/i3c-master-cdns.c

75

#define CTRL_BUS_MODE_MASK GENMASK(1, 0)

drivers/i3c/master/i3c-master-cdns.c

81

#define PRESCL_CTRL0_I3C_MAX GENMASK(9, 0)

drivers/i3c/master/i3c-master-cdns.c

82

#define PRESCL_CTRL0_I2C_MAX GENMASK(15, 0)

drivers/i3c/master/i3c-master-cdns.c

85

#define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)

drivers/i3c/master/i3c-master-cdns.c

87

#define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)

drivers/i3c/master/i3c-master-cdns.c

875

ret |= (addr & GENMASK(6, 0)) << 1;

drivers/i3c/master/i3c-master-cdns.c

878

ret |= (addr & GENMASK(9, 7)) << 6;

drivers/i3c/master/mipi-i3c-hci/cmd.h

25

#define RESP_STATUS(resp) FIELD_GET(GENMASK(31, 28), resp)

drivers/i3c/master/mipi-i3c-hci/cmd.h

26

#define RESP_TID(resp) FIELD_GET(GENMASK(27, 24), resp)

drivers/i3c/master/mipi-i3c-hci/cmd.h

27

#define RESP_DATA_LENGTH(resp) FIELD_GET(GENMASK(21, 0), resp)

drivers/i3c/master/mipi-i3c-hci/cmd.h

29

#define RESP_ERR_FIELD GENMASK(31, 28)

drivers/i3c/master/mipi-i3c-hci/core.c

100

#define PIO_REGS_OFFSET GENMASK(15, 0) /* PIO Offset */

drivers/i3c/master/mipi-i3c-hci/core.c

103

#define EXT_CAPS_OFFSET GENMASK(15, 0)

drivers/i3c/master/mipi-i3c-hci/core.c

45

#define MASTER_DYNAMIC_ADDR(v) FIELD_PREP(GENMASK(22, 16), v)

drivers/i3c/master/mipi-i3c-hci/core.c

51

#define HC_CAP_MAX_DATA_LENGTH GENMASK(24, 22)

drivers/i3c/master/mipi-i3c-hci/core.c

52

#define HC_CAP_CMD_SIZE GENMASK(21, 20)

drivers/i3c/master/mipi-i3c-hci/core.c

66

#define BUS_RESET_TYPE GENMASK(30, 29)

drivers/i3c/master/mipi-i3c-hci/core.c

700

reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));

drivers/i3c/master/mipi-i3c-hci/core.c

86

#define DAT_ENTRY_SIZE GENMASK(31, 28)

drivers/i3c/master/mipi-i3c-hci/core.c

87

#define DAT_TABLE_SIZE GENMASK(18, 12)

drivers/i3c/master/mipi-i3c-hci/core.c

88

#define DAT_TABLE_OFFSET GENMASK(11, 0)

drivers/i3c/master/mipi-i3c-hci/core.c

91

#define DCT_ENTRY_SIZE GENMASK(31, 28)

drivers/i3c/master/mipi-i3c-hci/core.c

92

#define DCT_TABLE_INDEX GENMASK(23, 19)

drivers/i3c/master/mipi-i3c-hci/core.c

93

#define DCT_TABLE_SIZE GENMASK(18, 12)

drivers/i3c/master/mipi-i3c-hci/core.c

94

#define DCT_TABLE_OFFSET GENMASK(11, 0)

drivers/i3c/master/mipi-i3c-hci/core.c

97

#define RING_HEADERS_OFFSET GENMASK(15, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

100

#define RING_OP2_CR_DEQ_PTR GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

116

#define RING_SG_LIST_SIZE GENMASK(15, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

124

#define DATA_BUF_BLOCK_SIZE GENMASK(15, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

44

#define PREAMBLE_SIZE GENMASK(31, 24) /* Preamble Section Size */

drivers/i3c/master/mipi-i3c-hci/dma.c

45

#define HEADER_SIZE GENMASK(23, 16) /* Ring Header Size */

drivers/i3c/master/mipi-i3c-hci/dma.c

46

#define MAX_HEADER_COUNT_CAP GENMASK(7, 4) /* HC Max Header Count */

drivers/i3c/master/mipi-i3c-hci/dma.c

47

#define MAX_HEADER_COUNT GENMASK(3, 0) /* Driver Max Header Count */

drivers/i3c/master/mipi-i3c-hci/dma.c

59

#define CR_XFER_STRUCT_SIZE GENMASK(31, 24)

drivers/i3c/master/mipi-i3c-hci/dma.c

60

#define CR_RESP_STRUCT_SIZE GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/dma.c

61

#define CR_RING_SIZE GENMASK(8, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

64

#define IBI_STATUS_STRUCT_SIZE GENMASK(31, 24)

drivers/i3c/master/mipi-i3c-hci/dma.c

65

#define IBI_STATUS_RING_SIZE GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/dma.c

66

#define IBI_DATA_CHUNK_SIZE GENMASK(12, 10)

drivers/i3c/master/mipi-i3c-hci/dma.c

67

#define IBI_DATA_CHUNK_COUNT GENMASK(9, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

94

#define RING_OP1_IBI_DEQ_PTR GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/dma.c

95

#define RING_OP1_CR_SW_DEQ_PTR GENMASK(15, 8)

drivers/i3c/master/mipi-i3c-hci/dma.c

96

#define RING_OP1_CR_ENQ_PTR GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/dma.c

99

#define RING_OP2_IBI_ENQ_PTR GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

119

unsigned int max_count = FIELD_GET(GENMASK(3, 0), autocmd_ext_caps);

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

121

unsigned int count = FIELD_GET(GENMASK(3, 0), autocmd_ext_config);

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

20

#define CAP_HEADER_LENGTH GENMASK(23, 8)

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

21

#define CAP_HEADER_ID GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

47

unsigned int operation_mode = FIELD_GET(GENMASK(5, 4), master_config);

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

61

unsigned int count = FIELD_GET(GENMASK(3, 0), bus_instance);

drivers/i3c/master/mipi-i3c-hci/hci.h

16

#define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0)

drivers/i3c/master/mipi-i3c-hci/hci.h

17

#define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32)

drivers/i3c/master/mipi-i3c-hci/hci.h

18

#define W2_MASK(h, l) GENMASK((h) - 64, (l) - 64)

drivers/i3c/master/mipi-i3c-hci/hci.h

19

#define W3_MASK(h, l) GENMASK((h) - 96, (l) - 96)

drivers/i3c/master/mipi-i3c-hci/ibi.h

19

#define IBI_HW_CONTEXT GENMASK(28, 26)

drivers/i3c/master/mipi-i3c-hci/ibi.h

22

#define IBI_CHUNKS GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/ibi.h

23

#define IBI_ID GENMASK(15, 8)

drivers/i3c/master/mipi-i3c-hci/ibi.h

24

#define IBI_TARGET_ADDR GENMASK(15, 9)

drivers/i3c/master/mipi-i3c-hci/ibi.h

26

#define IBI_DATA_LENGTH GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

55

#define INTEL_LTR_SCALE_MASK GENMASK(11, 10)

drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

58

#define INTEL_LTR_VALUE_MASK GENMASK(9, 0)

drivers/i3c/master/mipi-i3c-hci/pio.c

31

#define QUEUE_IBI_STATUS_THLD GENMASK(31, 24)

drivers/i3c/master/mipi-i3c-hci/pio.c

32

#define QUEUE_IBI_DATA_THLD GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/pio.c

33

#define QUEUE_RESP_BUF_THLD GENMASK(15, 8)

drivers/i3c/master/mipi-i3c-hci/pio.c

34

#define QUEUE_CMD_EMPTY_BUF_THLD GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/pio.c

37

#define DATA_RX_START_THLD GENMASK(26, 24)

drivers/i3c/master/mipi-i3c-hci/pio.c

38

#define DATA_TX_START_THLD GENMASK(18, 16)

drivers/i3c/master/mipi-i3c-hci/pio.c

39

#define DATA_RX_BUF_THLD GENMASK(10, 8)

drivers/i3c/master/mipi-i3c-hci/pio.c

40

#define DATA_TX_BUF_THLD GENMASK(2, 0)

drivers/i3c/master/mipi-i3c-hci/pio.c

43

#define TX_DATA_BUFFER_SIZE GENMASK(31, 24)

drivers/i3c/master/mipi-i3c-hci/pio.c

44

#define RX_DATA_BUFFER_SIZE GENMASK(23, 16)

drivers/i3c/master/mipi-i3c-hci/pio.c

45

#define IBI_STATUS_SIZE GENMASK(15, 8)

drivers/i3c/master/mipi-i3c-hci/pio.c

46

#define CR_QUEUE_SIZE GENMASK(7, 0)

drivers/i3c/master/mipi-i3c-hci/pio.c

76

#define CUR_IBI_Q_LEVEL GENMASK(28, 20)

drivers/i3c/master/mipi-i3c-hci/pio.c

77

#define CUR_RESP_Q_LEVEL GENMASK(18, 10)

drivers/i3c/master/mipi-i3c-hci/pio.c

78

#define CUR_CMD_Q_EMPTY_LEVEL GENMASK(8, 0)

drivers/i3c/master/mipi-i3c-hci/pio.c

81

#define CUR_RX_BUF_LVL GENMASK(26, 16)

drivers/i3c/master/mipi-i3c-hci/pio.c

82

#define CUR_TX_BUF_LVL GENMASK(10, 0)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

31

#define XFERMODE_VALID_XFER_ADD_FUNC GENMASK(21, 16)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

32

#define XFERMODE_ML_DATA_XFER_CODING GENMASK(15, 11)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

33

#define XFERMODE_ML_ADDL_LANES GENMASK(10, 8)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

35

#define XFERMODE_MODE GENMASK(3, 0)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

75

#define XFERRATE_MODE_ID GENMASK(31, 28)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

76

#define XFERRATE_RATE_ID GENMASK(22, 20)

drivers/i3c/master/mipi-i3c-hci/xfer_mode_rate.h

77

#define XFERRATE_ACTUAL_RATE_KHZ GENMASK(19, 0)

drivers/i3c/master/renesas-i3c.c

101

#define NCMDQP_DEV_INDEX(x) FIELD_PREP(GENMASK(20, 16), x)

drivers/i3c/master/renesas-i3c.c

102

#define NCMDQP_BYTE_CNT(x) FIELD_PREP(GENMASK(25, 23), x)

drivers/i3c/master/renesas-i3c.c

103

#define NCMDQP_DEV_COUNT(x) FIELD_PREP(GENMASK(29, 26), x)

drivers/i3c/master/renesas-i3c.c

104

#define NCMDQP_MODE(x) FIELD_PREP(GENMASK(28, 26), x)

drivers/i3c/master/renesas-i3c.c

105

#define NCMDQP_RNW(x) FIELD_PREP(GENMASK(29, 29), x)

drivers/i3c/master/renesas-i3c.c

108

#define NCMDQP_DATA_LENGTH(x) FIELD_PREP(GENMASK(31, 16), x)

drivers/i3c/master/renesas-i3c.c

121

#define NRSPQP_DATA_LEN(x) FIELD_GET(GENMASK(15, 0), x)

drivers/i3c/master/renesas-i3c.c

122

#define NRSPQP_ERR_STATUS(x) FIELD_GET(GENMASK(31, 28), x)

drivers/i3c/master/renesas-i3c.c

128

#define NQTHCTL_CMDQTH(x) FIELD_PREP(GENMASK(1, 0), x)

drivers/i3c/master/renesas-i3c.c

129

#define NQTHCTL_IBIDSSZ(x) FIELD_PREP(GENMASK(23, 16), x)

drivers/i3c/master/renesas-i3c.c

1369

i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0);

drivers/i3c/master/renesas-i3c.c

192

#define DATBAS_DVSTAD(x) FIELD_PREP(GENMASK(6, 0), x)

drivers/i3c/master/renesas-i3c.c

193

#define DATBAS_DVDYAD(x) FIELD_PREP(GENMASK(23, 16), x)

drivers/i3c/master/renesas-i3c.c

196

#define NDBSTLV0_RDBLV(x) FIELD_GET(GENMASK(15, 8), x)

drivers/i3c/master/renesas-i3c.c

325

if (!(i3c->free_pos & GENMASK(i3c->maxdevs - 1, 0)))

drivers/i3c/master/renesas-i3c.c

38

#define MSDVAD_MDYAD(x) FIELD_PREP(GENMASK(21, 16), x)

drivers/i3c/master/renesas-i3c.c

55

#define REFCKCTL_IREFCKS(x) FIELD_PREP(GENMASK(2, 0), x)

drivers/i3c/master/renesas-i3c.c

58

#define STDBR_SBRLO(cond, x) FIELD_PREP(GENMASK(7, 0), (x) >> (cond))

drivers/i3c/master/renesas-i3c.c

59

#define STDBR_SBRHO(cond, x) FIELD_PREP(GENMASK(15, 8), (x) >> (cond))

drivers/i3c/master/renesas-i3c.c

60

#define STDBR_SBRLP(x) FIELD_PREP(GENMASK(21, 16), x)

drivers/i3c/master/renesas-i3c.c

61

#define STDBR_SBRHP(x) FIELD_PREP(GENMASK(29, 24), x)

drivers/i3c/master/renesas-i3c.c

65

#define EXTBR_EBRLO(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/i3c/master/renesas-i3c.c

66

#define EXTBR_EBRHO(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/i3c/master/renesas-i3c.c

67

#define EXTBR_EBRLP(x) FIELD_PREP(GENMASK(21, 16), x)

drivers/i3c/master/renesas-i3c.c

68

#define EXTBR_EBRHP(x) FIELD_PREP(GENMASK(29, 24), x)

drivers/i3c/master/renesas-i3c.c

691

newdevs = GENMASK(i3c->maxdevs - cmd->rx_count - 1, 0);

drivers/i3c/master/renesas-i3c.c

71

#define BFRECDT_FRECYC(x) FIELD_PREP(GENMASK(8, 0), x)

drivers/i3c/master/renesas-i3c.c

74

#define BAVLCDT_AVLCYC(x) FIELD_PREP(GENMASK(8, 0), x)

drivers/i3c/master/renesas-i3c.c

77

#define BIDLCDT_IDLCYC(x) FIELD_PREP(GENMASK(17, 0), x)

drivers/i3c/master/renesas-i3c.c

95

#define NCMDQP_CMD_ATTR(x) FIELD_PREP(GENMASK(2, 0), x)

drivers/i3c/master/renesas-i3c.c

98

#define NCMDQP_TID(x) FIELD_PREP(GENMASK(6, 3), x)

drivers/i3c/master/renesas-i3c.c

99

#define NCMDQP_CMD(x) FIELD_PREP(GENMASK(14, 7), x)

drivers/i3c/master/svc-i3c-master.c

107

#define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4)

drivers/i3c/master/svc-i3c-master.c

109

#define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x))

drivers/i3c/master/svc-i3c-master.c

110

#define SVC_I3C_MDATACTRL_TXCOUNT(x) FIELD_GET(GENMASK(20, 16), (x))

drivers/i3c/master/svc-i3c-master.c

130

#define SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x))

drivers/i3c/master/svc-i3c-master.c

140

#define SVC_I3C_EVENT_IBI GENMASK(7, 0)

drivers/i3c/master/svc-i3c-master.c

2033

master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);

drivers/i3c/master/svc-i3c-master.c

28

#define SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x))

drivers/i3c/master/svc-i3c-master.c

30

#define SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x))

drivers/i3c/master/svc-i3c-master.c

31

#define SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x))

drivers/i3c/master/svc-i3c-master.c

32

#define SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x))

drivers/i3c/master/svc-i3c-master.c

34

#define SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x))

drivers/i3c/master/svc-i3c-master.c

35

#define SVC_I3C_MCONFIG_SKEW_MASK GENMASK(27, 25)

drivers/i3c/master/svc-i3c-master.c

36

#define SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x))

drivers/i3c/master/svc-i3c-master.c

39

#define SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0)

drivers/i3c/master/svc-i3c-master.c

54

#define SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6)

drivers/i3c/master/svc-i3c-master.c

58

#define SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x))

drivers/i3c/master/svc-i3c-master.c

59

#define SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x))

drivers/i3c/master/svc-i3c-master.c

62

#define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x))

drivers/i3c/master/svc-i3c-master.c

68

#define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x))

drivers/i3c/master/svc-i3c-master.c

719

ppbaud = FIELD_GET(GENMASK(11, 8), mconfig);

drivers/i3c/master/svc-i3c-master.c

722

mconfig &= ~GENMASK(24, 16);

drivers/i3c/master/svc-i3c-master.c

86

#define SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x))

drivers/i3c/master/svc-i3c-master.c

876

if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))

drivers/i3c/master/svc-i3c-master.c

89

#define SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \

drivers/iio/accel/adis16201.c

191

m = GENMASK(11, 0);

drivers/iio/accel/adis16201.c

194

m = GENMASK(8, 0);

drivers/iio/accel/adis16209.c

119

m = GENMASK(13, 0);

drivers/iio/accel/adxl313.h

40

#define ADXL313_RATE_MSK GENMASK(3, 0)

drivers/iio/accel/adxl313.h

44

#define ADXL313_POWER_CTL_INACT_MSK GENMASK(5, 4)

drivers/iio/accel/adxl313.h

48

#define ADXL313_RANGE_MSK GENMASK(1, 0)

drivers/iio/accel/adxl313.h

62

#define ADXL313_REG_FIFO_STATUS_ENTRIES_MSK GENMASK(5, 0)

drivers/iio/accel/adxl313.h

64

#define ADXL313_REG_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0)

drivers/iio/accel/adxl313.h

65

#define ADXL313_REG_FIFO_CTL_MODE_MSK GENMASK(7, 6)

drivers/iio/accel/adxl313_core.c

30

#define ADXL313_ACT_XYZ_EN GENMASK(6, 4)

drivers/iio/accel/adxl313_core.c

31

#define ADXL313_INACT_XYZ_EN GENMASK(2, 0)

drivers/iio/accel/adxl345.h

52

#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0)

drivers/iio/accel/adxl345.h

55

#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6)

drivers/iio/accel/adxl345.h

72

#define ADXL345_BW_RATE_MSK GENMASK(3, 0)

drivers/iio/accel/adxl345.h

76

#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0)

drivers/iio/accel/adxl345.h

83

#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0)

drivers/iio/accel/adxl345_core.c

36

#define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0)

drivers/iio/accel/adxl355_core.c

48

#define ADXL355_FILTER_ODR_MSK GENMASK(3, 0)

drivers/iio/accel/adxl355_core.c

49

#define ADXL355_FILTER_HPF_MSK GENMASK(6, 4)

drivers/iio/accel/adxl355_core.c

55

#define ADXL355_POWER_CTL_MODE_MSK GENMASK(1, 0)

drivers/iio/accel/adxl355_core.c

646

GENMASK(3, 0),

drivers/iio/accel/adxl367.c

31

#define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)

drivers/iio/accel/adxl367.c

38

#define ADXL367_DATA_MASK GENMASK(15, 2)

drivers/iio/accel/adxl367.c

45

#define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)

drivers/iio/accel/adxl367.c

52

#define ADXL367_THRESH_MAX GENMASK(12, 0)

drivers/iio/accel/adxl367.c

53

#define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)

drivers/iio/accel/adxl367.c

54

#define ADXL367_THRESH_H_MASK GENMASK(6, 0)

drivers/iio/accel/adxl367.c

55

#define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)

drivers/iio/accel/adxl367.c

56

#define ADXL367_THRESH_L_MASK GENMASK(7, 2)

drivers/iio/accel/adxl367.c

60

#define ADXL367_TIME_ACT_MAX GENMASK(7, 0)

drivers/iio/accel/adxl367.c

61

#define ADXL367_TIME_INACT_MAX GENMASK(15, 0)

drivers/iio/accel/adxl367.c

62

#define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)

drivers/iio/accel/adxl367.c

63

#define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)

drivers/iio/accel/adxl367.c

64

#define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)

drivers/iio/accel/adxl367.c

65

#define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)

drivers/iio/accel/adxl367.c

68

#define ADXL367_ACT_EN_MASK GENMASK(1, 0)

drivers/iio/accel/adxl367.c

69

#define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)

drivers/iio/accel/adxl367.c

72

#define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)

drivers/iio/accel/adxl367.c

73

#define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)

drivers/iio/accel/adxl367.c

81

#define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)

drivers/iio/accel/adxl367.c

82

#define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)

drivers/iio/accel/adxl367.c

90

#define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)

drivers/iio/accel/adxl367.c

93

#define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)

drivers/iio/accel/adxl367.c

96

#define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)

drivers/iio/accel/adxl372.c

101

#define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3)

drivers/iio/accel/adxl372.c

103

#define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1)

drivers/iio/accel/adxl372.c

141

#define ADXL372_THRESH_VAL_H_MSK GENMASK(10, 3)

drivers/iio/accel/adxl372.c

143

#define ADXL372_THRESH_VAL_L_MSK GENMASK(2, 0)

drivers/iio/accel/adxl372.c

344

ret = regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5),

drivers/iio/accel/adxl380.c

307

ret = regmap_write(st->regmap, reg + 1, th & GENMASK(7, 0));

drivers/iio/accel/adxl380.c

311

ret = regmap_update_bits(st->regmap, reg, GENMASK(2, 0), th >> 8);

drivers/iio/accel/adxl380.c

53

#define ADXL380_ACT_INACT_AXIS_EN_MSK GENMASK(2, 0)

drivers/iio/accel/adxl380.c

59

#define ADXL380_THRESH_MAX GENMASK(12, 0)

drivers/iio/accel/adxl380.c

60

#define ADXL380_TIME_MAX GENMASK(24, 0)

drivers/iio/accel/adxl380.c

64

#define ADXL380_FIFO_MODE_MSK GENMASK(5, 4)

drivers/iio/accel/adxl380.c

78

#define ADXL380_TAP_TIME_MAX GENMASK(7, 0)

drivers/iio/accel/adxl380.c

81

#define ADXL380_TAP_AXIS_MSK GENMASK(1, 0)

drivers/iio/accel/adxl380.c

89

#define ADXL380_FILTER_LPF_MODE_MSK GENMASK(5, 4)

drivers/iio/accel/adxl380.c

91

#define ADXL380_FILTER_HPF_CORNER_MSK GENMASK(2, 0)

drivers/iio/accel/adxl380.c

94

#define ADXL380_OP_MODE_RANGE_MSK GENMASK(7, 6)

drivers/iio/accel/adxl380.c

95

#define ADXL380_OP_MODE_MSK GENMASK(3, 0)

drivers/iio/accel/bma180.c

121

#define BMA250_RANGE_MASK GENMASK(3, 0) /* Range of accel values */

drivers/iio/accel/bma180.c

122

#define BMA250_BW_MASK GENMASK(4, 0) /* Accel bandwidth */

drivers/iio/accel/bma180.c

69

#define BMA023_RANGE_MASK GENMASK(4, 3) /* Range of accel values */

drivers/iio/accel/bma180.c

70

#define BMA023_BW_MASK GENMASK(2, 0) /* Accel bandwidth */

drivers/iio/accel/bma220.h

15

#define BMA220_WDT_MASK GENMASK(2, 1)

drivers/iio/accel/bma220_core.c

37

#define BMA220_HIGH_DUR_MSK GENMASK(5, 0)

drivers/iio/accel/bma220_core.c

38

#define BMA220_HIGH_HY_MSK GENMASK(7, 6)

drivers/iio/accel/bma220_core.c

40

#define BMA220_HIGH_TH_MSK GENMASK(3, 0)

drivers/iio/accel/bma220_core.c

41

#define BMA220_LOW_TH_MSK GENMASK(7, 4)

drivers/iio/accel/bma220_core.c

43

#define BMA220_LOW_DUR_MSK GENMASK(5, 0)

drivers/iio/accel/bma220_core.c

44

#define BMA220_LOW_HY_MSK GENMASK(7, 6)

drivers/iio/accel/bma220_core.c

46

#define BMA220_TT_DUR_MSK GENMASK(2, 0)

drivers/iio/accel/bma220_core.c

47

#define BMA220_TT_TH_MSK GENMASK(6, 3)

drivers/iio/accel/bma220_core.c

49

#define BMA220_SLOPE_DUR_MSK GENMASK(1, 0)

drivers/iio/accel/bma220_core.c

50

#define BMA220_SLOPE_TH_MSK GENMASK(5, 2)

drivers/iio/accel/bma220_core.c

73

#define BMA220_INT_LATCH_MSK GENMASK(6, 4)

drivers/iio/accel/bma220_core.c

77

#define BMA220_FILTER_MASK GENMASK(3, 0)

drivers/iio/accel/bma220_core.c

79

#define BMA220_RANGE_MASK GENMASK(1, 0)

drivers/iio/accel/bma400.h

112

#define BMA400_TWO_BITS_MASK GENMASK(1, 0)

drivers/iio/accel/bma400.h

121

#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0)

drivers/iio/accel/bma400.h

122

#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2)

drivers/iio/accel/bma400.h

156

#define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0)

drivers/iio/accel/bma400.h

159

#define BMA400_TAP_CONFIG1_TICSTH_MASK GENMASK(1, 0)

drivers/iio/accel/bma400.h

160

#define BMA400_TAP_CONFIG1_QUIET_MASK GENMASK(3, 2)

drivers/iio/accel/bma400.h

161

#define BMA400_TAP_CONFIG1_QUIETDT_MASK GENMASK(5, 4)

drivers/iio/accel/bma400.h

49

#define BMA400_INT_STAT1_STEP_INT_MASK GENMASK(9, 8)

drivers/iio/accel/bma400.h

77

#define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5)

drivers/iio/accel/bma400.h

80

#define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0)

drivers/iio/accel/bma400.h

87

#define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4)

drivers/iio/accel/bma400.h

88

#define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6)

drivers/iio/accel/bmi088-accel-core.c

79

#define BMIO088_ACCEL_ACC_RANGE_MSK GENMASK(1, 0)

drivers/iio/accel/fxls8962af-core.c

120

#define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5)

drivers/iio/accel/fxls8962af-core.c

47

#define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0)

drivers/iio/accel/fxls8962af-core.c

585

val_masked = val & GENMASK(11, 0);

drivers/iio/accel/fxls8962af-core.c

61

#define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1)

drivers/iio/accel/fxls8962af-core.c

67

#define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4)

drivers/iio/accel/fxls8962af-core.c

85

#define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0)

drivers/iio/accel/fxls8962af-core.c

87

#define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0)

drivers/iio/accel/fxls8962af-core.c

94

#define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5)

drivers/iio/accel/fxls8962af-core.c

97

#define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0)

drivers/iio/accel/kionix-kx022a.h

113

#define KX132_MASK_BUF_SMP_LVL GENMASK(9, 0)

drivers/iio/accel/kionix-kx022a.h

25

#define KX022A_MASK_GSEL GENMASK(4, 3)

drivers/iio/accel/kionix-kx022a.h

30

#define KX022A_GSEL_16 GENMASK(4, 3)

drivers/iio/accel/kionix-kx022a.h

50

#define KX022A_MASK_WM_TH GENMASK(6, 0)

drivers/iio/accel/kionix-kx022a.h

58

#define KX022A_MASK_ODR GENMASK(3, 0)

drivers/iio/accel/kionix-kx022a.h

92

#define KX132_GSEL_16 GENMASK(4, 3)

drivers/iio/accel/mma8452.c

45

#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)

drivers/iio/accel/mma8452.c

51

#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)

drivers/iio/accel/mma8452.c

72

#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)

drivers/iio/accel/mma8452.c

77

#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)

drivers/iio/accel/mma9551.c

32

#define MMA9551_TILT_ANG_THRESH_MASK GENMASK(3, 0)

drivers/iio/accel/mma9553.c

22

#define MMA9553_MASK_CONF_WORD GENMASK(15, 0)

drivers/iio/accel/mma9553.c

28

#define MMA9553_MASK_CONF_STEPLEN GENMASK(7, 0)

drivers/iio/accel/mma9553.c

31

#define MMA9553_MASK_CONF_HEIGHT GENMASK(15, 8)

drivers/iio/accel/mma9553.c

32

#define MMA9553_MASK_CONF_WEIGHT GENMASK(7, 0)

drivers/iio/accel/mma9553.c

35

#define MMA9553_MASK_CONF_FILTSTEP GENMASK(15, 8)

drivers/iio/accel/mma9553.c

37

#define MMA9553_MASK_CONF_FILTTIME GENMASK(6, 0)

drivers/iio/accel/mma9553.c

40

#define MMA9553_MASK_CONF_SPDPRD GENMASK(15, 8)

drivers/iio/accel/mma9553.c

41

#define MMA9553_MASK_CONF_STEPCOALESCE GENMASK(7, 0)

drivers/iio/accel/mma9553.c

44

#define MMA9553_MAX_ACTTHD GENMASK(15, 0)

drivers/iio/accel/mma9553.c

53

#define MMA9553_MASK_STATUS_ACTIVITY GENMASK(10, 8)

drivers/iio/accel/mma9553.c

54

#define MMA9553_MASK_STATUS_VERSION GENMASK(7, 0)

drivers/iio/accel/msa311.c

341

GENMASK(_field->msb, _field->lsb); \

drivers/iio/accel/mxc4005.c

42

#define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)

drivers/iio/accel/sca3000.c

29

#define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)

drivers/iio/accel/sca3000.c

30

#define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)

drivers/iio/accel/sca3000.c

747

GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/accel/sca3300.c

34

#define SCA3300_STATUS_MASK GENMASK(8, 0)

drivers/iio/accel/sca3300.c

43

#define SCA3300_MASK_RS_STATUS GENMASK(1, 0)

drivers/iio/accel/st_accel_core.c

1166

.mask = GENMASK(7, 4),

drivers/iio/accel/st_accel_core.c

1182

.mask = GENMASK(7, 4),

drivers/iio/accel/st_accel_core.c

1191

.mask = GENMASK(5, 3),

drivers/iio/accel/st_accel_core.c

1235

.mask = GENMASK(2, 0),

drivers/iio/accel/stk8312.c

42

#define STK8312_RNG_MASK GENMASK(7, 6)

drivers/iio/accel/stk8312.c

43

#define STK8312_SR_MASK GENMASK(2, 0)

drivers/iio/accel/stk8312.c

45

#define STK8312_ALL_CHANNEL_MASK GENMASK(2, 0)

drivers/iio/adc/88pm886-gpadc.c

164

ret = regmap_update_bits(gpadc->map, reg, GENMASK(3, 0), i);

drivers/iio/adc/ad4030.c

1072

GENMASK(1, 0),

drivers/iio/adc/ad4030.c

1080

GENMASK(3, 0),

drivers/iio/adc/ad4030.c

40

#define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3)

drivers/iio/adc/ad4030.c

52

#define AD4030_REG_AVG_MASK_AVG_VAL GENMASK(4, 0)

drivers/iio/adc/ad4030.c

71

#define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0)

drivers/iio/adc/ad4030.c

72

#define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6)

drivers/iio/adc/ad4062.c

40

#define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0)

drivers/iio/adc/ad4062.c

51

#define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0)

drivers/iio/adc/ad4062.c

57

#define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0)

drivers/iio/adc/ad4062.c

58

#define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4)

drivers/iio/adc/ad4062.c

60

#define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0)

drivers/iio/adc/ad4062.c

61

#define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4)

drivers/iio/adc/ad4062.c

63

#define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4)

drivers/iio/adc/ad4080.c

106

#define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4)

drivers/iio/adc/ad4080.c

107

#define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0)

drivers/iio/adc/ad4080.c

120

#define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0)

drivers/iio/adc/ad4080.c

123

#define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3)

drivers/iio/adc/ad4080.c

124

#define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0)

drivers/iio/adc/ad4080.c

75

#define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0)

drivers/iio/adc/ad4080.c

90

#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4)

drivers/iio/adc/ad4080.c

95

#define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4)

drivers/iio/adc/ad4130.c

101

#define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0)

drivers/iio/adc/ad4130.c

47

#define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2)

drivers/iio/adc/ad4130.c

48

#define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)

drivers/iio/adc/ad4130.c

55

#define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8)

drivers/iio/adc/ad4130.c

56

#define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4)

drivers/iio/adc/ad4130.c

57

#define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0)

drivers/iio/adc/ad4130.c

71

#define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20)

drivers/iio/adc/ad4130.c

72

#define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13)

drivers/iio/adc/ad4130.c

73

#define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8)

drivers/iio/adc/ad4130.c

74

#define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4)

drivers/iio/adc/ad4130.c

75

#define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0)

drivers/iio/adc/ad4130.c

78

#define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13)

drivers/iio/adc/ad4130.c

79

#define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10)

drivers/iio/adc/ad4130.c

80

#define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8)

drivers/iio/adc/ad4130.c

83

#define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4)

drivers/iio/adc/ad4130.c

84

#define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)

drivers/iio/adc/ad4130.c

87

#define AD4130_FILTER_MODE_MASK GENMASK(15, 12)

drivers/iio/adc/ad4130.c

88

#define AD4130_FILTER_SELECT_MASK GENMASK(10, 0)

drivers/iio/adc/ad4130.c

99

#define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16)

drivers/iio/adc/ad4134.c

55

#define AD4134_DATA_PACKET_CONFIG_FRAME_MASK GENMASK(5, 4)

drivers/iio/adc/ad4134.c

59

#define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0)

drivers/iio/adc/ad4170-4.c

102

#define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8)

drivers/iio/adc/ad4170-4.c

103

#define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0)

drivers/iio/adc/ad4170-4.c

106

#define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14)

drivers/iio/adc/ad4170-4.c

107

#define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8)

drivers/iio/adc/ad4170-4.c

110

#define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10)

drivers/iio/adc/ad4170-4.c

111

#define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8)

drivers/iio/adc/ad4170-4.c

112

#define AD4170_AFE_REF_SELECT_MSK GENMASK(6, 5)

drivers/iio/adc/ad4170-4.c

114

#define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0)

drivers/iio/adc/ad4170-4.c

117

#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)

drivers/iio/adc/ad4170-4.c

120

#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8)

drivers/iio/adc/ad4170-4.c

121

#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0)

drivers/iio/adc/ad4170-4.c

124

#define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0)

drivers/iio/adc/ad4170-4.c

125

#define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2)

drivers/iio/adc/ad4170-4.c

126

#define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4)

drivers/iio/adc/ad4170-4.c

127

#define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6)

drivers/iio/adc/ad4170-4.c

1388

rshift = precision_bits - bipolar + (pga & GENMASK(2, 0)) - lshift;

drivers/iio/adc/ad4170-4.c

85

#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4)

drivers/iio/adc/ad4170-4.c

88

#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0)

drivers/iio/adc/ad4170-4.c

92

#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)

drivers/iio/adc/ad4170-4.c

93

#define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0)

drivers/iio/adc/ad4170-4.c

99

#define AD4170_CHAN_SETUP_SETUP_MSK GENMASK(2, 0)

drivers/iio/adc/ad4695.c

64

#define AD4695_REG_REF_CTRL_VREF_SET GENMASK(4, 2)

drivers/iio/adc/ad4695.c

69

#define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS GENMASK(6, 0)

drivers/iio/adc/ad4695.c

80

#define AD4695_REG_CONFIG_IN_PAIR GENMASK(5, 4)

drivers/iio/adc/ad4695.c

82

#define AD4695_REG_CONFIG_IN_OSR_SET GENMASK(1, 0)

drivers/iio/adc/ad4695.c

89

#define AD4695_REG_AS_SLOT_INX GENMASK(3, 0)

drivers/iio/adc/ad4851.c

64

#define AD4851_PACKET_FORMAT_MASK GENMASK(1, 0)

drivers/iio/adc/ad4851.c

67

#define AD4851_OS_RATIO_MSK GENMASK(3, 0)

drivers/iio/adc/ad7091r8.c

17

#define AD7091R8_REG_ADDR_MSK GENMASK(15, 11)

drivers/iio/adc/ad7091r8.c

19

#define AD7091R8_REG_DATA_MSK GENMASK(9, 0)

drivers/iio/adc/ad7124.c

106

#define AD7124_FILTER_POST_FILTER GENMASK(19, 17)

drivers/iio/adc/ad7124.c

112

#define AD7124_FILTER_FS GENMASK(10, 0)

drivers/iio/adc/ad7124.c

54

#define AD7124_ADC_CONTROL_CLK_SEL GENMASK(1, 0)

drivers/iio/adc/ad7124.c

59

#define AD7124_ADC_CONTROL_MODE GENMASK(5, 2)

drivers/iio/adc/ad7124.c

689

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7124.c

69

#define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6)

drivers/iio/adc/ad7124.c

77

#define AD7124_ID_SILICON_REVISION GENMASK(3, 0)

drivers/iio/adc/ad7124.c

78

#define AD7124_ID_DEVICE_ID GENMASK(7, 4)

drivers/iio/adc/ad7124.c

84

#define AD7124_CHANNEL_SETUP GENMASK(14, 12)

drivers/iio/adc/ad7124.c

85

#define AD7124_CHANNEL_AINP GENMASK(9, 5)

drivers/iio/adc/ad7124.c

86

#define AD7124_CHANNEL_AINM GENMASK(4, 0)

drivers/iio/adc/ad7124.c

92

#define AD7124_CONFIG_IN_BUFF GENMASK(6, 5)

drivers/iio/adc/ad7124.c

95

#define AD7124_CONFIG_REF_SEL GENMASK(4, 3)

drivers/iio/adc/ad7124.c

96

#define AD7124_CONFIG_PGA GENMASK(2, 0)

drivers/iio/adc/ad7124.c

99

#define AD7124_FILTER_FILTER GENMASK(23, 21)

drivers/iio/adc/ad7173.c

131

#define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)

drivers/iio/adc/ad7173.c

132

#define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)

drivers/iio/adc/ad7173.c

134

#define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)

drivers/iio/adc/ad7173.c

154

#define AD7173_FILTER_SINC3_MAP_DIV GENMASK(14, 0)

drivers/iio/adc/ad7173.c

156

#define AD7173_FILTER_ENHFILT_MASK GENMASK(10, 8)

drivers/iio/adc/ad7173.c

158

#define AD7173_FILTER_ODR_MASK GENMASK(5, 0)

drivers/iio/adc/ad7173.c

62

#define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)

drivers/iio/adc/ad7173.c

63

#define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)

drivers/iio/adc/ad7173.c

64

#define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)

drivers/iio/adc/ad7173.c

899

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7173.c

916

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7173.c

933

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7173.c

94

#define AD7173_ID_MASK GENMASK(15, 4)

drivers/iio/adc/ad7173.c

98

#define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)

drivers/iio/adc/ad7173.c

99

#define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)

drivers/iio/adc/ad7192.c

102

#define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */

drivers/iio/adc/ad7192.c

107

#define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */

drivers/iio/adc/ad7192.c

153

#define AD7192_ID_MASK GENMASK(3, 0)

drivers/iio/adc/ad7192.c

367

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7192.c

381

.status_ch_mask = GENMASK(3, 0),

drivers/iio/adc/ad7192.c

52

#define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */

drivers/iio/adc/ad7192.c

65

#define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */

drivers/iio/adc/ad7192.c

67

#define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */

drivers/iio/adc/ad7192.c

68

#define AD7192_MODE_AVG_MASK GENMASK(17, 16)

drivers/iio/adc/ad7192.c

76

#define AD7192_MODE_RATE_MASK GENMASK(9, 0)

drivers/iio/adc/ad7280a.c

102

#define AD7280A_READ_ADDR_MSK GENMASK(7, 2)

drivers/iio/adc/ad7280a.c

106

#define AD7280A_TRANS_WRITE_DEVADDR_MSK GENMASK(31, 27)

drivers/iio/adc/ad7280a.c

107

#define AD7280A_TRANS_WRITE_ADDR_MSK GENMASK(26, 21)

drivers/iio/adc/ad7280a.c

108

#define AD7280A_TRANS_WRITE_VAL_MSK GENMASK(20, 13)

drivers/iio/adc/ad7280a.c

110

#define AD7280A_TRANS_WRITE_CRC_MSK GENMASK(10, 3)

drivers/iio/adc/ad7280a.c

114

#define AD7280A_TRANS_READ_DEVADDR_MSK GENMASK(31, 27)

drivers/iio/adc/ad7280a.c

115

#define AD7280A_TRANS_READ_CONV_CHANADDR_MSK GENMASK(26, 23)

drivers/iio/adc/ad7280a.c

116

#define AD7280A_TRANS_READ_CONV_DATA_MSK GENMASK(22, 11)

drivers/iio/adc/ad7280a.c

117

#define AD7280A_TRANS_READ_REG_REGADDR_MSK GENMASK(26, 21)

drivers/iio/adc/ad7280a.c

118

#define AD7280A_TRANS_READ_REG_DATA_MSK GENMASK(20, 13)

drivers/iio/adc/ad7280a.c

120

#define AD7280A_TRANS_READ_CRC_MSK GENMASK(9, 2)

drivers/iio/adc/ad7280a.c

44

#define AD7280A_CTRL_HB_CONV_INPUT_MSK GENMASK(7, 6)

drivers/iio/adc/ad7280a.c

49

#define AD7280A_CTRL_HB_CONV_RREAD_MSK GENMASK(5, 4)

drivers/iio/adc/ad7280a.c

57

#define AD7280A_CTRL_HB_CONV_AVG_MSK GENMASK(2, 1)

drivers/iio/adc/ad7280a.c

66

#define AD7280A_CTRL_LB_ACQ_TIME_MSK GENMASK(6, 5)

drivers/iio/adc/ad7280a.c

83

#define AD7280A_ALERT_REMOVE_MSK GENMASK(3, 0)

drivers/iio/adc/ad7280a.c

92

#define AD7280A_CELL_BALANCE_CHAN_BITMAP_MSK GENMASK(7, 2)

drivers/iio/adc/ad7280a.c

94

#define AD7280A_CB_TIMER_VAL_MSK GENMASK(7, 3)

drivers/iio/adc/ad7291.c

60

#define AD7291_VOLTAGE_MASK GENMASK(15, 8)

drivers/iio/adc/ad7291.c

66

#define AD7291_VALUE_MASK GENMASK(11, 0)

drivers/iio/adc/ad7292.c

36

#define AD7292_ADC_DATA_MASK GENMASK(15, 6)

drivers/iio/adc/ad7298.c

249

*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad7380.c

1408

GENMASK(scan_type->realbits - 1, 0);

drivers/iio/adc/ad7380.c

1415

GENMASK(scan_type->realbits - 1, 0);

drivers/iio/adc/ad7380.c

521

GENMASK(1, 0),

drivers/iio/adc/ad7380.c

526

GENMASK(3, 0),

drivers/iio/adc/ad7380.c

571

[AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0),

drivers/iio/adc/ad7380.c

572

[AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2),

drivers/iio/adc/ad7380.c

573

[AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0),

drivers/iio/adc/ad7380.c

578

[AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0),

drivers/iio/adc/ad7380.c

579

[AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4),

drivers/iio/adc/ad7380.c

580

[AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0),

drivers/iio/adc/ad7380.c

59

#define AD7380_REG_REGADDR GENMASK(14, 12)

drivers/iio/adc/ad7380.c

60

#define AD7380_REG_DATA GENMASK(11, 0)

drivers/iio/adc/ad7380.c

72

#define AD7380_CONFIG1_OSR GENMASK(8, 6)

drivers/iio/adc/ad7380.c

80

#define AD7380_CONFIG2_SDO2 GENMASK(9, 8)

drivers/iio/adc/ad7380.c

82

#define AD7380_CONFIG2_RESET GENMASK(7, 0)

drivers/iio/adc/ad7380.c

87

#define AD7380_ALERT_LOW_TH GENMASK(11, 0)

drivers/iio/adc/ad7380.c

88

#define AD7380_ALERT_HIGH_TH GENMASK(11, 0)

drivers/iio/adc/ad7476.c

146

GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad7606.c

704

*val &= GENMASK(realbits - 1, 0);

drivers/iio/adc/ad7606.c

843

values[0] = val & GENMASK(2, 0);

drivers/iio/adc/ad7606.h

14

#define AD7616_OS_MASK GENMASK(4, 2)

drivers/iio/adc/ad7606.h

37

#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1)))

drivers/iio/adc/ad7606.h

39

((GENMASK(3, 0) & (mode)) << (4 * ((ch) & 0x1)))

drivers/iio/adc/ad7606.h

44

#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0)

drivers/iio/adc/ad7768-1.c

100

#define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0)

drivers/iio/adc/ad7768-1.c

105

#define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0)

drivers/iio/adc/ad7768-1.c

108

#define AD7768_GPIO_WRITE_MSK GENMASK(3, 0)

drivers/iio/adc/ad7768-1.c

111

#define AD7768_GPIO_READ_MSK GENMASK(3, 0)

drivers/iio/adc/ad7768-1.c

604

regval = FIELD_PREP(GENMASK(12, 0), dec_rate);

drivers/iio/adc/ad7768-1.c

83

#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)

drivers/iio/adc/ad7768-1.c

85

#define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)

drivers/iio/adc/ad7768-1.c

90

#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)

drivers/iio/adc/ad7768-1.c

92

#define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)

drivers/iio/adc/ad7768-1.c

96

#define AD7768_CONV_MODE_MSK GENMASK(2, 0)

drivers/iio/adc/ad7779.c

109

#define AD7779_FREQ_MSB_MSK GENMASK(15, 8)

drivers/iio/adc/ad7779.c

110

#define AD7779_FREQ_LSB_MSK GENMASK(7, 0)

drivers/iio/adc/ad7779.c

111

#define AD7779_UPPER GENMASK(23, 16)

drivers/iio/adc/ad7779.c

112

#define AD7779_MID GENMASK(15, 8)

drivers/iio/adc/ad7779.c

113

#define AD7779_LOWER GENMASK(7, 0)

drivers/iio/adc/ad7779.c

115

#define AD7779_REG_MSK GENMASK(6, 0)

drivers/iio/adc/ad7779.c

81

#define AD7779_USRMOD_INIT_MSK GENMASK(6, 4)

drivers/iio/adc/ad7779.c

84

#define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6)

drivers/iio/adc/ad7779.c

86

#define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1)

drivers/iio/adc/ad7779.c

88

#define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6)

drivers/iio/adc/ad7780.c

41

#define AD7780_PATTERN_MASK GENMASK(1, 0)

drivers/iio/adc/ad7780.c

44

#define AD7170_PATTERN_MASK GENMASK(2, 0)

drivers/iio/adc/ad7887.c

163

*val &= GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad7944.c

370

*val &= GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad7944.c

623

scan_masks[0] = GENMASK(n_chain_dev - 1, 0);

drivers/iio/adc/ad7949.c

16

#define AD7949_CFG_MASK_TOTAL GENMASK(13, 0)

drivers/iio/adc/ad7949.c

173

*val = ad7949_adc->buffer & GENMASK(13, 0);

drivers/iio/adc/ad7949.c

22

#define AD7949_CFG_MASK_INCC GENMASK(12, 10)

drivers/iio/adc/ad7949.c

31

#define AD7949_CFG_MASK_INX GENMASK(9, 7)

drivers/iio/adc/ad7949.c

37

#define AD7949_CFG_MASK_REF GENMASK(5, 3)

drivers/iio/adc/ad7949.c

45

#define AD7949_CFG_MASK_SEQ GENMASK(2, 1)

drivers/iio/adc/ad799x.c

251

st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);

drivers/iio/adc/ad799x.c

306

GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad799x.c

465

if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))

drivers/iio/adc/ad799x.c

490

GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ad799x.c

70

#define AD7998_CYC_MASK GENMASK(2, 0)

drivers/iio/adc/ad9467.c

107

#define AD9434_REG_VREF_MASK GENMASK(4, 0)

drivers/iio/adc/ad9467.c

397

.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,

drivers/iio/adc/ad9467.c

414

.test_mask = GENMASK(AN877_ADC_TESTMODE_USER, AN877_ADC_TESTMODE_OFF),

drivers/iio/adc/ad9467.c

431

.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,

drivers/iio/adc/ad9467.c

448

.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,

drivers/iio/adc/ad9467.c

467

GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF),

drivers/iio/adc/ad9467.c

485

.test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY,

drivers/iio/adc/ad9467.c

503

.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,

drivers/iio/adc/ad9467.c

630

GENMASK(st->info->num_channels - 1, 0));

drivers/iio/adc/ad9467.c

76

#define AN877_ADC_OUTPUT_MODE_MASK GENMASK(1, 0)

drivers/iio/adc/ad9467.c

91

#define AD9211_REG_VREF_MASK GENMASK(4, 0)

drivers/iio/adc/ade9000.c

100

#define ADE9000_REG_ADDR_MASK GENMASK(15, 4)

drivers/iio/adc/ade9000.c

105

#define ADE9000_WF_MODE_MASK GENMASK(7, 6)

drivers/iio/adc/ade9000.c

106

#define ADE9000_WF_SRC_MASK GENMASK(9, 8)

drivers/iio/adc/ade9000.c

1253

ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, GENMASK(31, 0));

drivers/iio/adc/ade9000.c

1495

ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));

drivers/iio/adc/ade9000.c

1556

return regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));

drivers/iio/adc/ade9000.c

647

{ ADE9000_REG_STATUS0, GENMASK(31, 0) },

drivers/iio/adc/ade9000.c

648

{ ADE9000_REG_STATUS1, GENMASK(31, 0) },

drivers/iio/adc/adi-axi-adc.c

46

#define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8)

drivers/iio/adc/adi-axi-adc.c

52

#define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0)

drivers/iio/adc/adi-axi-adc.c

71

#define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4)

drivers/iio/adc/adi-axi-adc.c

79

#define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1)

drivers/iio/adc/adi-axi-adc.c

86

#define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16)

drivers/iio/adc/adi-axi-adc.c

89

#define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0)

drivers/iio/adc/adi-axi-adc.c

93

#define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0)

drivers/iio/adc/aspeed_adc.c

50

#define ASPEED_ADC_OP_MODE GENMASK(3, 1)

drivers/iio/adc/aspeed_adc.c

60

#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6)

drivers/iio/adc/aspeed_adc.c

631

.field = GENMASK(31, 28),

drivers/iio/adc/aspeed_adc.c

636

.field = GENMASK(3, 0),

drivers/iio/adc/aspeed_adc.c

641

.field = GENMASK(7, 4),

drivers/iio/adc/aspeed_adc.c

646

.field = GENMASK(3, 0),

drivers/iio/adc/aspeed_adc.c

651

.field = GENMASK(7, 4),

drivers/iio/adc/aspeed_adc.c

73

#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16)

drivers/iio/adc/at91-sama5d2_adc.c

159

#define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22)

drivers/iio/adc/at91-sama5d2_adc.c

179

#define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)

drivers/iio/adc/at91-sama5d2_adc.c

194

#define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)

drivers/iio/adc/at91-sama5d2_adc.c

198

#define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)

drivers/iio/adc/at91-sama5d2_adc.c

202

#define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)

drivers/iio/adc/at91-sama5d2_adc.c

221

#define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)

drivers/iio/adc/at91-sama5d2_adc.c

233

#define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)

drivers/iio/adc/at91-sama5d2_adc.c

326

#define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)

drivers/iio/adc/at91-sama5d2_adc.c

720

.osr_mask = GENMASK(17, 16),

drivers/iio/adc/at91-sama5d2_adc.c

742

.osr_mask = GENMASK(18, 16),

drivers/iio/adc/at91-sama5d2_adc.c

79

#define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)

drivers/iio/adc/at91-sama5d2_adc.c

790

return mask & GENMASK(st->soc_info.platform->nr_channels, 0);

drivers/iio/adc/at91-sama5d2_adc.c

82

#define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)

drivers/iio/adc/at91_adc.c

378

if (status & GENMASK(st->num_channels - 1, 0))

drivers/iio/adc/at91_adc.c

445

if (status & GENMASK(st->num_channels - 1, 0))

drivers/iio/adc/axp20x_adc.c

26

#define AXP192_ADC_EN1_MASK GENMASK(7, 0)

drivers/iio/adc/axp20x_adc.c

27

#define AXP192_ADC_EN2_MASK (GENMASK(3, 0) | BIT(7))

drivers/iio/adc/axp20x_adc.c

29

#define AXP20X_ADC_EN1_MASK GENMASK(7, 0)

drivers/iio/adc/axp20x_adc.c

30

#define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7))

drivers/iio/adc/axp20x_adc.c

32

#define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0))

drivers/iio/adc/axp20x_adc.c

34

#define AXP717_ADC_EN1_MASK GENMASK(7, 0)

drivers/iio/adc/axp20x_adc.c

44

#define AXP20X_ADC_RATE_MASK GENMASK(7, 6)

drivers/iio/adc/axp20x_adc.c

54

#define AXP717_ADC_DATA_MASK GENMASK(13, 0)

drivers/iio/adc/axp20x_adc.c

56

#define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4)

drivers/iio/adc/axp288_adc.c

30

#define AXP288_ADC_TS_BIAS_MASK GENMASK(5, 4)

drivers/iio/adc/axp288_adc.c

35

#define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0)

drivers/iio/adc/berlin2-adc.c

32

#define BERLIN2_SM_CTRL_ADC_SEL_MASK GENMASK(8, 5)

drivers/iio/adc/berlin2-adc.c

38

#define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK GENMASK(11, 10)

drivers/iio/adc/berlin2-adc.c

55

#define BERLIN2_SM_ADC_MASK GENMASK(9, 0)

drivers/iio/adc/berlin2-adc.c

58

#define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK GENMASK(15, 0)

drivers/iio/adc/berlin2-adc.c

60

#define BERLIN2_SM_ADC_STATUS_INT_EN_MASK GENMASK(31, 16)

drivers/iio/adc/berlin2-adc.c

65

#define BERLIN2_SM_TSEN_MASK GENMASK(9, 0)

drivers/iio/adc/berlin2-adc.c

72

#define BERLIN2_SM_TSEN_CTRL_TRIM_MASK GENMASK(25, 22)

drivers/iio/adc/cc10001_adc.c

331

channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);

drivers/iio/adc/cc10001_adc.c

39

#define CC10001_ADC_DATA_MASK GENMASK(9, 0)

drivers/iio/adc/cc10001_adc.c

41

#define CC10001_ADC_CH_MASK GENMASK(2, 0)

drivers/iio/adc/imx8qxp-adc.c

47

#define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0)

drivers/iio/adc/imx8qxp-adc.c

51

#define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24)

drivers/iio/adc/imx8qxp-adc.c

52

#define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16)

drivers/iio/adc/imx8qxp-adc.c

53

#define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8)

drivers/iio/adc/imx8qxp-adc.c

54

#define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0)

drivers/iio/adc/imx8qxp-adc.c

55

#define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8)

drivers/iio/adc/imx8qxp-adc.c

59

#define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0)

drivers/iio/adc/imx8qxp-adc.c

60

#define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24)

drivers/iio/adc/imx8qxp-adc.c

61

#define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16)

drivers/iio/adc/imx8qxp-adc.c

62

#define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12)

drivers/iio/adc/imx8qxp-adc.c

64

#define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7)

drivers/iio/adc/imx8qxp-adc.c

65

#define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0)

drivers/iio/adc/imx8qxp-adc.c

67

#define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16)

drivers/iio/adc/imx8qxp-adc.c

68

#define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6)

drivers/iio/adc/imx8qxp-adc.c

69

#define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4)

drivers/iio/adc/imx8qxp-adc.c

70

#define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0)

drivers/iio/adc/imx8qxp-adc.c

71

#define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16)

drivers/iio/adc/imx8qxp-adc.c

72

#define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0)

drivers/iio/adc/imx8qxp-adc.c

73

#define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3)

drivers/iio/adc/imx8qxp-adc.c

76

#define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0)

drivers/iio/adc/imx93_adc.c

51

#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0)

drivers/iio/adc/imx93_adc.c

60

#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0)

drivers/iio/adc/ina2xx-adc.c

66

#define INA2XX_MODE_MASK GENMASK(3, 0)

drivers/iio/adc/ina2xx-adc.c

69

#define INA219_PGA_MASK GENMASK(12, 11)

drivers/iio/adc/ina2xx-adc.c

77

#define INA226_AVG_MASK GENMASK(11, 9)

drivers/iio/adc/ina2xx-adc.c

81

#define INA219_ITB_MASK GENMASK(10, 7)

drivers/iio/adc/ina2xx-adc.c

83

#define INA226_ITB_MASK GENMASK(8, 6)

drivers/iio/adc/ina2xx-adc.c

87

#define INA219_ITS_MASK GENMASK(6, 3)

drivers/iio/adc/ina2xx-adc.c

89

#define INA226_ITS_MASK GENMASK(5, 3)

drivers/iio/adc/ingenic-adc.c

43

#define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))

drivers/iio/adc/intel_dc_ti_adc.c

195

*val = be16_to_cpu(buf) & GENMASK(9, 0);

drivers/iio/adc/intel_dc_ti_adc.c

30

#define DC_TI_ADC_CH_SEL GENMASK(2, 1)

drivers/iio/adc/intel_dc_ti_adc.c

35

#define DC_TI_VBAT_GE GENMASK(3, 0)

drivers/iio/adc/intel_dc_ti_adc.c

36

#define DC_TI_VBAT_ZSE GENMASK(7, 4)

drivers/iio/adc/ltc2309.c

21

#define LTC2309_DIN_CH_MASK GENMASK(7, 4)

drivers/iio/adc/max1027.c

195

GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)), \

drivers/iio/adc/max1027.c

196

GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)), \

drivers/iio/adc/max1027.c

197

GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)), \

drivers/iio/adc/max1027.c

198

GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp))

drivers/iio/adc/max1027.c

202

GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)), \

drivers/iio/adc/max1027.c

203

GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp))

drivers/iio/adc/max1027.c

207

GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)), \

drivers/iio/adc/max1027.c

208

GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp))

drivers/iio/adc/max11410.c

35

#define MAX11410_FILTER_RATE_MASK GENMASK(3, 0)

drivers/iio/adc/max11410.c

37

#define MAX11410_FILTER_LINEF_MASK GENMASK(5, 4)

drivers/iio/adc/max11410.c

41

#define MAX11410_CTRL_REFSEL_MASK GENMASK(2, 0)

drivers/iio/adc/max11410.c

48

#define MAX11410_PGA_GAIN_MASK GENMASK(2, 0)

drivers/iio/adc/max11410.c

49

#define MAX11410_PGA_SIG_PATH_MASK GENMASK(5, 4)

drivers/iio/adc/max1241.c

15

#define MAX1241_VAL_MASK GENMASK(11, 0)

drivers/iio/adc/max14001.c

51

#define MAX14001_MASK_ADDR GENMASK(15, 11)

drivers/iio/adc/max14001.c

53

#define MAX14001_MASK_DATA GENMASK(9, 0)

drivers/iio/adc/max34408.c

43

#define MAX34408_STATUS_OC_MSK GENMASK(1, 0)

drivers/iio/adc/max34408.c

44

#define MAX34409_STATUS_OC_MSK GENMASK(3, 0)

drivers/iio/adc/max34408.c

57

#define MAX34408_OCDELAY_OCD_MSK GENMASK(6, 0)

drivers/iio/adc/max34408.c

61

#define MAX34408_SDDELAY_SHD_MSK GENMASK(6, 0)

drivers/iio/adc/max9611.c

36

#define MAX9611_MUX_MASK GENMASK(3, 0)

drivers/iio/adc/max9611.c

85

#define MAX9611_TEMP_MASK GENMASK(15, 7)

drivers/iio/adc/mcp320x.c

184

raw |= GENMASK(31, 22); /* underrange or negative */

drivers/iio/adc/mcp3564.c

102

#define MCP3464_CONFIG3_CONV_MODE_MASK GENMASK(7, 6)

drivers/iio/adc/mcp3564.c

114

#define MCP3564_MUX_VIN_P_MASK GENMASK(7, 4)

drivers/iio/adc/mcp3564.c

115

#define MCP3564_MUX_VIN_N_MASK GENMASK(3, 0)

drivers/iio/adc/mcp3564.c

120

#define MCP3564_SCAN_CH_SEL_MASK GENMASK(15, 0)

drivers/iio/adc/mcp3564.c

122

#define MCP3564_SCAN_DELAY_TIME_MASK GENMASK(23, 21)

drivers/iio/adc/mcp3564.c

146

#define MCP3564_CMD_HW_ADDR_MASK GENMASK(7, 6)

drivers/iio/adc/mcp3564.c

147

#define MCP3564_CMD_ADDR_MASK GENMASK(5, 2)

drivers/iio/adc/mcp3564.c

149

#define MCP3564_HW_ADDR_MASK GENMASK(1, 0)

drivers/iio/adc/mcp3564.c

161

#define MCP3564_HW_ID_MASK GENMASK(3, 0)

drivers/iio/adc/mcp3564.c

32

#define MCP3564_CONFIG0_ADC_MODE_MASK GENMASK(1, 0)

drivers/iio/adc/mcp3564.c

34

#define MCP3564_CONFIG0_CS_SEL_MASK GENMASK(3, 2)

drivers/iio/adc/mcp3564.c

43

#define MCP3564_CONFIG0_CLK_SEL_MASK GENMASK(5, 4)

drivers/iio/adc/mcp3564.c

48

#define MCP3564_CONFIG1_OVERSPL_RATIO_MASK GENMASK(5, 2)

drivers/iio/adc/mcp3564.c

54

#define MCP3564_CONFIG2_HARDWARE_GAIN_MASK GENMASK(5, 3)

drivers/iio/adc/mcp3564.c

56

#define MCP3564_CONFIG2_BOOST_CURRENT_MASK GENMASK(7, 6)

drivers/iio/adc/mcp3564.c

87

#define MCP3464_CONFIG3_DATA_FORMAT_MASK GENMASK(5, 4)

drivers/iio/adc/mcp3911.c

35

#define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch))

drivers/iio/adc/mcp3911.c

40

#define MCP3911_STATUSCOM_READ GENMASK(7, 6)

drivers/iio/adc/mcp3911.c

49

#define MCP3911_CONFIG_OSR GENMASK(13, 11)

drivers/iio/adc/mcp3911.c

65

#define MCP3911_REG_MASK GENMASK(4, 1)

drivers/iio/adc/mcp3911.c

71

#define MCP3910_STATUSCOM_READ GENMASK(23, 22)

drivers/iio/adc/mcp3911.c

78

#define MCP3910_CONFIG0_OSR GENMASK(15, 13)

drivers/iio/adc/meson_saradc.c

106

#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)

drivers/iio/adc/meson_saradc.c

114

#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)

drivers/iio/adc/meson_saradc.c

125

#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)

drivers/iio/adc/meson_saradc.c

133

#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)

drivers/iio/adc/meson_saradc.c

145

#define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)

drivers/iio/adc/meson_saradc.c

147

#define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)

drivers/iio/adc/meson_saradc.c

149

#define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)

drivers/iio/adc/meson_saradc.c

169

#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)

drivers/iio/adc/meson_saradc.c

179

#define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)

drivers/iio/adc/meson_saradc.c

27

#define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)

drivers/iio/adc/meson_saradc.c

33

#define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)

drivers/iio/adc/meson_saradc.c

34

#define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)

drivers/iio/adc/meson_saradc.c

35

#define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)

drivers/iio/adc/meson_saradc.c

38

#define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)

drivers/iio/adc/meson_saradc.c

41

#define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)

drivers/iio/adc/meson_saradc.c

469

fifo_val &= GENMASK(priv->param->resolution - 1, 0);

drivers/iio/adc/meson_saradc.c

48

#define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)

drivers/iio/adc/meson_saradc.c

50

(GENMASK(2, 0) << ((_chan) * 3))

drivers/iio/adc/meson_saradc.c

56

(GENMASK(17, 16) << ((_chan) * 2))

drivers/iio/adc/meson_saradc.c

60

(GENMASK(1, 0) << ((_chan) * 2))

drivers/iio/adc/meson_saradc.c

68

#define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)

drivers/iio/adc/meson_saradc.c

71

#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)

drivers/iio/adc/meson_saradc.c

72

#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)

drivers/iio/adc/meson_saradc.c

75

#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)

drivers/iio/adc/meson_saradc.c

76

#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)

drivers/iio/adc/meson_saradc.c

79

#define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)

drivers/iio/adc/meson_saradc.c

82

#define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)

drivers/iio/adc/meson_saradc.c

83

#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)

drivers/iio/adc/meson_saradc.c

84

#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)

drivers/iio/adc/meson_saradc.c

87

#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)

drivers/iio/adc/meson_saradc.c

88

#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)

drivers/iio/adc/meson_saradc.c

91

#define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)

drivers/iio/adc/meson_saradc.c

92

#define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)

drivers/iio/adc/mp2629_adc.c

79

rval &= GENMASK(6, 0);

drivers/iio/adc/mt6359-auxadc.c

42

#define MT6358_DCM_CK_SW_EN GENMASK(1, 0)

drivers/iio/adc/mt6359-auxadc.c

50

#define MT6363_EXT_CHAN_MASK GENMASK(2, 0)

drivers/iio/adc/mt6359-auxadc.c

51

#define MT6363_EXT_PURES_MASK GENMASK(4, 3)

drivers/iio/adc/mt6359-auxadc.c

752

*out = val & GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/mt6360-adc.c

27

#define MT6360_AICR_MASK GENMASK(7, 2)

drivers/iio/adc/mt6360-adc.c

33

#define MT6360_PREFERCH_MASK GENMASK(7, 4)

drivers/iio/adc/mt6360-adc.c

35

#define MT6360_RPTCH_MASK GENMASK(3, 0)

drivers/iio/adc/mt6370-adc.c

29

#define MT6370_ADC_IN_SEL_MASK GENMASK(7, 4)

drivers/iio/adc/mt6370-adc.c

30

#define MT6370_AICR_ICHG_MASK GENMASK(7, 2)

drivers/iio/adc/mt6370-adc.c

31

#define MT6370_VENID_MASK GENMASK(7, 4)

drivers/iio/adc/nct7201.c

339

__le16 data = cpu_to_le16(GENMASK(chip->num_vin_channels - 1, 0));

drivers/iio/adc/nct7201.c

50

#define NCT7201_REG_VIN_MASK GENMASK(15, 3)

drivers/iio/adc/npcm_adc.c

60

#define NPCM_ADCCON_CH_MASK GENMASK(27, 24)

drivers/iio/adc/npcm_adc.c

63

#define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)

drivers/iio/adc/npcm_adc.c

69

.data_mask = GENMASK(9, 0),

drivers/iio/adc/npcm_adc.c

75

.data_mask = GENMASK(11, 0),

drivers/iio/adc/nxp-sar-adc.c

105

#define NXP_SAR_ADC_CH_MASK GENMASK(7, 0)

drivers/iio/adc/nxp-sar-adc.c

42

#define NXP_SAR_ADC_CDR_CDATA_MASK GENMASK(11, 0)

drivers/iio/adc/nxp-sar-adc.c

51

#define NXP_SAR_ADC_MCR_TSAMP_MASK GENMASK(10, 9)

drivers/iio/adc/nxp-sar-adc.c

52

#define NXP_SAR_ADC_MCR_NRSMPL_MASK GENMASK(12, 11)

drivers/iio/adc/pac1921.c

30

#define PAC1921_GAIN_DI_GAIN_MASK GENMASK(5, 3)

drivers/iio/adc/pac1921.c

31

#define PAC1921_GAIN_DV_GAIN_MASK GENMASK(2, 0)

drivers/iio/adc/pac1921.c

34

#define PAC1921_INT_CFG_SMPL_MASK GENMASK(7, 4)

drivers/iio/adc/pac1921.c

41

#define PAC1921_CONTROL_MXSL_MASK GENMASK(7, 6)

drivers/iio/adc/pac1921.c

51

#define PAC1921_RES_MASK GENMASK(15, 6)

drivers/iio/adc/pac1934.c

156

#define PAC1934_CRTL_SAMPLE_RATE_MASK GENMASK(7, 6)

drivers/iio/adc/qcom-spmi-adc5.c

71

#define ADC_CHANNEL_MASK GENMASK(7, 0)

drivers/iio/adc/qcom-spmi-adc5.c

89

#define ADC_APP_SID_MASK GENMASK(3, 0)

drivers/iio/adc/qcom-spmi-rradc.c

193

#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)

drivers/iio/adc/qcom-spmi-rradc.c

50

#define BATT_ID_SETTLE_MASK GENMASK(7, 5)

drivers/iio/adc/rockchip_saradc.c

202

info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);

drivers/iio/adc/rockchip_saradc.c

55

#define SARADC2_CONV_CHANNELS GENMASK(3, 0)

drivers/iio/adc/rohm-bd79112.c

395

gpio_channels = GENMASK(31, 0);

drivers/iio/adc/rohm-bd79124.c

56

#define BD79124_MSK_CONV_MODE GENMASK(6, 5)

drivers/iio/adc/rohm-bd79124.c

59

#define BD79124_MSK_AUTO_INTERVAL GENMASK(1, 0)

drivers/iio/adc/rohm-bd79124.c

68

#define BD79124_MSK_SEQ_MODE GENMASK(1, 0)

drivers/iio/adc/rohm-bd79124.c

72

#define BD79124_MSK_HYSTERESIS GENMASK(3, 0)

drivers/iio/adc/rohm-bd79124.c

74

#define BD79124_HIGH_LIMIT_MAX GENMASK(11, 0)

drivers/iio/adc/rohm-bd79124.c

941

gpio_channels = GENMASK(7, 0);

drivers/iio/adc/rzg2l_adc.c

200

reg &= ~GENMASK(hw_params->num_channels - 1, 0);

drivers/iio/adc/rzg2l_adc.c

311

intst = reg & GENMASK(hw_params->num_channels - 1, 0);

drivers/iio/adc/rzg2l_adc.c

36

#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)

drivers/iio/adc/rzg2l_adc.c

37

#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)

drivers/iio/adc/rzg2l_adc.c

38

#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)

drivers/iio/adc/rzg2l_adc.c

48

#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)

drivers/iio/adc/rzg2l_adc.c

491

.adsmp_mask = GENMASK(15, 0),

drivers/iio/adc/rzg2l_adc.c

492

.adint_inten_mask = GENMASK(7, 0),

drivers/iio/adc/rzg2l_adc.c

500

.adsmp_mask = GENMASK(7, 0),

drivers/iio/adc/rzg2l_adc.c

501

.adint_inten_mask = GENMASK(11, 0),

drivers/iio/adc/rzg2l_adc.c

54

#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)

drivers/iio/adc/rzn1-adc.c

46

#define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK GENMASK(5, 3)

drivers/iio/adc/rzn1-adc.c

47

#define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK GENMASK(2, 0)

drivers/iio/adc/rzn1-adc.c

51

#define RZN1_ADC_ADCX_DATA_DATA_MASK GENMASK(11, 0)

drivers/iio/adc/rzt2h_adc.c

20

#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13)

drivers/iio/adc/sc27xx_adc.c

38

#define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)

drivers/iio/adc/sc27xx_adc.c

42

#define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)

drivers/iio/adc/sc27xx_adc.c

43

#define SC27XX_ADC_SCALE_MASK GENMASK(10, 9)

drivers/iio/adc/sc27xx_adc.c

58

#define SC27XX_ADC_DATA_MASK GENMASK(11, 0)

drivers/iio/adc/sc27xx_adc.c

74

#define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)

drivers/iio/adc/sophgo-cv1800b-adc.c

32

#define CV1800B_MASK_STARTUP_CYCLE GENMASK(4, 0)

drivers/iio/adc/sophgo-cv1800b-adc.c

33

#define CV1800B_MASK_SAMPLE_WINDOW GENMASK(11, 8)

drivers/iio/adc/sophgo-cv1800b-adc.c

34

#define CV1800B_MASK_CLKDIV GENMASK(15, 12)

drivers/iio/adc/sophgo-cv1800b-adc.c

35

#define CV1800B_MASK_COMPARE_CYCLE GENMASK(19, 16)

drivers/iio/adc/sophgo-cv1800b-adc.c

37

#define CV1800B_ADC_CH_RESULT GENMASK(11, 0)

drivers/iio/adc/spear_adc.c

33

#define SPEAR_ADC_STATUS_CHANNEL_NUM_MASK GENMASK(3, 1)

drivers/iio/adc/spear_adc.c

35

#define SPEAR_ADC_STATUS_AVG_SAMPLE_MASK GENMASK(8, 5)

drivers/iio/adc/stm32-adc-core.h

149

#define STM32H7_LINCALRDYW_MASK GENMASK(27, 22)

drivers/iio/adc/stm32-adc-core.h

159

#define STM32H7_EXTEN_MASK GENMASK(11, 10)

drivers/iio/adc/stm32-adc-core.h

161

#define STM32H7_EXTSEL_MASK GENMASK(9, 5)

drivers/iio/adc/stm32-adc-core.h

163

#define STM32H7_RES_MASK GENMASK(4, 2)

drivers/iio/adc/stm32-adc-core.h

165

#define STM32H7_DMNGT_MASK GENMASK(1, 0)

drivers/iio/adc/stm32-adc-core.h

168

#define STM32H7_OVSR_MASK GENMASK(25, 16) /* Correspond to OSVR field in datasheet */

drivers/iio/adc/stm32-adc-core.h

170

#define STM32H7_OVSS_MASK GENMASK(8, 5)

drivers/iio/adc/stm32-adc-core.h

182

#define STM32H7_DIFSEL_MASK GENMASK(19, 0)

drivers/iio/adc/stm32-adc-core.h

186

#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)

drivers/iio/adc/stm32-adc-core.h

188

#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)

drivers/iio/adc/stm32-adc-core.h

192

#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)

drivers/iio/adc/stm32-adc-core.h

204

#define STM32H7_PRESC_MASK GENMASK(21, 18)

drivers/iio/adc/stm32-adc-core.h

206

#define STM32H7_CKMODE_MASK GENMASK(17, 16)

drivers/iio/adc/stm32-adc-core.h

213

#define STM32MP1_ADCNUM_MASK GENMASK(3, 0)

drivers/iio/adc/stm32-adc-core.h

215

#define STM32MP1_MULPIPE_MASK GENMASK(7, 4)

drivers/iio/adc/stm32-adc-core.h

217

#define STM32MP1_OPBITS_MASK GENMASK(11, 8)

drivers/iio/adc/stm32-adc-core.h

219

#define STM32MP1_IDLEVALUE_MASK GENMASK(15, 12)

drivers/iio/adc/stm32-adc-core.h

223

#define STM32MP1_MINREV_MASK GENMASK(3, 0)

drivers/iio/adc/stm32-adc-core.h

225

#define STM32MP1_MAJREV_MASK GENMASK(7, 4)

drivers/iio/adc/stm32-adc-core.h

228

#define STM32MP1_IPIDR_MASK GENMASK(31, 0)

drivers/iio/adc/stm32-adc-core.h

231

#define STM32MP1_SIDR_MASK GENMASK(31, 0)

drivers/iio/adc/stm32-adc-core.h

238

#define STM32MP13_RES_MASK GENMASK(4, 3)

drivers/iio/adc/stm32-adc-core.h

241

#define STM32MP13_OVSR_MASK GENMASK(4, 2)

drivers/iio/adc/stm32-adc-core.h

243

#define STM32MP13_OVSS_MASK GENMASK(8, 5)

drivers/iio/adc/stm32-adc-core.h

247

#define STM32MP13_DIFSEL_MASK GENMASK(18, 0)

drivers/iio/adc/stm32-adc-core.h

251

#define STM32MP13_CALFACT_D_MASK GENMASK(22, 16)

drivers/iio/adc/stm32-adc-core.h

253

#define STM32MP13_CALFACT_S_MASK GENMASK(6, 0)

drivers/iio/adc/stm32-adc-core.h

65

#define STM32F4_RES_MASK GENMASK(25, 24)

drivers/iio/adc/stm32-adc-core.h

72

#define STM32F4_EXTEN_MASK GENMASK(29, 28)

drivers/iio/adc/stm32-adc-core.h

74

#define STM32F4_EXTSEL_MASK GENMASK(27, 24)

drivers/iio/adc/stm32-adc-core.h

90

#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)

drivers/iio/adc/stm32-adc.c

365

{ STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },

drivers/iio/adc/stm32-adc.c

367

{ STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

368

{ STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },

drivers/iio/adc/stm32-adc.c

369

{ STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },

drivers/iio/adc/stm32-adc.c

370

{ STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },

drivers/iio/adc/stm32-adc.c

371

{ STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },

drivers/iio/adc/stm32-adc.c

372

{ STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },

drivers/iio/adc/stm32-adc.c

373

{ STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

374

{ STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },

drivers/iio/adc/stm32-adc.c

375

{ STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },

drivers/iio/adc/stm32-adc.c

376

{ STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },

drivers/iio/adc/stm32-adc.c

377

{ STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },

drivers/iio/adc/stm32-adc.c

378

{ STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },

drivers/iio/adc/stm32-adc.c

379

{ STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

380

{ STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },

drivers/iio/adc/stm32-adc.c

381

{ STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },

drivers/iio/adc/stm32-adc.c

382

{ STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },

drivers/iio/adc/stm32-adc.c

411

{ 1, GENMASK(2, 0), 0 },

drivers/iio/adc/stm32-adc.c

412

{ 1, GENMASK(5, 3), 3 },

drivers/iio/adc/stm32-adc.c

413

{ 1, GENMASK(8, 6), 6 },

drivers/iio/adc/stm32-adc.c

414

{ 1, GENMASK(11, 9), 9 },

drivers/iio/adc/stm32-adc.c

415

{ 1, GENMASK(14, 12), 12 },

drivers/iio/adc/stm32-adc.c

416

{ 1, GENMASK(17, 15), 15 },

drivers/iio/adc/stm32-adc.c

417

{ 1, GENMASK(20, 18), 18 },

drivers/iio/adc/stm32-adc.c

418

{ 1, GENMASK(23, 21), 21 },

drivers/iio/adc/stm32-adc.c

419

{ 1, GENMASK(26, 24), 24 },

drivers/iio/adc/stm32-adc.c

420

{ 1, GENMASK(29, 27), 27 },

drivers/iio/adc/stm32-adc.c

422

{ 0, GENMASK(2, 0), 0 },

drivers/iio/adc/stm32-adc.c

423

{ 0, GENMASK(5, 3), 3 },

drivers/iio/adc/stm32-adc.c

424

{ 0, GENMASK(8, 6), 6 },

drivers/iio/adc/stm32-adc.c

425

{ 0, GENMASK(11, 9), 9 },

drivers/iio/adc/stm32-adc.c

426

{ 0, GENMASK(14, 12), 12 },

drivers/iio/adc/stm32-adc.c

427

{ 0, GENMASK(17, 15), 15 },

drivers/iio/adc/stm32-adc.c

428

{ 0, GENMASK(20, 18), 18 },

drivers/iio/adc/stm32-adc.c

429

{ 0, GENMASK(23, 21), 21 },

drivers/iio/adc/stm32-adc.c

430

{ 0, GENMASK(26, 24), 24 },

drivers/iio/adc/stm32-adc.c

455

{ STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },

drivers/iio/adc/stm32-adc.c

457

{ STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },

drivers/iio/adc/stm32-adc.c

458

{ STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },

drivers/iio/adc/stm32-adc.c

459

{ STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },

drivers/iio/adc/stm32-adc.c

460

{ STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },

drivers/iio/adc/stm32-adc.c

461

{ STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

462

{ STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },

drivers/iio/adc/stm32-adc.c

463

{ STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },

drivers/iio/adc/stm32-adc.c

464

{ STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },

drivers/iio/adc/stm32-adc.c

465

{ STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },

drivers/iio/adc/stm32-adc.c

466

{ STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

467

{ STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },

drivers/iio/adc/stm32-adc.c

468

{ STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },

drivers/iio/adc/stm32-adc.c

469

{ STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },

drivers/iio/adc/stm32-adc.c

470

{ STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },

drivers/iio/adc/stm32-adc.c

471

{ STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },

drivers/iio/adc/stm32-adc.c

472

{ STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },

drivers/iio/adc/stm32-adc.c

504

{ 0, GENMASK(2, 0), 0 },

drivers/iio/adc/stm32-adc.c

505

{ 0, GENMASK(5, 3), 3 },

drivers/iio/adc/stm32-adc.c

506

{ 0, GENMASK(8, 6), 6 },

drivers/iio/adc/stm32-adc.c

507

{ 0, GENMASK(11, 9), 9 },

drivers/iio/adc/stm32-adc.c

508

{ 0, GENMASK(14, 12), 12 },

drivers/iio/adc/stm32-adc.c

509

{ 0, GENMASK(17, 15), 15 },

drivers/iio/adc/stm32-adc.c

510

{ 0, GENMASK(20, 18), 18 },

drivers/iio/adc/stm32-adc.c

511

{ 0, GENMASK(23, 21), 21 },

drivers/iio/adc/stm32-adc.c

512

{ 0, GENMASK(26, 24), 24 },

drivers/iio/adc/stm32-adc.c

513

{ 0, GENMASK(29, 27), 27 },

drivers/iio/adc/stm32-adc.c

515

{ 1, GENMASK(2, 0), 0 },

drivers/iio/adc/stm32-adc.c

516

{ 1, GENMASK(5, 3), 3 },

drivers/iio/adc/stm32-adc.c

517

{ 1, GENMASK(8, 6), 6 },

drivers/iio/adc/stm32-adc.c

518

{ 1, GENMASK(11, 9), 9 },

drivers/iio/adc/stm32-adc.c

519

{ 1, GENMASK(14, 12), 12 },

drivers/iio/adc/stm32-adc.c

520

{ 1, GENMASK(17, 15), 15 },

drivers/iio/adc/stm32-adc.c

521

{ 1, GENMASK(20, 18), 18 },

drivers/iio/adc/stm32-adc.c

522

{ 1, GENMASK(23, 21), 21 },

drivers/iio/adc/stm32-adc.c

523

{ 1, GENMASK(26, 24), 24 },

drivers/iio/adc/stm32-adc.c

524

{ 1, GENMASK(29, 27), 27 },

drivers/iio/adc/stm32-adc.c

934

ovsr_bits = GENMASK(ovs_idx - 1, 0);

drivers/iio/adc/stm32-dfsdm.h

124

#define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)

drivers/iio/adc/stm32-dfsdm.h

126

#define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)

drivers/iio/adc/stm32-dfsdm.h

136

#define DFSDM_CR1_RCH_MASK GENMASK(26, 24)

drivers/iio/adc/stm32-dfsdm.h

144

#define DFSDM_CR2_IE_MASK GENMASK(6, 0)

drivers/iio/adc/stm32-dfsdm.h

160

#define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)

drivers/iio/adc/stm32-dfsdm.h

162

#define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)

drivers/iio/adc/stm32-dfsdm.h

180

#define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)

drivers/iio/adc/stm32-dfsdm.h

182

#define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)

drivers/iio/adc/stm32-dfsdm.h

190

#define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)

drivers/iio/adc/stm32-dfsdm.h

195

#define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)

drivers/iio/adc/stm32-dfsdm.h

202

#define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)

drivers/iio/adc/stm32-dfsdm.h

204

#define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)

drivers/iio/adc/stm32-dfsdm.h

206

#define DFSDM_FCR_FORD_MASK GENMASK(31, 29)

drivers/iio/adc/stm32-dfsdm.h

210

#define DFSDM_DATAR_CH_MASK GENMASK(2, 0)

drivers/iio/adc/stm32-dfsdm.h

212

#define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)

drivers/iio/adc/stm32-dfsdm.h

215

#define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)

drivers/iio/adc/stm32-dfsdm.h

217

#define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)

drivers/iio/adc/stm32-dfsdm.h

221

#define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)

drivers/iio/adc/stm32-dfsdm.h

223

#define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)

drivers/iio/adc/stm32-dfsdm.h

227

#define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)

drivers/iio/adc/stm32-dfsdm.h

229

#define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)

drivers/iio/adc/stm32-dfsdm.h

233

#define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)

drivers/iio/adc/stm32-dfsdm.h

235

#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)

drivers/iio/adc/stm32-dfsdm.h

247

#define DFSDM_HWCFGR_NBT_MASK GENMASK(7, 0)

drivers/iio/adc/stm32-dfsdm.h

248

#define DFSDM_HWCFGR_NBF_MASK GENMASK(15, 8)

drivers/iio/adc/stm32-dfsdm.h

251

#define DFSDM_VERR_MINREV_MASK GENMASK(3, 0)

drivers/iio/adc/stm32-dfsdm.h

252

#define DFSDM_VERR_MAJREV_MASK GENMASK(7, 4)

drivers/iio/adc/stm32-dfsdm.h

51

#define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)

drivers/iio/adc/stm32-dfsdm.h

53

#define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)

drivers/iio/adc/stm32-dfsdm.h

63

#define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)

drivers/iio/adc/stm32-dfsdm.h

65

#define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)

drivers/iio/adc/stm32-dfsdm.h

67

#define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)

drivers/iio/adc/stm32-dfsdm.h

75

#define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)

drivers/iio/adc/stm32-dfsdm.h

77

#define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)

drivers/iio/adc/stm32-dfsdm.h

81

#define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)

drivers/iio/adc/stm32-dfsdm.h

83

#define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)

drivers/iio/adc/stm32-dfsdm.h

85

#define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)

drivers/iio/adc/stm32-dfsdm.h

87

#define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)

drivers/iio/adc/sun20i-gpadc-iio.c

135

writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS);

drivers/iio/adc/sun20i-gpadc-iio.c

41

#define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18)

drivers/iio/adc/ti-adc108s102.c

57

#define ADC108S102_RES_DATA(res) ((u16)res & GENMASK(11, 0))

drivers/iio/adc/ti-ads1015.c

51

#define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)

drivers/iio/adc/ti-ads1015.c

55

#define ADS1015_CFG_DR_MASK GENMASK(7, 5)

drivers/iio/adc/ti-ads1015.c

57

#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)

drivers/iio/adc/ti-ads1015.c

58

#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)

drivers/iio/adc/ti-ads1018.c

35

#define ADS1018_CFG_MUX_MASK GENMASK(14, 12)

drivers/iio/adc/ti-ads1018.c

37

#define ADS1018_CFG_PGA_MASK GENMASK(11, 9)

drivers/iio/adc/ti-ads1018.c

44

#define ADS1018_CFG_DRATE_MASK GENMASK(7, 5)

drivers/iio/adc/ti-ads1100.c

34

#define ADS1100_DR_MASK GENMASK(3, 2)

drivers/iio/adc/ti-ads1100.c

36

#define ADS1100_PGA_MASK GENMASK(1, 0)

drivers/iio/adc/ti-ads1119.c

45

#define ADS1119_CONFIG_DR_FIELD GENMASK(3, 2)

drivers/iio/adc/ti-ads1119.c

47

#define ADS1119_CONFIG_MUX_FIELD GENMASK(7, 5)

drivers/iio/adc/ti-ads1298.c

42

#define ADS1298_MASK_ID_FAMILY GENMASK(7, 3)

drivers/iio/adc/ti-ads1298.c

43

#define ADS1298_MASK_ID_CHANNELS GENMASK(2, 0)

drivers/iio/adc/ti-ads1298.c

49

#define ADS1298_MASK_CONFIG1_DR GENMASK(2, 0)

drivers/iio/adc/ti-ads1298.c

59

#define ADS1298_MASK_CONFIG2_TEST_FREQ_DC GENMASK(1, 0)

drivers/iio/adc/ti-ads1298.c

71

#define ADS1298_MASK_CH_PGA GENMASK(6, 4)

drivers/iio/adc/ti-ads1298.c

72

#define ADS1298_MASK_CH_MUX GENMASK(2, 0)

drivers/iio/adc/ti-ads131e08.c

35

#define ADS131E08_CMD_RREG(r) (BIT(5) | (r & GENMASK(4, 0)))

drivers/iio/adc/ti-ads131e08.c

36

#define ADS131E08_CMD_WREG(r) (BIT(6) | (r & GENMASK(4, 0)))

drivers/iio/adc/ti-ads131e08.c

44

#define ADS131E08_CFG1R_DR_MASK GENMASK(2, 0)

drivers/iio/adc/ti-ads131e08.c

51

#define ADS131E08_CHR_GAIN_MASK GENMASK(6, 4)

drivers/iio/adc/ti-ads131e08.c

52

#define ADS131E08_CHR_MUX_MASK GENMASK(2, 0)

drivers/iio/adc/ti-ads131m02.c

76

#define ADS131M_CMD_ADDR_MASK GENMASK(11, 7)

drivers/iio/adc/ti-ads131m02.c

77

#define ADS131M_CMD_NUM_MASK GENMASK(6, 0)

drivers/iio/adc/ti-ads7138.c

54

#define ADS7138_OSR_CFG_MASK GENMASK(2, 0)

drivers/iio/adc/ti-ads7138.c

56

#define ADS7138_OPMODE_CFG_FREQ_MASK GENMASK(4, 0)

drivers/iio/adc/ti-ads7138.c

59

#define ADS7138_THRESHOLD_LSB_MASK GENMASK(7, 4)

drivers/iio/adc/ti-ads7924.c

64

#define ADS7924_MODECNTRL_MODE_MASK GENMASK(7, 2)

drivers/iio/adc/ti-ads7924.c

66

#define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0)

drivers/iio/adc/ti-ads7924.c

93

#define ADS7924_ACQTIME_MASK GENMASK(4, 0)

drivers/iio/adc/ti-ads7924.c

95

#define ADS7924_PWRUPTIME_MASK GENMASK(4, 0)

drivers/iio/adc/ti-tlc4541.c

142

*val &= GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/adc/ti-tsc2046.c

49

#define TI_TSC2046_ADDR GENMASK(6, 4)

drivers/iio/adc/ti-tsc2046.c

85

#define TI_TSC2046_DATA_12BIT GENMASK(14, 3)

drivers/iio/adc/xilinx-ams.c

102

#define AMS_PS_SEQ_MASK GENMASK(21, 0)

drivers/iio/adc/xilinx-ams.c

128

#define AMS_PL_ALARM_MASK GENMASK(31, 16)

drivers/iio/adc/xilinx-ams.c

129

#define AMS_ISR0_ALARM_MASK GENMASK(31, 0)

drivers/iio/adc/xilinx-ams.c

130

#define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0))

drivers/iio/adc/xilinx-ams.c

133

#define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0)

drivers/iio/adc/xilinx-ams.c

134

#define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3)

drivers/iio/adc/xilinx-ams.c

135

#define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8)

drivers/iio/adc/xilinx-ams.c

136

#define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1)

drivers/iio/adc/xilinx-ams.c

137

#define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8)

drivers/iio/adc/xilinx-ams.c

138

#define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0)

drivers/iio/adc/xilinx-ams.c

91

#define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0)

drivers/iio/adc/xilinx-ams.c

93

#define AMS_CONF1_SEQ_MASK GENMASK(15, 12)

drivers/iio/adc/xilinx-ams.c

98

#define AMS_REG_SEQ0_MASK GENMASK(15, 0)

drivers/iio/adc/xilinx-ams.c

99

#define AMS_REG_SEQ2_MASK GENMASK(21, 16)

drivers/iio/addac/ad74115.c

1397

AD74115_CH_FUNC_SETUP_REG, GENMASK(3, 0));

drivers/iio/addac/ad74115.c

1409

AD74115_BURNOUT_CONFIG_REG, GENMASK(14, 12));

drivers/iio/addac/ad74115.c

1414

AD74115_BURNOUT_CONFIG_REG, GENMASK(9, 7));

drivers/iio/addac/ad74115.c

1419

AD74115_BURNOUT_CONFIG_REG, GENMASK(4, 2));

drivers/iio/addac/ad74115.c

1423

AD74115_ADC_CONFIG_REG, GENMASK(3, 2)),

drivers/iio/addac/ad74115.c

1455

AD74115_RTD3W4W_CONFIG_REG, GENMASK(1, 0)),

drivers/iio/addac/ad74115.c

32

#define AD74115_ADC_CONFIG_CONV2_RATE_MASK GENMASK(15, 13)

drivers/iio/addac/ad74115.c

33

#define AD74115_ADC_CONFIG_CONV1_RATE_MASK GENMASK(12, 10)

drivers/iio/addac/ad74115.c

34

#define AD74115_ADC_CONFIG_CONV2_RANGE_MASK GENMASK(9, 7)

drivers/iio/addac/ad74115.c

35

#define AD74115_ADC_CONFIG_CONV1_RANGE_MASK GENMASK(6, 4)

drivers/iio/addac/ad74115.c

41

#define AD74115_DIN_SINK_MASK GENMASK(11, 7)

drivers/iio/addac/ad74115.c

42

#define AD74115_DIN_DEBOUNCE_MASK GENMASK(4, 0)

drivers/iio/addac/ad74115.c

45

#define AD74115_COMP_THRESH_MASK GENMASK(6, 0)

drivers/iio/addac/ad74115.c

48

#define AD74115_OUTPUT_SLEW_EN_MASK GENMASK(6, 5)

drivers/iio/addac/ad74115.c

49

#define AD74115_OUTPUT_SLEW_LIN_STEP_MASK GENMASK(4, 3)

drivers/iio/addac/ad74115.c

50

#define AD74115_OUTPUT_SLEW_LIN_RATE_MASK GENMASK(2, 1)

drivers/iio/addac/ad74115.c

66

#define AD74115_GPIO_CONFIG_SELECT_MASK GENMASK(2, 0)

drivers/iio/addac/ad74115.c

71

#define AD74115_ADC_CONV_SEQ_MASK GENMASK(13, 12)

drivers/iio/addac/ad74115.c

87

#define AD74115_ADC_CODE_MAX ((int)GENMASK(15, 0))

drivers/iio/addac/ad74115.c

92

#define AD74115_DAC_CODE_MAX ((int)GENMASK(13, 0))

drivers/iio/addac/ad74413r.c

102

#define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5)

drivers/iio/addac/ad74413r.c

103

#define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3)

drivers/iio/addac/ad74413r.c

115

#define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0)

drivers/iio/addac/ad74413r.c

117

#define AD74413R_DIN_SINK_MASK GENMASK(9, 6)

drivers/iio/addac/ad74413r.c

120

#define AD74413R_DAC_CODE_MAX GENMASK(12, 0)

drivers/iio/addac/ad74413r.c

126

#define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0)

drivers/iio/addac/ad74413r.c

134

#define AD74413R_CONV_SEQ_MASK GENMASK(9, 8)

drivers/iio/addac/ad74413r.c

144

#define AD74413R_ADC_RESULT_MAX GENMASK(15, 0)

drivers/iio/addac/ad74413r.c

99

#define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)

drivers/iio/addac/stx104.c

65

#define STX104_FC GENMASK(3, 0)

drivers/iio/addac/stx104.c

66

#define STX104_LC GENMASK(7, 4)

drivers/iio/addac/stx104.c

76

#define STX104_ALSS GENMASK(1, 0)

drivers/iio/addac/stx104.c

80

#define STX104_GAIN GENMASK(1, 0)

drivers/iio/addac/stx104.c

82

#define STX104_RBK GENMASK(7, 4)

drivers/iio/amplifiers/ada4250.c

29

#define ADA4250_GAIN_MUX_MSK GENMASK(2, 0)

drivers/iio/amplifiers/ada4250.c

38

#define ADA4250_CAL_CFG_BIAS_MSK GENMASK(7, 0)

drivers/iio/amplifiers/ada4250.c

41

#define ADA4250_BIAS_SET_MSK GENMASK(3, 2)

drivers/iio/amplifiers/ada4250.c

42

#define ADA4250_RANGE_SET_MSK GENMASK(1, 0)

drivers/iio/amplifiers/hmc425a.c

35

#define LTC6373_CONVERSION_MASK GENMASK(2, 0)

drivers/iio/amplifiers/hmc425a.c

36

#define LTC6373_SHUTDOWN GENMASK(2, 0)

drivers/iio/cdc/ad7150.c

34

#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)

drivers/iio/cdc/ad7150.c

35

#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)

drivers/iio/cdc/ad7150.c

43

#define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)

drivers/iio/cdc/ad7746.c

53

#define AD7746_VTSETUP_VTMD_MASK GENMASK(6, 5)

drivers/iio/cdc/ad7746.c

69

#define AD7746_EXCSETUP_EXCLVL_MASK GENMASK(1, 0)

drivers/iio/cdc/ad7746.c

72

#define AD7746_CONF_VTFS_MASK GENMASK(7, 6)

drivers/iio/cdc/ad7746.c

73

#define AD7746_CONF_CAPFS_MASK GENMASK(5, 3)

drivers/iio/cdc/ad7746.c

74

#define AD7746_CONF_MODE_MASK GENMASK(2, 0)

drivers/iio/cdc/ad7746.c

84

#define AD7746_CAPDAC_DACP_MASK GENMASK(6, 0)

drivers/iio/chemical/bme680.h

22

#define BME680_GAS_RANGE_MASK GENMASK(3, 0)

drivers/iio/chemical/bme680.h

25

#define BME680_OSRS_HUMIDITY_MASK GENMASK(2, 0)

drivers/iio/chemical/bme680.h

28

#define BME680_OSRS_TEMP_MASK GENMASK(7, 5)

drivers/iio/chemical/bme680.h

29

#define BME680_OSRS_PRESS_MASK GENMASK(4, 2)

drivers/iio/chemical/bme680.h

30

#define BME680_MODE_MASK GENMASK(1, 0)

drivers/iio/chemical/bme680.h

33

#define BME680_FILTER_MASK GENMASK(4, 2)

drivers/iio/chemical/bme680.h

41

#define BME680_BIT_H1_DATA_MASK GENMASK(3, 0)

drivers/iio/chemical/bme680.h

43

#define BME680_RHRANGE_MASK GENMASK(5, 4)

drivers/iio/chemical/bme680.h

45

#define BME680_RSERROR_MASK GENMASK(7, 4)

drivers/iio/chemical/bme680.h

49

#define BME680_ADC_GAS_RES GENMASK(15, 6)

drivers/iio/chemical/bme680.h

54

#define BME680_NB_CONV_MASK GENMASK(3, 0)

drivers/iio/chemical/bme680.h

66

#define BME680_MEAS_TRIM_MASK GENMASK(24, 4)

drivers/iio/chemical/ens160_core.c

53

#define ENS160_STATUS_VALIDITY_FLAG GENMASK(3, 2)

drivers/iio/chemical/scd30_core.c

111

fraction = mantissa & GENMASK(shift - 1, 0);

drivers/iio/chemical/scd30_core.c

93

mantissa = float32 & GENMASK(22, 0),

drivers/iio/chemical/sps30.c

42

int mantissa = val & GENMASK(22, 0);

drivers/iio/chemical/sps30.c

63

fraction = mantissa & GENMASK(shift - 1, 0);

drivers/iio/chemical/vz89x.c

249

*val = le32_to_cpup((__le32 *) tmp) & GENMASK(23, 0);

drivers/iio/dac/ad3530r.c

45

#define AD3530R_REG_VAL_MASK GENMASK(15, 0)

drivers/iio/dac/ad3530r.c

46

#define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan))

drivers/iio/dac/ad3530r.c

52

#define AD3530R_DAC_MAX_VAL GENMASK(15, 0)

drivers/iio/dac/ad3552r.h

119

#define AD3552R_MASK_ALL_CH GENMASK(1, 0)

drivers/iio/dac/ad3552r.h

122

#define AD3552R_ADDR_MASK GENMASK(6, 0)

drivers/iio/dac/ad3552r.h

123

#define AD3552R_MASK_DAC_12B GENMASK(15, 4)

drivers/iio/dac/ad3552r.h

23

#define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)

drivers/iio/dac/ad3552r.h

24

#define AD3552R_MASK_OPERATING_MODES GENMASK(1, 0)

drivers/iio/dac/ad3552r.h

26

#define AD3552R_MASK_CLASS GENMASK(7, 0)

drivers/iio/dac/ad3552r.h

30

#define AD3552R_MASK_GRADE GENMASK(7, 4)

drivers/iio/dac/ad3552r.h

31

#define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)

drivers/iio/dac/ad3552r.h

37

#define AD3552R_MASK_LENGTH GENMASK(7, 0)

drivers/iio/dac/ad3552r.h

39

#define AD3552R_MASK_MULTI_IO_MODE GENMASK(7, 6)

drivers/iio/dac/ad3552r.h

43

(GENMASK(7, 6) | GENMASK(1, 0))

drivers/iio/dac/ad3552r.h

55

#define AD3552R_MASK_SDO_DRIVE_STRENGTH GENMASK(3, 2)

drivers/iio/dac/ad3552r.h

61

#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM GENMASK(4, 3)

drivers/iio/dac/ad3552r.h

63

#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL GENMASK(1, 0)

drivers/iio/dac/ad3552r.h

81

#define AD3552R_MASK_CH0_RANGE GENMASK(2, 0)

drivers/iio/dac/ad3552r.h

82

#define AD3552R_MASK_CH1_RANGE GENMASK(6, 4)

drivers/iio/dac/ad3552r.h

83

#define AD3552R_MASK_CH_OUTPUT_RANGE GENMASK(7, 0)

drivers/iio/dac/ad3552r.h

85

((ch) ? GENMASK(7, 4) : GENMASK(3, 0))

drivers/iio/dac/ad3552r.h

87

#define AD3552R_MASK_CH_OFFSET_BITS_0_7 GENMASK(7, 0)

drivers/iio/dac/ad3552r.h

90

#define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)

drivers/iio/dac/ad3552r.h

91

#define AD3552R_MASK_CH_GAIN_SCALING_P GENMASK(4, 3)

drivers/iio/dac/ad5504.c

24

#define AD5504_RES_MASK GENMASK(11, 0)

drivers/iio/dac/ad5592r-base.c

380

read_val &= GENMASK(11, 0);

drivers/iio/dac/ad5686.c

136

GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/dac/ad5758.c

51

#define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0)

drivers/iio/dac/ad5758.c

59

#define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9)

drivers/iio/dac/ad5758.c

61

#define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13)

drivers/iio/dac/ad5758.c

72

#define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0)

drivers/iio/dac/ad5758.c

74

#define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5)

drivers/iio/dac/ad5758.c

78

#define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1)

drivers/iio/dac/ad5766.c

19

#define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16)

drivers/iio/dac/ad5766.c

20

#define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0)

drivers/iio/dac/ad5766.c

21

#define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))

drivers/iio/dac/ad5766.c

268

const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/dac/ad5766.c

32

#define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))

drivers/iio/dac/ad5766.c

33

#define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))

drivers/iio/dac/ad5766.c

39

#define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))

drivers/iio/dac/ad5766.c

534

st->dither_enable = GENMASK(15, 0);

drivers/iio/dac/ad5770r.c

363

st->transf_buf[1] = (val & GENMASK(5, 0)) << 2;

drivers/iio/dac/ad5770r.c

68

#define AD5770R_RANGE_OUTPUT_SCALING(x) (((x) & GENMASK(5, 0)) << 2)

drivers/iio/dac/ad5770r.c

69

#define AD5770R_RANGE_MODE(x) ((x) & GENMASK(1, 0))

drivers/iio/dac/ad5770r.c

73

#define AD5770R_REF_SEL(x) ((x) & GENMASK(1, 0))

drivers/iio/dac/ad5791.c

28

#define AD5791_DAC_MASK GENMASK(19, 0)

drivers/iio/dac/ad5791.c

369

val &= GENMASK(chan->scan_type.realbits - 1, 0);

drivers/iio/dac/ad7293.c

110

#define AD7293_TRANSF_LEN_MSK GENMASK(17, 16)

drivers/iio/dac/ad7293.c

112

#define AD7293_REG_ADDR_MSK GENMASK(7, 0)

drivers/iio/dac/ad7293.c

113

#define AD7293_REG_VOUT_OFFSET_MSK GENMASK(5, 4)

drivers/iio/dac/ad7293.c

114

#define AD7293_REG_DATA_RAW_MSK GENMASK(15, 4)

drivers/iio/dac/ad7293.c

23

#define AD7293_PAGE_ADDR_MSK GENMASK(15, 8)

drivers/iio/dac/ad8460.c

39

#define AD8460_FAULT_LIMIT_MSK GENMASK(6, 0)

drivers/iio/dac/ad8460.c

42

#define AD8460_PATTERN_DEPTH_MSK GENMASK(3, 0)

drivers/iio/dac/ad8460.c

44

#define AD8460_QUIESCENT_CURRENT_MSK GENMASK(7, 0)

drivers/iio/dac/ad8460.c

48

#define AD8460_DATA_BYTE_LOW_MSK GENMASK(7, 0)

drivers/iio/dac/ad8460.c

49

#define AD8460_DATA_BYTE_HIGH_MSK GENMASK(5, 0)

drivers/iio/dac/ad8460.c

50

#define AD8460_DATA_BYTE_FULL_MSK GENMASK(13, 0)

drivers/iio/dac/ad9739a.c

31

#define AD9739A_FSC_MSB GENMASK(1, 0)

drivers/iio/dac/ad9739a.c

35

#define AD9739A_DAC_DEC GENMASK(1, 0)

drivers/iio/dac/ad9739a.c

37

#define AD9739A_RCVR_LOOP_EN_MASK GENMASK(1, 0)

drivers/iio/dac/ad9739a.c

39

#define AD9739A_FINE_DEL_SKW_MASK GENMASK(3, 0)

drivers/iio/dac/adi-axi-dac.c

61

#define AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16)

drivers/iio/dac/adi-axi-dac.c

62

#define AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8)

drivers/iio/dac/adi-axi-dac.c

66

#define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24)

drivers/iio/dac/adi-axi-dac.c

67

#define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2)

drivers/iio/dac/adi-axi-dac.c

79

#define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0)

drivers/iio/dac/adi-axi-dac.c

81

#define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16)

drivers/iio/dac/adi-axi-dac.c

82

#define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0)

drivers/iio/dac/adi-axi-dac.c

85

#define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0)

drivers/iio/dac/ltc1660.c

90

if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))

drivers/iio/dac/ltc2688.c

45

#define LTC2688_CH_SPAN_MSK GENMASK(2, 0)

drivers/iio/dac/ltc2688.c

47

#define LTC2688_CH_TD_SEL_MSK GENMASK(5, 4)

drivers/iio/dac/ltc2688.c

49

#define LTC2688_CH_DIT_PER_MSK GENMASK(8, 6)

drivers/iio/dac/ltc2688.c

50

#define LTC2688_CH_DIT_PH_MSK GENMASK(10, 9)

drivers/iio/dac/ltc2688.c

53

#define LTC2688_DITHER_RAW_MASK GENMASK(15, 2)

drivers/iio/dac/ltc2688.c

54

#define LTC2688_CH_CALIBBIAS_MASK GENMASK(15, 2)

drivers/iio/dac/max22007.c

59

#define MAX22007_DAC_DATA_MASK GENMASK(15, 4)

drivers/iio/dac/max22007.c

60

#define MAX22007_DAC_MAX_RAW GENMASK(11, 0)

drivers/iio/dac/mcp4728.c

30

#define MCP4728_CMD_MASK GENMASK(7, 3)

drivers/iio/dac/mcp4728.c

31

#define MCP4728_CHSEL_MASK GENMASK(2, 1)

drivers/iio/dac/mcp4728.c

35

#define MCP4728_PDMODE_MASK GENMASK(6, 5)

drivers/iio/dac/mcp4728.c

38

#define MCP4728_DAC_H_MASK GENMASK(3, 0)

drivers/iio/dac/mcp4728.c

388

if (val < 0 || val > GENMASK(MCP4728_RESOLUTION - 1, 0))

drivers/iio/dac/mcp4728.c

39

#define MCP4728_DAC_L_MASK GENMASK(7, 0)

drivers/iio/dac/mcp47feb02.c

37

#define MCP47FEB02_DAC_CTRL_MASK GENMASK(1, 0)

drivers/iio/dac/mcp47feb02.c

42

#define MCP47FEB02_GAIN_BITS_MASK GENMASK(15, 8)

drivers/iio/dac/mcp47feb02.c

50

#define MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK GENMASK(7, 0)

drivers/iio/dac/mcp47feb02.c

53

#define DAC_CTRL_MASK(ch) (GENMASK(1, 0) << (2 * (ch)))

drivers/iio/dac/mcp47feb02.c

62

#define READFLAG_MASK GENMASK(2, 1)

drivers/iio/dac/mcp4922.c

95

if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))

drivers/iio/dac/rohm-bd79703.c

18

#define BD79703_REG_OUT_ALL GENMASK(2, 0)

drivers/iio/filter/admv8818.c

67

#define ADMV8818_SW_IN_WR0_MSK GENMASK(5, 3)

drivers/iio/filter/admv8818.c

68

#define ADMV8818_SW_OUT_WR0_MSK GENMASK(2, 0)

drivers/iio/filter/admv8818.c

71

#define ADMV8818_HPF_WR0_MSK GENMASK(7, 4)

drivers/iio/filter/admv8818.c

72

#define ADMV8818_LPF_WR0_MSK GENMASK(3, 0)

drivers/iio/frequency/adf4371.c

32

#define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1)

drivers/iio/frequency/adf4371.c

38

#define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4371.c

42

#define ADF4371_MOD2WORD_MSK GENMASK(5, 0)

drivers/iio/frequency/adf4371.c

52

#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)

drivers/iio/frequency/adf4371.c

60

#define ADF4371_TIMEOUT_MSK GENMASK(1, 0)

drivers/iio/frequency/adf4371.c

64

#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0)

drivers/iio/frequency/adf4377.c

101

#define ADF4377_0013_M_VCO_CORE_MSK GENMASK(5, 4)

drivers/iio/frequency/adf4377.c

102

#define ADF4377_0013_VCO_BIAS_MSK GENMASK(3, 0)

drivers/iio/frequency/adf4377.c

111

#define ADF4377_0014_M_VCO_BAND_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

114

#define ADF4377_0015_BLEED_I_LSB_MSK GENMASK(7, 6)

drivers/iio/frequency/adf4377.c

117

#define ADF4377_0015_CP_I_MSK GENMASK(3, 0)

drivers/iio/frequency/adf4377.c

141

#define ADF4377_0016_BLEED_I_MSB_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

145

#define ADF4377_0016_N_DEL_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4377.c

149

#define ADF4377_0018_R_DEL_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4377.c

156

#define ADF4377_0019_CLKOUT2_OP_MSK GENMASK(7, 6)

drivers/iio/frequency/adf4377.c

157

#define ADF4377_0019_CLKOUT1_OP_MSK GENMASK(5, 4)

drivers/iio/frequency/adf4377.c

183

#define ADF4377_001B_LD_COUNT_MSK GENMASK(4, 0)

drivers/iio/frequency/adf4377.c

202

#define ADF4377_001D_MUXOUT_MSK GENMASK(7, 4)

drivers/iio/frequency/adf4377.c

220

#define ADF4377_001F_R01F_RSV1_MSK GENMASK(4, 0)

drivers/iio/frequency/adf4377.c

247

#define ADF4377_0023_R023_RSV1_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4377.c

258

#define ADF4377_0025_R025_RSV1_MSK GENMASK(5, 0)

drivers/iio/frequency/adf4377.c

264

#define ADF4377_0026_VCO_BAND_DIV_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

267

#define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

271

#define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4377.c

274

#define ADF4377_0029_VCO_ALC_TO_LSB_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

278

#define ADF4377_002A_VCO_ALC_TO_MSB_MSK GENMASK(6, 0)

drivers/iio/frequency/adf4377.c

284

#define ADF4377_002D_ADC_CLK_DIV_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

296

#define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0)

drivers/iio/frequency/adf4377.c

309

#define ADF4377_0032_R032_RSV1_MSK GENMASK(5, 0)

drivers/iio/frequency/adf4377.c

359

#define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0)

drivers/iio/frequency/adf4377.c

362

#define ADF4377_004C_CHIP_TEMP_LSB_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

368

#define ADF4377_004F_VCO_BAND_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

371

#define ADF4377_0051_VCO_BIAS_MSK GENMASK(3, 0)

drivers/iio/frequency/adf4377.c

374

#define ADF4377_0054_CHIP_VERSION_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

64

#define ADF4377_000A_SCRATCHPAD_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

73

#define ADF4377_000F_R00F_RSV1_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

76

#define ADF4377_0010_N_INT_LSB_MSK GENMASK(7, 0)

drivers/iio/frequency/adf4377.c

81

#define ADF4377_0011_DCLK_DIV2_MSK GENMASK(5, 4)

drivers/iio/frequency/adf4377.c

82

#define ADF4377_0011_N_INT_MSB_MSK GENMASK(3, 0)

drivers/iio/frequency/adf4377.c

91

#define ADF4377_0012_CLKOUT_DIV_MSK GENMASK(7, 6)

drivers/iio/frequency/adf4377.c

92

#define ADF4377_0012_R_DIV_MSK GENMASK(5, 0)

drivers/iio/frequency/admv1013.c

38

#define ADMV1013_CHIP_ID_MSK GENMASK(11, 4)

drivers/iio/frequency/admv1013.c

40

#define ADMV1013_REVISION_ID_MSK GENMASK(3, 0)

drivers/iio/frequency/admv1013.c

51

#define ADMV1013_QUAD_PD_MSK GENMASK(13, 11)

drivers/iio/frequency/admv1013.c

57

#define ADMV1013_LOAMP_PH_ADJ_FINE_MSK GENMASK(13, 7)

drivers/iio/frequency/admv1013.c

58

#define ADMV1013_MIXER_VGATE_MSK GENMASK(6, 0)

drivers/iio/frequency/admv1013.c

61

#define ADMV1013_MIXER_OFF_ADJ_P_MSK GENMASK(15, 9)

drivers/iio/frequency/admv1013.c

62

#define ADMV1013_MIXER_OFF_ADJ_N_MSK GENMASK(8, 2)

drivers/iio/frequency/admv1013.c

65

#define ADMV1013_QUAD_SE_MODE_MSK GENMASK(9, 6)

drivers/iio/frequency/admv1013.c

66

#define ADMV1013_QUAD_FILTERS_MSK GENMASK(3, 0)

drivers/iio/frequency/admv1013.c

69

#define ADMV1013_VVA_TEMP_COMP_MSK GENMASK(15, 0)

drivers/iio/frequency/admv1013.c

73

#define ADMV1013_REG_ADDR_READ_MSK GENMASK(6, 1)

drivers/iio/frequency/admv1013.c

74

#define ADMV1013_REG_ADDR_WRITE_MSK GENMASK(22, 17)

drivers/iio/frequency/admv1013.c

75

#define ADMV1013_REG_DATA_MSK GENMASK(16, 1)

drivers/iio/frequency/admv1014.c

40

#define ADMV1014_CHIP_ID_MSK GENMASK(11, 4)

drivers/iio/frequency/admv1014.c

42

#define ADMV1014_REVISION_ID_MSK GENMASK(3, 0)

drivers/iio/frequency/admv1014.c

52

#define ADMV1014_P1DB_COMPENSATION_MSK GENMASK(13, 12)

drivers/iio/frequency/admv1014.c

61

#define ADMV1014_QUAD_SE_MODE_MSK GENMASK(9, 6)

drivers/iio/frequency/admv1014.c

62

#define ADMV1014_QUAD_FILTERS_MSK GENMASK(3, 0)

drivers/iio/frequency/admv1014.c

65

#define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK GENMASK(15, 9)

drivers/iio/frequency/admv1014.c

66

#define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK GENMASK(8, 2)

drivers/iio/frequency/admv1014.c

69

#define ADMV1014_MIXER_VGATE_MSK GENMASK(15, 9)

drivers/iio/frequency/admv1014.c

70

#define ADMV1014_DET_PROG_MSK GENMASK(6, 0)

drivers/iio/frequency/admv1014.c

73

#define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK GENMASK(11, 8)

drivers/iio/frequency/admv1014.c

74

#define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK GENMASK(7, 4)

drivers/iio/frequency/admv1014.c

75

#define ADMV1014_IF_AMP_FINE_GAIN_I_MSK GENMASK(3, 0)

drivers/iio/frequency/admv1014.c

78

#define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK GENMASK(15, 12)

drivers/iio/frequency/admv1014.c

79

#define ADMV1014_BB_AMP_OFFSET_Q_MSK GENMASK(9, 5)

drivers/iio/frequency/admv1014.c

80

#define ADMV1014_BB_AMP_OFFSET_I_MSK GENMASK(4, 0)

drivers/iio/frequency/admv1014.c

83

#define ADMV1014_BB_AMP_REF_GEN_MSK GENMASK(6, 3)

drivers/iio/frequency/admv1014.c

84

#define ADMV1014_BB_AMP_GAIN_CTRL_MSK GENMASK(2, 1)

drivers/iio/frequency/admv1014.c

88

#define ADMV1014_VVA_TEMP_COMP_MSK GENMASK(15, 0)

drivers/iio/frequency/admv1014.c

92

#define ADMV1014_REG_ADDR_READ_MSK GENMASK(6, 1)

drivers/iio/frequency/admv1014.c

93

#define ADMV1014_REG_ADDR_WRITE_MSK GENMASK(22, 17)

drivers/iio/frequency/admv1014.c

94

#define ADMV1014_REG_DATA_MSK GENMASK(16, 1)

drivers/iio/frequency/admv4420.c

65

#define ADMV4420_REF_DIVIDER_MAX_VAL GENMASK(9, 0)

drivers/iio/frequency/admv4420.c

66

#define ADMV4420_N_COUNTER_INT_MAX GENMASK(15, 0)

drivers/iio/frequency/admv4420.c

67

#define ADMV4420_N_COUNTER_FRAC_MAX GENMASK(23, 0)

drivers/iio/frequency/admv4420.c

68

#define ADMV4420_N_COUNTER_MOD_MAX GENMASK(23, 0)

drivers/iio/frequency/adrf6780.c

109

*val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0);

drivers/iio/frequency/adrf6780.c

34

#define ADRF6780_CHIP_ID_MSK GENMASK(11, 4)

drivers/iio/frequency/adrf6780.c

36

#define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0)

drivers/iio/frequency/adrf6780.c

56

#define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0)

drivers/iio/frequency/adrf6780.c

60

#define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4)

drivers/iio/frequency/adrf6780.c

61

#define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0)

drivers/iio/frequency/adrf6780.c

71

#define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0)

drivers/iio/gyro/adxrs290.c

44

#define ADXRS290_SYNC_MASK GENMASK(1, 0)

drivers/iio/gyro/adxrs290.c

46

#define ADXRS290_LPF_MASK GENMASK(2, 0)

drivers/iio/gyro/adxrs290.c

48

#define ADXRS290_HPF_MASK GENMASK(7, 4)

drivers/iio/gyro/st_gyro_core.c

231

.mask = GENMASK(7, 6),

drivers/iio/gyro/st_gyro_core.c

251

.mask = GENMASK(5, 4),

drivers/iio/gyro/st_gyro_core.c

286

.mask = GENMASK(2, 0),

drivers/iio/health/afe440x.h

77

#define AFE440X_CONTROL3_CLKDIV GENMASK(2, 0)

drivers/iio/health/max30100.c

55

#define MAX30100_REG_SPO2_CONFIG_PW_MASK GENMASK(1, 0)

drivers/iio/health/max30102.c

73

#define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)

drivers/iio/health/max30102.c

78

#define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))

drivers/iio/humidity/am2315.c

28

#define AM2315_ALL_CHANNEL_MASK GENMASK(1, 0)

drivers/iio/humidity/ens210.c

140

*val = regval & GENMASK(15, 0);

drivers/iio/humidity/hdc2010.c

38

#define HDC2010_MEAS_CONF GENMASK(2, 1)

drivers/iio/humidity/hdc2010.c

41

#define HDC2010_AMM GENMASK(6, 4)

drivers/iio/humidity/hdc3020.c

350

put_unaligned_be16(val & GENMASK(13, 0), &buf[2]);

drivers/iio/humidity/hdc3020.c

55

#define HDC3020_THRESH_TEMP_MASK GENMASK(8, 0)

drivers/iio/humidity/hdc3020.c

57

#define HDC3020_THRESH_HUM_MASK GENMASK(15, 9)

drivers/iio/humidity/si7020.c

42

#define SI7020_HEATER_VAL GENMASK(3, 0)

drivers/iio/imu/adis16475.c

1609

if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X))

drivers/iio/imu/adis16475.c

48

#define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0)

drivers/iio/imu/adis16475.c

54

#define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)

drivers/iio/imu/adis16475.c

80

#define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)

drivers/iio/imu/adis16475.c

81

#define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7)

drivers/iio/imu/adis16475.c

84

#define ADIS16575_WM_LVL_MASK GENMASK(15, 4)

drivers/iio/imu/adis16480.c

123

#define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)

drivers/iio/imu/adis16480.c

129

#define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)

drivers/iio/imu/adis16480.c

136

#define ADIS16545_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)

drivers/iio/imu/adis16480.c

137

#define ADIS16545_BURST_DATA_SEL_1_CHN_MASK GENMASK(16, 11)

drivers/iio/imu/adis16550.c

268

*readval = (*readval & GENMASK(31, 16)) | data;

drivers/iio/imu/adis16550.c

269

} else if ((writeval & GENMASK(15, 0)) != data && reg != ADIS16550_REG_COMMAND) {

drivers/iio/imu/adis16550.c

29

#define ADIS16550_BURST_DATA_GYRO_ACCEL_MASK GENMASK(6, 1)

drivers/iio/imu/adis16550.c

30

#define ADIS16550_BURST_DATA_DELTA_ANG_VEL_MASK GENMASK(12, 7)

drivers/iio/imu/adis16550.c

76

#define ADIS16550_SPI_DATA_MASK GENMASK(31, 16)

drivers/iio/imu/adis16550.c

77

#define ADIS16550_SPI_REG_MASK GENMASK(14, 8)

drivers/iio/imu/adis16550.c

79

#define ADIS16550_SPI_CRC_MASK GENMASK(3, 0)

drivers/iio/imu/adis16550.c

80

#define ADIS16550_SPI_SV_MASK GENMASK(7, 6)

drivers/iio/imu/bmi160/bmi160_core.c

40

#define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0)

drivers/iio/imu/bmi160/bmi160_core.c

41

#define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4)

drivers/iio/imu/bmi160/bmi160_core.c

50

#define BMI160_GYRO_CONFIG_ODR_MASK GENMASK(3, 0)

drivers/iio/imu/bmi160/bmi160_core.c

51

#define BMI160_GYRO_CONFIG_BWP_MASK GENMASK(5, 4)

drivers/iio/imu/bmi270/bmi270_core.c

109

#define BMI270_STEP_SC26_WTRMRK_MSK GENMASK(9, 0)

drivers/iio/imu/bmi270/bmi270_core.c

113

#define BMI270_FEAT_MOTION_DURATION_MSK GENMASK(12, 0)

drivers/iio/imu/bmi270/bmi270_core.c

117

#define BMI270_FEAT_MOTION_XYZ_EN_MSK GENMASK(15, 13)

drivers/iio/imu/bmi270/bmi270_core.c

118

#define BMI270_FEAT_MOTION_THRESHOLD_MSK GENMASK(10, 0)

drivers/iio/imu/bmi270/bmi270_core.c

119

#define BMI270_FEAT_MOTION_OUT_CONF_MSK GENMASK(14, 11)

drivers/iio/imu/bmi270/bmi270_core.c

122

#define BMI270_MOTION_XYZ_MSK GENMASK(2, 0)

drivers/iio/imu/bmi270/bmi270_core.c

125

#define BMI270_MOTION_THRES_FULL_SCALE GENMASK(10, 0)

drivers/iio/imu/bmi270/bmi270_core.c

27

#define BMI270_CHIP_ID_MSK GENMASK(7, 0)

drivers/iio/imu/bmi270/bmi270_core.c

38

#define BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK GENMASK(7, 6)

drivers/iio/imu/bmi270/bmi270_core.c

43

#define BMI270_INTERNAL_STATUS_MSG_MSK GENMASK(3, 0)

drivers/iio/imu/bmi270/bmi270_core.c

53

#define BMI270_ACC_CONF_ODR_MSK GENMASK(3, 0)

drivers/iio/imu/bmi270/bmi270_core.c

55

#define BMI270_ACC_CONF_BWP_MSK GENMASK(6, 4)

drivers/iio/imu/bmi270/bmi270_core.c

60

#define BMI270_ACC_CONF_RANGE_MSK GENMASK(1, 0)

drivers/iio/imu/bmi270/bmi270_core.c

63

#define BMI270_GYR_CONF_ODR_MSK GENMASK(3, 0)

drivers/iio/imu/bmi270/bmi270_core.c

65

#define BMI270_GYR_CONF_BWP_MSK GENMASK(5, 4)

drivers/iio/imu/bmi270/bmi270_core.c

71

#define BMI270_GYR_CONF_RANGE_MSK GENMASK(2, 0)

drivers/iio/imu/bmi270/bmi270_core.c

78

#define BMI270_INT_IO_LVL_OD_OP_MSK GENMASK(3, 1)

drivers/iio/imu/bmi323/bmi323.h

100

#define BMI323_NOMOTION_MSK GENMASK(1, 0)

drivers/iio/imu/bmi323/bmi323.h

101

#define BMI323_MOTION_MSK GENMASK(3, 2)

drivers/iio/imu/bmi323/bmi323.h

102

#define BMI323_STEP_CNT_MSK GENMASK(11, 10)

drivers/iio/imu/bmi323/bmi323.h

103

#define BMI323_TAP_MSK GENMASK(1, 0)

drivers/iio/imu/bmi323/bmi323.h

104

#define BMI323_TMP_DRDY_MSK GENMASK(7, 6)

drivers/iio/imu/bmi323/bmi323.h

105

#define BMI323_GYR_DRDY_MSK GENMASK(9, 8)

drivers/iio/imu/bmi323/bmi323.h

106

#define BMI323_ACC_DRDY_MSK GENMASK(11, 10)

drivers/iio/imu/bmi323/bmi323.h

107

#define BMI323_FIFO_WTRMRK_MSK GENMASK(13, 12)

drivers/iio/imu/bmi323/bmi323.h

108

#define BMI323_FIFO_FULL_MSK GENMASK(15, 14)

drivers/iio/imu/bmi323/bmi323.h

128

#define BMI323_GEN_HOLD_DUR_MSK GENMASK(4, 1)

drivers/iio/imu/bmi323/bmi323.h

136

#define BMI323_MO1_SLOPE_TH_MSK GENMASK(11, 0)

drivers/iio/imu/bmi323/bmi323.h

137

#define BMI323_MO2_HYSTR_MSK GENMASK(9, 0)

drivers/iio/imu/bmi323/bmi323.h

138

#define BMI323_MO3_DURA_MSK GENMASK(12, 0)

drivers/iio/imu/bmi323/bmi323.h

142

#define BMI323_STEP_SC1_WTRMRK_MSK GENMASK(9, 0)

drivers/iio/imu/bmi323/bmi323.h

148

#define BMI323_TAP1_AXIS_SEL_MSK GENMASK(1, 0)

drivers/iio/imu/bmi323/bmi323.h

149

#define BMI323_AXIS_XYZ_MSK GENMASK(1, 0)

drivers/iio/imu/bmi323/bmi323.h

151

#define BMI323_TAP1_MAX_PEAKS_MSK GENMASK(5, 3)

drivers/iio/imu/bmi323/bmi323.h

152

#define BMI323_TAP1_MODE_MSK GENMASK(7, 6)

drivers/iio/imu/bmi323/bmi323.h

154

#define BMI323_TAP2_THRES_MSK GENMASK(9, 0)

drivers/iio/imu/bmi323/bmi323.h

155

#define BMI323_TAP2_MAX_DUR_MSK GENMASK(15, 10)

drivers/iio/imu/bmi323/bmi323.h

157

#define BMI323_TAP3_QUIET_TIM_MSK GENMASK(15, 12)

drivers/iio/imu/bmi323/bmi323.h

158

#define BMI323_TAP3_QT_BW_TAP_MSK GENMASK(11, 8)

drivers/iio/imu/bmi323/bmi323.h

159

#define BMI323_TAP3_QT_AFT_GES_MSK GENMASK(15, 12)

drivers/iio/imu/bmi323/bmi323.h

22

#define BMI323_CHIP_ID_MSK GENMASK(7, 0)

drivers/iio/imu/bmi323/bmi323.h

31

#define BMI323_ALL_CHAN_MSK GENMASK(5, 0)

drivers/iio/imu/bmi323/bmi323.h

44

#define BMI323_STATUS_ACC_GYR_DRDY_MSK GENMASK(13, 12)

drivers/iio/imu/bmi323/bmi323.h

50

#define BMI323_FEAT_IO0_XYZ_NOMOTION_MSK GENMASK(2, 0)

drivers/iio/imu/bmi323/bmi323.h

51

#define BMI323_FEAT_IO0_XYZ_MOTION_MSK GENMASK(5, 3)

drivers/iio/imu/bmi323/bmi323.h

52

#define BMI323_FEAT_XYZ_MSK GENMASK(2, 0)

drivers/iio/imu/bmi323/bmi323.h

57

#define BMI323_FEAT_IO1_ERR_MSK GENMASK(3, 0)

drivers/iio/imu/bmi323/bmi323.h

71

#define BMI323_ACC_GYRO_CONF_MODE_MSK GENMASK(14, 12)

drivers/iio/imu/bmi323/bmi323.h

72

#define BMI323_ACC_GYRO_CONF_ODR_MSK GENMASK(3, 0)

drivers/iio/imu/bmi323/bmi323.h

73

#define BMI323_ACC_GYRO_CONF_SCL_MSK GENMASK(6, 4)

drivers/iio/imu/bmi323/bmi323.h

75

#define BMI323_ACC_GYRO_CONF_AVG_MSK GENMASK(10, 8)

drivers/iio/imu/bmi323/bmi323.h

81

#define BMI323_FIFO_CONF_ACC_GYR_EN_MSK GENMASK(10, 9)

drivers/iio/imu/bmi323/bmi323.h

82

#define BMI323_FIFO_ACC_GYR_MSK GENMASK(1, 0)

drivers/iio/imu/bmi323/bmi323.h

91

#define BMI323_IO_INT1_LVL_OD_OP_MSK GENMASK(2, 0)

drivers/iio/imu/bmi323/bmi323.h

95

#define BMI323_IO_INT2_LVL_OD_OP_MSK GENMASK(10, 8)

drivers/iio/imu/bno055/bno055.c

103

#define BNO055_ACC_CONFIG_LPF_MASK GENMASK(4, 2)

drivers/iio/imu/bno055/bno055.c

104

#define BNO055_ACC_CONFIG_RANGE_MASK GENMASK(1, 0)

drivers/iio/imu/bno055/bno055.c

107

#define BNO055_MAG_CONFIG_ODR_MASK GENMASK(2, 0)

drivers/iio/imu/bno055/bno055.c

109

#define BNO055_GYR_CONFIG_RANGE_MASK GENMASK(2, 0)

drivers/iio/imu/bno055/bno055.c

110

#define BNO055_GYR_CONFIG_LPF_MASK GENMASK(5, 3)

drivers/iio/imu/bno055/bno055.c

1188

calib = ((val >> which) & GENMASK(1, 0)) + 1;

drivers/iio/imu/bno055/bno055.c

281

.selector_mask = GENMASK(7, 0),

drivers/iio/imu/fxos8700_core.c

148

#define FXOS8700_CTRL_ODR_MSK GENMASK(5, 3)

drivers/iio/imu/fxos8700_core.c

151

#define FXOS8700_HMS_MASK GENMASK(1, 0)

drivers/iio/imu/fxos8700_core.c

152

#define FXOS8700_OS_MASK GENMASK(4, 2)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

207

#define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

214

#define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

217

#define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

232

#define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

269

#define INV_ICM42600_INT_STATUS2_WOM_INT GENMASK(2, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

292

#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

305

FIELD_PREP(GENMASK(3, 2), (_mode))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

307

FIELD_PREP(GENMASK(1, 0), (_mode))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

311

FIELD_PREP(GENMASK(7, 5), (_fs))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

313

FIELD_PREP(GENMASK(3, 0), (_odr))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

317

FIELD_PREP(GENMASK(7, 5), (_fs))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

319

FIELD_PREP(GENMASK(3, 0), (_odr))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

323

FIELD_PREP(GENMASK(7, 4), (_f))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

325

FIELD_PREP(GENMASK(3, 0), (_f))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

328

#define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

354

cpu_to_le16((_wm) & GENMASK(11, 0))

drivers/iio/imu/inv_icm42600/inv_icm42600.h

375

#define INV_ICM42600_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

397

#define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600.h

404

#define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0)

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

25

#define INV_ICM42600_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2)

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

586

GENMASK(7, 5), val);

drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c

597

GENMASK(6, 5) | GENMASK(3, 0), val);

drivers/iio/imu/inv_icm45600/inv_icm45600.h

198

#define INV_ICM45600_DRIVE_CONFIG0_SPI_MASK GENMASK(3, 1)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

20

#define INV_ICM45600_REG_BANK_MASK GENMASK(15, 8)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

21

#define INV_ICM45600_REG_ADDR_MASK GENMASK(7, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

214

#define INV_ICM45600_FIFO_CONFIG0_MODE_MASK GENMASK(7, 6)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

218

#define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MASK GENMASK(5, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

266

#define INV_ICM45600_PWR_MGMT0_GYRO_MODE_MASK GENMASK(3, 2)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

267

#define INV_ICM45600_PWR_MGMT0_ACCEL_MODE_MASK GENMASK(1, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

270

#define INV_ICM45600_ACCEL_CONFIG0_FS_MASK GENMASK(6, 4)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

271

#define INV_ICM45600_ACCEL_CONFIG0_ODR_MASK GENMASK(3, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

273

#define INV_ICM45600_GYRO_CONFIG0_FS_MASK GENMASK(7, 4)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

274

#define INV_ICM45600_GYRO_CONFIG0_ODR_MASK GENMASK(3, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

310

#define INV_ICM45600_GYRO_OFFUSER_MASK GENMASK(13, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

313

#define INV_ICM45600_IPREG_SYS1_170_GYRO_LP_AVG_MASK GENMASK(4, 1)

drivers/iio/imu/inv_icm45600/inv_icm45600.h

320

#define INV_ICM45600_ACCEL_OFFUSER_MASK GENMASK(13, 0)

drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c

29

#define INV_ICM45600_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2)

drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

270

#define INV_ICM20608_BIT_WOM_INT_EN GENMASK(7, 5)

drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

278

#define INV_ICM20608_BIT_WOM_INT GENMASK(7, 5)

drivers/iio/imu/smi240.c

27

#define SMI240_SOFT_CONFIG_BITE_REP_MASK GENMASK(6, 4)

drivers/iio/imu/smi240.c

47

#define SMI240_CRC_MASK GENMASK(2, 0)

drivers/iio/imu/smi240.c

50

#define SMI240_READ_DATA_MASK GENMASK(19, 4)

drivers/iio/imu/smi240.c

53

#define SMI240_WRITE_BUS_ID_MASK GENMASK(31, 30)

drivers/iio/imu/smi240.c

54

#define SMI240_WRITE_ADDR_MASK GENMASK(29, 22)

drivers/iio/imu/smi240.c

57

#define SMI240_WRITE_DATA_MASK GENMASK(18, 3)

drivers/iio/imu/smi330/smi330_core.c

40

#define SMI330_CHIP_ID_MASK GENMASK(7, 0)

drivers/iio/imu/smi330/smi330_core.c

45

#define SMI330_INT_STATUS_ACC_GYR_DRDY_MASK GENMASK(13, 12)

drivers/iio/imu/smi330/smi330_core.c

46

#define SMI330_CFG_ODR_MASK GENMASK(3, 0)

drivers/iio/imu/smi330/smi330_core.c

47

#define SMI330_CFG_RANGE_MASK GENMASK(6, 4)

drivers/iio/imu/smi330/smi330_core.c

49

#define SMI330_CFG_AVG_NUM_MASK GENMASK(10, 8)

drivers/iio/imu/smi330/smi330_core.c

50

#define SMI330_CFG_MODE_MASK GENMASK(14, 12)

drivers/iio/imu/smi330/smi330_core.c

51

#define SMI330_IO_INT_CTRL_INT1_MASK GENMASK(2, 0)

drivers/iio/imu/smi330/smi330_core.c

52

#define SMI330_IO_INT_CTRL_INT2_MASK GENMASK(10, 8)

drivers/iio/imu/smi330/smi330_core.c

54

#define SMI330_INT_MAP2_ACC_DRDY_MASK GENMASK(11, 10)

drivers/iio/imu/smi330/smi330_core.c

55

#define SMI330_INT_MAP2_GYR_DRDY_MASK GENMASK(9, 8)

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c

68

#define ST_LSM6DSX_FIFO_MODE_MASK GENMASK(2, 0)

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c

69

#define ST_LSM6DSX_FIFO_ODR_MASK GENMASK(6, 3)

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1000

.mask = GENMASK(8, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1004

.mask = GENMASK(9, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1016

.mask = GENMASK(7, 6),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1039

.mask = GENMASK(1, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1063

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1123

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1137

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1153

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1164

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1204

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1208

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1216

.mask = GENMASK(8, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1220

.mask = GENMASK(9, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1232

.mask = GENMASK(7, 6),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1247

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1303

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1318

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1335

.mask = GENMASK(1, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1346

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1382

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1386

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1394

.mask = GENMASK(7, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1398

.mask = GENMASK(8, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1410

.mask = GENMASK(7, 6),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1432

.mask = GENMASK(1, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1456

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1470

.mask = GENMASK(4, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1474

.mask = GENMASK(4, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1478

.mask = GENMASK(4, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1534

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1548

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1564

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1575

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

1611

.mask = GENMASK(1, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

195

.mask = GENMASK(7, 5),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

208

.mask = GENMASK(7, 5),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

223

.mask = GENMASK(4, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

234

.mask = GENMASK(4, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

299

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

312

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

327

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

338

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

374

.mask = GENMASK(2, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

378

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

386

.mask = GENMASK(11, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

390

.mask = GENMASK(11, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

410

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

418

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

466

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

479

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

494

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

505

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

541

.mask = GENMASK(2, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

545

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

553

.mask = GENMASK(11, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

557

.mask = GENMASK(11, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

577

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

585

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

645

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

658

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

673

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

684

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

738

.mask = GENMASK(2, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

742

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

746

.mask = GENMASK(2, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

754

.mask = GENMASK(10, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

758

.mask = GENMASK(10, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

778

.mask = GENMASK(5, 3),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

796

.mask = GENMASK(5, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

823

.mask = GENMASK(5, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

907

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

921

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

937

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

948

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

988

.mask = GENMASK(3, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

992

.mask = GENMASK(7, 4),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

102

.mask = GENMASK(4, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

117

.mask = GENMASK(6, 5),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

140

.mask = GENMASK(1, 0),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

37

#define ST_LS6DSX_READ_OP_MASK GENMASK(2, 0)

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

51

.mask = GENMASK(3, 2),

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c

73

.mask = GENMASK(1, 0),

drivers/iio/light/adux1020.c

48

#define ADUX1020_CHIP_ID_MASK GENMASK(11, 0)

drivers/iio/light/adux1020.c

53

#define ADUX1020_OP_MODE_MASK GENMASK(3, 0)

drivers/iio/light/adux1020.c

54

#define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4)

drivers/iio/light/adux1020.c

57

#define ADUX1020_MODE_INT_MASK GENMASK(7, 0)

drivers/iio/light/adux1020.c

65

#define ADUX1020_MODE_INT_STATUS_MASK GENMASK(7, 0)

drivers/iio/light/adux1020.c

66

#define ADUX1020_FIFO_STATUS_MASK GENMASK(15, 8)

drivers/iio/light/adux1020.c

77

#define ADUX1020_PROX_FREQ_MASK GENMASK(7, 4)

drivers/iio/light/adux1020.c

80

#define ADUX1020_LED_CURRENT_MASK GENMASK(3, 0)

drivers/iio/light/al3000a.c

22

#define AL3000A_GAIN_MASK GENMASK(5, 0)

drivers/iio/light/al3010.c

33

#define AL3010_GAIN_MASK GENMASK(6,4)

drivers/iio/light/al3320a.c

42

#define AL3320A_GAIN_MASK GENMASK(2, 1)

drivers/iio/light/as73211.c

52

#define AS73211_OSR_DOS_MASK GENMASK(2, 0)

drivers/iio/light/as73211.c

56

#define AS73211_AGEN_DEVID_MASK GENMASK(7, 4)

drivers/iio/light/as73211.c

58

#define AS73211_AGEN_MUT_MASK GENMASK(3, 0)

drivers/iio/light/as73211.c

61

#define AS73211_CREG1_GAIN_MASK GENMASK(7, 4)

drivers/iio/light/as73211.c

63

#define AS73211_CREG1_TIME_MASK GENMASK(3, 0)

drivers/iio/light/as73211.c

65

#define AS73211_CREG3_CCLK_MASK GENMASK(1, 0)

drivers/iio/light/bh1745.c

33

#define BH1745_SYS_CTRL_PART_ID_MASK GENMASK(5, 0)

drivers/iio/light/bh1745.c

38

#define BH1745_CTRL1_MEASUREMENT_TIME_MASK GENMASK(2, 0)

drivers/iio/light/bh1745.c

43

#define BH1745_CTRL2_ADC_GAIN_MASK GENMASK(1, 0)

drivers/iio/light/bh1745.c

48

#define BH1745_INTR_SOURCE_MASK GENMASK(3, 2)

drivers/iio/light/bh1780.c

29

#define BH1780_REVMASK GENMASK(3,0)

drivers/iio/light/bh1780.c

30

#define BH1780_POWMASK GENMASK(1,0)

drivers/iio/light/cm32181.c

153

cm32181->init_regs_bitmap &= GENMASK(count - 1, 0);

drivers/iio/light/cm3323.c

29

#define CM3323_CONF_IT_MASK GENMASK(6, 4)

drivers/iio/light/gp2ap002.c

82

#define GP2AP002_HYS_HYSC_MASK GENMASK(6, 5)

drivers/iio/light/gp2ap002.c

84

#define GP2AP002_HYS_HYSF_MASK GENMASK(3, 0)

drivers/iio/light/gp2ap002.c

95

#define GP2AP002_CYCLE_CYCL_MASK GENMASK(5, 3)

drivers/iio/light/iqs621-als.c

20

#define IQS621_ALS_FLAGS_RANGE GENMASK(3, 0)

drivers/iio/light/isl29125.c

37

#define ISL29125_MODE_MASK GENMASK(2, 0)

drivers/iio/light/isl76682.c

32

#define ISL76682_COMMAND_RANGE_LUX_MASK GENMASK(1, 0)

drivers/iio/light/ltr390.c

59

#define LTR390_ALS_UVS_GAIN_MASK GENMASK(2, 0)

drivers/iio/light/ltr390.c

60

#define LTR390_ALS_UVS_MEAS_RATE_MASK GENMASK(2, 0)

drivers/iio/light/ltr390.c

61

#define LTR390_ALS_UVS_INT_TIME_MASK GENMASK(6, 4)

drivers/iio/light/ltr390.c

63

#define LTR390_INT_PST_MASK GENMASK(7, 4)

drivers/iio/light/max44009.c

38

#define MAX44009_CFG_TIM_MASK GENMASK(2, 0)

drivers/iio/light/opt4001.c

26

#define OPT4001_EXPONENT_MASK GENMASK(15, 12)

drivers/iio/light/opt4001.c

27

#define OPT4001_MSB_MASK GENMASK(11, 0)

drivers/iio/light/opt4001.c

28

#define OPT4001_LSB_MASK GENMASK(15, 8)

drivers/iio/light/opt4001.c

29

#define OPT4001_COUNTER_MASK GENMASK(7, 4)

drivers/iio/light/opt4001.c

30

#define OPT4001_CRC_MASK GENMASK(3, 0)

drivers/iio/light/opt4001.c

33

#define OPT4001_DEVICE_ID_MASK GENMASK(11, 0)

drivers/iio/light/opt4001.c

36

#define OPT4001_CTRL_QWAKE_MASK GENMASK(15, 15)

drivers/iio/light/opt4001.c

37

#define OPT4001_CTRL_RANGE_MASK GENMASK(13, 10)

drivers/iio/light/opt4001.c

38

#define OPT4001_CTRL_CONV_TIME_MASK GENMASK(9, 6)

drivers/iio/light/opt4001.c

39

#define OPT4001_CTRL_OPER_MODE_MASK GENMASK(5, 4)

drivers/iio/light/opt4001.c

40

#define OPT4001_CTRL_LATCH_MASK GENMASK(3, 3)

drivers/iio/light/opt4001.c

41

#define OPT4001_CTRL_INT_POL_MASK GENMASK(2, 2)

drivers/iio/light/opt4001.c

42

#define OPT4001_CTRL_FAULT_COUNT GENMASK(0, 1)

drivers/iio/light/opt4060.c

43

#define OPT4060_EXPONENT_MASK GENMASK(15, 12)

drivers/iio/light/opt4060.c

44

#define OPT4060_MSB_MASK GENMASK(11, 0)

drivers/iio/light/opt4060.c

45

#define OPT4060_LSB_MASK GENMASK(15, 8)

drivers/iio/light/opt4060.c

46

#define OPT4060_COUNTER_MASK GENMASK(7, 4)

drivers/iio/light/opt4060.c

47

#define OPT4060_CRC_MASK GENMASK(3, 0)

drivers/iio/light/opt4060.c

50

#define OPT4060_DEVICE_ID_MASK GENMASK(11, 0)

drivers/iio/light/opt4060.c

54

#define OPT4060_CTRL_RANGE_MASK GENMASK(13, 10)

drivers/iio/light/opt4060.c

55

#define OPT4060_CTRL_CONV_TIME_MASK GENMASK(9, 6)

drivers/iio/light/opt4060.c

56

#define OPT4060_CTRL_OPER_MODE_MASK GENMASK(5, 4)

drivers/iio/light/opt4060.c

59

#define OPT4060_CTRL_FAULT_COUNT_MASK GENMASK(1, 0)

drivers/iio/light/opt4060.c

62

#define OPT4060_INT_CTRL_THRESH_SEL GENMASK(6, 5)

drivers/iio/light/opt4060.c

64

#define OPT4060_INT_CTRL_INT_CFG GENMASK(3, 2)

drivers/iio/light/pa12203001.c

37

#define PA12203001_PX_NORMAL_MODE_MASK GENMASK(7, 6)

drivers/iio/light/pa12203001.c

38

#define PA12203001_AFSR_MASK GENMASK(5, 4)

drivers/iio/light/rohm-bu27034.c

26

#define BU27034_MASK_PART_ID GENMASK(5, 0)

drivers/iio/light/rohm-bu27034.c

29

#define BU27034_MASK_MEAS_MODE GENMASK(2, 0)

drivers/iio/light/rohm-bu27034.c

32

#define BU27034_MASK_D01_GAIN GENMASK(7, 3)

drivers/iio/light/rohm-bu27034.c

93

GENMASK(BU27034_CHAN_DATA1, BU27034_CHAN_DATA0),

drivers/iio/light/rohm-bu27034.c

94

GENMASK(BU27034_CHAN_DATA1, BU27034_CHAN_ALS), 0

drivers/iio/light/rpr0521.c

41

#define RPR0521_MODE_MEAS_TIME_MASK GENMASK(3, 0)

drivers/iio/light/rpr0521.c

42

#define RPR0521_ALS_DATA0_GAIN_MASK GENMASK(5, 4)

drivers/iio/light/rpr0521.c

44

#define RPR0521_ALS_DATA1_GAIN_MASK GENMASK(3, 2)

drivers/iio/light/rpr0521.c

46

#define RPR0521_PXS_GAIN_MASK GENMASK(5, 4)

drivers/iio/light/rpr0521.c

48

#define RPR0521_PXS_PERSISTENCE_MASK GENMASK(3, 0)

drivers/iio/light/si1133.c

69

#define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (x & GENMASK(2, 0)) << 3

drivers/iio/light/tcs3414.c

43

#define TCS3414_INTEG_MASK GENMASK(1, 0)

drivers/iio/light/tcs3414.c

48

#define TCS3414_GAIN_MASK GENMASK(5, 4)

drivers/iio/light/tsl2563.c

58

#define TSL2563_CTRL_POWER_MASK GENMASK(1, 0)

drivers/iio/light/tsl2563.c

63

#define TSL2563_TIMING_MASK GENMASK(1, 0)

drivers/iio/light/tsl2563.c

69

#define TSL2563_INT_MASK GENMASK(5, 4)

drivers/iio/light/tsl2563.c

70

#define TSL2563_INT_PERSIST(n) ((n) & GENMASK(3, 0))

drivers/iio/light/tsl2591.c

105

#define TSL2591_PACKAGE_ID_MASK GENMASK(5, 4)

drivers/iio/light/tsl2591.c

108

#define TSL2591_DEVICE_ID_MASK GENMASK(7, 0)

drivers/iio/light/us5182d.c

79

#define US5182D_OPMODE_MASK GENMASK(5, 4)

drivers/iio/light/vcnl4000.c

87

#define VCNL4040_ALS_CONF_IT GENMASK(7, 6) /* Ambient integration time */

drivers/iio/light/vcnl4000.c

89

#define VCNL4040_ALS_CONF_PERS GENMASK(3, 2) /* Ambient interrupt persistence setting */

drivers/iio/light/vcnl4000.c

91

#define VCNL4040_PS_CONF2_PS_IT GENMASK(3, 1) /* Proximity integration time */

drivers/iio/light/vcnl4000.c

92

#define VCNL4040_CONF1_PS_PERS GENMASK(5, 4) /* Proximity interrupt persistence setting */

drivers/iio/light/vcnl4000.c

94

#define VCNL4040_PS_CONF2_PS_INT GENMASK(9, 8) /* Proximity interrupt mode */

drivers/iio/light/vcnl4000.c

95

#define VCNL4040_PS_CONF3_MPS GENMASK(6, 5) /* Proximity multi pulse number */

drivers/iio/light/vcnl4000.c

96

#define VCNL4040_PS_MS_LED_I GENMASK(10, 8) /* Proximity current */

drivers/iio/light/vcnl4035.c

40

#define VCNL4035_ALS_IT_MASK GENMASK(7, 5)

drivers/iio/light/vcnl4035.c

41

#define VCNL4035_ALS_PERS_MASK GENMASK(3, 2)

drivers/iio/light/vcnl4035.c

44

#define VCNL4035_DEV_ID_MASK GENMASK(7, 0)

drivers/iio/light/veml6030.c

47

#define VEML6030_ALS_IT GENMASK(9, 6)

drivers/iio/light/veml6030.c

48

#define VEML6030_PSM GENMASK(2, 1)

drivers/iio/light/veml6030.c

49

#define VEML6030_ALS_PERS GENMASK(5, 4)

drivers/iio/light/veml6030.c

50

#define VEML6030_ALS_GAIN GENMASK(12, 11)

drivers/iio/light/veml6030.c

57

#define VEML6035_GAIN_M GENMASK(12, 10)

drivers/iio/light/veml6040.c

29

#define VEML6040_CONF_IT_MSK GENMASK(6, 4)

drivers/iio/light/veml6046x00.c

50

#define VEML6046X00_CONF0_IT GENMASK(6, 4)

drivers/iio/light/veml6046x00.c

52

#define VEML6046X00_CONF1_PERS GENMASK(2, 1)

drivers/iio/light/veml6046x00.c

53

#define VEML6046X00_CONF1_GAIN GENMASK(4, 3)

drivers/iio/light/veml6070.c

29

#define VEML6070_COMMAND_IT GENMASK(3, 2) /* bit mask integration time */

drivers/iio/light/veml6075.c

28

#define VEML6075_CONF_IT GENMASK(6, 4) /* intregration time */

drivers/iio/magnetometer/als31300.c

322

static const unsigned long als31300_scan_masks[] = { GENMASK(3, 0), 0 };

drivers/iio/magnetometer/als31300.c

43

#define ALS31300_VOL_MODE_LPDCM GENMASK(6, 4)

drivers/iio/magnetometer/als31300.c

52

#define ALS31300_VOL_MODE_SLEEP GENMASK(1, 0)

drivers/iio/magnetometer/als31300.c

57

#define ALS31300_VOL_MSB_TEMPERATURE GENMASK(5, 0)

drivers/iio/magnetometer/als31300.c

60

#define ALS31300_VOL_MSB_Z_AXIS GENMASK(15, 8)

drivers/iio/magnetometer/als31300.c

61

#define ALS31300_VOL_MSB_Y_AXIS GENMASK(23, 16)

drivers/iio/magnetometer/als31300.c

62

#define ALS31300_VOL_MSB_X_AXIS GENMASK(31, 24)

drivers/iio/magnetometer/als31300.c

64

#define ALS31300_VOL_LSB_TEMPERATURE GENMASK(5, 0)

drivers/iio/magnetometer/als31300.c

65

#define ALS31300_VOL_LSB_HALL_STATUS GENMASK(7, 7)

drivers/iio/magnetometer/als31300.c

66

#define ALS31300_VOL_LSB_Z_AXIS GENMASK(11, 8)

drivers/iio/magnetometer/als31300.c

67

#define ALS31300_VOL_LSB_Y_AXIS GENMASK(15, 12)

drivers/iio/magnetometer/als31300.c

68

#define ALS31300_VOL_LSB_X_AXIS GENMASK(19, 16)

drivers/iio/magnetometer/bmc150_magn.c

52

#define BMC150_MAGN_MASK_OPMODE GENMASK(2, 1)

drivers/iio/magnetometer/bmc150_magn.c

57

#define BMC150_MAGN_MASK_ODR GENMASK(5, 3)

drivers/iio/magnetometer/bmc150_magn.c

77

#define BMC150_MAGN_REG_REP_DATAMASK GENMASK(7, 0)

drivers/iio/magnetometer/mag3110.c

42

#define MAG3110_SYSMOD_MODE_MASK GENMASK(1, 0)

drivers/iio/magnetometer/mmc5633.c

65

#define MMC5633_CTRL1_BW_MASK GENMASK(1, 0)

drivers/iio/magnetometer/si7210.c

201

*val = dspsig & GENMASK(14, 0);

drivers/iio/magnetometer/si7210.c

219

temp = FIELD_GET(GENMASK(14, 3), dspsig);

drivers/iio/magnetometer/si7210.c

31

#define SI7210_MASK_DSPSIGSEL GENMASK(2, 0)

drivers/iio/magnetometer/st_magn_core.c

435

.mask = GENMASK(4, 2),

drivers/iio/magnetometer/st_magn_core.c

447

.mask = GENMASK(1, 0),

drivers/iio/magnetometer/st_magn_core.c

453

.mask = GENMASK(6, 5),

drivers/iio/magnetometer/st_magn_core.c

492

.mask = GENMASK(2, 0),

drivers/iio/magnetometer/tlv493d.c

414

static const unsigned long tlv493d_scan_masks[] = { GENMASK(3, 0), 0 };

drivers/iio/magnetometer/tlv493d.c

62

#define TLV493D_BX_MAG_X_AXIS_MSB GENMASK(7, 0)

drivers/iio/magnetometer/tlv493d.c

63

#define TLV493D_BX2_MAG_X_AXIS_LSB GENMASK(7, 4)

drivers/iio/magnetometer/tlv493d.c

64

#define TLV493D_BY_MAG_Y_AXIS_MSB GENMASK(7, 0)

drivers/iio/magnetometer/tlv493d.c

65

#define TLV493D_BX2_MAG_Y_AXIS_LSB GENMASK(3, 0)

drivers/iio/magnetometer/tlv493d.c

66

#define TLV493D_BZ_MAG_Z_AXIS_MSB GENMASK(7, 0)

drivers/iio/magnetometer/tlv493d.c

67

#define TLV493D_BZ2_MAG_Z_AXIS_LSB GENMASK(3, 0)

drivers/iio/magnetometer/tlv493d.c

68

#define TLV493D_TEMP_TEMP_MSB GENMASK(7, 4)

drivers/iio/magnetometer/tlv493d.c

69

#define TLV493D_TEMP2_TEMP_LSB GENMASK(7, 0)

drivers/iio/magnetometer/tlv493d.c

70

#define TLV493D_TEMP_CHANNEL GENMASK(1, 0)

drivers/iio/magnetometer/tlv493d.c

71

#define TLV493D_MODE1_MOD_LOWFAST GENMASK(1, 0)

drivers/iio/magnetometer/tlv493d.c

73

#define TLV493D_RD_REG_RES1_WR_MASK GENMASK(4, 3)

drivers/iio/magnetometer/tlv493d.c

74

#define TLV493D_RD_REG_RES2_WR_MASK GENMASK(7, 0)

drivers/iio/magnetometer/tlv493d.c

75

#define TLV493D_RD_REG_RES3_WR_MASK GENMASK(4, 0)

drivers/iio/magnetometer/tmag5273.c

62

#define TMAG5273_AVG_MODE_MASK GENMASK(4, 2)

drivers/iio/magnetometer/tmag5273.c

71

#define TMAG5273_OP_MODE_MASK GENMASK(1, 0)

drivers/iio/magnetometer/tmag5273.c

78

#define TMAG5273_MAG_CH_EN_MASK GENMASK(7, 4)

drivers/iio/magnetometer/tmag5273.c

84

#define TMAG5273_ANGLE_EN_MASK GENMASK(3, 2)

drivers/iio/magnetometer/tmag5273.c

94

#define TMAG5273_VERSION_MASK GENMASK(1, 0)

drivers/iio/magnetometer/yamaha-yas530.c

1099

c->Cx = FIELD_GET(GENMASK(31, 23), val1) - 256;

drivers/iio/magnetometer/yamaha-yas530.c

1100

c->Cy1 = FIELD_GET(GENMASK(22, 14), val1) - 256;

drivers/iio/magnetometer/yamaha-yas530.c

1101

c->Cy2 = FIELD_GET(GENMASK(13, 5), val1) - 256;

drivers/iio/magnetometer/yamaha-yas530.c

1102

c->a2 = FIELD_GET(GENMASK(28, 22), val2) - 64;

drivers/iio/magnetometer/yamaha-yas530.c

1103

c->a3 = FIELD_GET(GENMASK(21, 15), val2) - 64;

drivers/iio/magnetometer/yamaha-yas530.c

1104

c->a4 = FIELD_GET(GENMASK(14, 7), val2) - 128;

drivers/iio/magnetometer/yamaha-yas530.c

1105

c->a5 = FIELD_GET(GENMASK(30, 22), val3) - 112;

drivers/iio/magnetometer/yamaha-yas530.c

1106

c->a6 = FIELD_GET(GENMASK(21, 15), val3) - 64;

drivers/iio/magnetometer/yamaha-yas530.c

1107

c->a7 = FIELD_GET(GENMASK(14, 7), val3) - 128;

drivers/iio/magnetometer/yamaha-yas530.c

1108

c->a8 = FIELD_GET(GENMASK(30, 24), val4) - 64;

drivers/iio/magnetometer/yamaha-yas530.c

1109

c->a9 = FIELD_GET(GENMASK(23, 15), val4) - 112;

drivers/iio/magnetometer/yamaha-yas530.c

1110

c->k = FIELD_GET(GENMASK(14, 8), val4);

drivers/iio/magnetometer/yamaha-yas530.c

120

#define YAS537_MAG_AVERAGE_32_MASK GENMASK(6, 4)

drivers/iio/magnetometer/yamaha-yas530.c

124

#define YAS537_MTC3_MASK_PREP GENMASK(7, 0)

drivers/iio/magnetometer/yamaha-yas530.c

125

#define YAS537_MTC3_MASK_GET GENMASK(7, 5)

drivers/iio/magnetometer/yamaha-yas530.c

127

#define YAS537_HCK_MASK_PREP GENMASK(4, 0)

drivers/iio/magnetometer/yamaha-yas530.c

128

#define YAS537_HCK_MASK_GET GENMASK(7, 4)

drivers/iio/magnetometer/yamaha-yas530.c

129

#define YAS537_LCK_MASK_PREP GENMASK(4, 0)

drivers/iio/magnetometer/yamaha-yas530.c

1292

buf = cpu_to_be16(GENMASK(9, 3));

drivers/iio/magnetometer/yamaha-yas530.c

1296

ret = regmap_write(yas5xx->map, YAS537_TRM, GENMASK(7, 0));

drivers/iio/magnetometer/yamaha-yas530.c

130

#define YAS537_LCK_MASK_GET GENMASK(3, 0)

drivers/iio/magnetometer/yamaha-yas530.c

131

#define YAS537_OC_MASK_GET GENMASK(5, 0)

drivers/iio/magnetometer/yamaha-yas530.c

254

val = FIELD_GET(GENMASK(14, 3), val);

drivers/iio/magnetometer/yamaha-yas530.c

269

val = FIELD_GET(GENMASK(14, 2), val);

drivers/iio/magnetometer/yamaha-yas530.c

326

val = FIELD_GET(GENMASK(14, 6), val);

drivers/iio/magnetometer/yamaha-yas530.c

340

val = FIELD_GET(GENMASK(14, 5), val);

drivers/iio/magnetometer/yamaha-yas530.c

403

xy1y2[0] = FIELD_GET(GENMASK(13, 0), get_unaligned_be16(&data[2]));

drivers/iio/magnetometer/yamaha-yas530.c

742

static const unsigned long yas5xx_scan_masks[] = { GENMASK(3, 0), 0 };

drivers/iio/magnetometer/yamaha-yas530.c

839

yas5xx->version = data[15] & GENMASK(1, 0);

drivers/iio/magnetometer/yamaha-yas530.c

84

#define YAS5XX_CONFIG_CCK_MASK GENMASK(4, 2)

drivers/iio/magnetometer/yamaha-yas530.c

859

c->f[0] = FIELD_GET(GENMASK(22, 21), val);

drivers/iio/magnetometer/yamaha-yas530.c

860

c->f[1] = FIELD_GET(GENMASK(14, 13), val);

drivers/iio/magnetometer/yamaha-yas530.c

861

c->f[2] = FIELD_GET(GENMASK(6, 5), val);

drivers/iio/magnetometer/yamaha-yas530.c

862

c->r[0] = sign_extend32(FIELD_GET(GENMASK(28, 23), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

863

c->r[1] = sign_extend32(FIELD_GET(GENMASK(20, 15), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

864

c->r[2] = sign_extend32(FIELD_GET(GENMASK(12, 7), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

914

c->f[0] = FIELD_GET(GENMASK(24, 23), val);

drivers/iio/magnetometer/yamaha-yas530.c

915

c->f[1] = FIELD_GET(GENMASK(16, 15), val);

drivers/iio/magnetometer/yamaha-yas530.c

916

c->f[2] = FIELD_GET(GENMASK(8, 7), val);

drivers/iio/magnetometer/yamaha-yas530.c

917

c->r[0] = sign_extend32(FIELD_GET(GENMASK(30, 25), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

918

c->r[1] = sign_extend32(FIELD_GET(GENMASK(22, 17), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

919

c->r[2] = sign_extend32(FIELD_GET(GENMASK(14, 7), val), 5);

drivers/iio/magnetometer/yamaha-yas530.c

943

if (!memchr_inv(data, 0x00, 16) && !FIELD_GET(GENMASK(5, 0), data[16]))

drivers/iio/magnetometer/yamaha-yas530.c

950

yas5xx->version = FIELD_GET(GENMASK(7, 6), data[16]);

drivers/iio/potentiometer/ad5110.c

144

data->tol = data->cfg->kohms * (val & GENMASK(6, 0)) * 10 / 8;

drivers/iio/pressure/bmp280.h

105

#define BMP580_DSP_IIR_PRESS_MASK GENMASK(5, 3)

drivers/iio/pressure/bmp280.h

106

#define BMP580_DSP_IIR_TEMP_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

116

#define BMP580_NVM_ROW_ADDR_MASK GENMASK(5, 0)

drivers/iio/pressure/bmp280.h

159

#define BMP380_FILTER_MASK GENMASK(3, 1)

drivers/iio/pressure/bmp280.h

169

#define BMP380_OSRS_TEMP_MASK GENMASK(5, 3)

drivers/iio/pressure/bmp280.h

170

#define BMP380_OSRS_PRESS_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

172

#define BMP380_ODRS_MASK GENMASK(4, 0)

drivers/iio/pressure/bmp280.h

174

#define BMP380_CTRL_SENSORS_MASK GENMASK(1, 0)

drivers/iio/pressure/bmp280.h

177

#define BMP380_MODE_MASK GENMASK(5, 4)

drivers/iio/pressure/bmp280.h

189

#define BMP380_INT_CTRL_SETTINGS_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

225

#define BMP280_MEAS_TRIM_MASK GENMASK(24, 4)

drivers/iio/pressure/bmp280.h

244

#define BMP280_FILTER_MASK GENMASK(4, 2)

drivers/iio/pressure/bmp280.h

251

#define BMP280_OSRS_TEMP_MASK GENMASK(7, 5)

drivers/iio/pressure/bmp280.h

259

#define BMP280_OSRS_PRESS_MASK GENMASK(4, 2)

drivers/iio/pressure/bmp280.h

267

#define BMP280_MODE_MASK GENMASK(1, 0)

drivers/iio/pressure/bmp280.h

290

#define BME280_COMP_H4_GET_MASK_UP GENMASK(15, 8)

drivers/iio/pressure/bmp280.h

291

#define BME280_COMP_H4_PREP_MASK_UP GENMASK(11, 4)

drivers/iio/pressure/bmp280.h

292

#define BME280_COMP_H4_MASK_LOW GENMASK(3, 0)

drivers/iio/pressure/bmp280.h

293

#define BME280_COMP_H5_MASK GENMASK(15, 4)

drivers/iio/pressure/bmp280.h

297

#define BME280_OSRS_HUMIDITY_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

313

#define BMP180_MEAS_CTRL_MASK GENMASK(4, 0)

drivers/iio/pressure/bmp280.h

317

#define BMP180_OSRS_PRESS_MASK GENMASK(7, 6)

drivers/iio/pressure/bmp280.h

63

#define BMP580_INT_CONFIG_MASK GENMASK(3, 0)

drivers/iio/pressure/bmp280.h

74

#define BMP580_OSR_PRESS_MASK GENMASK(5, 3)

drivers/iio/pressure/bmp280.h

75

#define BMP580_OSR_TEMP_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

77

#define BMP580_EFF_OSR_PRESS_MASK GENMASK(5, 3)

drivers/iio/pressure/bmp280.h

78

#define BMP580_EFF_OSR_TEMP_MASK GENMASK(2, 0)

drivers/iio/pressure/bmp280.h

81

#define BMP580_ODR_MASK GENMASK(6, 2)

drivers/iio/pressure/bmp280.h

82

#define BMP580_MODE_MASK GENMASK(1, 0)

drivers/iio/pressure/bmp280.h

89

#define BMP580_DSP_COMP_MASK GENMASK(1, 0)

drivers/iio/pressure/dps310.c

131

c1 = ((coef[1] & GENMASK(3, 0)) << 8) | coef[2];

drivers/iio/pressure/dps310.c

142

c10 = ((coef[5] & GENMASK(3, 0)) << 16) | (coef[6] << 8) | coef[7];

drivers/iio/pressure/dps310.c

267

*val = BIT(reg_val & GENMASK(2, 0));

drivers/iio/pressure/dps310.c

284

*val = BIT(reg_val & GENMASK(2, 0));

drivers/iio/pressure/dps310.c

35

#define DPS310_PRS_RATE_BITS GENMASK(6, 4)

drivers/iio/pressure/dps310.c

36

#define DPS310_PRS_PRC_BITS GENMASK(3, 0)

drivers/iio/pressure/dps310.c

38

#define DPS310_TMP_RATE_BITS GENMASK(6, 4)

drivers/iio/pressure/dps310.c

389

*val = scale_factors[reg_val & GENMASK(2, 0)];

drivers/iio/pressure/dps310.c

39

#define DPS310_TMP_PRC_BITS GENMASK(3, 0)

drivers/iio/pressure/dps310.c

402

*val = scale_factors[reg_val & GENMASK(2, 0)];

drivers/iio/pressure/dps310.c

42

#define DPS310_MEAS_CTRL_BITS GENMASK(2, 0)

drivers/iio/pressure/hp206c.c

103

return get_unaligned_be24(&values[0]) & GENMASK(19, 0);

drivers/iio/pressure/hsc030pa.c

41

#define HSC_STATUS_MASK GENMASK(7, 6)

drivers/iio/pressure/hsc030pa.c

42

#define HSC_TEMPERATURE_MASK GENMASK(15, 5)

drivers/iio/pressure/hsc030pa.c

43

#define HSC_PRESSURE_MASK GENMASK(29, 16)

drivers/iio/pressure/mpl3115.c

53

#define MPL3115_PT_DATA_EVENT_ALL GENMASK(2, 0)

drivers/iio/pressure/mpl3115.c

58

#define MPL3115_CTRL1_OS_258MS GENMASK(5, 4) /* 64x oversampling */

drivers/iio/pressure/mpl3115.c

60

#define MPL3115_CTRL2_ST GENMASK(3, 0)

drivers/iio/pressure/rohm-bm1390.c

34

#define BM1390_MASK_MEAS_MODE GENMASK(1, 0)

drivers/iio/pressure/rohm-bm1390.c

37

#define BM1390_MASK_AVE_NUM GENMASK(7, 5)

drivers/iio/pressure/rohm-bm1390.c

45

#define BM1390_MASK_IIR_MODE GENMASK(1, 0)

drivers/iio/pressure/rohm-bm1390.c

57

#define BM1390_MASK_FIFO_LVL GENMASK(2, 0)

drivers/iio/proximity/aw96103.c

46

#define AW96103_THHYST_MASK GENMASK(13, 12)

drivers/iio/proximity/aw96103.c

47

#define AW96103_INDEB_MASK GENMASK(11, 10)

drivers/iio/proximity/aw96103.c

48

#define AW96103_OUTDEB_MASK GENMASK(9, 8)

drivers/iio/proximity/aw96103.c

51

#define AW96103_BLRSTRNG_MASK GENMASK(5, 0)

drivers/iio/proximity/aw96103.c

52

#define AW96103_CHIPID_MASK GENMASK(31, 16)

drivers/iio/proximity/aw96103.c

54

#define AW96103_CHAN_EN_MASK GENMASK(5, 0)

drivers/iio/proximity/hx9023s.c

101

#define HX9023S_INTERRUPT_MASK GENMASK(9, 0)

drivers/iio/proximity/hx9023s.c

102

#define HX9023S_PROX_DEBOUNCE_MASK GENMASK(3, 0)

drivers/iio/proximity/hx9023s.c

416

tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;

drivers/iio/proximity/hx9023s.c

436

tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;

drivers/iio/proximity/hx9023s.c

445

__le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));

drivers/iio/proximity/hx9023s.c

448

data->ch_data[ch].thres.near = ((val / 32) & GENMASK(9, 0)) * 32;

drivers/iio/proximity/hx9023s.c

457

__le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));

drivers/iio/proximity/hx9023s.c

460

data->ch_data[ch].thres.far = ((val / 32) & GENMASK(9, 0)) * 32;

drivers/iio/proximity/hx9023s.c

570

value = FIELD_GET(GENMASK(11, 0), value);

drivers/iio/proximity/irsd200.c

56

#define IRS_UPPER_COUNT(count) FIELD_GET(GENMASK(7, 4), count)

drivers/iio/proximity/irsd200.c

57

#define IRS_LOWER_COUNT(count) FIELD_GET(GENMASK(3, 0), count)

drivers/iio/proximity/rfd77402.c

53

#define RFD77402_STATUS_PM_MASK GENMASK(4, 0)

drivers/iio/proximity/rfd77402.c

59

#define RFD77402_RESULT_DIST_MASK GENMASK(12, 2)

drivers/iio/proximity/rfd77402.c

60

#define RFD77402_RESULT_ERR_MASK GENMASK(14, 13)

drivers/iio/proximity/sx9310.c

32

#define SX9310_REG_STAT1_COMPSTAT_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9310.c

40

#define SX9310_REG_PROX_CTRL0_SENSOREN_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9310.c

41

#define SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK GENMASK(7, 4)

drivers/iio/proximity/sx9310.c

45

#define SX9310_REG_PROX_CTRL2_COMBMODE_MASK GENMASK(7, 6)

drivers/iio/proximity/sx9310.c

50

#define SX9310_REG_PROX_CTRL2_SHIELDEN_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9310.c

54

#define SX9310_REG_PROX_CTRL3_GAIN0_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9310.c

56

#define SX9310_REG_PROX_CTRL3_GAIN12_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9310.c

59

#define SX9310_REG_PROX_CTRL4_RESOLUTION_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9310.c

70

#define SX9310_REG_PROX_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9310.c

72

#define SX9310_REG_PROX_CTRL5_RAWFILT_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9310.c

79

#define SX9310_REG_PROX_CTRL7_AVGPOSFILT_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9310.c

83

#define SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK GENMASK(7, 3)

drivers/iio/proximity/sx9310.c

90

#define SX9310_REG_PROX_CTRL10_HYST_MASK GENMASK(5, 4)

drivers/iio/proximity/sx9310.c

92

#define SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9310.c

93

#define SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9324.c

105

#define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3)

drivers/iio/proximity/sx9324.c

107

#define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9324.c

110

#define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4)

drivers/iio/proximity/sx9324.c

111

#define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9324.c

112

#define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9324.c

123

#define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9324.c

33

#define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9324.c

45

#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)

drivers/iio/proximity/sx9324.c

48

#define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9324.c

57

GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \

drivers/iio/proximity/sx9324.c

62

GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \

drivers/iio/proximity/sx9324.c

70

#define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9324.c

77

GENMASK(2 * (_pin) + 1, 2 * (_pin))

drivers/iio/proximity/sx9324.c

85

#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9324.c

87

#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9324.c

91

#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)

drivers/iio/proximity/sx9324.c

96

#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9360.c

34

#define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1)

drivers/iio/proximity/sx9360.c

42

#define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9360.c

44

#define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9360.c

53

#define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9360.c

59

#define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9360.c

67

#define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)

drivers/iio/proximity/sx9360.c

69

#define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9360.c

72

#define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3)

drivers/iio/proximity/sx9360.c

75

#define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6)

drivers/iio/proximity/sx9360.c

79

#define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3)

drivers/iio/proximity/sx9360.c

81

#define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0)

drivers/iio/proximity/sx9360.c

84

#define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4)

drivers/iio/proximity/sx9360.c

85

#define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)

drivers/iio/proximity/sx9360.c

86

#define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0)

drivers/iio/proximity/sx9500.c

61

#define SX9500_SCAN_PERIOD_MASK GENMASK(6, 4)

drivers/iio/proximity/sx9500.c

73

#define SX9500_COMPSTAT_MASK GENMASK(3, 0)

drivers/iio/proximity/sx9500.c

76

#define SX9500_CHAN_MASK GENMASK(SX9500_NUM_CHANNELS - 1, 0)

drivers/iio/proximity/vl53l0x-i2c.c

33

#define VL_REG_SYSRANGE_MODE_MASK GENMASK(3, 0)

drivers/iio/resolver/ad2s1210.c

75

#define AD2S1210_SET_ENRES GENMASK(3, 2)

drivers/iio/resolver/ad2s1210.c

76

#define AD2S1210_SET_RES GENMASK(1, 0)

drivers/iio/temperature/ltc2983.c

105

#define LTC2983_COMMON_HARD_FAULT_MASK GENMASK(31, 30)

drivers/iio/temperature/ltc2983.c

106

#define LTC2983_COMMON_SOFT_FAULT_MASK GENMASK(27, 25)

drivers/iio/temperature/ltc2983.c

110

#define LTC2983_STATUS_UP_MASK GENMASK(7, 6)

drivers/iio/temperature/ltc2983.c

113

#define LTC2983_STATUS_CHAN_SEL_MASK GENMASK(4, 0)

drivers/iio/temperature/ltc2983.c

120

#define LTC2983_NOTCH_FREQ_MASK GENMASK(1, 0)

drivers/iio/temperature/ltc2983.c

124

#define LTC2983_DATA_MASK GENMASK(23, 0)

drivers/iio/temperature/ltc2983.c

127

#define LTC2983_CHAN_TYPE_MASK GENMASK(31, 27)

drivers/iio/temperature/ltc2983.c

131

#define LTC2983_CHAN_ASSIGN_MASK GENMASK(26, 22)

drivers/iio/temperature/ltc2983.c

134

#define LTC2983_CUSTOM_LEN_MASK GENMASK(5, 0)

drivers/iio/temperature/ltc2983.c

137

#define LTC2983_CUSTOM_ADDR_MASK GENMASK(11, 6)

drivers/iio/temperature/ltc2983.c

140

#define LTC2983_THERMOCOUPLE_CFG_MASK GENMASK(21, 18)

drivers/iio/temperature/ltc2983.c

143

#define LTC2983_THERMOCOUPLE_HARD_FAULT_MASK GENMASK(31, 29)

drivers/iio/temperature/ltc2983.c

144

#define LTC2983_THERMOCOUPLE_SOFT_FAULT_MASK GENMASK(28, 25)

drivers/iio/temperature/ltc2983.c

146

#define LTC2983_RTD_CFG_MASK GENMASK(21, 18)

drivers/iio/temperature/ltc2983.c

148

#define LTC2983_RTD_EXC_CURRENT_MASK GENMASK(17, 14)

drivers/iio/temperature/ltc2983.c

151

#define LTC2983_RTD_CURVE_MASK GENMASK(13, 12)

drivers/iio/temperature/ltc2983.c

1527

.read_flag_mask = GENMASK(1, 0),

drivers/iio/temperature/ltc2983.c

154

#define LTC2983_THERMISTOR_CFG_MASK GENMASK(21, 19)

drivers/iio/temperature/ltc2983.c

157

#define LTC2983_THERMISTOR_EXC_CURRENT_MASK GENMASK(18, 15)

drivers/iio/temperature/ltc2983.c

161

#define LTC2983_DIODE_CFG_MASK GENMASK(26, 24)

drivers/iio/temperature/ltc2983.c

163

#define LTC2983_DIODE_EXC_CURRENT_MASK GENMASK(23, 22)

drivers/iio/temperature/ltc2983.c

166

#define LTC2983_DIODE_IDEAL_FACTOR_MASK GENMASK(21, 0)

drivers/iio/temperature/ltc2983.c

170

#define LTC2983_R_SENSE_VAL_MASK GENMASK(26, 0)

drivers/iio/temperature/ltc2983.c

53

#define LTC2983_EEPROM_STATUS_FAILURE_MASK GENMASK(3, 1)

drivers/iio/temperature/ltc2983.c

54

#define LTC2983_EEPROM_READ_FAILURE_MASK GENMASK(7, 0)

drivers/iio/temperature/ltc2983.c

66

#define LTC2983_THERMOCOUPLE_OC_CURR_MASK GENMASK(1, 0)

drivers/iio/temperature/ltc2983.c

97

#define LTC2983_RTD_KELVIN_R_SENSE_MASK GENMASK(3, 2)

drivers/iio/temperature/ltc2983.c

98

#define LTC2983_RTD_N_WIRES_MASK GENMASK(3, 2)

drivers/iio/temperature/max31856.c

30

#define MAX31856_CR0_OCFAULT_MASK GENMASK(5, 4)

drivers/iio/temperature/max31856.c

32

#define MAX31856_AVERAGING_MASK GENMASK(6, 4)

drivers/iio/temperature/max31856.c

34

#define MAX31856_TC_TYPE_MASK GENMASK(3, 0)

drivers/iio/temperature/mcp9600.c

33

#define MCP9600_SENSOR_TYPE_MASK GENMASK(6, 4)

drivers/iio/temperature/mcp9600.c

44

#define MCP9600_ALERT_LIMIT_MASK GENMASK(15, 2)

drivers/iio/temperature/mlx90632.c

105

#define MLX90632_STAT_CYCLE_POS GENMASK(6, 2) /* Data position */

drivers/iio/temperature/mlx90632.c

127

#define MLX90632_ID_MASK GENMASK(14, 0) /* DSP version and device ID in EE_VERSION */

drivers/iio/temperature/mlx90632.c

129

#define MLX90632_DSP_MASK GENMASK(7, 0) /* DSP version in EE_VERSION */

drivers/iio/temperature/mlx90632.c

72

#define MLX90632_CFG_PWR_MASK GENMASK(2, 1) /* PowerMode Mask */

drivers/iio/temperature/mlx90632.c

73

#define MLX90632_CFG_MTYP_MASK GENMASK(8, 4) /* Meas select Mask */

drivers/iio/temperature/mlx90632.c

83

#define MLX90632_EE_RR GENMASK(10, 8) /* Only Refresh Rate bits */

drivers/iio/temperature/mlx90635.c

107

#define MLX90635_VERSION_MASK (GENMASK(15, 12) | GENMASK(7, 4))

drivers/iio/temperature/mlx90635.c

108

#define MLX90635_DSP_VERSION(reg) (((reg & GENMASK(14, 12)) >> 9) | ((reg & GENMASK(6, 4)) >> 4))

drivers/iio/temperature/mlx90635.c

55

#define MLX90635_STAT_CYCLE_POS GENMASK(4, 2) /* Data position */

drivers/iio/temperature/mlx90635.c

68

#define MLX90635_CTRL1_REFRESH_RATE_MASK GENMASK(2, 0)

drivers/iio/temperature/mlx90635.c

69

#define MLX90635_CTRL1_RES_CTRL_MASK GENMASK(4, 3)

drivers/iio/temperature/mlx90635.c

74

#define MLX90635_CTRL2_BURST_CNT_MASK GENMASK(10, 6) /* Burst count */

drivers/iio/temperature/mlx90635.c

75

#define MLX90635_CTRL2_MODE_MASK GENMASK(12, 11) /* Power mode */

drivers/iio/temperature/tmp006.c

38

#define TMP006_CONFIG_MOD_MASK GENMASK(14, 12)

drivers/iio/temperature/tmp006.c

40

#define TMP006_CONFIG_CR_MASK GENMASK(11, 9)

drivers/iio/temperature/tmp007.c

45

#define TMP007_CONFIG_CR_MASK GENMASK(11, 9)

drivers/infiniband/core/umem.c

114

GENMASK(BITS_PER_LONG - 1,

drivers/infiniband/core/umem.c

152

pgsz_bitmap &= GENMASK(count_trailing_zeros(mask), 0);

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1096

#define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1110

#define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1124

#define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1128

#define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1129

#define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1130

#define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1131

#define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1132

#define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1133

#define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1134

#define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1135

#define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0)

drivers/infiniband/hw/efa/efa_admin_cmds_defs.h

1136

#define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8)

drivers/infiniband/hw/efa/efa_admin_defs.h

159

#define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)

drivers/infiniband/hw/efa/efa_admin_defs.h

165

#define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)

drivers/infiniband/hw/efa/efa_admin_defs.h

173

#define EFA_ADMIN_EQE_EVENT_TYPE_MASK GENMASK(8, 1)

drivers/infiniband/hw/efa/efa_com.c

902

addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0);

drivers/infiniband/hw/efa/efa_com.c

903

addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0);

drivers/infiniband/hw/efa/efa_io_defs.h

359

#define EFA_IO_TX_META_DESC_OP_TYPE_MASK GENMASK(3, 0)

drivers/infiniband/hw/efa/efa_io_defs.h

370

#define EFA_IO_TX_BUF_DESC_LKEY_MASK GENMASK(23, 0)

drivers/infiniband/hw/efa/efa_io_defs.h

376

#define EFA_IO_FAST_MR_REG_REQ_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)

drivers/infiniband/hw/efa/efa_io_defs.h

377

#define EFA_IO_FAST_MR_REG_REQ_PBL_MODE_MASK GENMASK(6, 5)

drivers/infiniband/hw/efa/efa_io_defs.h

380

#define EFA_IO_RX_DESC_LKEY_MASK GENMASK(23, 0)

drivers/infiniband/hw/efa/efa_io_defs.h

386

#define EFA_IO_CDESC_COMMON_Q_TYPE_MASK GENMASK(2, 1)

drivers/infiniband/hw/efa/efa_io_defs.h

388

#define EFA_IO_CDESC_COMMON_OP_TYPE_MASK GENMASK(6, 4)

drivers/infiniband/hw/erdma/erdma_hw.h

208

#define ERDMA_CMD_CONFIG_DEVICE_PGSHIFT_MASK GENMASK(4, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

242

#define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

243

#define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK GENMASK(23, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

244

#define ERDMA_CMD_CREATE_CQ_CQN_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

247

#define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

250

#define ERDMA_CMD_CREATE_CQ_EQN_MASK GENMASK(9, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

253

#define ERDMA_CMD_CREATE_CQ_DB_CFG_MASK GENMASK(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

268

#define ERDMA_CMD_MR_VERSION_MASK GENMASK(30, 28)

drivers/infiniband/hw/erdma/erdma_hw.h

269

#define ERDMA_CMD_MR_KEY_MASK GENMASK(27, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

270

#define ERDMA_CMD_MR_MPT_IDX_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

273

#define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12)

drivers/infiniband/hw/erdma/erdma_hw.h

274

#define ERDMA_CMD_REGMR_TYPE_MASK GENMASK(7, 6)

drivers/infiniband/hw/erdma/erdma_hw.h

275

#define ERDMA_CMD_REGMR_RIGHT_MASK GENMASK(5, 1)

drivers/infiniband/hw/erdma/erdma_hw.h

278

#define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27)

drivers/infiniband/hw/erdma/erdma_hw.h

279

#define ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK GENMASK(26, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

280

#define ERDMA_CMD_REGMR_MTT_LEVEL_MASK GENMASK(21, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

281

#define ERDMA_CMD_REGMR_MTT_CNT_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

306

#define ERDMA_CMD_CREATE_AV_FL_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

336

#define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

337

#define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

338

#define ERDMA_CMD_MODIFY_QP_QPN_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

353

#define ERDMA_CMD_MODIFY_QP_DQPN_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

383

#define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

384

#define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

387

#define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

388

#define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

391

#define ERDMA_CMD_CREATE_QP_TYPE_MASK GENMASK(3, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

394

#define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28)

drivers/infiniband/hw/erdma/erdma_hw.h

396

#define ERDMA_CMD_CREATE_QP_CQN_MASK GENMASK(23, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

399

#define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12)

drivers/infiniband/hw/erdma/erdma_hw.h

400

#define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK GENMASK(11, 1)

drivers/infiniband/hw/erdma/erdma_hw.h

404

#define ERDMA_CMD_CREATE_QP_SQDB_CFG_MASK GENMASK(31, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

405

#define ERDMA_CMD_CREATE_QP_RQDB_CFG_MASK GENMASK(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

490

#define ERDMA_CMD_SET_GID_SGID_IDX_MASK GENMASK(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

526

#define ERDMA_CQE_HDR_OPCODE_MASK GENMASK(23, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

527

#define ERDMA_CQE_HDR_QTYPE_MASK GENMASK(15, 8)

drivers/infiniband/hw/erdma/erdma_hw.h

528

#define ERDMA_CQE_HDR_SYNDROME_MASK GENMASK(7, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

535

#define ERDMA_CQE_SL_MASK GENMASK(27, 20)

drivers/infiniband/hw/erdma/erdma_hw.h

536

#define ERDMA_CQE_SQPN_MASK GENMASK(19, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

590

#define ERDMA_SQE_MR_ACCESS_MASK GENMASK(5, 1)

drivers/infiniband/hw/erdma/erdma_hw.h

591

#define ERDMA_SQE_MR_MTT_TYPE_MASK GENMASK(7, 6)

drivers/infiniband/hw/erdma/erdma_hw.h

592

#define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12)

drivers/infiniband/hw/erdma/erdma_hw.h

670

#define ERDMA_AEQE_HDR_TYPE_MASK GENMASK(23, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

671

#define ERDMA_AEQE_HDR_SUBTYPE_MASK GENMASK(7, 0)

drivers/infiniband/hw/hns/hns_roce_common.h

101

FIELD_GET(GENMASK((field_h) % 32, (field_l) % 32), \

drivers/infiniband/hw/hns/hns_roce_common.h

75

~cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \

drivers/infiniband/hw/hns/hns_roce_common.h

92

GENMASK((field_h) % 32, (field_l) % 32), val)); \

drivers/infiniband/hw/hns/hns_roce_cq.c

141

return (u8)(cqn & GENMASK(1, 0));

drivers/infiniband/hw/hns/hns_roce_device.h

105

#define CQ_BANKID_MASK GENMASK(1, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1074

#define MB_ST_COMPLETE_M GENMASK(7, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1416

#define HNS_ROCE_V2_EQN_M GENMASK(23, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1419

#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1420

#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1421

#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

1422

#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

794

#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

797

#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

800

#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

803

#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

832

#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

837

#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

840

#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

843

#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

864

#define V2_DB_PRODUCER_IDX_M GENMASK(15, 0)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

867

#define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0)

drivers/infiniband/hw/hns/hns_roce_qp.c

449

return (u8)(qpn & GENMASK(2, 0));

drivers/infiniband/hw/ionic/ionic_res.h

130

u32 grp_bits = (bitid & GENMASK(half_qid_shift - 1, qgrp_shift)) << 1;

drivers/infiniband/hw/ionic/ionic_res.h

149

u32 grp_bits = (qid & GENMASK(half_qid_shift, qgrp_shift + 1)) >> 1;

drivers/infiniband/hw/irdma/cm.h

390

#define IRDMA_DSCP_VAL GENMASK(7, 2)

drivers/infiniband/hw/irdma/defs.h

563

#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)

drivers/infiniband/hw/irdma/defs.h

694

#define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0)

drivers/infiniband/hw/irdma/defs.h

742

#define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16)

drivers/infiniband/hw/irdma/i40iw_hw.h

101

#define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13)

drivers/infiniband/hw/irdma/i40iw_hw.h

103

#define I40E_PFINT_CEQCTL_NEXTQ_INDX GENMASK(26, 16)

drivers/infiniband/hw/irdma/i40iw_hw.h

105

#define I40E_PFINT_CEQCTL_NEXTQ_TYPE GENMASK(28, 27)

drivers/infiniband/hw/irdma/i40iw_hw.h

117

#define I40E_PFINT_DYN_CTLN_ITR_INDX GENMASK(4, 3)

drivers/infiniband/hw/irdma/i40iw_hw.h

121

#define I40E_CQPSQ_CQ_CEQID GENMASK(30, 24)

drivers/infiniband/hw/irdma/i40iw_hw.h

89

#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0)

drivers/infiniband/hw/irdma/i40iw_hw.h

90

#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE GENMASK(12, 11)

drivers/infiniband/hw/irdma/i40iw_hw.h

97

#define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0)

drivers/infiniband/hw/irdma/i40iw_hw.h

99

#define I40E_PFINT_CEQCTL_ITR_INDX GENMASK(12, 11)

drivers/infiniband/hw/irdma/irdma.h

11

#define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0)

drivers/infiniband/hw/irdma/irdma.h

12

#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16)

drivers/infiniband/hw/irdma/irdma.h

13

#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4)

drivers/infiniband/hw/irdma/irdma.h

14

#define IRDMA_GLINT_RATE_INTERVAL GENMASK(5, 0)

drivers/infiniband/hw/irdma/irdma.h

18

#define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3)

drivers/infiniband/hw/irdma/irdma.h

19

#define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5)

drivers/infiniband/hw/irdma/irdma.h

20

#define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11)

drivers/infiniband/hw/irdma/irdma.h

22

#define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0)

drivers/infiniband/hw/irdma/irdma.h

23

#define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0)

drivers/infiniband/hw/irdma/irdma.h

24

#define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11)

drivers/infiniband/hw/irdma/irdma.h

26

#define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0)

drivers/infiniband/hw/irdma/irdma.h

28

#define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16)

drivers/infiniband/hw/irdma/irdma.h

31

#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2)

drivers/infiniband/hw/irdma/irdma.h

32

#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12)

drivers/infiniband/hw/irdma/irdma.h

6

#define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20)

drivers/infiniband/hw/irdma/irdma.h

8

#define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0)

drivers/infiniband/hw/irdma/uk.c

1247

#define IRDMA_CQMAJERR_HIGH_NIBBLE GENMASK(15, 12)

drivers/infiniband/hw/irdma/verbs.c

71

props->timestamp_mask = GENMASK(31, 0);

drivers/infiniband/hw/mlx5/mlx5_ib.h

63

return GENMASK(largest_pg_shift, pgsz_shift);

drivers/infiniband/hw/mlx5/mlx5_ib.h

74

return GENMASK(largest_offset_shift, offset_shift);

drivers/infiniband/hw/mlx5/mlx5_ib.h

94

GENMASK(31, order_base_2(scale)), scale, \

drivers/input/joystick/adc-joystick.c

96

val &= GENMASK(msb, 0);

drivers/input/joystick/qwiic-joystick.c

21

#define QWIIC_JSK_MAX_AXIS GENMASK(9, 0)

drivers/input/joystick/xpad.c

1075

input_report_key(dev, BTN_MODE, data[4] & GENMASK(1, 0));

drivers/input/keyboard/adp5588-keys.c

117

#define ADP5588_KEC GENMASK(3, 0)

drivers/input/keyboard/adp5588-keys.c

165

#define KEY_EV_MASK GENMASK(6, 0)

drivers/input/keyboard/ep93xx_keypad.c

33

#define KEY_INIT_DBNC_MASK GENMASK(23, 16)

drivers/input/keyboard/ep93xx_keypad.c

39

#define KEY_INIT_PRSCL_MASK GENMASK(9, 0)

drivers/input/keyboard/ep93xx_keypad.c

43

#define KEY_DIAG_MASK GENMASK(5, 0)

drivers/input/keyboard/ep93xx_keypad.c

51

#define KEY_REG_KEY2_MASK GENMASK(11, 6)

drivers/input/keyboard/ep93xx_keypad.c

53

#define KEY_REG_KEY1_MASK GENMASK(5, 0)

drivers/input/keyboard/mt6779-keypad.c

19

#define MTK_KPD_DEBOUNCE_MASK GENMASK(13, 0)

drivers/input/keyboard/mt6779-keypad.c

23

#define MTK_KPD_SEL_COL GENMASK(15, 10)

drivers/input/keyboard/mt6779-keypad.c

24

#define MTK_KPD_SEL_ROW GENMASK(9, 4)

drivers/input/keyboard/mt6779-keypad.c

25

#define MTK_KPD_SEL_COLMASK(c) GENMASK((c) + 9, 10)

drivers/input/keyboard/mt6779-keypad.c

26

#define MTK_KPD_SEL_ROWMASK(r) GENMASK((r) + 3, 4)

drivers/input/keyboard/mtk-pmic-keys.c

24

#define MTK_PMIC_RST_DU_MASK GENMASK(9, 8)

drivers/input/keyboard/mtk-pmic-keys.c

28

#define MTK_PMIC_MT6331_RST_DU_MASK GENMASK(13, 12)

drivers/input/keyboard/pxa27x_keypad.c

48

#define KPC_MKRN_MASK GENMASK(28, 26)

drivers/input/keyboard/pxa27x_keypad.c

49

#define KPC_MKCN_MASK GENMASK(25, 23)

drivers/input/keyboard/pxa27x_keypad.c

50

#define KPC_DKN_MASK GENMASK(8, 6)

drivers/input/keyboard/pxa27x_keypad.c

529

keypad->direct_key_mask = GENMASK(direct_key_num - 1, 0) & ~mask;

drivers/input/keyboard/pxa27x_keypad.c

61

#define KPC_MS_ALL GENMASK(20, 13)

drivers/input/keyboard/pxa27x_keypad.c

74

#define KPDK_DK_MASK GENMASK(7, 0)

drivers/input/keyboard/pxa27x_keypad.c

82

#define KPREC_RECOUNT0_MASK GENMASK(7, 0)

drivers/input/keyboard/pxa27x_keypad.c

83

#define KPREC_RECOUNT1_MASK GENMASK(23, 16)

drivers/input/keyboard/pxa27x_keypad.c

91

#define KPAS_MUKP_MASK GENMASK(30, 26)

drivers/input/keyboard/pxa27x_keypad.c

92

#define KPAS_RP_MASK GENMASK(7, 4)

drivers/input/keyboard/pxa27x_keypad.c

93

#define KPAS_CP_MASK GENMASK(3, 0)

drivers/input/keyboard/pxa27x_keypad.c

98

#define KPASMKP_MKC_MASK GENMASK(7, 0)

drivers/input/keyboard/samsung-keypad.c

92

row_state[col] = ~val & GENMASK(keypad->rows - 1, 0);

drivers/input/keyboard/tm2-touchkey.c

32

#define TM2_TOUCHKEY_BIT_KEYCODE GENMASK(2, 0)

drivers/input/misc/aw86927.c

101

#define AW86927_SYSCTRL3_EN_RAMINIT_MASK GENMASK(2, 2)

drivers/input/misc/aw86927.c

106

#define AW86927_SYSCTRL4_WAVDAT_MODE_MASK GENMASK(6, 5)

drivers/input/misc/aw86927.c

108

#define AW86927_SYSCTRL4_INT_EDGE_MODE_MASK GENMASK(4, 4)

drivers/input/misc/aw86927.c

110

#define AW86927_SYSCTRL4_INT_MODE_MASK GENMASK(3, 3)

drivers/input/misc/aw86927.c

112

#define AW86927_SYSCTRL4_GAIN_BYPASS_MASK GENMASK(0, 0)

drivers/input/misc/aw86927.c

115

#define AW86927_PWMCFG1_PRC_EN_MASK GENMASK(7, 7)

drivers/input/misc/aw86927.c

119

#define AW86927_PWMCFG3_PR_EN_MASK GENMASK(7, 7)

drivers/input/misc/aw86927.c

120

#define AW86927_PWMCFG3_PRCTIME_MASK GENMASK(6, 0)

drivers/input/misc/aw86927.c

123

#define AW86927_PWMCFG4_PRTIME_MASK GENMASK(7, 0)

drivers/input/misc/aw86927.c

126

#define AW86927_VBATCTRL_VBAT_MODE_MASK GENMASK(6, 6)

drivers/input/misc/aw86927.c

130

#define AW86927_DETCFG1_DET_GO_MASK GENMASK(1, 0)

drivers/input/misc/aw86927.c

135

#define AW86927_DETCFG2_DET_SEQ0_MASK GENMASK(6, 3)

drivers/input/misc/aw86927.c

137

#define AW86927_DETCFG2_D2S_GAIN_MASK GENMASK(2, 0)

drivers/input/misc/aw86927.c

151

#define AW86927_ANACFG12_BST_SKIP_MASK GENMASK(7, 7)

drivers/input/misc/aw86927.c

155

#define AW86927_ANACFG13_BST_PC_MASK GENMASK(7, 4)

drivers/input/misc/aw86927.c

159

#define AW86927_ANACFG15_BST_PEAK_MODE_MASK GENMASK(7, 7)

drivers/input/misc/aw86927.c

163

#define AW86927_ANACFG16_BST_SRC_MASK GENMASK(4, 4)

drivers/input/misc/aw86927.c

41

#define AW86927_PLAYCFG1_BST_MODE_MASK GENMASK(7, 7)

drivers/input/misc/aw86927.c

43

#define AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK GENMASK(6, 0)

drivers/input/misc/aw86927.c

49

#define AW86927_PLAYCFG3_AUTO_BST_MASK GENMASK(4, 4)

drivers/input/misc/aw86927.c

52

#define AW86927_PLAYCFG3_PLAY_MODE_MASK GENMASK(1, 0)

drivers/input/misc/aw86927.c

60

#define AW86927_WAVCFG1_WAVSEQ1_MASK GENMASK(6, 0)

drivers/input/misc/aw86927.c

63

#define AW86927_WAVCFG2_WAVSEQ2_MASK GENMASK(6, 0)

drivers/input/misc/aw86927.c

66

#define AW86927_WAVCFG9_SEQ1LOOP_MASK GENMASK(7, 4)

drivers/input/misc/aw86927.c

70

#define AW86927_CONTCFG1_BRK_BST_MD_MASK GENMASK(6, 6)

drivers/input/misc/aw86927.c

73

#define AW86927_CONTCFG5_BST_BRK_GAIN_MASK GENMASK(7, 4)

drivers/input/misc/aw86927.c

74

#define AW86927_CONTCFG5_BRK_GAIN_MASK GENMASK(3, 0)

drivers/input/misc/aw86927.c

77

#define AW86927_CONTCFG10_BRK_TIME_MASK GENMASK(7, 0)

drivers/input/misc/aw86927.c

81

#define AW86927_CONTCFG13_TSET_MASK GENMASK(7, 4)

drivers/input/misc/aw86927.c

82

#define AW86927_CONTCFG13_BEME_SET_MASK GENMASK(3, 0)

drivers/input/misc/aw86927.c

88

#define AW86927_GLBRD5_STATE_MASK GENMASK(3, 0)

drivers/input/misc/aw86927.c

98

#define AW86927_SYSCTRL3_STANDBY_MASK GENMASK(5, 5)

drivers/input/misc/cs40l50-vibra.c

38

#define CS40L50_GPIO_NUM_MASK GENMASK(14, 12)

drivers/input/misc/da7280.c

105

#define DA7280_FULL_BRAKE_THR_MASK GENMASK(3, 0)

drivers/input/misc/da7280.c

113

#define DA7280_BEMF_FAULT_LIM_MASK GENMASK(1, 0)

drivers/input/misc/da7280.c

116

#define DA7280_OPERATION_MODE_MASK GENMASK(2, 0)

drivers/input/misc/da7280.c

121

#define DA7280_PS_SEQ_ID_MASK GENMASK(3, 0)

drivers/input/misc/da7280.c

122

#define DA7280_PS_SEQ_LOOP_MASK GENMASK(7, 4)

drivers/input/misc/da7280.c

125

#define DA7280_GPI0_POLARITY_MASK GENMASK(1, 0)

drivers/input/misc/da7280.c

127

#define DA7280_GPI0_SEQUENCE_ID_MASK GENMASK(6, 3)

drivers/input/misc/da7280.c

130

#define DA7280_GPI1_POLARITY_MASK GENMASK(1, 0)

drivers/input/misc/da7280.c

132

#define DA7280_GPI1_SEQUENCE_ID_MASK GENMASK(6, 3)

drivers/input/misc/da7280.c

135

#define DA7280_GPI2_POLARITY_MASK GENMASK(1, 0)

drivers/input/misc/da7280.c

137

#define DA7280_GPI2_SEQUENCE_ID_MASK GENMASK(6, 3)

drivers/input/misc/da7280.c

94

#define DA7280_IMAX_MASK GENMASK(4, 0)

drivers/input/misc/iqs269a.c

103

#define IQS269_MISC_B_FILT_STR_SLIDER GENMASK(1, 0)

drivers/input/misc/iqs269a.c

117

#define IQS269_CHx_ENG_A_ATI_MODE_MASK GENMASK(9, 8)

drivers/input/misc/iqs269a.c

121

#define IQS269_CHx_ENG_A_PROJ_BIAS_MASK GENMASK(6, 5)

drivers/input/misc/iqs269a.c

124

#define IQS269_CHx_ENG_A_SENSE_MODE_MASK GENMASK(3, 0)

drivers/input/misc/iqs269a.c

128

#define IQS269_CHx_ENG_B_SENSE_FREQ_MASK GENMASK(10, 9)

drivers/input/misc/iqs269a.c

132

#define IQS269_CHx_ENG_B_ATI_BASE_MASK GENMASK(7, 6)

drivers/input/misc/iqs269a.c

137

#define IQS269_CHx_ENG_B_ATI_TARGET_MASK GENMASK(5, 0)

drivers/input/misc/iqs269a.c

142

#define IQS269_CHx_HYST_DEEP_MASK GENMASK(7, 4)

drivers/input/misc/iqs269a.c

144

#define IQS269_CHx_HYST_TOUCH_MASK GENMASK(3, 0)

drivers/input/misc/iqs269a.c

35

#define IQS269_SYS_FLAGS_PWR_MODE_MASK GENMASK(12, 11)

drivers/input/misc/iqs269a.c

44

#define IQS269_CAL_DATA_A_HALL_BIN_L_MASK GENMASK(15, 12)

drivers/input/misc/iqs269a.c

46

#define IQS269_CAL_DATA_A_HALL_BIN_R_MASK GENMASK(11, 8)

drivers/input/misc/iqs269a.c

53

#define IQS269_SYS_SETTINGS_PWR_MODE_MASK GENMASK(12, 11)

drivers/input/misc/iqs269a.c

56

#define IQS269_SYS_SETTINGS_ULP_UPDATE_MASK GENMASK(10, 8)

drivers/input/misc/iqs269a.c

66

#define IQS269_FILT_STR_LP_LTA_MASK GENMASK(7, 6)

drivers/input/misc/iqs269a.c

68

#define IQS269_FILT_STR_LP_CNT_MASK GENMASK(5, 4)

drivers/input/misc/iqs269a.c

70

#define IQS269_FILT_STR_NP_LTA_MASK GENMASK(3, 2)

drivers/input/misc/iqs269a.c

72

#define IQS269_FILT_STR_NP_CNT_MASK GENMASK(1, 0)

drivers/input/misc/iqs269a.c

91

#define IQS269_MISC_A_GPIO3_SELECT_MASK GENMASK(10, 8)

drivers/input/misc/iqs269a.c

94

#define IQS269_MISC_A_TX_FREQ_MASK GENMASK(5, 4)

drivers/input/misc/iqs269a.c

99

#define IQS269_MISC_B_RESEED_UI_SEL_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

1007

if (val & ~GENMASK(1, 0)) {

drivers/input/misc/iqs626a.c

101

#define IQS626_CHx_ENG_1_SENSE_FREQ_MASK GENMASK(2, 1)

drivers/input/misc/iqs626a.c

106

#define IQS626_CHx_ENG_2_LOCAL_CAP_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

110

#define IQS626_CHx_ENG_2_SENSE_MODE_MASK GENMASK(3, 0)

drivers/input/misc/iqs626a.c

113

#define IQS626_CHx_ENG_3_TX_FREQ_MASK GENMASK(5, 4)

drivers/input/misc/iqs626a.c

126

#define IQS626_CHx_ATI_BASE_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

131

#define IQS626_CHx_ATI_TARGET_MASK GENMASK(5, 0)

drivers/input/misc/iqs626a.c

135

#define IQS626_CHx_HYST_DEEP_MASK GENMASK(7, 4)

drivers/input/misc/iqs626a.c

137

#define IQS626_CHx_HYST_TOUCH_MASK GENMASK(3, 0)

drivers/input/misc/iqs626a.c

140

#define IQS626_FILT_STR_NP_TPx_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

142

#define IQS626_FILT_STR_LP_TPx_MASK GENMASK(5, 4)

drivers/input/misc/iqs626a.c

145

#define IQS626_FILT_STR_NP_CNT_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

147

#define IQS626_FILT_STR_LP_CNT_MASK GENMASK(5, 4)

drivers/input/misc/iqs626a.c

149

#define IQS626_FILT_STR_NP_LTA_MASK GENMASK(3, 2)

drivers/input/misc/iqs626a.c

151

#define IQS626_FILT_STR_LP_LTA_MASK GENMASK(1, 0)

drivers/input/misc/iqs626a.c

1587

if (flags.gesture & GENMASK(IQS626_GESTURE_TAP, 0)) {

drivers/input/misc/iqs626a.c

34

#define IQS626_SYS_FLAGS_PWR_MODE_MASK GENMASK(9, 8)

drivers/input/misc/iqs626a.c

43

#define IQS626_SYS_SETTINGS_PWR_MODE_MASK GENMASK(12, 11)

drivers/input/misc/iqs626a.c

46

#define IQS626_SYS_SETTINGS_ULP_UPDATE_MASK GENMASK(10, 8)

drivers/input/misc/iqs626a.c

55

#define IQS626_MISC_A_TPx_LTA_UPDATE_MASK GENMASK(6, 4)

drivers/input/misc/iqs626a.c

59

#define IQS626_MISC_A_GPIO3_SELECT_MASK GENMASK(2, 0)

drivers/input/misc/iqs626a.c

74

#define IQS626_MISC_B_RESEED_UI_SEL_MASK GENMASK(7, 6)

drivers/input/misc/iqs626a.c

81

#define IQS626_MISC_B_FILT_STR_TPx GENMASK(1, 0)

drivers/input/misc/iqs626a.c

92

#define IQS626_CHx_ENG_0_ATI_MODE_MASK GENMASK(1, 0)

drivers/input/misc/iqs626a.c

97

#define IQS626_CHx_ENG_1_PROJ_BIAS_MASK GENMASK(5, 4)

drivers/input/misc/iqs7222.c

2119

val_max = GENMASK(reg_width - 1, 0) * val_pitch;

drivers/input/misc/iqs7222.c

2127

setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,

drivers/input/misc/iqs7222.c

2229

cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);

drivers/input/misc/iqs7222.c

2366

chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);

drivers/input/misc/iqs7222.c

2493

sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);

drivers/input/misc/iqs7222.c

2710

tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);

drivers/input/misc/iqs7222.c

36

#define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)

drivers/input/misc/iqs7222.c

41

#define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)

drivers/input/misc/iqs7222.c

42

#define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)

drivers/input/misc/iqs7222.c

44

#define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)

drivers/input/misc/iqs7222.c

49

#define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)

drivers/input/misc/iqs7222.c

52

#define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)

drivers/input/misc/pm8xxx-vibrator.c

38

.drv_mask = GENMASK(7, 3),

drivers/input/misc/pm8xxx-vibrator.c

48

.drv_mask = GENMASK(4, 0),

drivers/input/misc/pm8xxx-vibrator.c

58

.drv_mask = GENMASK(7, 0),

drivers/input/misc/pm8xxx-vibrator.c

61

.drv2_mask = GENMASK(3, 0),

drivers/input/misc/sc27xx-vibra.c

15

#define CUR_DRV_CAL_SEL GENMASK(13, 12)

drivers/input/mouse/synaptics.c

805

unsigned int ext_mask = GENMASK(ext_bits - 1, 0);

drivers/input/mouse/synaptics.h

126

#define SYN_ID_MODEL(i) (((i) & GENMASK(7, 4)) >> 4)

drivers/input/mouse/synaptics.h

127

#define SYN_ID_MAJOR(i) (((i) & GENMASK(3, 0)) >> 0)

drivers/input/mouse/synaptics.h

128

#define SYN_ID_MINOR(i) (((i) & GENMASK(23, 16)) >> 16)

drivers/input/mouse/synaptics.h

130

#define SYN_ID_IS_SYNAPTICS(i) (((i) & GENMASK(15, 8)) == 0x004700U)

drivers/input/mouse/synaptics.h

35

#define SYN_MODEL_SENSOR(m) (((m) & GENMASK(21, 16)) >> 16)

drivers/input/mouse/synaptics.h

36

#define SYN_MODEL_HARDWARE(m) (((m) & GENMASK(15, 9)) >> 9)

drivers/input/mouse/synaptics.h

40

#define SYN_MODEL_GEOMETRY(m) ((m) & GENMASK(3, 0))

drivers/input/mouse/synaptics.h

50

#define SYN_CAP_SUBMODEL_ID(c) (((c) & GENMASK(15, 8)) >> 8)

drivers/input/mouse/synaptics.h

51

#define SYN_EXT_CAP_REQUESTS(c) (((c) & GENMASK(22, 20)) >> 20)

drivers/input/mouse/synaptics.h

52

#define SYN_CAP_MB_MASK GENMASK(15, 12)

drivers/input/mouse/synaptics.h

54

#define SYN_CAP_PRODUCT_ID(ec) (((ec) & GENMASK(23, 16)) >> 16)

drivers/input/rmi4/rmi_f21.c

14

#define RMI_F21_SENSOR_COUNT_MASK GENMASK(3, 0)

drivers/input/rmi4/rmi_f21.c

18

#define RMI_F21_FINGER_COUNT_MASK GENMASK(3, 0)

drivers/input/touchscreen/cyttsp5.c

32

#define CY_NUM_BTN_EVENT_ID GENMASK(CY_BITS_PER_BTN - 1, 0)

drivers/input/touchscreen/cyttsp5.c

76

#define HID_OUTPUT_RESPONSE_CMD_MASK GENMASK(6, 0)

drivers/input/touchscreen/cyttsp5.c

80

#define HID_SYSINFO_BTN_MASK GENMASK(7, 0)

drivers/input/touchscreen/goodix_berlin_core.c

46

#define GOODIX_BERLIN_TOUCH_COUNT_MASK GENMASK(3, 0)

drivers/input/touchscreen/goodix_berlin_core.c

50

#define GOODIX_BERLIN_POINT_TYPE_MASK GENMASK(3, 0)

drivers/input/touchscreen/goodix_berlin_core.c

54

#define GOODIX_BERLIN_TOUCH_ID_MASK GENMASK(7, 4)

drivers/input/touchscreen/hynitron-cst816x.c

121

tch->abs_x = get_unaligned_be16(&tch->abs_x) & GENMASK(11, 0);

drivers/input/touchscreen/hynitron-cst816x.c

122

tch->abs_y = get_unaligned_be16(&tch->abs_y) & GENMASK(11, 0);

drivers/input/touchscreen/hynitron_cstxxx.c

65

#define CST3XX_TOUCH_COUNT_MASK GENMASK(6, 0)

drivers/input/touchscreen/imagis.c

40

#define IST3038C_X_MASK GENMASK(23, 12)

drivers/input/touchscreen/imagis.c

41

#define IST3038C_Y_MASK GENMASK(11, 0)

drivers/input/touchscreen/imagis.c

42

#define IST3038C_AREA_MASK GENMASK(27, 24)

drivers/input/touchscreen/imagis.c

43

#define IST3038C_FINGER_COUNT_MASK GENMASK(15, 12)

drivers/input/touchscreen/imagis.c

44

#define IST3038C_FINGER_STATUS_MASK GENMASK(9, 0)

drivers/input/touchscreen/imagis.c

45

#define IST3032C_KEY_STATUS_MASK GENMASK(20, 16)

drivers/input/touchscreen/imx6ul_tsc.c

25

#define ADC_ADCH_MASK GENMASK(4, 0)

drivers/input/touchscreen/imx6ul_tsc.c

30

#define ADC_CONV_MODE_MASK GENMASK(3, 2)

drivers/input/touchscreen/imx6ul_tsc.c

33

#define ADC_INPUT_CLK_MASK GENMASK(1, 0)

drivers/input/touchscreen/imx6ul_tsc.c

35

#define ADC_CLK_DIV_MASK GENMASK(6, 5)

drivers/input/touchscreen/imx6ul_tsc.c

38

#define ADC_AVGS_MASK GENMASK(15, 14)

drivers/input/touchscreen/imx6ul_tsc.c

68

#define X_VALUE_MASK GENMASK(27, 16)

drivers/input/touchscreen/imx6ul_tsc.c

69

#define Y_VALUE_MASK GENMASK(11, 0)

drivers/input/touchscreen/imx6ul_tsc.c

72

#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8)

drivers/input/touchscreen/imx6ul_tsc.c

81

#define DE_GLITCH_MASK GENMASK(30, 29)

drivers/input/touchscreen/imx6ul_tsc.c

86

#define STATE_MACHINE_MASK GENMASK(22, 20)

drivers/input/touchscreen/iqs7211.c

1677

val_max = GENMASK(reg_width - 1, 0) * val_pitch;

drivers/input/touchscreen/iqs7211.c

1685

reg_field.mask = GENMASK(reg_shift + reg_width - 1, reg_shift);

drivers/input/touchscreen/iqs7211.c

1969

reg_field.mask = GENMASK(IQS7211_NUM_CRX - 1, 0);

drivers/input/touchscreen/iqs7211.c

2008

reg_field.mask = GENMASK(dev_desc->num_ctx - 1, 0);

drivers/input/touchscreen/iqs7211.c

2274

charge_mode = info_flags & GENMASK(dev_desc->charge_shift + 2,

drivers/input/touchscreen/iqs7211.c

29

#define IQS7211_EVENT_MASK_ALL GENMASK(14, 8)

drivers/input/touchscreen/novatek-nvt-ts.c

38

#define NVT_TS_TOUCH_TYPE_MASK GENMASK(2, 0)

drivers/input/touchscreen/resistive-adc-touch.c

24

#define GRTS_MAX_POS_MASK GENMASK(11, 0)

drivers/interconnect/qcom/icc-rpmh.c

22

#define QOS_SLV_URG_MSG_EN_MASK GENMASK(3, 3)

drivers/interconnect/qcom/icc-rpmh.c

23

#define QOS_DFLT_PRIO_MASK GENMASK(6, 4)

drivers/interconnect/qcom/icc-rpmh.c

24

#define QOS_DISABLE_MASK GENMASK(24, 24)

drivers/interconnect/qcom/osm-l3.c

20

#define LUT_SRC GENMASK(31, 30)

drivers/interconnect/qcom/osm-l3.c

21

#define LUT_L_VAL GENMASK(7, 0)

drivers/iommu/amd/init.c

2443

xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0);

drivers/iommu/apple-dart.c

103

#define DART_T8110_TLB_CMD_OP GENMASK(10, 8)

drivers/iommu/apple-dart.c

106

#define DART_T8110_TLB_CMD_STREAM GENMASK(7, 0)

drivers/iommu/apple-dart.c

109

#define DART_T8110_ERROR_STREAM GENMASK(27, 20)

drivers/iommu/apple-dart.c

110

#define DART_T8110_ERROR_CODE GENMASK(14, 0)

drivers/iommu/apple-dart.c

136

#define DART_T8110_TCR_REMAP GENMASK(11, 8)

drivers/iommu/apple-dart.c

44

#define DART_PARAMS1_PAGE_SHIFT GENMASK(27, 24)

drivers/iommu/apple-dart.c

58

#define DART_T8020_ERROR_STREAM GENMASK(27, 24)

drivers/iommu/apple-dart.c

59

#define DART_T8020_ERROR_CODE GENMASK(11, 0)

drivers/iommu/apple-dart.c

92

#define DART_T8110_PARAMS3_PA_WIDTH GENMASK(29, 24)

drivers/iommu/apple-dart.c

93

#define DART_T8110_PARAMS3_VA_WIDTH GENMASK(21, 16)

drivers/iommu/apple-dart.c

94

#define DART_T8110_PARAMS3_VER_MAJ GENMASK(15, 8)

drivers/iommu/apple-dart.c

95

#define DART_T8110_PARAMS3_VER_MIN GENMASK(7, 0)

drivers/iommu/apple-dart.c

98

#define DART_T8110_PARAMS4_NUM_CLIENTS GENMASK(24, 16)

drivers/iommu/apple-dart.c

99

#define DART_T8110_PARAMS4_NUM_SIDS GENMASK(8, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

612

mask = GENMASK(limit - 1, sbidx);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

100

#define CR1_TABLE_OC GENMASK(9, 8)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

101

#define CR1_TABLE_IC GENMASK(7, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

102

#define CR1_QUEUE_SH GENMASK(5, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

103

#define CR1_QUEUE_OC GENMASK(3, 2)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

104

#define CR1_QUEUE_IC GENMASK(1, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

148

#define STRTAB_BASE_CFG_FMT GENMASK(17, 16)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

151

#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

152

#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

176

#define MSI_CFG2_SH GENMASK(5, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

177

#define MSI_CFG2_MEMATTR GENMASK(3, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

196

#define Q_BASE_LOG2SIZE GENMASK(4, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

23

#define IDR0_ST_LVL GENMASK(28, 27)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

25

#define IDR0_STALL_MODEL GENMASK(25, 24)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

28

#define IDR0_TTENDIAN GENMASK(22, 21)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

385

#define CMDQ_CONS_ERR GENMASK(30, 24)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

40

#define IDR0_HTTU GENMASK(7, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

44

#define IDR0_TTF GENMASK(3, 2)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

54

#define IDR1_CMDQS GENMASK(25, 21)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

55

#define IDR1_EVTQS GENMASK(20, 16)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

56

#define IDR1_PRIQS GENMASK(15, 11)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

57

#define IDR1_SSIDSIZE GENMASK(10, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

58

#define IDR1_SIDSIZE GENMASK(5, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

63

#define IDR3_BBM GENMASK(12, 11)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

66

#define IDR5_STALL_MAX GENMASK(31, 16)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

70

#define IDR5_OAS GENMASK(2, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

78

#define IDR5_VAX GENMASK(11, 10)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

82

#define IIDR_PRODUCTID GENMASK(31, 20)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

83

#define IIDR_VARIANT GENMASK(19, 16)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

84

#define IIDR_REVISION GENMASK(15, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

85

#define IIDR_IMPLEMENTER GENMASK(11, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

99

#define CR1_TABLE_SH GENMASK(11, 10)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

29

#define CMDQV_NUM_SID_PER_VM_LOG2 GENMASK(15, 12)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

30

#define CMDQV_NUM_VINTF_LOG2 GENMASK(11, 8)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

31

#define CMDQV_NUM_VCMDQ_LOG2 GENMASK(7, 4)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

32

#define CMDQV_VER GENMASK(3, 0)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

42

#define CMDQV_CMDQ_ALLOC_VINTF GENMASK(20, 15)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

43

#define CMDQV_CMDQ_ALLOC_LVCMDQ GENMASK(7, 1)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

51

#define VINTF_VMID GENMASK(16, 1)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

55

#define VINTF_STATUS GENMASK(3, 1)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

70

#define VCMDQ_CONS_ERR GENMASK(30, 24)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

85

#define VCMDQ_ADDR GENMASK(47, 5)

drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

86

#define VCMDQ_LOG2SIZE GENMASK(4, 0)

drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c

280

smmu->pgsize_bitmap &= GENMASK(PAGE_SHIFT, 0);

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

31

#define DEBUG_SID_HALT_SID GENMASK(9, 0)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

35

#define DEBUG_TXN_AXCACHE GENMASK(5, 2)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

36

#define DEBUG_TXN_AXPROT GENMASK(8, 6)

drivers/iommu/arm/arm-smmu/arm-smmu.h

102

#define ARM_SMMU_SMR_MASK GENMASK(31, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

103

#define ARM_SMMU_SMR_ID GENMASK(15, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

106

#define ARM_SMMU_S2CR_PRIVCFG GENMASK(25, 24)

drivers/iommu/arm/arm-smmu/arm-smmu.h

113

#define ARM_SMMU_S2CR_TYPE GENMASK(17, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

120

#define ARM_SMMU_S2CR_CBNDX GENMASK(7, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

124

#define ARM_SMMU_CBAR_IRPTNDX GENMASK(31, 24)

drivers/iommu/arm/arm-smmu/arm-smmu.h

125

#define ARM_SMMU_CBAR_TYPE GENMASK(17, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

132

#define ARM_SMMU_CBAR_S1_MEMATTR GENMASK(15, 12)

drivers/iommu/arm/arm-smmu/arm-smmu.h

134

#define ARM_SMMU_CBAR_S1_BPSHCFG GENMASK(9, 8)

drivers/iommu/arm/arm-smmu/arm-smmu.h

136

#define ARM_SMMU_CBAR_VMID GENMASK(7, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

139

#define ARM_SMMU_CBFRSYNRA_SID GENMASK(15, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

142

#define ARM_SMMU_CBA2R_VMID16 GENMASK(31, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

164

#define ARM_SMMU_TCR2_SEP GENMASK(17, 15)

drivers/iommu/arm/arm-smmu/arm-smmu.h

167

#define ARM_SMMU_TCR2_PASIZE GENMASK(3, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

177

#define ARM_SMMU_TCR_TG0 GENMASK(15, 14)

drivers/iommu/arm/arm-smmu/arm-smmu.h

178

#define ARM_SMMU_TCR_SH0 GENMASK(13, 12)

drivers/iommu/arm/arm-smmu/arm-smmu.h

179

#define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10)

drivers/iommu/arm/arm-smmu/arm-smmu.h

180

#define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8)

drivers/iommu/arm/arm-smmu/arm-smmu.h

182

#define ARM_SMMU_TCR_T0SZ GENMASK(5, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

185

#define ARM_SMMU_VTCR_PS GENMASK(18, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

190

#define ARM_SMMU_VTCR_SL0 GENMASK(7, 6)

drivers/iommu/arm/arm-smmu/arm-smmu.h

203

#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)

drivers/iommu/arm/arm-smmu/arm-smmu.h

229

#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

236

#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

29

#define ARM_SMMU_sCR0_BSU GENMASK(15, 14)

drivers/iommu/arm/arm-smmu/arm-smmu.h

53

#define ARM_SMMU_ID0_NUMIRPT GENMASK(23, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

55

#define ARM_SMMU_ID0_NUMSIDB GENMASK(12, 9)

drivers/iommu/arm/arm-smmu/arm-smmu.h

57

#define ARM_SMMU_ID0_NUMSMRG GENMASK(7, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

61

#define ARM_SMMU_ID1_NUMPAGENDXB GENMASK(30, 28)

drivers/iommu/arm/arm-smmu/arm-smmu.h

62

#define ARM_SMMU_ID1_NUMS2CB GENMASK(23, 16)

drivers/iommu/arm/arm-smmu/arm-smmu.h

63

#define ARM_SMMU_ID1_NUMCB GENMASK(7, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

70

#define ARM_SMMU_ID2_UBS GENMASK(11, 8)

drivers/iommu/arm/arm-smmu/arm-smmu.h

71

#define ARM_SMMU_ID2_OAS GENMASK(7, 4)

drivers/iommu/arm/arm-smmu/arm-smmu.h

72

#define ARM_SMMU_ID2_IAS GENMASK(3, 0)

drivers/iommu/arm/arm-smmu/arm-smmu.h

80

#define ARM_SMMU_ID7_MAJOR GENMASK(7, 4)

drivers/iommu/arm/arm-smmu/arm-smmu.h

81

#define ARM_SMMU_ID7_MINOR GENMASK(3, 0)

drivers/iommu/dma-iommu.c

879

order_mask &= GENMASK(MAX_PAGE_ORDER, 0);

drivers/iommu/dma-iommu.c

899

for (order_mask &= GENMASK(__fls(count), 0);

drivers/iommu/generic_pt/kunit_iommu_pt.h

420

if ((priv->safe_pgsize_bitmap & GENMASK(30, 21)) != (BIT(30) | BIT(21)))

drivers/iommu/iommu.c

2529

pgsizes = domain->pgsize_bitmap & GENMASK(__fls(size), 0);

drivers/iommu/iommu.c

2533

pgsizes &= GENMASK(__ffs(addr_merge), 0);

drivers/iommu/iommu.c

2545

pgsizes = domain->pgsize_bitmap & ~GENMASK(pgsize_idx, 0);

drivers/iommu/mtk_iommu.c

100

#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)

drivers/iommu/mtk_iommu.c

1835

.banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */

drivers/iommu/mtk_iommu.c

1836

[4] = GENMASK(31, 20), /* USB */

drivers/iommu/mtk_iommu.c

314

((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\

drivers/iommu/mtk_iommu.c

94

#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)

drivers/iommu/mtk_iommu.c

95

#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)

drivers/iommu/mtk_iommu.c

98

#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)

drivers/iommu/mtk_iommu.c

99

#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)

drivers/iommu/riscv/iommu-bits.h

200

#define RISCV_IOMMU_IOCOUNTINH_HPM GENMASK(31, 1)

drivers/iommu/rockchip-iommu.c

201

#define DTE_HI_MASK1 GENMASK(11, 8)

drivers/iommu/rockchip-iommu.c

202

#define DTE_HI_MASK2 GENMASK(7, 4)

drivers/iommu/sprd-iommu.c

35

#define SPRD_VERSION_MASK GENMASK(15, 8)

drivers/iommu/sun50i-iommu.c

162

#define SUN50I_IOVA_DTE_MASK GENMASK(31, 20)

drivers/iommu/sun50i-iommu.c

163

#define SUN50I_IOVA_PTE_MASK GENMASK(19, 12)

drivers/iommu/sun50i-iommu.c

164

#define SUN50I_IOVA_PAGE_MASK GENMASK(11, 0)

drivers/iommu/sun50i-iommu.c

193

#define SUN50I_DTE_PT_ADDRESS_MASK GENMASK(31, 10)

drivers/iommu/sun50i-iommu.c

194

#define SUN50I_DTE_PT_ATTRS GENMASK(1, 0)

drivers/iommu/sun50i-iommu.c

253

#define SUN50I_PTE_PAGE_ADDRESS_MASK GENMASK(31, 12)

drivers/iommu/sun50i-iommu.c

254

#define SUN50I_PTE_ACI_MASK GENMASK(7, 4)

drivers/iommu/sun50i-iommu.c

308

iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_MASK_REG, GENMASK(31, 12));

drivers/iommu/sun50i-iommu.c

51

#define IOMMU_TLB_FLUSH_MICRO_TLB(i) (BIT(i) & GENMASK(5, 0))

drivers/irqchip/irq-apple-aic.c

112

#define AIC2_VERSION_VER GENMASK(7, 0)

drivers/irqchip/irq-apple-aic.c

115

#define AIC2_INFO1_NR_IRQ GENMASK(15, 0)

drivers/irqchip/irq-apple-aic.c

116

#define AIC2_INFO1_LAST_DIE GENMASK(27, 24)

drivers/irqchip/irq-apple-aic.c

121

#define AIC2_INFO3_MAX_IRQ GENMASK(15, 0)

drivers/irqchip/irq-apple-aic.c

122

#define AIC2_INFO3_MAX_DIE GENMASK(27, 24)

drivers/irqchip/irq-apple-aic.c

156

#define AIC2_IRQ_CFG_TARGET GENMASK(3, 0)

drivers/irqchip/irq-apple-aic.c

157

#define AIC2_IRQ_CFG_DELAY_IDX GENMASK(7, 5)

drivers/irqchip/irq-apple-aic.c

160

#define MASK_BIT(x) BIT((x) & GENMASK(4, 0))

drivers/irqchip/irq-apple-aic.c

169

#define IPI_RR_CPU GENMASK(7, 0)

drivers/irqchip/irq-apple-aic.c

171

#define IPI_RR_CLUSTER GENMASK(23, 16)

drivers/irqchip/irq-apple-aic.c

172

#define IPI_RR_TYPE GENMASK(29, 28)

drivers/irqchip/irq-apple-aic.c

192

#define UPMCR0_IMODE GENMASK(18, 16)

drivers/irqchip/irq-apple-aic.c

72

#define AIC_INFO_NR_IRQ GENMASK(15, 0)

drivers/irqchip/irq-apple-aic.c

78

#define AIC_EVENT_DIE GENMASK(31, 24)

drivers/irqchip/irq-apple-aic.c

79

#define AIC_EVENT_TYPE GENMASK(23, 16)

drivers/irqchip/irq-apple-aic.c

80

#define AIC_EVENT_NUM GENMASK(15, 0)

drivers/irqchip/irq-armada-370-xp.c

118

#define MPIC_INT_CONTROL_NUMINT_MASK GENMASK(12, 2)

drivers/irqchip/irq-armada-370-xp.c

123

#define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0)

drivers/irqchip/irq-armada-370-xp.c

131

#define MPIC_CPU_INTACK_IID_MASK GENMASK(9, 0)

drivers/irqchip/irq-armada-370-xp.c

141

#define IPI_DOORBELL_MASK GENMASK(7, 0)

drivers/irqchip/irq-armada-370-xp.c

144

#define PCI_MSI_DOORBELL_MASK GENMASK(31, 16)

drivers/irqchip/irq-armada-370-xp.c

149

#define PCI_MSI_FULL_DOORBELL_MASK GENMASK(31, 0)

drivers/irqchip/irq-armada-370-xp.c

150

#define PCI_MSI_FULL_DOORBELL_SRC0_MASK GENMASK(15, 0)

drivers/irqchip/irq-armada-370-xp.c

151

#define PCI_MSI_FULL_DOORBELL_SRC1_MASK GENMASK(31, 16)

drivers/irqchip/irq-aspeed-scu-ic.c

18

#define ASPEED_SCU_IC_STATUS GENMASK(28, 16)

drivers/irqchip/irq-aspeed-scu-ic.c

20

#define AST2700_SCU_IC_STATUS GENMASK(15, 0)

drivers/irqchip/irq-aspeed-scu-ic.c

41

SCU_VARIANT("aspeed,ast2400-scu-ic", 0, GENMASK(15, 0), 7, 0x00, 0x00),

drivers/irqchip/irq-aspeed-scu-ic.c

42

SCU_VARIANT("aspeed,ast2500-scu-ic", 0, GENMASK(15, 0), 7, 0x00, 0x00),

drivers/irqchip/irq-aspeed-scu-ic.c

43

SCU_VARIANT("aspeed,ast2600-scu-ic0", 0, GENMASK(5, 0), 6, 0x00, 0x00),

drivers/irqchip/irq-aspeed-scu-ic.c

44

SCU_VARIANT("aspeed,ast2600-scu-ic1", 4, GENMASK(5, 4), 2, 0x00, 0x00),

drivers/irqchip/irq-aspeed-scu-ic.c

45

SCU_VARIANT("aspeed,ast2700-scu-ic0", 0, GENMASK(3, 0), 4, 0x00, 0x04),

drivers/irqchip/irq-aspeed-scu-ic.c

46

SCU_VARIANT("aspeed,ast2700-scu-ic1", 0, GENMASK(3, 0), 4, 0x00, 0x04),

drivers/irqchip/irq-aspeed-scu-ic.c

47

SCU_VARIANT("aspeed,ast2700-scu-ic2", 0, GENMASK(3, 0), 4, 0x04, 0x00),

drivers/irqchip/irq-aspeed-scu-ic.c

48

SCU_VARIANT("aspeed,ast2700-scu-ic3", 0, GENMASK(1, 0), 2, 0x04, 0x00),

drivers/irqchip/irq-atmel-aic-common.c

27

#define AT91_AIC_PRIOR GENMASK(2, 0)

drivers/irqchip/irq-atmel-aic-common.c

31

#define AT91_AIC_SRCTYPE GENMASK(6, 5)

drivers/irqchip/irq-davinci-cp-intc.c

37

#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)

drivers/irqchip/irq-gic-v3-its.c

2552

return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));

drivers/irqchip/irq-gic-v3-its.c

5180

devid = GENMASK(device_ids(its) - 1, 0);

drivers/irqchip/irq-gic-v3.c

1798

d->rdists.gicd_typer &= ~GENMASK(9, 8);

drivers/irqchip/irq-gic-v3.c

268

case 8192 ... GENMASK(23, 0):

drivers/irqchip/irq-gic-v5-irs.c

603

u16 iaffid_mask = GENMASK(iaffid_bits - 1, 0);

drivers/irqchip/irq-gic-v5-irs.c

864

if (gicc->iaffid & ~GENMASK(current_iaffid_bits - 1, 0)) {

drivers/irqchip/irq-gic-v5-its.c

357

l2_idx = event_id & GENMASK(l2_bits - 1, 0);

drivers/irqchip/irq-gic-v5-its.c

436

l2_idx = device_id & GENMASK(l2_bits - 1, 0);

drivers/irqchip/irq-gic-v5-its.c

474

its_dev->device_id, (u32)GENMASK(device_id_bits - 1, 0));

drivers/irqchip/irq-gic-v5.c

25

#define GICV5_IRQ_PRI_MI (GICV5_IRQ_PRI_MASK & GENMASK(4, 5 - pri_bits))

drivers/irqchip/irq-gic.c

786

val &= ~GENMASK(shift + 7, shift);

drivers/irqchip/irq-loongson-htpic.c

67

writel(GENMASK(31, 0), htpic->base + i * 0x4);

drivers/irqchip/irq-loongson-pch-lpc.c

145

writel(GENMASK(17, 0), priv->base + LPC_INT_CLR);

drivers/irqchip/irq-owl-sirq.c

26

#define INTC_EXTCTL_TYPE_MASK GENMASK(7, 6)

drivers/irqchip/irq-owl-sirq.c

33

#define INTC_EXTCTL_SIRQ0_MASK GENMASK(23, 16)

drivers/irqchip/irq-owl-sirq.c

34

#define INTC_EXTCTL_SIRQ1_MASK GENMASK(15, 8)

drivers/irqchip/irq-owl-sirq.c

35

#define INTC_EXTCTL_SIRQ2_MASK GENMASK(7, 0)

drivers/irqchip/irq-pruss-intc.c

498

hwirq = hipir & GENMASK(9, 0);

drivers/irqchip/irq-renesas-rza1.c

62

writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,

drivers/irqchip/irq-renesas-rzg2l.c

38

#define TSSEL_MASK GENMASK(7, 0)

drivers/irqchip/irq-renesas-rzg2l.c

58

#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))

drivers/irqchip/irq-renesas-rzg2l.c

59

#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))

drivers/irqchip/irq-renesas-rzt2h.c

44

#define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2))

drivers/irqchip/irq-renesas-rzt2h.c

45

#define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) << ((i) * 2))

drivers/irqchip/irq-renesas-rzt2h.c

53

#define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10))

drivers/irqchip/irq-renesas-rzt2h.c

54

#define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), val) << ((x) * 10))

drivers/irqchip/irq-renesas-rzv2h.c

120

#define ICU_DMAC_DkRQ_SEL_MASK GENMASK(9, 0)

drivers/irqchip/irq-renesas-rzv2h.c

72

ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \

drivers/irqchip/irq-renesas-rzv2h.c

87

#define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))

drivers/irqchip/irq-renesas-rzv2h.c

88

#define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))

drivers/irqchip/irq-stm32mp-exti.c

33

#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4)

drivers/irqchip/irq-stm32mp-exti.c

37

#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24)

drivers/irqchip/irq-tegra.c

151

writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);

drivers/irqchip/irq-tegra.c

154

writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);

drivers/irqchip/irq-tegra.c

175

writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);

drivers/irqchip/irq-tegra.c

180

writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);

drivers/irqchip/irq-tegra.c

319

writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);

drivers/irqchip/qcom-pdc.c

34

#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0)

drivers/leds/blink/leds-bcm63138.c

278

GENMASK(shift_bits - 1, 0));

drivers/leds/blink/leds-lgm-sso.c

222

regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);

drivers/leds/blink/leds-lgm-sso.c

229

regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);

drivers/leds/blink/leds-lgm-sso.c

37

#define SSO_CON1_FCDSC GENMASK(21, 20) /* Fixed Divider Shift Clock */

drivers/leds/blink/leds-lgm-sso.c

38

#define SSO_CON1_FPID GENMASK(24, 23)

drivers/leds/blink/leds-lgm-sso.c

39

#define SSO_CON1_GPTD GENMASK(26, 25)

drivers/leds/blink/leds-lgm-sso.c

40

#define SSO_CON1_US GENMASK(31, 30)

drivers/leds/flash/leds-mt6360.c

30

#define MT6360_ISNK_MASK GENMASK(4, 0)

drivers/leds/flash/leds-mt6360.c

44

#define MT6360_ITORCH_MASK GENMASK(4, 0)

drivers/leds/flash/leds-mt6360.c

45

#define MT6360_ISTROBE_MASK GENMASK(6, 0)

drivers/leds/flash/leds-mt6360.c

46

#define MT6360_STRBTO_MASK GENMASK(6, 0)

drivers/leds/flash/leds-mt6370-flash.c

38

#define MT6370_ITORCH_MASK GENMASK(4, 0)

drivers/leds/flash/leds-mt6370-flash.c

39

#define MT6370_ISTROBE_MASK GENMASK(6, 0)

drivers/leds/flash/leds-mt6370-flash.c

40

#define MT6370_STRBTO_MASK GENMASK(6, 0)

drivers/leds/flash/leds-mt6370-flash.c

44

#define MT6370_FLCSEN_MASK_ALL GENMASK(1, 0)

drivers/leds/flash/leds-qcom-flash.c

46

#define FLASH_TIMER_VAL_MASK GENMASK(6, 0)

drivers/leds/flash/leds-qcom-flash.c

59

#define FLASH_IRES_MASK_3CH GENMASK(1, 0)

drivers/leds/flash/leds-rt4505.c

20

#define RT4505_FLASHTO_MASK GENMASK(2, 0)

drivers/leds/flash/leds-rt4505.c

21

#define RT4505_ITORCH_MASK GENMASK(7, 5)

drivers/leds/flash/leds-rt4505.c

23

#define RT4505_IFLASH_MASK GENMASK(4, 0)

drivers/leds/flash/leds-rt4505.c

24

#define RT4505_ENABLE_MASK GENMASK(5, 0)

drivers/leds/flash/leds-sy7802.c

36

#define SY7802_MODE_MASK GENMASK(1, 0)

drivers/leds/flash/leds-sy7802.c

44

(GENMASK(2, 0) << (SY7802_TORCH_CURRENT_SHIFT * (_id)))

drivers/leds/flash/leds-sy7802.c

50

(GENMASK(3, 0) << (SY7802_FLASH_CURRENT_SHIFT * (_id)))

drivers/leds/flash/leds-tps6131x.c

18

#define TPS6131X_REG_0_DCLC13 GENMASK(5, 3)

drivers/leds/flash/leds-tps6131x.c

20

#define TPS6131X_REG_0_DCLC2 GENMASK(2, 0)

drivers/leds/flash/leds-tps6131x.c

24

#define TPS6131X_REG_1_MODE GENMASK(7, 6)

drivers/leds/flash/leds-tps6131x.c

26

#define TPS6131X_REG_1_FC2 GENMASK(5, 0)

drivers/leds/flash/leds-tps6131x.c

30

#define TPS6131X_REG_2_MODE GENMASK(7, 6)

drivers/leds/flash/leds-tps6131x.c

33

#define TPS6131X_REG_2_FC13 GENMASK(4, 0)

drivers/leds/flash/leds-tps6131x.c

37

#define TPS6131X_REG_3_STIM GENMASK(7, 5)

drivers/leds/flash/leds-tps6131x.c

50

#define TPS6131X_REG_4_INDC GENMASK(3, 0)

drivers/leds/flash/leds-tps6131x.c

68

#define TPS6131X_REG_6_OV GENMASK(3, 0)

drivers/leds/flash/leds-tps6131x.c

73

#define TPS6131X_REG_7_BATDROOP GENMASK(6, 4)

drivers/leds/flash/leds-tps6131x.c

75

#define TPS6131X_REG_7_REVID GENMASK(2, 0)

drivers/leds/leds-as3668.c

26

#define AS3668_CURR1_MODE_MASK GENMASK(1, 0)

drivers/leds/leds-as3668.c

27

#define AS3668_CURR2_MODE_MASK GENMASK(3, 2)

drivers/leds/leds-as3668.c

28

#define AS3668_CURR3_MODE_MASK GENMASK(5, 4)

drivers/leds/leds-as3668.c

29

#define AS3668_CURR4_MODE_MASK GENMASK(7, 6)

drivers/leds/leds-aw200xx.c

34

#define AW200XX_PAGE_MASK (GENMASK(7, 6) | GENMASK(2, 0))

drivers/leds/leds-aw200xx.c

63

#define AW200XX_GCCR_IMAX_MASK GENMASK(7, 4)

drivers/leds/leds-cht-wcove.c

35

#define CHT_WC_LED_I_MASK GENMASK(3, 2) /* LED current limit mask */

drivers/leds/leds-cht-wcove.c

41

#define CHT_WC_LED_F_MASK GENMASK(5, 4)

drivers/leds/leds-cht-wcove.c

47

#define CHT_WC_LED_EFF_MASK GENMASK(2, 1)

drivers/leds/leds-cr0014114.c

38

#define CR_MAX_BRIGHTNESS GENMASK(6, 0)

drivers/leds/leds-el15203000.c

168

t = inv ? ~val & GENMASK(4, 0) : val;

drivers/leds/leds-is31fl319x.c

42

#define IS31FL3190_CURRENT_MASK GENMASK(4, 2)

drivers/leds/leds-is31fl319x.c

72

#define IS31FL3196_CONFIG2_CS_MASK GENMASK(2, 0)

drivers/leds/leds-is31fl32xx.c

353

GENMASK(cdef->enable_bits_per_led_control_register-1, 0);

drivers/leds/leds-lp5569.c

46

#define LP5569_FADER_MAPPING_MASK GENMASK(7, 5)

drivers/leds/leds-lp5569.c

52

#define LP5569_CP_MODE_MASK GENMASK(4, 3)

drivers/leds/leds-lp55xx-common.c

42

#define LP55xx_MODE_ENG_MASK GENMASK(1, 0)

drivers/leds/leds-lp55xx-common.c

53

#define LP55xx_EXEC_ENG_MASK GENMASK(1, 0)

drivers/leds/leds-lp55xx-common.c

70

#define LP55xx_FADER_MAPPING_MASK GENMASK(7, 6)

drivers/leds/leds-lp8864.c

23

#define LP8864_BRT_MODE_MASK GENMASK(9, 8)

drivers/leds/leds-lp8864.c

28

#define LP8864_LED_STATUS_WR_MASK GENMASK(14, 9) /* Writeable bits in the LED_STATUS reg */

drivers/leds/leds-max77650.c

20

#define MAX77650_LED_BR_MASK GENMASK(4, 0)

drivers/leds/leds-max77650.c

21

#define MAX77650_LED_EN_MASK GENMASK(7, 6)

drivers/leds/leds-max77650.c

28

#define MAX77650_LED_ENABLE GENMASK(7, 6)

drivers/leds/leds-max77650.c

33

#define MAX77650_LED_B_DEFAULT GENMASK(3, 0)

drivers/leds/leds-max77705.c

18

#define MAX77705_LED_EN_MASK GENMASK(1, 0)

drivers/leds/leds-mlxreg.c

24

#define MLXREG_LED_CAPABILITY_CLEAR GENMASK(31, 8) /* Clear mask */

drivers/leds/leds-sc27xx-bltc.c

31

#define SC27XX_DUTY_MASK GENMASK(15, 0)

drivers/leds/leds-sc27xx-bltc.c

32

#define SC27XX_MOD_MASK GENMASK(7, 0)

drivers/leds/leds-sc27xx-bltc.c

35

#define SC27XX_CURVE_L_MASK GENMASK(7, 0)

drivers/leds/leds-sc27xx-bltc.c

36

#define SC27XX_CURVE_H_MASK GENMASK(15, 8)

drivers/leds/leds-sun50i-a100.c

27

#define LEDC_CTRL_REG_DATA_LENGTH GENMASK(28, 16)

drivers/leds/leds-sun50i-a100.c

28

#define LEDC_CTRL_REG_RGB_MODE GENMASK(8, 6)

drivers/leds/leds-sun50i-a100.c

31

#define LEDC_T01_TIMING_CTRL_REG_T1H GENMASK(26, 21)

drivers/leds/leds-sun50i-a100.c

32

#define LEDC_T01_TIMING_CTRL_REG_T1L GENMASK(20, 16)

drivers/leds/leds-sun50i-a100.c

33

#define LEDC_T01_TIMING_CTRL_REG_T0H GENMASK(10, 6)

drivers/leds/leds-sun50i-a100.c

34

#define LEDC_T01_TIMING_CTRL_REG_T0L GENMASK(5, 0)

drivers/leds/leds-sun50i-a100.c

36

#define LEDC_RESET_TIMING_CTRL_REG_TR GENMASK(28, 16)

drivers/leds/leds-sun50i-a100.c

37

#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM GENMASK(9, 0)

drivers/leds/leds-sun50i-a100.c

41

#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL GENMASK(4, 0)

drivers/leds/leds-sun50i-a100.c

47

#define LEDC_INT_STS_REG_FIFO_WLW GENMASK(15, 10)

drivers/leds/rgb/leds-mt6370-rgb.c

107

#define MT6370_VENDOR_ID_MASK GENMASK(7, 4)

drivers/leds/rgb/leds-qcom-lpg.c

26

#define PWM_CLK_SELECT_MASK GENMASK(1, 0)

drivers/leds/rgb/leds-qcom-lpg.c

28

#define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)

drivers/leds/rgb/leds-qcom-lpg.c

29

#define PWM_SIZE_HI_RES_MASK GENMASK(6, 4)

drivers/leds/rgb/leds-qcom-lpg.c

31

#define PWM_FREQ_PRE_DIV_MASK GENMASK(6, 5)

drivers/leds/rgb/leds-qcom-lpg.c

32

#define PWM_FREQ_EXP_MASK GENMASK(2, 0)

drivers/leds/rgb/leds-qcom-lpg.c

561

val |= GENMASK(5, 4);

drivers/mailbox/arm_mhuv3.c

103

#define implementer GENMASK(11, 0)

drivers/mailbox/arm_mhuv3.c

104

#define revision GENMASK(15, 12)

drivers/mailbox/arm_mhuv3.c

105

#define variant GENMASK(19, 16)

drivers/mailbox/arm_mhuv3.c

106

#define product_id GENMASK(31, 20)

drivers/mailbox/arm_mhuv3.c

111

#define arch_minor_rev GENMASK(3, 0)

drivers/mailbox/arm_mhuv3.c

112

#define arch_major_rev GENMASK(7, 4)

drivers/mailbox/arm_mhuv3.c

51

#define id GENMASK(3, 0)

drivers/mailbox/arm_mhuv3.c

56

#define dbe_spt GENMASK(3, 0)

drivers/mailbox/arm_mhuv3.c

57

#define fe_spt GENMASK(7, 4)

drivers/mailbox/arm_mhuv3.c

58

#define fce_spt GENMASK(11, 8)

drivers/mailbox/arm_mhuv3.c

63

#define auto_op_spt GENMASK(3, 0)

drivers/mailbox/arm_mhuv3.c

68

#define num_dbch GENMASK(7, 0)

drivers/mailbox/arm_mhuv3.c

73

#define num_ffch GENMASK(7, 0)

drivers/mailbox/arm_mhuv3.c

78

#define ffch_depth GENMASK(25, 16)

drivers/mailbox/arm_mhuv3.c

83

#define num_fch GENMASK(9, 0)

drivers/mailbox/arm_mhuv3.c

85

#define num_fcg GENMASK(15, 11)

drivers/mailbox/arm_mhuv3.c

86

#define num_fch_per_grp GENMASK(20, 16)

drivers/mailbox/arm_mhuv3.c

87

#define fch_ws GENMASK(28, 21)

drivers/mailbox/bcm74110-mailbox.c

73

#define BCM_MSG_VERSION_MASK GENMASK(31, 29)

drivers/mailbox/bcm74110-mailbox.c

77

#define BCM_MSG_SVC_MASK GENMASK(26, 24)

drivers/mailbox/bcm74110-mailbox.c

78

#define BCM_MSG_FUNC_MASK GENMASK(23, 16)

drivers/mailbox/bcm74110-mailbox.c

79

#define BCM_MSG_LENGTH_MASK GENMASK(15, 4)

drivers/mailbox/bcm74110-mailbox.c

80

#define BCM_MSG_SLOT_MASK GENMASK(3, 0)

drivers/mailbox/exynos-mailbox.c

29

#define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0)

drivers/mailbox/exynos-mailbox.c

30

#define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0)

drivers/mailbox/imx-mailbox.c

36

#define IMX_MU_V2_TR_MASK GENMASK(7, 0)

drivers/mailbox/imx-mailbox.c

37

#define IMX_MU_V2_RR_MASK GENMASK(15, 8)

drivers/mailbox/mailbox-mpfs.c

46

#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS)

drivers/mailbox/mailbox-mpfs.c

63

#define SCB_STATUS_MASK GENMASK(SCB_STATUS_POS + SCB_MASK_WIDTH - 1, SCB_STATUS_POS)

drivers/mailbox/mtk-cmdq-mailbox.c

44

#define GCE_CTRL_BY_SW GENMASK(2, 0)

drivers/mailbox/mtk-cmdq-mailbox.c

45

#define GCE_DDR_EN GENMASK(18, 16)

drivers/mailbox/mtk-cmdq-mailbox.c

49

#define GCE_VM_ID_MAP_HOST_VM GENMASK(2, 0)

drivers/mailbox/mtk-cmdq-mailbox.c

52

#define GCE_VM_CPR_GSIZE_MAX GENMASK(3, 0)

drivers/mailbox/mtk-cmdq-mailbox.c

709

cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0);

drivers/mailbox/qcom-ipcc.c

26

#define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)

drivers/mailbox/qcom-ipcc.c

27

#define IPCC_CLIENT_ID_MASK GENMASK(31, 16)

drivers/mailbox/qcom-ipcc.c

29

#define IPCC_NO_PENDING_IRQ GENMASK(31, 0)

drivers/mailbox/sprd-mailbox.c

31

#define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16)

drivers/mailbox/sprd-mailbox.c

32

#define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8)

drivers/mailbox/sprd-mailbox.c

34

#define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0)

drivers/mailbox/sprd-mailbox.c

37

#define SPRD_INBOX_R2_FIFO_OVERFLOW_DELIVER_RST GENMASK(31, 0)

drivers/mailbox/sprd-mailbox.c

40

#define SPRD_INBOX_R2_FIFO_DELIVER_MASK GENMASK(15, 0)

drivers/mailbox/sprd-mailbox.c

43

#define SPRD_INBOX_R2_FIFO_OVERFLOW_MASK GENMASK(31, 16)

drivers/mailbox/sprd-mailbox.c

44

#define SPRD_INBOX_R2_FIFO_BUSY_MASK GENMASK(15, 0)

drivers/mailbox/sprd-mailbox.c

47

#define SPRD_MBOX_IRQ_CLR GENMASK(31, 0)

drivers/mailbox/sprd-mailbox.c

53

#define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0)

drivers/mailbox/sprd-mailbox.c

59

#define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0)

drivers/mailbox/sprd-mailbox.c

63

#define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0)

drivers/mailbox/stm32-ipcc.c

29

#define IPCFGR_CHAN_MASK GENMASK(7, 0)

drivers/mailbox/stm32-ipcc.c

32

#define VER_MINREV_MASK GENMASK(3, 0)

drivers/mailbox/stm32-ipcc.c

33

#define VER_MAJREV_MASK GENMASK(7, 4)

drivers/mailbox/stm32-ipcc.c

35

#define RX_BIT_MASK GENMASK(15, 0)

drivers/mailbox/stm32-ipcc.c

38

#define TX_BIT_MASK GENMASK(31, 16)

drivers/mailbox/sun6i-msgbox.c

37

#define FIFO_STAT_MASK GENMASK(0, 0)

drivers/mailbox/sun6i-msgbox.c

40

#define MSG_STAT_MASK GENMASK(2, 0)

drivers/mailbox/zynqmp-ipi-mailbox.c

63

#define SRC_BITMASK GENMASK(11, 8)

drivers/md/dm-pcache/cache.h

56

#define PCACHE_CACHE_FLAGS_CACHE_MODE_MASK GENMASK(5, 2)

drivers/md/dm-pcache/cache.h

62

#define PCACHE_CACHE_FLAGS_GC_PERCENT_MASK GENMASK(12, 6)

drivers/md/dm-pcache/segment.h

18

#define PCACHE_SEG_INFO_FLAGS_TYPE_MASK GENMASK(4, 1)

drivers/media/cec/platform/meson/ao-cec-g12a.c

118

#define CECB_CTRL_TYPE GENMASK(2, 1)

drivers/media/cec/platform/meson/ao-cec-g12a.c

125

#define CECB_CTRL2_RISE_DEL_MAX GENMASK(4, 0)

drivers/media/cec/platform/meson/ao-cec-g12a.c

33

#define CECB_CLK_CNTL_N1 GENMASK(11, 0)

drivers/media/cec/platform/meson/ao-cec-g12a.c

34

#define CECB_CLK_CNTL_N2 GENMASK(23, 12)

drivers/media/cec/platform/meson/ao-cec-g12a.c

41

#define CECB_CLK_CNTL_M1 GENMASK(11, 0)

drivers/media/cec/platform/meson/ao-cec-g12a.c

42

#define CECB_CLK_CNTL_M2 GENMASK(23, 12)

drivers/media/cec/platform/meson/ao-cec-g12a.c

67

#define CECB_GEN_CNTL_CLK_CTRL_MASK GENMASK(2, 1)

drivers/media/cec/platform/meson/ao-cec-g12a.c

73

#define CECB_GEN_CNTL_FILTER_TICK_SEL GENMASK(9, 8)

drivers/media/cec/platform/meson/ao-cec-g12a.c

74

#define CECB_GEN_CNTL_FILTER_DEL GENMASK(14, 12)

drivers/media/cec/platform/meson/ao-cec-g12a.c

86

#define CECB_RW_ADDR GENMASK(7, 0)

drivers/media/cec/platform/meson/ao-cec-g12a.c

87

#define CECB_RW_WR_DATA GENMASK(15, 8)

drivers/media/cec/platform/meson/ao-cec-g12a.c

90

#define CECB_RW_RD_DATA GENMASK(31, 24)

drivers/media/cec/platform/meson/ao-cec.c

41

#define CEC_GEN_CNTL_CLK_CTRL_MASK GENMASK(2, 1)

drivers/media/cec/platform/meson/ao-cec.c

54

#define CEC_RW_ADDR GENMASK(7, 0)

drivers/media/cec/platform/meson/ao-cec.c

55

#define CEC_RW_WR_DATA GENMASK(15, 8)

drivers/media/cec/platform/meson/ao-cec.c

58

#define CEC_RW_RD_DATA GENMASK(31, 24)

drivers/media/cec/platform/stm32/stm32-cec.c

33

#define OAR GENMASK(30, 16)

drivers/media/cec/platform/stm32/stm32-cec.c

40

#define SFT GENMASK(2, 0)

drivers/media/dvb-frontends/cxd2880/cxd2880_common.c

18

return (int)(GENMASK(31, bitlen) | value);

drivers/media/dvb-frontends/cxd2880/cxd2880_common.c

20

return (int)(GENMASK(bitlen - 1, 0) & value);

drivers/media/dvb-frontends/lnbh29.c

33

#define LNBH29_VSEL_MASK GENMASK(2, 0)

drivers/media/dvb-frontends/mn88443x.c

101

#define MDSET_T_GI_MASK GENMASK(1, 0)

drivers/media/dvb-frontends/mn88443x.c

108

#define ADCSET1_T_REFSEL_MASK GENMASK(1, 0)

drivers/media/dvb-frontends/mn88443x.c

123

#define MDRD_T_SEGID_MASK GENMASK(5, 4)

drivers/media/dvb-frontends/mn88443x.c

127

#define MDRD_T_FFTS_MASK GENMASK(3, 2)

drivers/media/dvb-frontends/mn88443x.c

131

#define MDRD_T_GI_MASK GENMASK(1, 0)

drivers/media/dvb-frontends/mn88443x.c

137

#define SSEQRD_T_SSEQSTRD_MASK GENMASK(3, 0)

drivers/media/dvb-frontends/mn88443x.c

68

#define TSSET1_TSASEL_MASK GENMASK(4, 3)

drivers/media/dvb-frontends/mn88443x.c

72

#define TSSET1_TSBSEL_MASK GENMASK(2, 1)

drivers/media/dvb-frontends/mn88443x.c

78

#define TSSET3_INTASEL_MASK GENMASK(7, 6)

drivers/media/dvb-frontends/mn88443x.c

82

#define TSSET3_INTBSEL_MASK GENMASK(5, 4)

drivers/media/dvb-frontends/mn88443x.c

88

#define PWDSET_OFDMPD_MASK GENMASK(3, 2)

drivers/media/dvb-frontends/mn88443x.c

90

#define PWDSET_PSKPD_MASK GENMASK(1, 0)

drivers/media/dvb-frontends/mn88443x.c

94

#define MDSET_T_MDAUTO_MASK GENMASK(7, 4)

drivers/media/dvb-frontends/mn88443x.c

97

#define MDSET_T_FFTS_MASK GENMASK(3, 2)

drivers/media/i2c/adv748x/adv748x.h

323

#define ADV748X_SDP_FRP_MASK GENMASK(2, 0)

drivers/media/i2c/ccs/ccs-reg-access.c

74

(val & GENMASK(9, 0)) * 15625 / 1024;

drivers/media/i2c/ds90ub913.c

48

#define UB913_REG_MODE_SEL_MODE_MASK GENMASK(3, 0)

drivers/media/i2c/ds90ub953.h

15

#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK GENMASK(5, 4)

drivers/media/i2c/ds90ub953.h

22

#define UB953_REG_MODE_SEL_MODE_MASK GENMASK(2, 0)

drivers/media/i2c/ds90ub953.h

98

#define UB953_IND_ANA_TEMP_STATIC_CFG_MASK GENMASK(6, 4)

drivers/media/i2c/ds90ub960.c

1812

ret = ub960_update_bits(priv, UB9702_RR_CHANNEL_MODE, GENMASK(4, 3),

drivers/media/i2c/ds90ub960.c

1819

return ub960_update_bits(priv, UB9702_RR_CHANNEL_MODE, GENMASK(4, 3),

drivers/media/i2c/ds90ub960.c

252

#define UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK GENMASK(2, 0)

drivers/media/i2c/ds90ub960.c

2602

UB9702_IR_RX_ANA_FPD_BC_CTL0, GENMASK(7, 5),

drivers/media/i2c/ds90ub960.c

2610

UB9702_IR_RX_ANA_FPD_BC_CTL2, GENMASK(6, 3),

drivers/media/i2c/ds90ub960.c

2640

ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 0,

drivers/media/i2c/ds90ub960.c

2648

ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4),

drivers/media/i2c/ds90ub960.c

266

#define UB960_RR_PORT_CONFIG_FPD3_MODE_MASK GENMASK(1, 0)

drivers/media/i2c/ds90ub960.c

2679

ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4), 0,

drivers/media/i2c/ds90ub960.c

2687

ub960_update_bits(priv, UB9702_SR_CSI_EXCLUSIVE_FWD2, GENMASK(5, 4),

drivers/media/i2c/ds90ub960.c

296

#define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK GENMASK(7, 6)

drivers/media/i2c/ds90ub960.c

334

#define UB960_RR_AEQ_STATUS_STATUS_2 GENMASK(5, 3)

drivers/media/i2c/ds90ub960.c

335

#define UB960_RR_AEQ_STATUS_STATUS_1 GENMASK(2, 0)

drivers/media/i2c/ds90ub960.c

339

#define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK GENMASK(7, 5)

drivers/media/i2c/ds90ub960.c

341

#define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK GENMASK(3, 1)

drivers/media/i2c/ds90ub960.c

3597

fwd_ctl = GENMASK(7, 4);

drivers/media/i2c/ds90ub960.c

393

#define UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0)

drivers/media/i2c/ds90ub960.c

397

#define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0)

drivers/media/i2c/dw9768.c

65

#define DW9768_AAC_MODE_SEL_MASK GENMASK(7, 5)

drivers/media/i2c/dw9768.c

66

#define DW9768_CLOCK_PRE_SCALE_SEL_MASK GENMASK(2, 0)

drivers/media/i2c/gc0308.c

1132

GENMASK(4, 0), gc0308->mode.out_format, &ret);

drivers/media/i2c/gc0308.c

917

GENMASK(1, 0), regval, NULL);

drivers/media/i2c/gc0308.c

957

GENMASK(1, 0), ctrl->val, NULL);

drivers/media/i2c/isl7998x.c

113

#define ISL7998X_REG_PX_DEC_SDT_NOW GENMASK(6, 4)

drivers/media/i2c/isl7998x.c

114

#define ISL7998X_REG_PX_DEC_SDT_STANDARD GENMASK(2, 0)

drivers/media/i2c/max2175.c

312

return (val & GENMASK(msb, lsb)) >> lsb;

drivers/media/i2c/max2175.c

355

int ret = regmap_update_bits(ctx->regmap, idx, GENMASK(msb, lsb),

drivers/media/i2c/max96714.c

33

#define MAX96714_DEV_REV_MASK GENMASK(3, 0)

drivers/media/i2c/max96714.c

37

#define MAX96714_PATTERN_CLK_FREQ GENMASK(1, 0)

drivers/media/i2c/max96714.c

45

#define MAX96714_PATGEN_MODE GENMASK(5, 4)

drivers/media/i2c/max96714.c

65

#define CSI_DPLL_FREQ_MASK GENMASK(4, 0)

drivers/media/i2c/max96714.c

71

#define MAX96714_MIPI_STDBY_MASK GENMASK(5, 4)

drivers/media/i2c/max96714.c

74

#define MAX96714_MIPI_POLARITY_MASK GENMASK(5, 0)

drivers/media/i2c/max96714.c

78

#define MAX96714_CSI2_LANE_CNT_MASK GENMASK(7, 6)

drivers/media/i2c/max96717.c

105

#define REFGEN_PREDEF_FREQ_MASK GENMASK(5, 4)

drivers/media/i2c/max96717.c

34

#define MAX96717_RCLKSEL GENMASK(1, 0)

drivers/media/i2c/max96717.c

40

#define MAX96717_DEV_REV_MASK GENMASK(3, 0)

drivers/media/i2c/max96717.c

51

#define MAX96717_PATTERN_CLK_FREQ GENMASK(3, 1)

drivers/media/i2c/max96717.c

64

#define MAX96717_VTX_MODE GENMASK(1, 0)

drivers/media/i2c/max96717.c

88

#define MAX96717_MIPI_LANES_CNT GENMASK(5, 4)

drivers/media/i2c/max96717.c

90

#define MAX96717_PHY2_LANES_MAP GENMASK(7, 4)

drivers/media/i2c/max96717.c

92

#define MAX96717_PHY1_LANES_MAP GENMASK(3, 0)

drivers/media/i2c/max96717.c

94

#define MAX96717_PHY1_LANES_POL GENMASK(6, 4)

drivers/media/i2c/max96717.c

96

#define MAX96717_PHY2_LANES_POL GENMASK(2, 0)

drivers/media/i2c/mt9m111.c

129

#define MT9M111_TPG_SEL_MASK GENMASK(2, 0)

drivers/media/i2c/mt9m111.c

130

#define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0)

drivers/media/i2c/mt9m111.c

132

#define MT9M111_RM_SKIP2_MASK GENMASK(3, 2)

drivers/media/i2c/mt9v111.c

70

#define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_MASK GENMASK(2, 0)

drivers/media/i2c/mt9v111.c

77

#define MT9V111_IFP_DECIMATION_MASK GENMASK(9, 0)

drivers/media/i2c/mt9v111.c

86

#define MT9V111_CORE_R05_MAX_HBLANK GENMASK(9, 0)

drivers/media/i2c/mt9v111.c

90

#define MT9V111_CORE_R06_MAX_VBLANK GENMASK(11, 0)

drivers/media/i2c/mt9v111.c

95

#define MT9V111_CORE_R09_PIXEL_INT_MASK GENMASK(11, 0)

drivers/media/i2c/ov02a10.c

20

#define OV02A10_ID_MASK GENMASK(15, 0)

drivers/media/i2c/ov08d10.c

25

#define OV08D10_ID_MASK GENMASK(15, 0)

drivers/media/i2c/ov4689.c

63

#define OV4689_TIMING_FLIP_MASK GENMASK(2, 1)

drivers/media/i2c/ov5647.c

61

#define OV5647_REG_MIPI_CTRL14_CHANNEL_MASK GENMASK(7, 6)

drivers/media/i2c/ov5648.c

101

#define OV5648_SRB_CTRL_SCLK_DIV(v) (((v) << 2) & GENMASK(3, 2))

drivers/media/i2c/ov5648.c

120

#define OV5648_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16)

drivers/media/i2c/ov5648.c

121

#define OV5648_EXPOSURE_CTRL_HH_VALUE(v) (((v) << 16) & GENMASK(19, 16))

drivers/media/i2c/ov5648.c

123

#define OV5648_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov5648.c

124

#define OV5648_EXPOSURE_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(15, 8))

drivers/media/i2c/ov5648.c

126

#define OV5648_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

127

#define OV5648_EXPOSURE_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

129

#define OV5648_MANUAL_CTRL_FRAME_DELAY(v) (((v) << 4) & GENMASK(5, 4))

drivers/media/i2c/ov5648.c

133

#define OV5648_GAIN_CTRL_H(v) (((v) & GENMASK(9, 8)) >> 8)

drivers/media/i2c/ov5648.c

134

#define OV5648_GAIN_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(9, 8))

drivers/media/i2c/ov5648.c

136

#define OV5648_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

137

#define OV5648_GAIN_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

217

#define OV5648_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

219

#define OV5648_CROP_START_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

221

#define OV5648_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

223

#define OV5648_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

225

#define OV5648_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

227

#define OV5648_CROP_END_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

229

#define OV5648_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

231

#define OV5648_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

233

#define OV5648_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

235

#define OV5648_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

237

#define OV5648_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

239

#define OV5648_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

241

#define OV5648_HTS_H(v) (((v) & GENMASK(12, 8)) >> 8)

drivers/media/i2c/ov5648.c

243

#define OV5648_HTS_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

245

#define OV5648_VTS_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov5648.c

247

#define OV5648_VTS_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

249

#define OV5648_OFFSET_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

251

#define OV5648_OFFSET_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

253

#define OV5648_OFFSET_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

255

#define OV5648_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

257

#define OV5648_SUB_INC_X_ODD(v) (((v) << 4) & GENMASK(7, 4))

drivers/media/i2c/ov5648.c

258

#define OV5648_SUB_INC_X_EVEN(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

260

#define OV5648_SUB_INC_Y_ODD(v) (((v) << 4) & GENMASK(7, 4))

drivers/media/i2c/ov5648.c

261

#define OV5648_SUB_INC_Y_EVEN(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

265

#define OV5648_HSYNCST_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

269

#define OV5648_HSYNCW_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

318

#define OV5648_BLC_CTRL1_START_LINE(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov5648.c

321

#define OV5648_BLC_CTRL2_RESET_FRAME_NUM(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov5648.c

324

#define OV5648_BLC_LINE_NUM(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

476

#define OV5648_GAIN_RED_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

478

#define OV5648_GAIN_RED_MAN_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

480

#define OV5648_GAIN_GREEN_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

482

#define OV5648_GAIN_GREEN_MAN_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

484

#define OV5648_GAIN_BLUE_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov5648.c

486

#define OV5648_GAIN_BLUE_MAN_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

64

#define OV5648_MIPI_SC_CTRL0_MIPI_LANES(v) (((v) << 5) & GENMASK(7, 5))

drivers/media/i2c/ov5648.c

76

#define OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4))

drivers/media/i2c/ov5648.c

77

#define OV5648_PLL_CTRL0_BITS(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

79

#define OV5648_PLL_CTRL1_SYS_DIV(v) (((v) << 4) & GENMASK(7, 4))

drivers/media/i2c/ov5648.c

80

#define OV5648_PLL_CTRL1_MIPI_DIV(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

82

#define OV5648_PLL_MUL(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov5648.c

85

#define OV5648_PLL_DIV_PLL_PRE_DIV(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

91

#define OV5648_PLLS_MUL(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov5648.c

93

#define OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4))

drivers/media/i2c/ov5648.c

94

#define OV5648_PLLS_CTRL_SYS_DIV(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov5648.c

96

#define OV5648_PLLS_DIV_PLLS_PRE_DIV(v) (((v) << 4) & GENMASK(5, 4))

drivers/media/i2c/ov5648.c

98

#define OV5648_PLLS_DIV_PLLS_SEL_DIV(v) ((v) & GENMASK(1, 0))

drivers/media/i2c/ov5670.c

35

GENMASK(7, 5))

drivers/media/i2c/ov5693.c

44

#define OV5693_EXPOSURE_CTRL_MASK GENMASK(19, 4)

drivers/media/i2c/ov5693.c

51

#define OV5693_GAIN_CTRL_MASK GENMASK(10, 4)

drivers/media/i2c/ov5693.c

61

#define OV5693_MWB_GAIN_MASK GENMASK(11, 0)

drivers/media/i2c/ov8865.c

102

GENMASK(7, 5))

drivers/media/i2c/ov8865.c

123

#define OV8865_MIPI_BIT_SEL(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

133

#define OV8865_SCLK_CTRL_SCLK_DIV(v) (((v) << 4) & GENMASK(7, 4))

drivers/media/i2c/ov8865.c

134

#define OV8865_SCLK_CTRL_SCLK_PRE_DIV(v) (((v) << 2) & GENMASK(3, 2))

drivers/media/i2c/ov8865.c

140

#define OV8865_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16)

drivers/media/i2c/ov8865.c

142

#define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

144

#define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

149

#define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8)

drivers/media/i2c/ov8865.c

151

#define OV8865_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

156

#define OV8865_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

158

#define OV8865_CROP_START_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

160

#define OV8865_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

162

#define OV8865_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

164

#define OV8865_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

166

#define OV8865_CROP_END_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

168

#define OV8865_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

170

#define OV8865_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

172

#define OV8865_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

174

#define OV8865_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

176

#define OV8865_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

178

#define OV8865_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

180

#define OV8865_HTS_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

182

#define OV8865_HTS_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

184

#define OV8865_VTS_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

186

#define OV8865_VTS_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

190

#define OV8865_OFFSET_X_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

192

#define OV8865_OFFSET_X_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

194

#define OV8865_OFFSET_Y_H(v) (((v) & GENMASK(14, 8)) >> 8)

drivers/media/i2c/ov8865.c

196

#define OV8865_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

198

#define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

200

#define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

202

#define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

204

#define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

206

#define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

208

#define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

210

#define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

212

#define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

227

#define OV8865_INC_Y_ODD(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

229

#define OV8865_INC_Y_EVEN(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

232

#define OV8865_ABLC_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

235

#define OV8865_ZLINE_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

249

#define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4))

drivers/media/i2c/ov8865.c

250

#define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0))

drivers/media/i2c/ov8865.c

288

#define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

296

#define OV8865_BLC_ANCHOR_LEFT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

298

#define OV8865_BLC_ANCHOR_LEFT_START_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

300

#define OV8865_BLC_ANCHOR_LEFT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

302

#define OV8865_BLC_ANCHOR_LEFT_END_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

304

#define OV8865_BLC_ANCHOR_RIGHT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

306

#define OV8865_BLC_ANCHOR_RIGHT_START_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

308

#define OV8865_BLC_ANCHOR_RIGHT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/media/i2c/ov8865.c

310

#define OV8865_BLC_ANCHOR_RIGHT_END_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

313

#define OV8865_BLC_TOP_ZLINE_START(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

315

#define OV8865_BLC_TOP_ZLINE_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

317

#define OV8865_BLC_TOP_BLKLINE_START(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

319

#define OV8865_BLC_TOP_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

321

#define OV8865_BLC_BOT_ZLINE_START(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

323

#define OV8865_BLC_BOT_ZLINE_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

325

#define OV8865_BLC_BOT_BLKLINE_START(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

327

#define OV8865_BLC_BOT_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))

drivers/media/i2c/ov8865.c

330

#define OV8865_BLC_OFFSET_LIMIT(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

335

#define OV8865_VFIFO_READ_START_H(v) (((v) & GENMASK(15, 8)) >> 8)

drivers/media/i2c/ov8865.c

337

#define OV8865_VFIFO_READ_START_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

35

#define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0))

drivers/media/i2c/ov8865.c

37

#define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)

drivers/media/i2c/ov8865.c

39

#define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

402

#define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0))

drivers/media/i2c/ov8865.c

403

#define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4))

drivers/media/i2c/ov8865.c

405

#define OV8865_MIPI_LANE_SEL23_LANE2(v) (((v) << 0) & GENMASK(2, 0))

drivers/media/i2c/ov8865.c

406

#define OV8865_MIPI_LANE_SEL23_LANE3(v) (((v) << 4) & GENMASK(6, 4))

drivers/media/i2c/ov8865.c

41

#define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0))

drivers/media/i2c/ov8865.c

424

#define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6)

drivers/media/i2c/ov8865.c

426

#define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

428

#define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6)

drivers/media/i2c/ov8865.c

43

#define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0))

drivers/media/i2c/ov8865.c

430

#define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

432

#define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6)

drivers/media/i2c/ov8865.c

434

#define OV8865_ISP_GAIN_BLUE_L(v) ((v) & GENMASK(5, 0))

drivers/media/i2c/ov8865.c

441

GENMASK(3, 2))

drivers/media/i2c/ov8865.c

442

#define OV8865_VAP_CTRL1_VSUB_COEF(v) (((v) - 1) & GENMASK(1, 0))

drivers/media/i2c/ov8865.c

45

#define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0))

drivers/media/i2c/ov8865.c

54

#define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0))

drivers/media/i2c/ov8865.c

56

#define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)

drivers/media/i2c/ov8865.c

58

#define OV8865_PLL_CTRLD_MUL_L(v) ((v) & GENMASK(7, 0))

drivers/media/i2c/ov8865.c

60

#define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0))

drivers/media/i2c/ov8865.c

62

#define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0))

drivers/media/i2c/ov8865.c

67

#define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0))

drivers/media/i2c/ov8865.c

97

#define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4))

drivers/media/i2c/ov8865.c

98

#define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0))

drivers/media/i2c/tc358746.c

108

#define NOL(val) FIELD_PREP(GENMASK(2, 1), (val))

drivers/media/i2c/tc358746.c

111

#define MODE(val) FIELD_PREP(GENMASK(31, 29), (val))

drivers/media/i2c/tc358746.c

113

#define ADDRESS(val) FIELD_PREP(GENMASK(28, 24), (val))

drivers/media/i2c/tc358746.c

115

#define DATA(val) FIELD_PREP(GENMASK(15, 0), (val))

drivers/media/i2c/tc358746.c

31

#define CHIPID GENMASK(15, 8)

drivers/media/i2c/tc358746.c

37

#define PDATAF_MASK GENMASK(9, 8)

drivers/media/i2c/tc358746.c

43

#define DATALANE_MASK GENMASK(1, 0)

drivers/media/i2c/tc358746.c

47

#define PDFMT(val) FIELD_PREP(GENMASK(7, 4), (val))

drivers/media/i2c/tc358746.c

50

#define MCLK_HIGH_MASK GENMASK(15, 8)

drivers/media/i2c/tc358746.c

51

#define MCLK_LOW_MASK GENMASK(7, 0)

drivers/media/i2c/tc358746.c

56

#define PLL_PRD_MASK GENMASK(15, 12)

drivers/media/i2c/tc358746.c

58

#define PLL_FBD_MASK GENMASK(8, 0)

drivers/media/i2c/tc358746.c

62

#define PLL_FRS_MASK GENMASK(11, 10)

drivers/media/i2c/tc358746.c

69

#define MCLKDIV_MASK GENMASK(3, 2)

drivers/media/i2c/tc358746.c

92

#define TCLK_ZEROCNT(val) FIELD_PREP(GENMASK(15, 8), (val))

drivers/media/i2c/tc358746.c

93

#define TCLK_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))

drivers/media/i2c/tc358746.c

97

#define THS_ZEROCNT(val) FIELD_PREP(GENMASK(14, 8), (val))

drivers/media/i2c/tc358746.c

98

#define THS_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))

drivers/media/i2c/tw9900.c

47

#define TW9900_STDNOW_MASK GENMASK(6, 4)

drivers/media/i2c/vd55g1.c

1112

ret = vd55g1_update_gpios(sensor, GENMASK(VD55G1_NB_GPIOS - 1, 0));

drivers/media/i2c/vd56g3.c

677

GENMASK(2, 0), 0, 0);

drivers/media/i2c/vd56g3.c

971

ret = vd56g3_write_gpiox(sensor, GENMASK(VD56G3_NB_GPIOS - 1, 0));

drivers/media/i2c/video-i2c.c

66

#define MLX90640_REG_CTL1_MASK GENMASK(9, 7)

drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c

133

*val = FIELD_GET(GENMASK(15, 8), completion);

drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c

37

#define IFC_REQ(req, addr, data) (FIELD_PREP(GENMASK(23, 16), data) | \

drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c

38

FIELD_PREP(GENMASK(15, 4), addr) | \

drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c

39

FIELD_PREP(GENMASK(1, 0), req))

drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c

78

val |= FIELD_PREP(GENMASK(6, 1), 13);

drivers/media/pci/intel/ipu6/ipu6-isys.c

289

writel(GENMASK(19, 0),

drivers/media/pci/intel/ipu6/ipu6-isys.c

295

writel(GENMASK(28, 0), base + IPU6_REG_ISYS_UNISPART_IRQ_CLEAR);

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

126

#define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK GENMASK(4, 0)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

195

#define BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK GENMASK(15, 0)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

23

#define IPU6_BUTTRESS_PWR_STATE_IS_PWR_MASK GENMASK(4, 3)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

26

#define IPU6_BUTTRESS_PWR_STATE_PS_PWR_MASK GENMASK(7, 6)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

46

#define BUTTRESS_REG_BTRS_CTRL_REF_CLK_IND GENMASK(9, 8)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

56

#define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL GENMASK(19, 16)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

57

#define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK GENMASK(15, 8)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

58

#define BUTTRESS_FREQ_CTL_RATIO_MASK GENMASK(7, 0)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

67

#define BUTTRESS_PWR_STATE_HH_STATUS_MASK GENMASK(12, 11)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

76

#define BUTTRESS_PWR_STATE_IS_PWR_FSM_MASK GENMASK(23, 19)

drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h

95

#define BUTTRESS_PWR_STATE_PS_PWR_FSM_MASK GENMASK(28, 24)

drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h

36

#define IPU6SE_CSI_RX_ERROR_IRQ_MASK GENMASK(18, 0)

drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h

37

#define IPU6_CSI_RX_ERROR_IRQ_MASK GENMASK(19, 0)

drivers/media/pci/intel/ipu6/ipu6-platform-isys-csi2-reg.h

48

#define PPI_INTF_CONFIG_NOF_ENABLED_DLANES_MASK GENMASK(4, 3)

drivers/media/pci/intel/ipu6/ipu6.c

672

sku_id = FIELD_GET(GENMASK(6, 4), val);

drivers/media/pci/intel/ipu6/ipu6.c

673

version = FIELD_GET(GENMASK(3, 0), val);

drivers/media/pci/tw686x/tw686x-video.c

370

mask = GENMASK(max_fps - 1, 0);

drivers/media/pci/zoran/zoran_device.c

828

fcnt = (stat_com & GENMASK(31, 24)) >> 24;

drivers/media/pci/zoran/zoran_device.c

829

size = (stat_com & GENMASK(22, 1)) >> 1;

drivers/media/platform/allegro-dvt/allegro-mail.c

108

dst[i++] = FIELD_PREP(GENMASK(31, 24), codec) |

drivers/media/platform/allegro-dvt/allegro-mail.c

109

FIELD_PREP(GENMASK(23, 8), param->constraint_set_flags) |

drivers/media/platform/allegro-dvt/allegro-mail.c

110

FIELD_PREP(GENMASK(7, 0), param->profile);

drivers/media/platform/allegro-dvt/allegro-mail.c

111

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->tier) |

drivers/media/platform/allegro-dvt/allegro-mail.c

112

FIELD_PREP(GENMASK(15, 0), param->level);

drivers/media/platform/allegro-dvt/allegro-mail.c

116

val |= FIELD_PREP(GENMASK(7, 4), param->log2_max_frame_num);

drivers/media/platform/allegro-dvt/allegro-mail.c

118

val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc - 1);

drivers/media/platform/allegro-dvt/allegro-mail.c

120

val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc);

drivers/media/platform/allegro-dvt/allegro-mail.c

145

dst[i++] = FIELD_PREP(GENMASK(15, 8), param->beta_offset) |

drivers/media/platform/allegro-dvt/allegro-mail.c

146

FIELD_PREP(GENMASK(7, 0), param->tc_offset);

drivers/media/platform/allegro-dvt/allegro-mail.c

153

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->clip_vrt_range) |

drivers/media/platform/allegro-dvt/allegro-mail.c

154

FIELD_PREP(GENMASK(15, 0), param->clip_hrz_range);

drivers/media/platform/allegro-dvt/allegro-mail.c

155

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->me_range[1]) |

drivers/media/platform/allegro-dvt/allegro-mail.c

156

FIELD_PREP(GENMASK(15, 0), param->me_range[0]);

drivers/media/platform/allegro-dvt/allegro-mail.c

157

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->me_range[3]) |

drivers/media/platform/allegro-dvt/allegro-mail.c

158

FIELD_PREP(GENMASK(15, 0), param->me_range[2]);

drivers/media/platform/allegro-dvt/allegro-mail.c

159

dst[i++] = FIELD_PREP(GENMASK(31, 24), param->min_tu_size) |

drivers/media/platform/allegro-dvt/allegro-mail.c

160

FIELD_PREP(GENMASK(23, 16), param->max_tu_size) |

drivers/media/platform/allegro-dvt/allegro-mail.c

161

FIELD_PREP(GENMASK(15, 8), param->min_cu_size) |

drivers/media/platform/allegro-dvt/allegro-mail.c

162

FIELD_PREP(GENMASK(8, 0), param->max_cu_size);

drivers/media/platform/allegro-dvt/allegro-mail.c

163

dst[i++] = FIELD_PREP(GENMASK(15, 8), param->max_transfo_depth_intra) |

drivers/media/platform/allegro-dvt/allegro-mail.c

164

FIELD_PREP(GENMASK(7, 0), param->max_transfo_depth_inter);

drivers/media/platform/allegro-dvt/allegro-mail.c

171

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->clk_ratio) |

drivers/media/platform/allegro-dvt/allegro-mail.c

172

FIELD_PREP(GENMASK(15, 0), param->framerate);

drivers/media/platform/allegro-dvt/allegro-mail.c

175

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->min_qp) |

drivers/media/platform/allegro-dvt/allegro-mail.c

176

FIELD_PREP(GENMASK(15, 0), param->initial_qp);

drivers/media/platform/allegro-dvt/allegro-mail.c

177

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->ip_delta) |

drivers/media/platform/allegro-dvt/allegro-mail.c

178

FIELD_PREP(GENMASK(15, 0), param->max_qp);

drivers/media/platform/allegro-dvt/allegro-mail.c

179

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->golden_ref) |

drivers/media/platform/allegro-dvt/allegro-mail.c

180

FIELD_PREP(GENMASK(15, 0), param->pb_delta);

drivers/media/platform/allegro-dvt/allegro-mail.c

181

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->golden_ref_frequency) |

drivers/media/platform/allegro-dvt/allegro-mail.c

182

FIELD_PREP(GENMASK(15, 0), param->golden_delta);

drivers/media/platform/allegro-dvt/allegro-mail.c

190

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->max_pixel_value) |

drivers/media/platform/allegro-dvt/allegro-mail.c

191

FIELD_PREP(GENMASK(15, 0), param->max_psnr);

drivers/media/platform/allegro-dvt/allegro-mail.c

202

dst[i++] = FIELD_PREP(GENMASK(31, 24), param->freq_golden_ref) |

drivers/media/platform/allegro-dvt/allegro-mail.c

203

FIELD_PREP(GENMASK(23, 16), param->num_b) |

drivers/media/platform/allegro-dvt/allegro-mail.c

204

FIELD_PREP(GENMASK(15, 0), param->gop_length);

drivers/media/platform/allegro-dvt/allegro-mail.c

211

dst[i++] = FIELD_PREP(GENMASK(31, 24), param->freq_golden_ref) |

drivers/media/platform/allegro-dvt/allegro-mail.c

212

FIELD_PREP(GENMASK(23, 16), param->num_b) |

drivers/media/platform/allegro-dvt/allegro-mail.c

213

FIELD_PREP(GENMASK(15, 0), param->gop_length);

drivers/media/platform/allegro-dvt/allegro-mail.c

260

param->num_ref_idx_l0 = FIELD_GET(GENMASK(7, 4), src[9]);

drivers/media/platform/allegro-dvt/allegro-mail.c

261

param->num_ref_idx_l1 = FIELD_GET(GENMASK(11, 8), src[9]);

drivers/media/platform/allegro-dvt/allegro-mail.c

327

dst[i++] = FIELD_PREP(GENMASK(31, 16), msg->padding) |

drivers/media/platform/allegro-dvt/allegro-mail.c

328

FIELD_PREP(GENMASK(15, 0), msg->pps_qp);

drivers/media/platform/allegro-dvt/allegro-mail.c

382

msg->num_ref_idx_l0 = FIELD_GET(GENMASK(7, 4), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

383

msg->num_ref_idx_l1 = FIELD_GET(GENMASK(11, 8), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

421

msg->skip = FIELD_GET(GENMASK(31, 16), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

422

msg->is_ref = FIELD_GET(GENMASK(15, 0), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

429

msg->num_row = FIELD_GET(GENMASK(31, 16), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

430

msg->num_column = FIELD_GET(GENMASK(15, 0), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

431

msg->num_ref_idx_l1 = FIELD_GET(GENMASK(31, 24), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

432

msg->num_ref_idx_l0 = FIELD_GET(GENMASK(23, 16), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

433

msg->qp = FIELD_GET(GENMASK(15, 0), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

444

msg->reserved = FIELD_GET(GENMASK(31, 24), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

445

msg->is_last_slice = FIELD_GET(GENMASK(23, 16), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

446

msg->is_first_slice = FIELD_GET(GENMASK(15, 8), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

447

msg->is_idr = FIELD_GET(GENMASK(7, 0), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

449

msg->reserved1 = FIELD_GET(GENMASK(31, 16), src[i]);

drivers/media/platform/allegro-dvt/allegro-mail.c

450

msg->pps_qp = FIELD_GET(GENMASK(15, 0), src[i++]);

drivers/media/platform/allegro-dvt/allegro-mail.c

505

dst[0] = FIELD_PREP(GENMASK(31, 16), header->type) |

drivers/media/platform/allegro-dvt/allegro-mail.c

506

FIELD_PREP(GENMASK(15, 0), size);

drivers/media/platform/allegro-dvt/allegro-mail.c

528

header->type = FIELD_GET(GENMASK(31, 16), src[0]);

drivers/media/platform/allegro-dvt/allegro-mail.c

98

dst[i++] = FIELD_PREP(GENMASK(31, 16), param->height) |

drivers/media/platform/allegro-dvt/allegro-mail.c

99

FIELD_PREP(GENMASK(15, 0), param->width);

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

10

#define ISP_TOP_INPUT_SIZE_VERT_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

12

#define ISP_TOP_INPUT_SIZE_HORIZ_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

130

#define ISP_TOP_BED_CTRL_YHS_STAT_EN_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

16

#define ISP_TOP_FRM_SIZE_CORE_VERT_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

177

#define ISP_TOP_3A_STAT_CRTL_AWB_POINT_MASK GENMASK(6, 4)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

179

#define ISP_TOP_3A_STAT_CRTL_AE_POINT_MASK GENMASK(9, 8)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

18

#define ISP_TOP_FRM_SIZE_CORE_HORIZ_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

181

#define ISP_TOP_3A_STAT_CRTL_AF_POINT_MASK GENMASK(13, 12)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

185

#define ISP_LSWB_BLC_OFST0_R_OFST_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

187

#define ISP_LSWB_BLC_OFST0_GR_OFST_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

191

#define ISP_LSWB_BLC_OFST1_GB_OFST_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

193

#define ISP_LSWB_BLC_OFST1_B_OFST_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

197

#define ISP_LSWB_BLC_PHSOFST_VERT_OFST_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

199

#define ISP_LSWB_BLC_PHSOFST_HORIZ_OFST_MASK GENMASK(3, 2)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

203

#define ISP_LSWB_WB_GAIN0_R_GAIN_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

205

#define ISP_LSWB_WB_GAIN0_GR_GAIN_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

209

#define ISP_LSWB_WB_GAIN1_GB_GAIN_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

211

#define ISP_LSWB_WB_GAIN1_B_GAIN_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

215

#define ISP_LSWB_WB_GAIN2_IR_GAIN_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

219

#define ISP_LSWB_WB_LIMIT0_WB_LIMIT_R_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

22

#define ISP_TOP_HOLD_SIZE_CORE_HORIZ_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

222

#define ISP_LSWB_WB_LIMIT0_WB_LIMIT_GR_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

227

#define ISP_LSWB_WB_LIMIT1_WB_LIMIT_GB_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

230

#define ISP_LSWB_WB_LIMIT1_WB_LIMIT_B_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

235

#define ISP_LSWB_WB_PHSOFST_VERT_OFST_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

237

#define ISP_LSWB_WB_PHSOFST_HORIZ_OFST_MASK GENMASK(3, 2)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

241

#define ISP_LSWB_LNS_PHSOFST_VERT_OFST_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

243

#define ISP_LSWB_LNS_PHSOFST_HORIZ_OFST_MASK GENMASK(3, 2)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

247

#define ISP_DMS_COMMON_PARAM0_VERT_PHS_OFST_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

249

#define ISP_DMS_COMMON_PARAM0_HORIZ_PHS_OFST_MASK GENMASK(3, 2)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

253

#define ISP_CM0_COEF00_01_MTX_00_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

255

#define ISP_CM0_COEF00_01_MTX_01_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

259

#define ISP_CM0_COEF02_10_MTX_02_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

261

#define ISP_CM0_COEF02_10_MTX_10_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

265

#define ISP_CM0_COEF11_12_MTX_11_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

267

#define ISP_CM0_COEF11_12_MTX_12_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

271

#define ISP_CM0_COEF20_21_MTX_20_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

273

#define ISP_CM0_COEF20_21_MTX_21_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

277

#define ISP_CM0_COEF22_OUP_OFST0_MTX_22_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

281

#define ISP_CCM_MTX_00_01_MTX_00_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

283

#define ISP_CCM_MTX_00_01_MTX_01_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

287

#define ISP_CCM_MTX_02_03_MTX_02_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

291

#define ISP_CCM_MTX_10_11_MTX_10_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

293

#define ISP_CCM_MTX_10_11_MTX_11_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

297

#define ISP_CCM_MTX_12_13_MTX_12_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

301

#define ISP_CCM_MTX_20_21_MTX_20_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

303

#define ISP_CCM_MTX_20_21_MTX_21_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

307

#define ISP_CCM_MTX_22_23_RS_MTX_22_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

314

#define ISP_PST_GM_LUT_DATA0(x) (((x) & GENMASK(15, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

315

#define ISP_PST_GM_LUT_DATA1(x) (((x) & GENMASK(15, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

323

#define DISP0_TOP_CRP2_START_V_START_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

325

#define DISP0_TOP_CRP2_START_H_START_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

329

#define DISP0_TOP_CRP2_SIZE_V_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

331

#define DISP0_TOP_CRP2_SIZE_H_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

335

#define DISP0_TOP_OUT_SIZE_SCL_OUT_HEIGHT_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

337

#define DISP0_TOP_OUT_SIZE_SCL_OUT_WIDTH_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

341

#define ISP_DISP0_TOP_IN_SIZE_VSIZE_MASK GENMASK(12, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

343

#define ISP_DISP0_TOP_IN_SIZE_HSIZE_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

347

#define DISP0_PPS_SCALE_EN_VSC_TAP_NUM_MASK GENMASK(3, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

349

#define DISP0_PPS_SCALE_EN_HSC_TAP_NUM_MASK GENMASK(7, 4)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

351

#define DISP0_PPS_SCALE_EN_PREVSC_FLT_NUM_MASK GENMASK(11, 8)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

353

#define DISP0_PPS_SCALE_EN_PREHSC_FLT_NUM_MASK GENMASK(15, 12)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

355

#define DISP0_PPS_SCALE_EN_PREVSC_RATE_MASK GENMASK(17, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

357

#define DISP0_PPS_SCALE_EN_PREHSC_RATE_MASK GENMASK(19, 18)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

371

#define DISP0_PPS_SCALE_EN_HSC_NOR_RS_BITS_MASK GENMASK(27, 24)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

373

#define DISP0_PPS_SCALE_EN_VSC_NOR_RS_BITS_MASK GENMASK(31, 28)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

377

#define DISP0_PPS_VSC_START_PHASE_STEP_VERT_FRAC_MASK GENMASK(23, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

379

#define DISP0_PPS_VSC_START_PHASE_STEP_VERT_INTE_MASK GENMASK(27, 24)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

383

#define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_FRAC_MASK GENMASK(23, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

385

#define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_INTE_MASK GENMASK(27, 24)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

396

#define ISP_SCALE0_COEF_IDX_LUMA_CTYPE_MASK GENMASK(12, 10)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

400

#define ISP_SCALE0_COEF_LUMA_DATA1(x) (((x) & GENMASK(10, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

401

#define ISP_SCALE0_COEF_LUMA_DATA0(x) (((x) & GENMASK(10, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

407

#define ISP_SCALE0_COEF_IDX_CHRO_CTYPE_MASK GENMASK(12, 10)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

411

#define ISP_SCALE0_COEF_CHRO_DATA1(x) (((x) & GENMASK(10, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

412

#define ISP_SCALE0_COEF_CHRO_DATA0(x) (((x) & GENMASK(10, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

415

#define ISP_AF_CTRL_VERT_OFST_MASK GENMASK(15, 14)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

417

#define ISP_AF_CTRL_HORIZ_OFST_MASK GENMASK(17, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

421

#define ISP_AF_HV_SIZE_GLB_WIN_YSIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

423

#define ISP_AF_HV_SIZE_GLB_WIN_XSIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

427

#define ISP_AF_HV_BLKNUM_V_NUM_MASK GENMASK(5, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

429

#define ISP_AF_HV_BLKNUM_H_NUM_MASK GENMASK(21, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

439

#define ISP_AF_IDX_DATA_VIDX_DATA(x) (((x) & GENMASK(15, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

440

#define ISP_AF_IDX_DATA_HIDX_DATA(x) (((x) & GENMASK(15, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

446

#define ISP_AE_CTRL_LUMA_MODE_MASK GENMASK(9, 8)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

450

#define ISP_AE_CTRL_VERT_OFST_MASK GENMASK(25, 24)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

452

#define ISP_AE_CTRL_HORIZ_OFST_MASK GENMASK(27, 26)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

456

#define ISP_AE_HV_SIZE_VERT_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

458

#define ISP_AE_HV_SIZE_HORIZ_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

46

#define ISP_TOP_PATH_SEL_CORE_MASK GENMASK(18, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

462

#define ISP_AE_HV_BLKNUM_V_NUM_MASK GENMASK(6, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

464

#define ISP_AE_HV_BLKNUM_H_NUM_MASK GENMASK(22, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

469

#define ISP_AE_IDX_DATA_VIDX_DATA(x) (((x) & GENMASK(15, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

470

#define ISP_AE_IDX_DATA_HIDX_DATA(x) (((x) & GENMASK(15, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

474

#define ISP_AE_BLK_WT_DATA_WT(i, x) (((x) & GENMASK(3, 0)) << ((i) * 4))

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

477

#define ISP_AWB_CTRL_VERT_OFST_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

479

#define ISP_AWB_CTRL_HORIZ_OFST_MASK GENMASK(3, 2)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

483

#define ISP_AWB_HV_SIZE_VERT_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

485

#define ISP_AWB_HV_SIZE_HORIZ_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

489

#define ISP_AWB_HV_BLKNUM_V_NUM_MASK GENMASK(5, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

491

#define ISP_AWB_HV_BLKNUM_H_NUM_MASK GENMASK(21, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

495

#define ISP_AWB_STAT_RG_MIN_VALUE_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

497

#define ISP_AWB_STAT_RG_MAX_VALUE_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

501

#define ISP_AWB_STAT_BG_MIN_VALUE_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

503

#define ISP_AWB_STAT_BG_MAX_VALUE_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

507

#define ISP_AWB_STAT_RG_HL_LOW_VALUE_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

509

#define ISP_AWB_STAT_RG_HL_HIGH_VALUE_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

51

#define ISP_TOP_DISPIN_SEL_DISP0_MASK GENMASK(3, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

513

#define ISP_AWB_STAT_BG_HL_LOW_VALUE_MASK GENMASK(11, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

515

#define ISP_AWB_STAT_BG_HL_HIGH_VALUE_MASK GENMASK(27, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

524

#define ISP_AWB_IDX_DATA_VIDX_DATA(x) (((x) & GENMASK(15, 0)) << 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

525

#define ISP_AWB_IDX_DATA_HIDX_DATA(x) (((x) & GENMASK(15, 0)) << 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

529

#define ISP_AWB_BLK_WT_DATA_WT(i, x) (((x) & GENMASK(3, 0)) << ((i) * 4))

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

532

#define ISP_WRMIFX3_0_CH0_CTRL0_STRIDE_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

536

#define ISP_WRMIFX3_0_CH0_CTRL1_PIX_BITS_MODE_MASK GENMASK(30, 27)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

54

#define ISP_TOP_DISPIN_SEL_DISP1_MASK GENMASK(7, 4)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

541

#define ISP_WRMIFX3_0_CH1_CTRL0_STRIDE_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

545

#define ISP_WRMIFX3_0_CH1_CTRL1_PIX_BITS_MODE_MASK GENMASK(30, 27)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

551

#define ISP_WRMIFX3_0_WIN_LUMA_H_LUMA_HEND_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

555

#define ISP_WRMIFX3_0_WIN_LUMA_V_LUMA_VEND_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

559

#define ISP_WRMIFX3_0_WIN_CHROM_H_CHROM_HEND_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

563

#define ISP_WRMIFX3_0_WIN_CHROM_V_CHROM_VEND_MASK GENMASK(28, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

57

#define ISP_TOP_DISPIN_SEL_DISP2_MASK GENMASK(11, 8)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

573

#define ISP_WRMIFX3_0_FMT_SIZE_HSIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

575

#define ISP_WRMIFX3_0_FMT_SIZE_VSIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

579

#define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

587

#define ISP_WRMIFX3_0_FMT_CTRL_MTX_PLANE_MASK GENMASK(5, 4)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

590

#define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_MASK GENMASK(18, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

597

#define VIU_DMAWR_BADDR0_AF_STATS_BASE_ADDR_MASK GENMASK(27, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

601

#define VIU_DMAWR_BADDR1_AWB_STATS_BASE_ADDR_MASK GENMASK(27, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

605

#define VIU_DMAWR_BADDR2_AE_STATS_BASE_ADDR_MASK GENMASK(27, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

609

#define VIU_DMAWR_SIZE0_AF_STATS_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

611

#define VIU_DMAWR_SIZE0_AWB_STATS_SIZE_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

615

#define VIU_DMAWR_SIZE1_AE_STATS_SIZE_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h

96

#define ISP_TOP_FED_CTRL_RAWCNR_EN_MASK GENMASK(6, 5)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

103

#define CSI2_VC_MODE_HS_ISP_SEL_VC_MASK GENMASK(23, 20)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

116

#define MIPI_ADAPT_DDR_RD0_CNTL1_PORT_SEL_MASK GENMASK(31, 30)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

121

#define MIPI_ADAPT_PIXEL0_CNTL0_WORK_MODE_MASK GENMASK(17, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

124

#define MIPI_ADAPT_PIXEL0_CNTL0_DATA_TYPE_MASK GENMASK(25, 20)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

130

#define MIPI_ADAPT_ALIG_CNTL0_H_NUM_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

132

#define MIPI_ADAPT_ALIG_CNTL0_V_NUM_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

136

#define MIPI_ADAPT_ALIG_CNTL1_HPE_NUM_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

140

#define MIPI_ADAPT_ALIG_CNTL2_VPE_NUM_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

42

#define ADAP_SUBMD_MASK GENMASK(17, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

45

#define ADAP_REG_ADDR_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

81

#define CSI2_GEN_CTRL0_ENABLE_PACKETS_MASK GENMASK(20, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

86

#define CSI2_X_START_END_ISP_X_START_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

88

#define CSI2_X_START_END_ISP_X_END_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

92

#define CSI2_Y_START_END_ISP_Y_START_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

94

#define CSI2_Y_START_END_ISP_Y_END_MASK GENMASK(31, 16)

drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c

98

#define CSI2_VC_MODE_VS_ISP_SEL_VC_MASK GENMASK(19, 16)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

102

#define MIPI_PHY_TCLK_SETTLE_CYCLES_MASK GENMASK(7, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

106

#define MIPI_PHY_THS_EXIT_CYCLES_MASK GENMASK(7, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

110

#define MIPI_PHY_THS_SKIP_CYCLES_MASK GENMASK(7, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

114

#define MIPI_PHY_THS_SETTLE_CYCLES_MASK GENMASK(7, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

117

#define MIPI_PHY_TINIT_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

121

#define MIPI_PHY_TULPS_C_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

125

#define MIPI_PHY_TULPS_S_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

129

#define MIPI_PHY_TMBIAS_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

133

#define MIPI_PHY_TLP_EN_W_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

137

#define MIPI_PHY_TLPOK_CYCLES_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

141

#define MIPI_PHY_TWD_INIT_DOG_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

145

#define MIPI_PHY_TWD_HS_DOG_MASK GENMASK(31, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

149

#define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_MASK GENMASK(3, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

154

#define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_MASK GENMASK(7, 4)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

159

#define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_MASK GENMASK(11, 8)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

164

#define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_MASK GENMASK(14, 12)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

171

#define MIPI_PHY_MUX_CTRL1_LANE3_SRC_MASK GENMASK(3, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

176

#define MIPI_PHY_MUX_CTRL1_LANE2_SRC_MASK GENMASK(7, 4)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

181

#define MIPI_PHY_MUX_CTRL1_LANE1_SRC_MASK GENMASK(11, 8)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

186

#define MIPI_PHY_MUX_CTRL1_LANE0_SRC_MASK GENMASK(14, 12)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

194

#define CSI2_HOST_N_LANES_MASK GENMASK(1, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

28

#define CSI2_SUBMD_MASK GENMASK(17, 16)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

31

#define CSI2_REG_ADDR_MASK GENMASK(15, 0)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

92

#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_MASK GENMASK(6, 2)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

94

#define MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_MASK GENMASK(9, 7)

drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c

98

#define MIPI_PHY_TCLK_MISS_CYCLES_MASK GENMASK(7, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

136

#define GE2D_DST_WRITE_RSP_CNT GENMASK(28, 17)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

137

#define GE2D_DP_STATUS GENMASK(16, 7)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

148

#define GE2D_WR_DST1_STATUS GENMASK(29, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

151

#define GE2D_RD_SRC2_STATE_Y GENMASK(13, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

156

#define GE2D_RD_SRC1_STATE_CR GENMASK(7, 6)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

157

#define GE2D_RD_SRC1_STATE_CB GENMASK(5, 4)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

158

#define GE2D_RD_SRC1_STATE_Y GENMASK(3, 2)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

164

#define GE2D_COLOR_R_Y GENMASK(31, 24)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

165

#define GE2D_COLOR_B_CB GENMASK(23, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

166

#define GE2D_COLOR_B_CR GENMASK(15, 8)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

167

#define GE2D_COLOR_ALPHA GENMASK(7, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

173

#define GE2D_START GENMASK(28, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

176

#define GE2D_END GENMASK(12, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

181

#define GE2D_SRC1_CANVAS_ADDR GENMASK(31, 24)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

188

#define GE2D_LUT_ADDR GENMASK(7, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

203

#define GE2D_DST2_CANVAS_ADDR GENMASK(23, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

204

#define GE2D_SRC2_CANVAS_ADDR GENMASK(15, 8)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

205

#define GE2D_DST1_CANVAS_ADDR GENMASK(7, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

22

#define GE2D_DST1_8B_MODE_SEL GENMASK(25, 24)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

228

#define GE2D_SRC1_COLOR_MULT_ALPHA_SEL GENMASK(26, 25)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

230

#define GE2D_ALU_BLEND_MODE GENMASK(22, 20)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

239

#define GE2D_ALU_SRC_COLOR_BLEND_FACTOR GENMASK(19, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

24

#define GE2D_SRC2_8B_MODE_SEL GENMASK(16, 15)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

240

#define GE2D_ALU_DST_COLOR_BLEND_FACTOR GENMASK(15, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

258

#define GE2D_ALU_OPERATION_LOGIC GENMASK(15, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

26

#define GE2D_SRC2_PIC_STRUCT GENMASK(13, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

277

#define GE2D_ALU_ALPHA_BLEND_MODE GENMASK(10, 8)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

278

#define GE2D_ALU_SRC_ALPHA_BLEND_FACTOR GENMASK(7, 4)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

279

#define GE2D_ALU_DST_ALPHA_BLEND_FACTOR GENMASK(3, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

28

#define GE2D_SRC1_8B_MODE_SEL GENMASK(6, 5)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

290

#define GE2D_ALU_ALPHA_OPERATION_LOGIC GENMASK(3, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

31

#define GE2D_SRC1_PIC_STRUCT GENMASK(2, 1)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

335

#define GE2D_DST2_BYTEMASK_VAL GENMASK(31, 28)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

336

#define GE2D_DST2_PIC_STRUCT GENMASK(27, 26)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

337

#define GE2D_DST2_8B_MODE_SEL GENMASK(25, 24)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

338

#define GE2D_DST2_COLOR_MAP GENMASK(22, 19)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

339

#define GE2D_DST2_FORMAT GENMASK(17, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

341

#define GE2D_DST2_X_DISCARD_MODE GENMASK(13, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

342

#define GE2D_DST2_Y_DISCARD_MODE GENMASK(11, 10)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

344

#define GE2D_DST1_X_DISCARD_MODE GENMASK(5, 4)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

345

#define GE2D_DST1_Y_DISCARD_MODE GENMASK(3, 2)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

353

#define GE2D_STRIDE_SIZE GENMASK(19, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

39

#define GE2D_INTERRUPT_CTRL GENMASK(25, 24)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

40

#define GE2D_SRC2_BURST_SIZE_CTRL GENMASK(23, 22)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

41

#define GE2D_SRC1_BURST_SIZE_CTRL GENMASK(21, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

42

#define GE2D_DST1_PIC_STRUCT GENMASK(15, 14)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

43

#define GE2D_SRC_RD_CTRL GENMASK(13, 12)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

48

#define GE2D_SRC1_GB_ALPHA GENMASK(7, 0)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

61

#define GE2D_DST1_COLOR_MAP GENMASK(22, 19)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

63

#define GE2D_DST1_FORMAT GENMASK(17, 16)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

65

#define GE2D_SRC2_COLOR_MAP GENMASK(14, 11)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

67

#define GE2D_SRC2_FORMAT GENMASK(9, 8)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

69

#define GE2D_SRC1_COLOR_MAP GENMASK(6, 3)

drivers/media/platform/amlogic/meson-ge2d/ge2d-regs.h

71

#define GE2D_SRC1_FORMAT GENMASK(1, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

147

#define MALI_C55_ISP_RAW_BYPASS_FR_BYPASS_MASK GENMASK(9, 8)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

156

#define MALI_C55_BAYER_ORDER_MASK GENMASK(1, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

164

#define MALI_C55_5BIN_HIST_SWITCH_MASK GENMASK(2, 1)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

173

#define MALI_C55_AEXP_HIST_SWITCH_MASK GENMASK(14, 13)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

188

#define MALI_C55_INPUT_WIDTH_MASK GENMASK(18, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

200

#define MALI_C55_DIGITAL_GAIN_MASK GENMASK(12, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

202

#define MALI_C55_DIGITAL_GAIN_OFFSET_MASK GENMASK(19, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

205

#define MALI_C55_SINTER_VIEW_FILTER_MASK GENMASK(1, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

206

#define MALI_C55_SINTER_SCALE_MODE_MASK GENMASK(3, 2)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

230

#define MALI_C55_MESH_SHADING_SCALE_MASK GENMASK(4, 2)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

232

#define MALI_C55_MESH_SHADING_PAGE_R_MASK GENMASK(9, 8)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

234

#define MALI_C55_MESH_SHADING_PAGE_G_MASK GENMASK(11, 10)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

236

#define MALI_C55_MESH_SHADING_PAGE_B_MASK GENMASK(13, 12)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

238

#define MALI_C55_MESH_SHADING_MESH_WIDTH_MASK GENMASK(21, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

240

#define MALI_C55_MESH_SHADING_MESH_HEIGHT_MASK GENMASK(29, 24)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

244

#define MALI_C55_MESH_SHADING_ALPHA_BANK_R_MASK GENMASK(2, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

245

#define MALI_C55_MESH_SHADING_ALPHA_BANK_G_MASK GENMASK(5, 3)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

247

#define MALI_C55_MESH_SHADING_ALPHA_BANK_B_MASK GENMASK(8, 6)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

25

#define MALI_C55_INTERRUPT_MASK_ALL GENMASK(31, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

250

#define MALI_C55_MESH_SHADING_ALPHA_R_MASK GENMASK(7, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

251

#define MALI_C55_MESH_SHADING_ALPHA_G_MASK GENMASK(15, 8)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

253

#define MALI_C55_MESH_SHADING_ALPHA_B_MASK GENMASK(23, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

256

#define MALI_c55_MESH_STRENGTH_MASK GENMASK(15, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

260

#define MALI_C55_AWB_GAIN00_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

261

#define MALI_C55_AWB_GAIN01_MASK GENMASK(27, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

264

#define MALI_C55_AWB_GAIN10_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

265

#define MALI_C55_AWB_GAIN11_MASK GENMASK(27, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

282

#define MALI_C55_CCM_COEF_MASK GENMASK(12, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

286

#define MALI_C55_CCM_ANTIFOG_GAIN_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

290

#define MALI_C55_CCM_ANTIFOG_OFFSET_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

296

#define MALI_C55_AWB_WHITE_LEVEL_MASK GENMASK(9, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

298

#define MALI_C55_AWB_BLACK_LEVEL_MASK GENMASK(9, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

300

#define MALI_C55_AWB_CR_MAX_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

302

#define MALI_C55_AWB_CR_MIN_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

304

#define MALI_C55_AWB_CB_MAX_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

306

#define MALI_C55_AWB_CB_MIN_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

308

#define MALI_C55_AWB_NODES_USED_HORIZ_MASK GENMASK(7, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

309

#define MALI_C55_AWB_NODES_USED_VERT_MASK GENMASK(15, 8)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

312

#define MALI_C55_AWB_CR_HIGH_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

314

#define MALI_C55_AWB_CR_LOW_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

316

#define MALI_C55_AWB_CB_HIGH_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

318

#define MALI_C55_AWB_CB_LOW_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

32

#define MALI_C55_REG_GEN_PREFETCH_MASK GENMASK(31, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

324

#define MALI_C55_AEXP_HIST_SKIP_X_MASK GENMASK(2, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

328

#define MALI_C55_AEXP_HIST_SKIP_Y_MASK GENMASK(6, 4)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

333

#define MALI_C55_AEXP_HIST_SCALE_BOTTOM_MASK GENMASK(3, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

334

#define MALI_C55_AEXP_HIST_SCALE_TOP_MASK GENMASK(7, 4)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

337

#define MALI_C55_AEXP_HIST_PLANE_MODE_MASK GENMASK(2, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

339

#define MALI_C55_AEXP_HIST_NODES_USED_HORIZ_MASK GENMASK(7, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

340

#define MALI_C55_AEXP_HIST_NODES_USED_VERT_MASK GENMASK(15, 8)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

363

#define MALI_C55_WRITER_MODE_MASK GENMASK(4, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

380

#define MALI_C55_WRITER_SUBMODE_MASK GENMASK(7, 6)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

393

#define MALI_C55_REG_Y_WRITER_MAX_BANKS_MASK GENMASK(2, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

398

#define MALI_C55_REG_UV_WRITER_MAX_BANKS_MASK GENMASK(2, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

426

#define MALI_C55_GAMMA_GAIN_R_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

427

#define MALI_C55_GAMMA_GAIN_G_MASK GENMASK(27, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

429

#define MALI_C55_GAMMA_GAIN_B_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

431

#define MALI_C55_GAMMA_OFFSET_R_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

432

#define MALI_C55_GAMMA_OFFSET_G_MASK GENMASK(27, 16)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

434

#define MALI_C55_GAMMA_OFFSET_B_MASK GENMASK(11, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

94

#define MALI_C55_REG_HBLANK_MASK GENMASK(15, 0)

drivers/media/platform/arm/mali-c55/mali-c55-registers.h

95

#define MALI_C55_REG_VBLANK_MASK GENMASK(31, 16)

drivers/media/platform/aspeed/aspeed-video.c

102

#define VE_CTRL_FRC GENMASK(23, 16)

drivers/media/platform/aspeed/aspeed-video.c

106

#define VE_TGS_FIRST GENMASK(28, 16)

drivers/media/platform/aspeed/aspeed-video.c

107

#define VE_TGS_LAST GENMASK(12, 0)

drivers/media/platform/aspeed/aspeed-video.c

119

#define VE_BCD_CTRL_THR GENMASK(23, 16)

drivers/media/platform/aspeed/aspeed-video.c

120

#define VE_BCD_CTRL_ABCD_THR GENMASK(31, 24)

drivers/media/platform/aspeed/aspeed-video.c

134

#define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3)

drivers/media/platform/aspeed/aspeed-video.c

135

#define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0)

drivers/media/platform/aspeed/aspeed-video.c

143

#define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6)

drivers/media/platform/aspeed/aspeed-video.c

144

#define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11)

drivers/media/platform/aspeed/aspeed-video.c

147

#define VE_COMP_CTRL_ENCODE GENMASK(21, 20)

drivers/media/platform/aspeed/aspeed-video.c

148

#define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22)

drivers/media/platform/aspeed/aspeed-video.c

149

#define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27)

drivers/media/platform/aspeed/aspeed-video.c

157

#define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0)

drivers/media/platform/aspeed/aspeed-video.c

162

#define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16)

drivers/media/platform/aspeed/aspeed-video.c

166

#define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0)

drivers/media/platform/aspeed/aspeed-video.c

167

#define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16)

drivers/media/platform/aspeed/aspeed-video.c

170

#define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0)

drivers/media/platform/aspeed/aspeed-video.c

174

#define VE_MODE_DETECT_V_LINES GENMASK(27, 16)

drivers/media/platform/aspeed/aspeed-video.c

181

#define VE_SYNC_STATUS_HSYNC GENMASK(11, 0)

drivers/media/platform/aspeed/aspeed-video.c

182

#define VE_SYNC_STATUS_VSYNC GENMASK(27, 16)

drivers/media/platform/aspeed/aspeed-video.c

201

#define VE_MODE_DT_HOR_TOLER GENMASK(31, 28)

drivers/media/platform/aspeed/aspeed-video.c

202

#define VE_MODE_DT_VER_TOLER GENMASK(27, 24)

drivers/media/platform/aspeed/aspeed-video.c

203

#define VE_MODE_DT_HOR_STABLE GENMASK(23, 20)

drivers/media/platform/aspeed/aspeed-video.c

204

#define VE_MODE_DT_VER_STABLE GENMASK(19, 16)

drivers/media/platform/aspeed/aspeed-video.c

205

#define VE_MODE_DT_EDG_THROD GENMASK(15, 8)

drivers/media/platform/aspeed/aspeed-video.c

217

#define GFX_CTRL_FMT GENMASK(9, 7)

drivers/media/platform/aspeed/aspeed-video.c

220

#define GFX_H_DISPLAY_DE GENMASK(28, 16)

drivers/media/platform/aspeed/aspeed-video.c

221

#define GFX_H_DISPLAY_TOTAL GENMASK(12, 0)

drivers/media/platform/aspeed/aspeed-video.c

224

#define GFX_V_DISPLAY_DE GENMASK(27, 16)

drivers/media/platform/aspeed/aspeed-video.c

225

#define GFX_V_DISPLAY_TOTAL GENMASK(11, 0)

drivers/media/platform/aspeed/aspeed-video.c

80

#define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10)

drivers/media/platform/aspeed/aspeed-video.c

96

#define VE_CTRL_CAPTURE_FMT GENMASK(7, 6)

drivers/media/platform/aspeed/aspeed-video.c

99

#define VE_CTRL_CLK_DELAY GENMASK(11, 9)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

127

#define UNICAM_CTATADJ_MASK GENMASK(7, 4)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

128

#define UNICAM_PTATADJ_MASK GENMASK(11, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

132

#define UNICAM_PT_MASK GENMASK(2, 1)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

133

#define UNICAM_NP_MASK GENMASK(7, 4)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

134

#define UNICAM_PP_MASK GENMASK(11, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

135

#define UNICAM_BS_MASK GENMASK(15, 12)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

136

#define UNICAM_BL_MASK GENMASK(17, 16)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

144

#define UNICAM_CLAC_MASK GENMASK(8, 5)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

148

#define UNICAM_CLT1_MASK GENMASK(7, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

149

#define UNICAM_CLT2_MASK GENMASK(15, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

164

#define UNICAM_DLT1_MASK GENMASK(7, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

165

#define UNICAM_DLT2_MASK GENMASK(15, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

166

#define UNICAM_DLT3_MASK GENMASK(23, 16)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

174

#define UNICAM_LIP_MASK GENMASK(6, 5)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

175

#define UNICAM_LCIE_MASK GENMASK(28, 16)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

178

#define UNICAM_ID0_MASK GENMASK(7, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

179

#define UNICAM_ID1_MASK GENMASK(15, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

180

#define UNICAM_ID2_MASK GENMASK(23, 16)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

181

#define UNICAM_ID3_MASK GENMASK(31, 24)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

191

#define UNICAM_PUM_MASK GENMASK(2, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

201

#define UNICAM_DDM_MASK GENMASK(6, 3)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

202

#define UNICAM_PPM_MASK GENMASK(9, 7)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

210

#define UNICAM_DEM_MASK GENMASK(11, 10)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

211

#define UNICAM_DEBL_MASK GENMASK(14, 12)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

212

#define UNICAM_ICM_MASK GENMASK(16, 15)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

213

#define UNICAM_IDM_MASK GENMASK(17, 17)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

216

#define UNICAM_ICFL_MASK GENMASK(4, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

217

#define UNICAM_ICFH_MASK GENMASK(9, 5)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

218

#define UNICAM_ICST_MASK GENMASK(12, 10)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

219

#define UNICAM_ICLT_MASK GENMASK(15, 13)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

220

#define UNICAM_ICLL_MASK GENMASK(31, 16)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

228

#define UNICAM_EDL_MASK GENMASK(15, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

239

#define UNICAM_PCVC_MASK GENMASK(7, 6)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

240

#define UNICAM_PCDT_MASK GENMASK(5, 0)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

79

#define UNICAM_CPM_MASK GENMASK(3, 3)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

83

#define UNICAM_DCM_MASK GENMASK(5, 5)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

87

#define UNICAM_PFT_MASK GENMASK(11, 8)

drivers/media/platform/broadcom/bcm2835-unicam-regs.h

88

#define UNICAM_OET_MASK GENMASK(20, 12)

drivers/media/platform/broadcom/bcm2835-unicam.c

956

val = 0x155 & GENMASK(unicam->pipe.num_data_lanes * 2 + 1, 0);

drivers/media/platform/cadence/cdns-csi2rx.c

36

#define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8)

drivers/media/platform/cadence/cdns-csi2rx.c

59

#define CSI2RX_STREAM_CFG_NUM_PIXELS_MASK GENMASK(5, 4)

drivers/media/platform/cadence/cdns-csi2rx.c

81

#define CSI2RX_ECC_ERRORS GENMASK(7, 4)

drivers/media/platform/cadence/cdns-csi2rx.c

82

#define CSI2RX_PACKET_ERRORS GENMASK(12, 9)

drivers/media/platform/cadence/cdns-csi2tx.c

25

#define CSI2TX_DEVICE_CONFIG_STREAMS_MASK GENMASK(6, 4)

drivers/media/platform/cadence/cdns-csi2tx.c

27

#define CSI2TX_DEVICE_CONFIG_LANES_MASK GENMASK(2, 0)

drivers/media/platform/cadence/cdns-csi2tx.c

36

#define CSI2TX_DPHY_CFG_MODE_MASK GENMASK(9, 8)

drivers/media/platform/cadence/cdns-csi2tx.c

60

#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8)

drivers/media/platform/chips-media/wave5/wave5-hw.c

50

#define FASTIO_ADDRESS_MASK GENMASK(15, 0)

drivers/media/platform/chips-media/wave5/wave5-hw.c

51

#define SEQ_PARAM_PROFILE_MASK GENMASK(30, 24)

drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h

37

#define MTK_JPEG_ADDR_MASK GENMASK(1, 0)

drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h

18

#define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)

drivers/media/platform/microchip/microchip-csi2dc.c

31

#define CSI2DC_GCFG_HLC_MASK GENMASK(7, 4)

drivers/media/platform/microchip/microchip-csi2dc.c

63

#define CSI2DC_VPCFG_DT_MASK GENMASK(5, 0)

drivers/media/platform/microchip/microchip-csi2dc.c

66

#define CSI2DC_VPCFG_VC_MASK GENMASK(7, 6)

drivers/media/platform/microchip/microchip-csi2dc.c

83

#define CSI2DC_VPCOL_COL_MASK GENMASK(15, 0)

drivers/media/platform/microchip/microchip-csi2dc.c

89

#define CSI2DC_VPROW_ROW_MASK GENMASK(15, 0)

drivers/media/platform/microchip/microchip-isc-base.c

1335

ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));

drivers/media/platform/microchip/microchip-isc-regs.h

115

#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20)

drivers/media/platform/microchip/microchip-isc-regs.h

118

#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24)

drivers/media/platform/microchip/microchip-isc-regs.h

121

#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

265

#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

269

#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

312

#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

32

#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)

drivers/media/platform/microchip/microchip-isc-regs.h

321

#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6)

drivers/media/platform/microchip/microchip-isc-regs.h

362

#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

369

#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4)

drivers/media/platform/microchip/microchip-isc-regs.h

376

#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8)

drivers/media/platform/microchip/microchip-isc-regs.h

384

#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)

drivers/media/platform/microchip/microchip-isc-regs.h

39

#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)

drivers/media/platform/microchip/microchip-isc-regs.h

48

#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

50

#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16)

drivers/media/platform/microchip/microchip-isc-regs.h

56

#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0)

drivers/media/platform/microchip/microchip-isc-regs.h

58

#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16)

drivers/media/platform/microchip/microchip-isc-regs.h

75

#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n) * 16 + 7), (n) * 16)

drivers/media/platform/microchip/microchip-isc-regs.h

77

#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n) * 17 + 8), ((n) * 16 + 8))

drivers/media/platform/nuvoton/npcm-regs.h

104

#define ECE_HEX_CTRL_ENC_GAP GENMASK(12, 8)

drivers/media/platform/nuvoton/npcm-regs.h

107

#define ECE_HEX_RECT_OFFSET_MASK GENMASK(22, 0)

drivers/media/platform/nuvoton/npcm-regs.h

115

#define INTCR_GFXIFDIS GENMASK(9, 8)

drivers/media/platform/nuvoton/npcm-regs.h

129

#define HVCNTL_MASK GENMASK(7, 0)

drivers/media/platform/nuvoton/npcm-regs.h

132

#define HVCNTH_MASK GENMASK(2, 0)

drivers/media/platform/nuvoton/npcm-regs.h

135

#define VVCNTL_MASK GENMASK(7, 0)

drivers/media/platform/nuvoton/npcm-regs.h

138

#define VVCNTH_MASK GENMASK(2, 0)

drivers/media/platform/nuvoton/npcm-regs.h

141

#define GPLLINDIV_MASK GENMASK(5, 0)

drivers/media/platform/nuvoton/npcm-regs.h

145

#define GPLLFBDIV_MASK GENMASK(7, 0)

drivers/media/platform/nuvoton/npcm-regs.h

148

#define GPLLST_PLLOTDIV1 GENMASK(2, 0)

drivers/media/platform/nuvoton/npcm-regs.h

149

#define GPLLST_PLLOTDIV2 GENMASK(5, 3)

drivers/media/platform/nuvoton/npcm-regs.h

150

#define GPLLST_GPLLFBDV109 GENMASK(7, 6)

drivers/media/platform/nuvoton/npcm-regs.h

17

#define VCD_FBA_LP GENMASK(15, 0)

drivers/media/platform/nuvoton/npcm-regs.h

18

#define VCD_FBB_LP GENMASK(31, 16)

drivers/media/platform/nuvoton/npcm-regs.h

21

#define VCD_CAP_RES_VERT_RES GENMASK(10, 0)

drivers/media/platform/nuvoton/npcm-regs.h

22

#define VCD_CAP_RES_HOR_RES GENMASK(26, 16)

drivers/media/platform/nuvoton/npcm-regs.h

33

#define VCD_CMD_OPERATION GENMASK(6, 4)

drivers/media/platform/nuvoton/npcm-regs.h

54

#define VCD_RCHG_IG_CHG0 GENMASK(2, 0)

drivers/media/platform/nuvoton/npcm-regs.h

55

#define VCD_RCHG_TIM_PRSCL GENMASK(12, 9)

drivers/media/platform/nuvoton/npcm-regs.h

58

#define VCD_VER_HI_TIME GENMASK(23, 0)

drivers/media/platform/nuvoton/npcm-regs.h

61

#define VCD_VER_HI_LAST GENMASK(23, 0)

drivers/media/platform/nuvoton/npcm-regs.h

64

#define VCD_HOR_AC_TIME GENMASK(13, 0)

drivers/media/platform/nuvoton/npcm-regs.h

67

#define VCD_HOR_AC_LAST GENMASK(13, 0)

drivers/media/platform/nuvoton/npcm-regs.h

90

#define ECE_RECT_DIMEN_WR GENMASK(10, 0)

drivers/media/platform/nuvoton/npcm-regs.h

91

#define ECE_RECT_DIMEN_WLTR GENMASK(14, 11)

drivers/media/platform/nuvoton/npcm-regs.h

92

#define ECE_RECT_DIMEN_HR GENMASK(26, 16)

drivers/media/platform/nuvoton/npcm-regs.h

93

#define ECE_RECT_DIMEN_HLTR GENMASK(30, 27)

drivers/media/platform/nvidia/tegra-vde/h264.c

391

value |= bitstream_data_size & GENMASK(19, 15);

drivers/media/platform/nxp/dw100/dw100_regs.h

102

#define DW100_INTERRUPT_STATUS_INT_ENABLE_MASK GENMASK(15, 8)

drivers/media/platform/nxp/dw100/dw100_regs.h

103

#define DW100_INTERRUPT_STATUS_INT_ENABLE(x) (((x) & GENMASK(7, 0)) << 8)

drivers/media/platform/nxp/dw100/dw100_regs.h

105

#define DW100_INTERRUPT_STATUS_INT_CLEAR(x) (((x) & GENMASK(7, 0)) << 24)

drivers/media/platform/nxp/dw100/dw100_regs.h

111

#define DW100_DST_IMG_Y_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))

drivers/media/platform/nxp/dw100/dw100_regs.h

112

#define DW100_DST_IMG_UV_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0))

drivers/media/platform/nxp/dw100/dw100_regs.h

21

#define DW100_DEWARP_CTRL_INPUT_FORMAT_MASK GENMASK(5, 4)

drivers/media/platform/nxp/dw100/dw100_regs.h

24

#define DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK GENMASK(7, 6)

drivers/media/platform/nxp/dw100/dw100_regs.h

29

#define DW100_DEWARP_CTRL_PREFETCH_MODE_MASK GENMASK(17, 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

33

#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD_MASK GENMASK(24, 18)

drivers/media/platform/nxp/dw100/dw100_regs.h

37

#define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))

drivers/media/platform/nxp/dw100/dw100_regs.h

39

#define DW100_MAP_LUT_SIZE_WIDTH(w) (((w) & GENMASK(10, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

40

#define DW100_MAP_LUT_SIZE_HEIGHT(h) (((h) & GENMASK(10, 0)) << 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

42

#define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))

drivers/media/platform/nxp/dw100/dw100_regs.h

44

#define DW100_IMG_UV_BASE(base) (((base) >> 4) & GENMASK(29, 0))

drivers/media/platform/nxp/dw100/dw100_regs.h

46

#define DW100_IMG_SIZE_WIDTH(w) (((w) & GENMASK(12, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

47

#define DW100_IMG_SIZE_HEIGHT(h) (((h) & GENMASK(12, 0)) << 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

69

#define DW100_SWAP_CONTROL_Y(x) (((x) & GENMASK(3, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

70

#define DW100_SWAP_CONTROL_UV(x) (((x) & GENMASK(3, 0)) << 4)

drivers/media/platform/nxp/dw100/dw100_regs.h

71

#define DW100_SWAP_CONTROL_SRC(x) (((x) & GENMASK(7, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

72

#define DW100_SWAP_CONTROL_DST(x) (((x) & GENMASK(7, 0)) << 8)

drivers/media/platform/nxp/dw100/dw100_regs.h

73

#define DW100_SWAP_CONTROL_SRC2(x) (((x) & GENMASK(7, 0)) << 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

74

#define DW100_SWAP_CONTROL_DST2(x) (((x) & GENMASK(7, 0)) << 24)

drivers/media/platform/nxp/dw100/dw100_regs.h

75

#define DW100_SWAP_CONTROL_SRC_MASK GENMASK(7, 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

76

#define DW100_SWAP_CONTROL_DST_MASK GENMASK(15, 8)

drivers/media/platform/nxp/dw100/dw100_regs.h

77

#define DW100_SWAP_CONTROL_SRC2_MASK GENMASK(23, 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

78

#define DW100_SWAP_CONTROL_DST2_MASK GENMASK(31, 24)

drivers/media/platform/nxp/dw100/dw100_regs.h

83

#define DW100_ROI_START_X(x) (((x) & GENMASK(12, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

84

#define DW100_ROI_START_Y(y) (((y) & GENMASK(12, 0)) << 16)

drivers/media/platform/nxp/dw100/dw100_regs.h

86

#define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0)

drivers/media/platform/nxp/dw100/dw100_regs.h

87

#define DW100_BOUNDARY_PIXEL_U(u) (((u) & GENMASK(7, 0)) << 8)

drivers/media/platform/nxp/dw100/dw100_regs.h

88

#define DW100_BOUNDARY_PIXEL_Y(y) (((y) & GENMASK(7, 0)) << 16)

drivers/media/platform/nxp/imx-mipi-csis.c

120

#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx-mipi-csis.c

122

#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)

drivers/media/platform/nxp/imx-mipi-csis.c

174

#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx-mipi-csis.c

179

#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK GENMASK(13, 12)

drivers/media/platform/nxp/imx-mipi-csis.c

182

#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK GENMASK(7, 2)

drivers/media/platform/nxp/imx-mipi-csis.c

61

#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK GENMASK(9, 8)

drivers/media/platform/nxp/imx-mipi-csis.c

69

#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK GENMASK(7, 4)

drivers/media/platform/nxp/imx8-isi/imx8-isi-gasket.c

21

#define GASKET_CTRL_DATA_TYPE(dt) FIELD_PREP(GENMASK(13, 8), dt)

drivers/media/platform/nxp/imx8-isi/imx8-isi-gasket.c

62

#define DISP_MIX_CAMERA_MUX_DATA_TYPE(x) FIELD_PREP(GENMASK(8, 3), x)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

100

#define CHNL_IMG_CTRL_DEC_Y_MASK GENMASK(9, 8)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

106

#define CHNL_IMG_CTRL_CSC_MODE_MASK GENMASK(2, 1)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

118

#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK GENMASK(7, 6)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

124

#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK GENMASK(4, 3)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

130

#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK GENMASK(1, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

139

#define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

141

#define CHNL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

177

#define CHNL_STS_OFLW_BYTES_MASK GENMASK(7, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

18

#define CHNL_CTRL_CHAIN_BUF_MASK GENMASK(26, 25)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

182

#define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

184

#define CHNL_SCALE_FACTOR_X_SCALE_MASK GENMASK(13, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

189

#define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

191

#define CHNL_SCALE_OFFSET_X_SCALE_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

196

#define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

198

#define CHNL_CROP_ULC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

203

#define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

205

#define CHNL_CROP_LRC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

210

#define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

212

#define CHNL_CSC_COEFF0_A1_MASK GENMASK(10, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

217

#define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

219

#define CHNL_CSC_COEFF1_A3_MASK GENMASK(10, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

224

#define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

226

#define CHNL_CSC_COEFF2_B2_MASK GENMASK(10, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

23

#define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

231

#define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

233

#define CHNL_CSC_COEFF3_C1_MASK GENMASK(10, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

238

#define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

240

#define CHNL_CSC_COEFF4_C3_MASK GENMASK(10, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

245

#define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

247

#define CHNL_CSC_COEFF5_D2_MASK GENMASK(8, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

25

#define CHNL_CTRL_MIPI_VC_ID_MASK GENMASK(7, 6)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

252

#define CHNL_ROI_0_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

258

#define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

260

#define CHNL_ROI_0_ULC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

265

#define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

267

#define CHNL_ROI_0_LRC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

272

#define CHNL_ROI_1_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

278

#define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

280

#define CHNL_ROI_1_ULC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

285

#define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

287

#define CHNL_ROI_1_LRC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

292

#define CHNL_ROI_2_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

298

#define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

300

#define CHNL_ROI_2_ULC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

305

#define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

307

#define CHNL_ROI_2_LRC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

31

#define CHNL_CTRL_SRC_INPUT_MASK GENMASK(2, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

312

#define CHNL_ROI_3_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

318

#define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

320

#define CHNL_ROI_3_ULC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

325

#define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

327

#define CHNL_ROI_3_LRC_Y_MASK GENMASK(11, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

340

#define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

348

#define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

350

#define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

355

#define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK GENMASK(31, 28)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

36

#define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(29, 24)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

386

#define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

388

#define CHNL_SCL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

392

#define CHNL_FLOW_CTRL_FC_DENOM_MASK GENMASK(7, 0)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

394

#define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

87

#define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

90

#define CHNL_IMG_CTRL_DEINT_MASK GENMASK(14, 12)

drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h

98

#define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)

drivers/media/platform/nxp/imx8mq-mipi-csi2.c

193

#define CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK GENMASK(9, 4)

drivers/media/platform/nxp/imx8mq-mipi-csi2.c

198

#define CSI2SS_DATA_TYPE_DISABLE_BF_MASK GENMASK(23, 0)

drivers/media/platform/qcom/camss/camss-csid-340.c

33

#define CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK GENMASK(1, 0)

drivers/media/platform/qcom/camss/camss-csid-340.c

34

#define CSI2_RX_CFG0_DLX_INPUT_SEL_MASK GENMASK(17, 4)

drivers/media/platform/qcom/camss/camss-csid-340.c

35

#define CSI2_RX_CFG0_PHY_NUM_SEL_MASK GENMASK(21, 20)

drivers/media/platform/qcom/camss/camss-csid-340.c

47

#define CSID_RDI_CFG0_DECODE_FORMAT_MASK GENMASK(15, 12)

drivers/media/platform/qcom/camss/camss-csid-340.c

49

#define CSID_RDI_CFG0_DT_MASK GENMASK(21, 16)

drivers/media/platform/qcom/camss/camss-csid-340.c

50

#define CSID_RDI_CFG0_VC_MASK GENMASK(23, 22)

drivers/media/platform/qcom/camss/camss-csid-340.c

51

#define CSID_RDI_CFG0_DTID_MASK GENMASK(28, 27)

drivers/media/platform/qcom/camss/camss-csid-680.c

120

#define CSI2_RX_CAPTURE_CTRL_LONG_PKT_DT GENMASK(9, 4)

drivers/media/platform/qcom/camss/camss-csid-680.c

121

#define CSI2_RX_CAPTURE_CTRL_LONG_PKT_VC GENMASK(14, 10)

drivers/media/platform/qcom/camss/camss-csid-680.c

122

#define CSI2_RX_CAPTURE_CTRL_SHORT_PKT_VC GENMASK(19, 15)

drivers/media/platform/qcom/camss/camss-csid-680.c

123

#define CSI2_RX_CAPTURE_CTRL_CPHY_PKT_DT GENMASK(20, 25)

drivers/media/platform/qcom/camss/camss-csid-680.c

124

#define CSI2_RX_CAPTURE_CTRL_CPHY_PKT_VC GENMASK(30, 26)

drivers/media/platform/qcom/camss/camss-csid-680.c

19

#define CSID_TOP_IO_PATH_CFG0_SFE_1 GENMASK(1, 0)

drivers/media/platform/qcom/camss/camss-csid-680.c

21

#define CSID_TOP_IO_PATH_CFG0_SBI_1 GENMASK(3, 0)

drivers/media/platform/qcom/camss/camss-csid-680.c

22

#define CSID_TOP_IO_PATH_CFG0_SBI_2 GENMASK(3, 1)

drivers/media/platform/qcom/camss/camss-vfe-340.c

36

#define TFE_BUS_IRQ_MASK_RUP_DONE_MASK GENMASK(3, 0)

drivers/media/platform/qcom/camss/camss-vfe-340.c

38

#define TFE_BUS_IRQ_MASK_BUF_DONE_MASK GENMASK(15, 8)

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

114

matrix_coeff = FIELD_GET(GENMASK(7, 0), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

115

transfer_char = FIELD_GET(GENMASK(15, 8), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

116

primaries = FIELD_GET(GENMASK(23, 16), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

117

colour_description_present_flag = FIELD_GET(GENMASK(24, 24), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

118

full_range = FIELD_GET(GENMASK(25, 25), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c

119

video_signal_type_present_flag = FIELD_GET(GENMASK(29, 29), event.colour_space);

drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c

272

payload[0] = FIELD_PREP(GENMASK(31, 16), left_offset) | top_offset;

drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c

273

payload[1] = FIELD_PREP(GENMASK(31, 16), right_offset) | bottom_offset;

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

100

#define CSI2_CH_CTRL_VC_MASK GENMASK(6, 5)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

101

#define CSI2_CH_CTRL_DT_MASK GENMASK(12, 7)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

102

#define CSI2_CH_CTRL_LC_MASK GENMASK(27, 18)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

105

#define CSI2_CH_COMP_CTRL_OFFSET_MASK GENMASK(15, 0)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

106

#define CSI2_CH_COMP_CTRL_SHIFT_MASK GENMASK(19, 16)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

107

#define CSI2_CH_COMP_CTRL_MODE_MASK GENMASK(25, 24)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

37

#define CSI2_DISCARDS_AMOUNT_MASK GENMASK(23, 0)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

39

#define CSI2_DISCARDS_DT_MASK GENMASK(29, 24)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

41

#define CSI2_DISCARDS_VC_MASK GENMASK(31, 30)

drivers/media/platform/raspberrypi/rp1-cfe/csi2.c

99

#define CSI2_CH_CTRL_CH_MODE_MASK GENMASK(2, 1)

drivers/media/platform/renesas/rcar_fdp1.c

102

#define FD1_CTL_STATUS_VINT_CNT_MASK GENMASK(31, 16)

drivers/media/platform/renesas/rcar_fdp1.c

128

#define FD1_RPF_SIZE_MASK GENMASK(12, 0)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

32

#define AMnMBVALID_MBVALID(x) GENMASK(x, 0)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

36

#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

39

#define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

41

#define AMnFIFOPNTR_FIFOWPNTR_B1 GENMASK(15, 8)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

42

#define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

44

#define AMnFIFOPNTR_FIFORPNTR_B1 GENMASK(31, 24)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

46

#define AMnIS_IS_MASK GENMASK(14, 7)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h

63

#define ICnMC_INF_MASK GENMASK(21, 16)

drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c

30

#define CSI2nMCG_SDLN GENMASK(11, 8)

drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h

29

#define RZV2H_IVC_PXFMT_DTYPE GENMASK(7, 0)

drivers/media/platform/rockchip/rkcif/rkcif-regs.h

107

#define RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM GENMASK(6, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c

450

mi_ctrl &= ~GENMASK(17, 16);

drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c

453

mi_ctrl &= ~GENMASK(19, 18);

drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

68

#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_MASK GENMASK(21, 20)

drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

71

#define ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK GENMASK(18, 13)

drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

78

#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_MASK GENMASK(11, 10)

drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

81

#define ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE_MASK GENMASK(8, 3)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

141

#define RKISP1_MI_CTRL_MP_FMT_MASK GENMASK(23, 22)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

142

#define RKISP1_MI_CTRL_SP_FMT_MASK GENMASK(30, 24)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

467

#define RKISP1_CIF_ISP_FLAGS_SHD_S_DATA_MASK GENMASK(27, 16)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

640

#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_MASK GENMASK(3, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

641

#define RKISP1_CIF_ISP_DPCC_SET_USE_MASK GENMASK(3, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

715

#define RKISP1_CIF_ISP_WDR_RGB_FACTOR_MASK GENMASK(11, 8)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

718

#define RKISP1_CIF_ISP_WDR_TONE_CURVE_YM_MASK GENMASK(12, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

720

#define RKISP1_CIF_ISP_WDR_RGB_OFFSET_MASK GENMASK(11, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

721

#define RKISP1_CIF_ISP_WDR_LUM_OFFSET_MASK GENMASK(27, 16)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

723

#define RKISP1_CIF_ISP_WDR_DMIN_THRESH_MASK GENMASK(11, 0)

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

724

#define RKISP1_CIF_ISP_WDR_DMIN_STRENGTH_MASK GENMASK(20, 16)

drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c

472

reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);

drivers/media/platform/rockchip/rkvdec/rkvdec.c

1133

reg &= GENMASK(31, 16);

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

100

#define NLR_NL_MASK GENMASK(15, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

18

#define CR_MODE_MASK GENMASK(17, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

52

#define FGOR_LO_MASK GENMASK(13, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

56

#define BGOR_LO_MASK GENMASK(13, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

59

#define FGPFCCR_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

60

#define FGPFCCR_AM_MASK GENMASK(17, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

61

#define FGPFCCR_CS_MASK GENMASK(15, 8)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

64

#define FGPFCCR_CM_MASK GENMASK(3, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

67

#define FGCOLR_REG_MASK GENMASK(23, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

68

#define FGCOLR_GREEN_MASK GENMASK(15, 8)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

69

#define FGCOLR_BLUE_MASK GENMASK(7, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

72

#define BGPFCCR_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

73

#define BGPFCCR_AM_MASK GENMASK(17, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

74

#define BGPFCCR_CS_MASK GENMASK(15, 8)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

77

#define BGPFCCR_CM_MASK GENMASK(3, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

80

#define BGCOLR_REG_MASK GENMASK(23, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

81

#define BGCOLR_GREEN_MASK GENMASK(15, 8)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

82

#define BGCOLR_BLUE_MASK GENMASK(7, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

85

#define OPFCCR_CM_MASK GENMASK(2, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

88

#define OCOLR_ALPHA_MASK GENMASK(31, 24)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

89

#define OCOLR_RED_MASK GENMASK(23, 16)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

90

#define OCOLR_GREEN_MASK GENMASK(15, 8)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

91

#define OCOLR_BLUE_MASK GENMASK(7, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

96

#define OOR_LO_MASK GENMASK(13, 0)

drivers/media/platform/st/stm32/dma2d/dma2d-regs.h

99

#define NLR_PL_MASK GENMASK(29, 16)

drivers/media/platform/st/stm32/stm32-csi.c

101

#define STM32_CSI_PTCR1_TDI_MASK GENMASK(7, 0)

drivers/media/platform/st/stm32/stm32-csi.c

92

#define STM32_CSI_PFCR_CCFR_MASK GENMASK(5, 0)

drivers/media/platform/st/stm32/stm32-csi.c

94

#define STM32_CSI_PFCR_HSFR_MASK GENMASK(14, 8)

drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c

41

#define DCMIPP_P0DCLMTR_LIMIT_MASK GENMASK(23, 0)

drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c

19

#define DCMIPP_P0FCTCR_FRATE_MASK GENMASK(1, 0)

drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c

31

#define DCMIPP_P0PPCR_BSM_MASK GENMASK(8, 7)

drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-input.c

46

#define DCMIPP_P0FSCR_DTMODE_MASK GENMASK(17, 16)

drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-input.c

50

#define DCMIPP_P0FSCR_DTIDA_MASK GENMASK(5, 0)

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

160

#define SUN6I_CSI_CH_FLD1_VSIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

161

#define SUN6I_CSI_CH_FLD1_VSIZE_VER_START(v) ((v) & GENMASK(12, 0))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

164

#define SUN6I_CSI_CH_HSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

165

#define SUN6I_CSI_CH_HSIZE_START(v) ((v) & GENMASK(12, 0))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

168

#define SUN6I_CSI_CH_VSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

169

#define SUN6I_CSI_CH_VSIZE_START(v) ((v) & GENMASK(12, 0))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

172

#define SUN6I_CSI_CH_BUF_LEN_CHROMA_LINE(v) (((v) << 16) & GENMASK(29, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

173

#define SUN6I_CSI_CH_BUF_LEN_LUMA_LINE(v) ((v) & GENMASK(13, 0))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

176

#define SUN6I_CSI_CH_FLIP_SIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

177

#define SUN6I_CSI_CH_FLIP_SIZE_VALID_LEN(v) ((v) & GENMASK(12, 0))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

18

#define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

29

#define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

57

#define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

70

#define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

71

#define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

72

#define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16))

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h

78

#define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8))

drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h

18

GENMASK(9, 8))

drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h

19

#define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0))

drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h

22

#define SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(ch, vc) (((vc) & GENMASK(1, 0)) << \

drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h

24

#define SUN6I_MIPI_CSI2_VCDT_RX_CH_DT(ch, t) (((t) & GENMASK(5, 0)) << \

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h

34

#define SUN8I_A83T_DPHY_ANA0_RINT(v) (((v) << 28) & GENMASK(29, 28))

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h

35

#define SUN8I_A83T_DPHY_ANA0_SNK(v) (((v) << 20) & GENMASK(22, 20))

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

135

GENMASK(22, 18))

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

137

GENMASK(17, 16))

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

139

GENMASK(5, 4))

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

141

#define SUN8I_A83T_MIPI_CSI2_VCDT0_CH_VC(ch, vc) (((vc) & GENMASK(1, 0)) << \

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

143

#define SUN8I_A83T_MIPI_CSI2_VCDT0_CH_DT(ch, t) (((t) & GENMASK(5, 0)) << \

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

146

#define SUN8I_A83T_MIPI_CSI2_VCDT1_CH_VC(ch, vc) (((vc) & GENMASK(1, 0)) << \

drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h

148

#define SUN8I_A83T_MIPI_CSI2_VCDT1_CH_DT(ch, t) (((t) & GENMASK(5, 0)) << \

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

101

#define REFFREQ_SEL_MASK GENMASK(11, 9)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

110

#define PHYCREG_CR_PARA_SELECTION_MODE_MASK GENMASK(1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

120

#define PHYCREG_CR_PARA_RD_DATA_MASK GENMASK(15, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

125

#define SCRAMB_EN_SEL_QST_MASK GENMASK(1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

133

#define VS_CNT_THR_QST_MASK GENMASK(27, 20)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

135

#define HS_POL_QST_MASK GENMASK(19, 18)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

137

#define VS_POL_QST_MASK GENMASK(17, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

140

#define VS_FILTER_ORDER_QST_MASK GENMASK(1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

145

#define OPMODE_STS_MASK GENMASK(6, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

147

#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK GENMASK(15, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

149

#define I2C_SDA_IN_HOLD_VALUE_QST_MASK GENMASK(7, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

15

#define UPDATE(x, h, l) FIELD_PREP(GENMASK((h), (l)), (x))

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

151

#define OPMODE_STS_MASK GENMASK(6, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

156

#define EESS_CTL_THR_QST_MASK GENMASK(19, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

158

#define OESS_CTL3_THR_QST_MASK GENMASK(11, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

16

#define HIWORD_UPDATE(v, h, l) FIELD_PREP_WM16(GENMASK((h), (l)), (v))

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

160

#define EESS_OESS_SEL_QST_MASK GENMASK(5, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

163

#define KEY_DECRYPT_SEED_QST_MASK GENMASK(15, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

176

#define VPROC_FMT_OVR_VALUE_MASK GENMASK(6, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

182

#define AFIFO_THR_LOW_QST_MASK GENMASK(25, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

184

#define AFIFO_THR_HIGH_QST_MASK GENMASK(9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

186

#define AFIFO_THR_MUTE_LOW_QST_MASK GENMASK(25, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

188

#define AFIFO_THR_MUTE_HIGH_QST_MASK GENMASK(9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

210

#define SCDC_SINKVERSION_QST_MASK GENMASK(7, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

213

#define AGEN_SPEAKER_ALLOC GENMASK(15, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

220

#define CED_CHLOCKMAXER_QST_MASK GENMASK(14, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

233

#define VIC_VAL_MASK GENMASK(6, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

270

#define UV_WID_MASK GENMASK(31, 28)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

272

#define Y_WID_MASK GENMASK(27, 24)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

274

#define DDR_STORE_FORMAT_MASK GENMASK(15, 12)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

294

#define LINE_FLAG_NUM_MASK GENMASK(31, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

296

#define LOCK_FRAME_NUM_MASK GENMASK(11, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

307

#define EDID_SLAVE_ADDR_MASK GENMASK(6, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

321

#define HDMIRX_TYPE_MASK GENMASK(8, 7)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

322

#define HDMIRX_COLOR_DEPTH_MASK GENMASK(6, 3)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

323

#define HDMIRX_FORMAT_MASK GENMASK(2, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

45

#define FREQ_TUNE_START_VAL_MASK GENMASK(9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

88

#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK GENMASK(30, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

90

#define AUDCLK_STABLE_FREQ_MARGIN_MASK GENMASK(11, 9)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

96

#define LDO_AFE_PROG_MASK GENMASK(24, 23)

drivers/media/platform/ti/cal/cal_regs.h

100

#define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)

drivers/media/platform/ti/cal/cal_regs.h

101

#define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)

drivers/media/platform/ti/cal/cal_regs.h

102

#define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)

drivers/media/platform/ti/cal/cal_regs.h

103

#define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)

drivers/media/platform/ti/cal/cal_regs.h

104

#define CAL_HL_HWINFO_VFIFO_MASK GENMASK(22, 19)

drivers/media/platform/ti/cal/cal_regs.h

105

#define CAL_HL_HWINFO_NCPORT_MASK GENMASK(27, 23)

drivers/media/platform/ti/cal/cal_regs.h

106

#define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)

drivers/media/platform/ti/cal/cal_regs.h

107

#define CAL_HL_HWINFO_NPPI_CTXS1_MASK GENMASK(31, 30)

drivers/media/platform/ti/cal/cal_regs.h

118

#define CAL_HL_SYSCONFIG_IDLE_MASK GENMASK(3, 2)

drivers/media/platform/ti/cal/cal_regs.h

137

#define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1)

drivers/media/platform/ti/cal/cal_regs.h

149

#define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5)

drivers/media/platform/ti/cal/cal_regs.h

164

#define CAL_PIX_PROC_DPCME_MASK GENMASK(15, 11)

drivers/media/platform/ti/cal/cal_regs.h

173

#define CAL_PIX_PROC_PACK_MASK GENMASK(18, 16)

drivers/media/platform/ti/cal/cal_regs.h

180

#define CAL_PIX_PROC_CPORT_MASK GENMASK(23, 19)

drivers/media/platform/ti/cal/cal_regs.h

185

#define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1)

drivers/media/platform/ti/cal/cal_regs.h

186

#define CAL_CTRL_BURSTSIZE_MASK GENMASK(6, 5)

drivers/media/platform/ti/cal/cal_regs.h

191

#define CAL_CTRL_LL_FORCE_STATE_MASK GENMASK(12, 7)

drivers/media/platform/ti/cal/cal_regs.h

192

#define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13)

drivers/media/platform/ti/cal/cal_regs.h

197

#define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24)

drivers/media/platform/ti/cal/cal_regs.h

199

#define CAL_CTRL1_PPI_GROUPING_MASK GENMASK(1, 0)

drivers/media/platform/ti/cal/cal_regs.h

204

#define CAL_CTRL1_INTERLEAVE01_MASK GENMASK(3, 2)

drivers/media/platform/ti/cal/cal_regs.h

209

#define CAL_CTRL1_INTERLEAVE23_MASK GENMASK(5, 4)

drivers/media/platform/ti/cal/cal_regs.h

215

#define CAL_LINE_NUMBER_EVT_CPORT_MASK GENMASK(4, 0)

drivers/media/platform/ti/cal/cal_regs.h

216

#define CAL_LINE_NUMBER_EVT_MASK GENMASK(29, 16)

drivers/media/platform/ti/cal/cal_regs.h

218

#define CAL_VPORT_CTRL1_PCLK_MASK GENMASK(16, 0)

drivers/media/platform/ti/cal/cal_regs.h

219

#define CAL_VPORT_CTRL1_XBLK_MASK GENMASK(24, 17)

drivers/media/platform/ti/cal/cal_regs.h

220

#define CAL_VPORT_CTRL1_YBLK_MASK GENMASK(30, 25)

drivers/media/platform/ti/cal/cal_regs.h

225

#define CAL_VPORT_CTRL2_CPORT_MASK GENMASK(4, 0)

drivers/media/platform/ti/cal/cal_regs.h

235

#define CAL_VPORT_CTRL2_RDY_THR_MASK GENMASK(31, 18)

drivers/media/platform/ti/cal/cal_regs.h

237

#define CAL_BYS_CTRL1_PCLK_MASK GENMASK(16, 0)

drivers/media/platform/ti/cal/cal_regs.h

238

#define CAL_BYS_CTRL1_XBLK_MASK GENMASK(24, 17)

drivers/media/platform/ti/cal/cal_regs.h

239

#define CAL_BYS_CTRL1_YBLK_MASK GENMASK(30, 25)

drivers/media/platform/ti/cal/cal_regs.h

242

#define CAL_BYS_CTRL2_CPORTIN_MASK GENMASK(4, 0)

drivers/media/platform/ti/cal/cal_regs.h

243

#define CAL_BYS_CTRL2_CPORTOUT_MASK GENMASK(9, 5)

drivers/media/platform/ti/cal/cal_regs.h

257

#define CAL_RD_DMA_CTRL_BW_LIMITER_MASK GENMASK(10, 2)

drivers/media/platform/ti/cal/cal_regs.h

258

#define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK GENMASK(14, 11)

drivers/media/platform/ti/cal/cal_regs.h

259

#define CAL_RD_DMA_CTRL_PCLK_MASK GENMASK(31, 15)

drivers/media/platform/ti/cal/cal_regs.h

261

#define CAL_RD_DMA_PIX_ADDR_MASK GENMASK(31, 3)

drivers/media/platform/ti/cal/cal_regs.h

263

#define CAL_RD_DMA_PIX_OFST_MASK GENMASK(31, 4)

drivers/media/platform/ti/cal/cal_regs.h

265

#define CAL_RD_DMA_XSIZE_MASK GENMASK(31, 19)

drivers/media/platform/ti/cal/cal_regs.h

267

#define CAL_RD_DMA_YSIZE_MASK GENMASK(29, 16)

drivers/media/platform/ti/cal/cal_regs.h

269

#define CAL_RD_DMA_INIT_ADDR_MASK GENMASK(31, 3)

drivers/media/platform/ti/cal/cal_regs.h

271

#define CAL_RD_DMA_INIT_OFST_MASK GENMASK(31, 3)

drivers/media/platform/ti/cal/cal_regs.h

273

#define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK GENMASK(2, 0)

drivers/media/platform/ti/cal/cal_regs.h

281

#define CAL_RD_DMA_CTRL2_PATTERN_MASK GENMASK(5, 4)

drivers/media/platform/ti/cal/cal_regs.h

289

#define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK GENMASK(29, 16)

drivers/media/platform/ti/cal/cal_regs.h

291

#define CAL_WR_DMA_CTRL_MODE_MASK GENMASK(2, 0)

drivers/media/platform/ti/cal/cal_regs.h

298

#define CAL_WR_DMA_CTRL_PATTERN_MASK GENMASK(4, 3)

drivers/media/platform/ti/cal/cal_regs.h

304

#define CAL_WR_DMA_CTRL_DTAG_MASK GENMASK(8, 6)

drivers/media/platform/ti/cal/cal_regs.h

313

#define CAL_WR_DMA_CTRL_CPORT_MASK GENMASK(13, 9)

drivers/media/platform/ti/cal/cal_regs.h

315

#define CAL_WR_DMA_CTRL_YSIZE_MASK GENMASK(31, 18)

drivers/media/platform/ti/cal/cal_regs.h

317

#define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4)

drivers/media/platform/ti/cal/cal_regs.h

319

#define CAL_WR_DMA_OFST_MASK GENMASK(18, 4)

drivers/media/platform/ti/cal/cal_regs.h

320

#define CAL_WR_DMA_OFST_CIRC_MODE_MASK GENMASK(23, 22)

drivers/media/platform/ti/cal/cal_regs.h

325

#define CAL_WR_DMA_OFST_CIRC_SIZE_MASK GENMASK(31, 24)

drivers/media/platform/ti/cal/cal_regs.h

327

#define CAL_WR_DMA_XSIZE_XSKIP_MASK GENMASK(15, 3)

drivers/media/platform/ti/cal/cal_regs.h

328

#define CAL_WR_DMA_XSIZE_MASK GENMASK(31, 19)

drivers/media/platform/ti/cal/cal_regs.h

336

#define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK GENMASK(2, 0)

drivers/media/platform/ti/cal/cal_regs.h

346

#define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK GENMASK(6, 4)

drivers/media/platform/ti/cal/cal_regs.h

348

#define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK GENMASK(10, 8)

drivers/media/platform/ti/cal/cal_regs.h

350

#define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK GENMASK(14, 12)

drivers/media/platform/ti/cal/cal_regs.h

352

#define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK GENMASK(18, 16)

drivers/media/platform/ti/cal/cal_regs.h

355

#define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK GENMASK(26, 25)

drivers/media/platform/ti/cal/cal_regs.h

359

#define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK GENMASK(28, 27)

drivers/media/platform/ti/cal/cal_regs.h

370

#define CAL_CSI2_SHORT_PACKET_MASK GENMASK(23, 0)

drivers/media/platform/ti/cal/cal_regs.h

392

#define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK GENMASK(19, 0)

drivers/media/platform/ti/cal/cal_regs.h

404

#define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK GENMASK(12, 0)

drivers/media/platform/ti/cal/cal_regs.h

416

#define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0)

drivers/media/platform/ti/cal/cal_regs.h

419

#define CAL_CSI2_CTX_VC_MASK GENMASK(7, 6)

drivers/media/platform/ti/cal/cal_regs.h

420

#define CAL_CSI2_CTX_CPORT_MASK GENMASK(12, 8)

drivers/media/platform/ti/cal/cal_regs.h

427

#define CAL_CSI2_CTX_LINES_MASK GENMASK(29, 16)

drivers/media/platform/ti/cal/cal_regs.h

429

#define CAL_CSI2_STATUS_FRAME_MASK GENMASK(15, 0)

drivers/media/platform/ti/cal/cal_regs.h

431

#define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK GENMASK(7, 0)

drivers/media/platform/ti/cal/cal_regs.h

432

#define CAL_CSI2_PHY_REG0_THS_TERM_MASK GENMASK(15, 8)

drivers/media/platform/ti/cal/cal_regs.h

437

#define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK GENMASK(7, 0)

drivers/media/platform/ti/cal/cal_regs.h

438

#define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK GENMASK(9, 8)

drivers/media/platform/ti/cal/cal_regs.h

439

#define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK GENMASK(17, 10)

drivers/media/platform/ti/cal/cal_regs.h

440

#define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK GENMASK(24, 18)

drivers/media/platform/ti/cal/cal_regs.h

444

#define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28)

drivers/media/platform/ti/cal/cal_regs.h

448

#define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK GENMASK(23, 0)

drivers/media/platform/ti/cal/cal_regs.h

449

#define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK GENMASK(25, 24)

drivers/media/platform/ti/cal/cal_regs.h

450

#define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK GENMASK(27, 26)

drivers/media/platform/ti/cal/cal_regs.h

451

#define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK GENMASK(29, 28)

drivers/media/platform/ti/cal/cal_regs.h

452

#define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK GENMASK(31, 30)

drivers/media/platform/ti/cal/cal_regs.h

455

#define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK GENMASK(2, 1)

drivers/media/platform/ti/cal/cal_regs.h

456

#define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK GENMASK(4, 3)

drivers/media/platform/ti/cal/cal_regs.h

459

#define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK GENMASK(12, 11)

drivers/media/platform/ti/cal/cal_regs.h

460

#define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK GENMASK(16, 13)

drivers/media/platform/ti/cal/cal_regs.h

91

#define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)

drivers/media/platform/ti/cal/cal_regs.h

92

#define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)

drivers/media/platform/ti/cal/cal_regs.h

93

#define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)

drivers/media/platform/ti/cal/cal_regs.h

94

#define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)

drivers/media/platform/ti/cal/cal_regs.h

95

#define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)

drivers/media/platform/ti/cal/cal_regs.h

96

#define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)

drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c

32

#define SHIM_DMACNTX_YUV422 GENMASK(27, 26)

drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c

34

#define SHIM_DMACNTX_SIZE GENMASK(21, 20)

drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c

35

#define SHIM_DMACNTX_FMT GENMASK(5, 0)

drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c

42

#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0)

drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c

43

#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16)

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

25

#define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

32

#define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

38

#define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

40

#define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

50

#define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

52

#define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

53

#define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

57

#define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

60

#define G1_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

64

#define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

65

#define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

68

#define G1_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

69

#define G1_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

70

#define G1_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

71

#define G1_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

75

#define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

76

#define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15))

drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c

78

#define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0))

drivers/media/platform/verisilicon/hantro_g1_regs.h

313

#define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))

drivers/media/platform/verisilicon/hantro_g1_regs.h

314

#define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16))

drivers/media/platform/verisilicon/hantro_g1_regs.h

321

#define G1_REG_PP_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/hantro_g1_regs.h

332

#define G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))

drivers/media/platform/verisilicon/hantro_g1_regs.h

333

#define G1_REG_PP_INPUT_SIZE_WIDTH(v) (((v) << 0) & GENMASK(8, 0))

drivers/media/platform/verisilicon/hantro_g1_regs.h

335

#define G1_REG_PP_PADD_R(v) (((v) << 23) & GENMASK(27, 23))

drivers/media/platform/verisilicon/hantro_g1_regs.h

336

#define G1_REG_PP_PADD_G(v) (((v) << 18) & GENMASK(22, 18))

drivers/media/platform/verisilicon/hantro_g1_regs.h

342

#define G1_REG_PP_PADD_B(v) (((v) << 18) & GENMASK(22, 18))

drivers/media/platform/verisilicon/hantro_g1_regs.h

347

#define G1_REG_PP_CONTROL_IN_FMT(v) (((v) << 29) & GENMASK(31, 29))

drivers/media/platform/verisilicon/hantro_g1_regs.h

348

#define G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))

drivers/media/platform/verisilicon/hantro_g1_regs.h

349

#define G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))

drivers/media/platform/verisilicon/hantro_g1_regs.h

350

#define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))

drivers/media/platform/verisilicon/hantro_g1_regs.h

352

#define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

101

#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

102

#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

104

#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

105

#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

107

#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

108

#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

110

#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

111

#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

113

#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

114

#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

115

#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

116

#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

117

#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

118

#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

120

#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

121

#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

122

#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

123

#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

124

#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

125

#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

127

#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

128

#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

129

#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

130

#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

132

#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

133

#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

134

#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

135

#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

136

#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

137

#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

139

#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

140

#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

141

#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

142

#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

143

#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

144

#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

146

#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

147

#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

148

#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

149

#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

151

#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

152

#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

153

#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

154

#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

156

#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

158

#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

160

#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

162

#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

163

#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

164

#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

165

#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

167

#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

168

#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

172

#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

173

#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

175

#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

176

#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

178

#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

179

#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

180

#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

181

#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

34

#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

36

#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

37

#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

39

#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

40

#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

41

#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

43

#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

53

#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

54

#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

55

#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

69

#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

70

#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

71

#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

75

#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

76

#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

77

#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

78

#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

79

#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

80

#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

82

#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

83

#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

84

#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

85

#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

86

#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

87

#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

89

#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

90

#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

92

#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

93

#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

95

#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

96

#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

98

#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c

99

#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

28

#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

30

#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

31

#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

33

#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

34

#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

35

#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

37

#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

47

#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

48

#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

49

#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

62

#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

63

#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

67

#define VDPU_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

70

#define VDPU_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

75

#define VDPU_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

76

#define VDPU_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

77

#define VDPU_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))

drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c

78

#define VDPU_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))

drivers/media/platform/xilinx/xilinx-csi2rxss.c

103

#define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

105

#define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

108

#define XCSI_VCXINF2R_DT GENMASK(5, 0)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

34

#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

35

#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

38

#define XCSI_CSR_PKTCNT GENMASK(31, 16)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

83

#define XCSI_SPKTR_DATA GENMASK(23, 8)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

84

#define XCSI_SPKTR_VC GENMASK(7, 6)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

85

#define XCSI_SPKTR_DT GENMASK(5, 0)

drivers/media/platform/xilinx/xilinx-csi2rxss.c

89

#define XCSI_VCXR_VCERR GENMASK(23, 0)

drivers/media/rc/ir-spi.c

116

idata->pulse = GENMASK(bits, 0);

drivers/media/rc/meson-ir.c

24

#define IR_DEC_LDR_ACTIVE_MAX GENMASK(28, 16)

drivers/media/rc/meson-ir.c

25

#define IR_DEC_LDR_ACTIVE_MIN GENMASK(12, 0)

drivers/media/rc/meson-ir.c

27

#define IR_DEC_LDR_IDLE_MAX GENMASK(28, 16)

drivers/media/rc/meson-ir.c

28

#define IR_DEC_LDR_IDLE_MIN GENMASK(12, 0)

drivers/media/rc/meson-ir.c

30

#define IR_DEC_LDR_REPEAT_MAX GENMASK(25, 16)

drivers/media/rc/meson-ir.c

31

#define IR_DEC_LDR_REPEAT_MIN GENMASK(9, 0)

drivers/media/rc/meson-ir.c

33

#define IR_DEC_BIT_0_MAX GENMASK(25, 16)

drivers/media/rc/meson-ir.c

34

#define IR_DEC_BIT_0_MIN GENMASK(9, 0)

drivers/media/rc/meson-ir.c

36

#define IR_DEC_REG0_FILTER GENMASK(30, 28)

drivers/media/rc/meson-ir.c

37

#define IR_DEC_REG0_FRAME_TIME_MAX GENMASK(24, 12)

drivers/media/rc/meson-ir.c

38

#define IR_DEC_REG0_BASE_TIME GENMASK(11, 0)

drivers/media/rc/meson-ir.c

42

#define IR_DEC_STATUS_BIT_1_MAX GENMASK(29, 20)

drivers/media/rc/meson-ir.c

43

#define IR_DEC_STATUS_BIT_1_MIN GENMASK(19, 10)

drivers/media/rc/meson-ir.c

46

#define IR_DEC_STATUS_FRAME_STATUS GENMASK(3, 0)

drivers/media/rc/meson-ir.c

48

#define IR_DEC_REG1_TIME_IV GENMASK(28, 16)

drivers/media/rc/meson-ir.c

49

#define IR_DEC_REG1_FRAME_LEN GENMASK(13, 8)

drivers/media/rc/meson-ir.c

52

#define IR_DEC_REG1_IRQSEL GENMASK(3, 2)

drivers/media/rc/meson-ir.c

55

#define IR_DEC_REG1_MODE GENMASK(8, 7)

drivers/media/rc/meson-ir.c

65

#define IR_DEC_REG2_MODE GENMASK(3, 0)

drivers/media/rc/meson-ir.c

67

#define IR_DEC_DURATN2_MAX GENMASK(25, 16)

drivers/media/rc/meson-ir.c

68

#define IR_DEC_DURATN2_MIN GENMASK(9, 0)

drivers/media/rc/meson-ir.c

70

#define IR_DEC_DURATN3_MAX GENMASK(25, 16)

drivers/media/rc/meson-ir.c

71

#define IR_DEC_DURATN3_MIN GENMASK(9, 0)

drivers/media/rc/mtk-cir.c

118

[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},

drivers/media/rc/mtk-cir.c

119

[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},

drivers/media/rc/mtk-cir.c

123

[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},

drivers/media/rc/mtk-cir.c

124

[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},

drivers/media/rc/mtk-cir.c

29

#define MTK_OK_COUNT_MASK (GENMASK(22, 16))

drivers/media/rc/mtk-cir.c

39

#define MTK_WIDTH_MASK (GENMASK(7, 0))

drivers/media/rc/mtk-cir.c

43

#define MTK_DG_CNT_MASK (GENMASK(12, 8))

drivers/media/rc/sunxi-cir.c

70

#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))

drivers/media/rc/sunxi-cir.c

72

#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))

drivers/media/test-drivers/vidtv/vidtv_psi.c

107

mask = GENMASK(12, 0);

drivers/media/test-drivers/vidtv/vidtv_psi.c

116

mask = GENMASK(12, 0);

drivers/media/test-drivers/vidtv/vidtv_psi.c

127

mask = GENMASK(15, desc_len_nbits);

drivers/media/test-drivers/vidtv/vidtv_psi.c

139

mask = GENMASK(15, 13);

drivers/media/test-drivers/vidtv/vidtv_psi.c

98

mask = GENMASK(11, 0);

drivers/media/test-drivers/vivid/vivid-ctrls.c

1861

s64 hdmi_input_mask = GENMASK(dev->num_hdmi_inputs - 1, 0);

drivers/media/test-drivers/vivid/vivid-ctrls.c

1888

s64 hdmi_output_mask = GENMASK(dev->num_hdmi_outputs - 1, 0);

drivers/media/usb/uvc/uvc_ctrl.c

566

.menu_mask = GENMASK(V4L2_CID_POWER_LINE_FREQUENCY_60HZ,

drivers/media/usb/uvc/uvc_ctrl.c

578

.menu_mask = GENMASK(V4L2_CID_POWER_LINE_FREQUENCY_60HZ,

drivers/media/usb/uvc/uvc_ctrl.c

590

.menu_mask = GENMASK(V4L2_CID_POWER_LINE_FREQUENCY_AUTO,

drivers/media/usb/uvc/uvc_ctrl.c

778

.menu_mask = GENMASK(V4L2_EXPOSURE_APERTURE_PRIORITY,

drivers/media/usb/uvc/uvc_v4l2.c

69

map->menu_mask = GENMASK(xmap->menu_count - 1, 0);

drivers/media/v4l2-core/v4l2-ctrls-core.c

501

if (lf->level > GENMASK(5, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

504

if (lf->sharpness > GENMASK(2, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

655

if (q->flags > GENMASK(2, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

663

q->delta_q_res > GENMASK(1, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

666

if (q->qm_y > GENMASK(3, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

667

q->qm_u > GENMASK(3, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

668

q->qm_v > GENMASK(3, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

679

if (s->flags > GENMASK(4, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

707

if (lf->flags > GENMASK(3, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

711

if (lf->level[i] > GENMASK(5, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

715

if (lf->sharpness > GENMASK(2, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

735

if (cdef->damping_minus_3 > GENMASK(1, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

736

cdef->bits > GENMASK(1, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

740

if (cdef->y_pri_strength[i] > GENMASK(3, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

742

cdef->uv_pri_strength[i] > GENMASK(3, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

762

if (fg->flags > GENMASK(4, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

765

if (fg->film_grain_params_ref_idx > GENMASK(2, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

768

fg->num_cr_points > GENMASK(3, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

769

fg->grain_scaling_minus_8 > GENMASK(1, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

770

fg->ar_coeff_lag > GENMASK(1, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

771

fg->ar_coeff_shift_minus_6 > GENMASK(1, 0) ||

drivers/media/v4l2-core/v4l2-ctrls-core.c

772

fg->grain_scale_shift > GENMASK(1, 0))

drivers/media/v4l2-core/v4l2-ctrls-core.c

836

if (f->superres_denom > GENMASK(2, 0) + 9)

drivers/memory/bt1-l2-ctl.c

24

#define L2_CTL_DATA_STALL_MASK GENMASK(1, L2_CTL_DATA_STALL_FLD)

drivers/memory/bt1-l2-ctl.c

26

#define L2_CTL_TAG_STALL_MASK GENMASK(3, L2_CTL_TAG_STALL_FLD)

drivers/memory/bt1-l2-ctl.c

28

#define L2_CTL_WS_STALL_MASK GENMASK(5, L2_CTL_WS_STALL_FLD)

drivers/memory/mtk-smi.c

45

#define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)

drivers/memory/renesas-rpc-if-regs.h

136

#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)

drivers/memory/renesas-rpc-if.c

348

return GENMASK(3, 4 - nbytes);

drivers/memory/renesas-rpc-if.c

387

rpc->enable |= RPCIF_SMENR_ADE(GENMASK(

drivers/memory/stm32-fmc2-ebi.c

41

#define FMC2_BCR_MTYP GENMASK(3, 2)

drivers/memory/stm32-fmc2-ebi.c

42

#define FMC2_BCR_MWID GENMASK(5, 4)

drivers/memory/stm32-fmc2-ebi.c

51

#define FMC2_BCR_CPSIZE GENMASK(18, 16)

drivers/memory/stm32-fmc2-ebi.c

53

#define FMC2_BCR_CSCOUNT GENMASK(21, 20)

drivers/memory/stm32-fmc2-ebi.c

54

#define FMC2_BCR_NBLSET GENMASK(23, 22)

drivers/memory/stm32-fmc2-ebi.c

57

#define FMC2_BXTR_ADDSET GENMASK(3, 0)

drivers/memory/stm32-fmc2-ebi.c

58

#define FMC2_BXTR_ADDHLD GENMASK(7, 4)

drivers/memory/stm32-fmc2-ebi.c

59

#define FMC2_BXTR_DATAST GENMASK(15, 8)

drivers/memory/stm32-fmc2-ebi.c

60

#define FMC2_BXTR_BUSTURN GENMASK(19, 16)

drivers/memory/stm32-fmc2-ebi.c

61

#define FMC2_BTR_CLKDIV GENMASK(23, 20)

drivers/memory/stm32-fmc2-ebi.c

62

#define FMC2_BTR_DATLAT GENMASK(27, 24)

drivers/memory/stm32-fmc2-ebi.c

63

#define FMC2_BXTR_ACCMOD GENMASK(29, 28)

drivers/memory/stm32-fmc2-ebi.c

64

#define FMC2_BXTR_DATAHLD GENMASK(31, 30)

drivers/memory/stm32-fmc2-ebi.c

67

#define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)

drivers/memory/stm32-fmc2-ebi.c

71

#define FMC2_CFGR_CLKDIV GENMASK(19, 16)

drivers/memory/stm32-fmc2-ebi.c

76

#define FMC2_SR_ISOST GENMASK(1, 0)

drivers/memory/stm32-fmc2-ebi.c

81

#define FMC2_CIDCFGR_SCID GENMASK(6, 4)

drivers/memory/stm32-fmc2-ebi.c

86

#define FMC2_SEMCR_SEMCID GENMASK(6, 4)

drivers/memory/stm32_omm.c

23

#define CR_MUXENMODE_MASK GENMASK(1, 0)

drivers/memory/stm32_omm.c

25

#define CR_CSSEL_OVR_MASK GENMASK(6, 5)

drivers/memory/stm32_omm.c

26

#define CR_REQ2ACK_MASK GENMASK(23, 16)

drivers/memory/tegra/tegra186.c

22

#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)

drivers/memory/tegra/tegra20-emc.c

112

#define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0)

drivers/memory/tegra/tegra20-emc.c

114

#define EMC_MRR_DEV_SELECTN GENMASK(31, 30)

drivers/memory/tegra/tegra20-emc.c

115

#define EMC_MRR_MRR_MA GENMASK(23, 16)

drivers/memory/tegra/tegra20-emc.c

116

#define EMC_MRR_MRR_DATA GENMASK(15, 0)

drivers/memory/tegra/tegra20-emc.c

118

#define EMC_ADR_CFG_0_EMEM_NUMDEV GENMASK(25, 24)

drivers/memory/tegra/tegra20.c

26

#define MC_STAT_CONTROL_CLIENT_ID GENMASK(13, 8)

drivers/memory/tegra/tegra20.c

27

#define MC_STAT_CONTROL_EVENT GENMASK(23, 16)

drivers/memory/tegra/tegra20.c

28

#define MC_STAT_CONTROL_PRI_EVENT GENMASK(25, 24)

drivers/memory/tegra/tegra20.c

29

#define MC_STAT_CONTROL_FILTER_CLIENT_ENABLE GENMASK(26, 26)

drivers/memory/tegra/tegra20.c

30

#define MC_STAT_CONTROL_FILTER_PRI GENMASK(29, 28)

drivers/memory/tegra/tegra210-emc-core.c

88

#define LPDDR2_MR4_SRR GENMASK(2, 0)

drivers/memory/tegra/tegra30-emc.c

219

#define EMC_MRR_DEV_SELECTN GENMASK(31, 30)

drivers/memory/tegra/tegra30-emc.c

220

#define EMC_MRR_MRR_MA GENMASK(23, 16)

drivers/memory/tegra/tegra30-emc.c

221

#define EMC_MRR_MRR_DATA GENMASK(15, 0)

drivers/mfd/atmel-smc.c

120

conf->timings &= ~GENMASK(shift + 3, shift);

drivers/mfd/atmel-smc.c

159

conf->setup &= ~GENMASK(shift + 7, shift);

drivers/mfd/atmel-smc.c

198

conf->pulse &= ~GENMASK(shift + 7, shift);

drivers/mfd/atmel-smc.c

236

conf->cycle &= ~GENMASK(shift + 15, shift);

drivers/mfd/atmel-smc.c

56

unsigned int lsbmask = GENMASK(msbpos - 1, 0);

drivers/mfd/atmel-smc.c

57

unsigned int msbmask = GENMASK(msbwidth - 1, 0);

drivers/mfd/intel-lpss.c

58

#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)

drivers/mfd/intel-lpss.c

61

#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)

drivers/mfd/intel-lpss.c

70

#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)

drivers/mfd/intel_soc_pmic_bxtwc.c

130

REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),

drivers/mfd/intel_soc_pmic_bxtwc.c

134

REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),

drivers/mfd/intel_soc_pmic_bxtwc.c

139

REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),

drivers/mfd/intel_soc_pmic_bxtwc.c

140

REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),

drivers/mfd/intel_soc_pmic_bxtwc.c

144

REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),

drivers/mfd/intel_soc_pmic_bxtwc.c

148

REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),

drivers/mfd/intel_soc_pmic_bxtwc.c

32

#define REG_ADDR_MASK GENMASK(15, 8)

drivers/mfd/intel_soc_pmic_bxtwc.c

34

#define REG_OFFSET_MASK GENMASK(7, 0)

drivers/mfd/intel_soc_pmic_chtwc.c

23

#define REG_OFFSET_MASK GENMASK(7, 0)

drivers/mfd/intel_soc_pmic_chtwc.c

24

#define REG_ADDR_MASK GENMASK(15, 8)

drivers/mfd/iqs62x.c

76

#define IQS62X_HALL_CAL_MASK GENMASK(3, 0)

drivers/mfd/ls2k-bmc-core.c

50

#define LS2K_BMC_PCIE_LTSSM_STS GENMASK(5, 0)

drivers/mfd/max77759.c

244

REGMAP_IRQ_REG(MAX77759_MAXQ_INT_GPIO, 0, GENMASK(1, 0)),

drivers/mfd/max77759.c

245

REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC1, 0, GENMASK(5, 2)),

drivers/mfd/max77759.c

246

REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC2, 1, GENMASK(7, 0)),

drivers/mfd/max77759.c

247

REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC3, 2, GENMASK(7, 0)),

drivers/mfd/max77759.c

248

REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC4, 3, GENMASK(7, 0)),

drivers/mfd/max77759.c

259

REGMAP_IRQ_REG(MAX77759_CHARGER_INT_1, 0, GENMASK(7, 0)),

drivers/mfd/max77759.c

260

REGMAP_IRQ_REG(MAX77759_CHARGER_INT_2, 1, GENMASK(7, 0)),

drivers/mfd/mt6370.c

24

#define MT6370_VENID_MASK GENMASK(7, 4)

drivers/mfd/qcom-pm8xxx.c

245

if (master & GENMASK(7, 1))

drivers/mfd/rt4831.c

20

#define RT4831_VID_MASK GENMASK(1, 0)

drivers/mfd/sec-irq.c

26

REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),

drivers/mfd/sec-irq.c

86

REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),

drivers/mfd/sprd-sc27xx-spi.c

35

#define SPRD_PMIC_CHG_TYPE_MASK GENMASK(7, 5)

drivers/mfd/upboard-fpga.c

28

#define UPBOARD_MANUFACTURER_ID_MASK GENMASK(7, 0)

drivers/mfd/upboard-fpga.c

37

#define UPBOARD_FW_ID_BUILD_MASK GENMASK(15, 12)

drivers/mfd/upboard-fpga.c

38

#define UPBOARD_FW_ID_MAJOR_MASK GENMASK(11, 8)

drivers/mfd/upboard-fpga.c

39

#define UPBOARD_FW_ID_MINOR_MASK GENMASK(7, 4)

drivers/mfd/upboard-fpga.c

40

#define UPBOARD_FW_ID_PATCH_MASK GENMASK(3, 0)

drivers/misc/amd-sbi/rmi-core.c

50

#define CPUID_MCA_FUNC_MASK GENMASK(31, 0)

drivers/misc/dw-xdata-pcie.c

31

#define CONTROL_LENGTH(a) FIELD_PREP(GENMASK(13, 2), a)

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

64

#define BYTE_LOW (GENMASK(7, 0))

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c

65

#define BYTE_HIGH (GENMASK(12, 8))

drivers/misc/mei/hw.h

424

#define MEI_MSG_MAX_LEN_MASK GENMASK(9, 0)

drivers/misc/mei/vsc-fw-loader.c

30

#define VSC_MAINSTEPPING_VERSION_MASK GENMASK(7, 4)

drivers/misc/mei/vsc-fw-loader.c

33

#define VSC_SUBSTEPPING_VERSION_MASK GENMASK(3, 0)

drivers/misc/mei/vsc-fw-loader.c

37

#define VSC_BOOT_IMG_OPTION_MASK GENMASK(15, 0)

drivers/misc/mrvl_cn10k_dpi.c

44

#define DPI_EBUS_PORTX_CFG_MPS(x) FIELD_PREP(GENMASK(6, 4), x)

drivers/misc/mrvl_cn10k_dpi.c

45

#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/misc/mrvl_cn10k_dpi.c

46

#define DPI_DMA_IDS2_INST_AURA(x) FIELD_PREP(GENMASK(19, 0), x)

drivers/misc/mrvl_cn10k_dpi.c

47

#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) FIELD_PREP(GENMASK(13, 0), x)

drivers/misc/mrvl_cn10k_dpi.c

48

#define DPI_EBUS_PORTX_CFG_MRRS(x) FIELD_PREP(GENMASK(2, 0), x)

drivers/misc/mrvl_cn10k_dpi.c

49

#define DPI_ENG_BUF_BLKS(x) FIELD_PREP(GENMASK(5, 0), x)

drivers/misc/ocxl/config.c

11

#define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)

drivers/misc/ocxl/config.c

12

#define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)

drivers/misc/ocxl/config.c

13

#define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)

drivers/misc/ocxl/config.c

14

#define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)

drivers/misc/ocxl/config.c

837

val = recv_cap & GENMASK(31, 0);

drivers/misc/ocxl/config.c

9

#define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)

drivers/misc/rp1/rp1_pci.c

19

#define RP1_HW_IRQ_MASK GENMASK(5, 0)

drivers/misc/xilinx_tmr_inject.c

29

#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16)

drivers/misc/xilinx_tmr_manager.c

30

#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0)

drivers/misc/xilinx_tmr_manager.c

31

#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8)

drivers/mmc/host/cavium.c

188

*reg |= FIELD_PREP(GENMASK(61, 60), bus_id);

drivers/mmc/host/cqhci.h

110

#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))

drivers/mmc/host/cqhci.h

111

#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)

drivers/mmc/host/cqhci.h

113

#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)

drivers/mmc/host/cqhci.h

114

#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)

drivers/mmc/host/cqhci.h

20

#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)

drivers/mmc/host/cqhci.h

21

#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)

drivers/mmc/host/cqhci.h

22

#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))

drivers/mmc/host/cqhci.h

27

#define CQHCI_CAP_ITCFMUL GENMASK(15, 12)

drivers/mmc/host/cqhci.h

95

#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)

drivers/mmc/host/cqhci.h

96

#define CQHCI_SSC1_CIT_MASK GENMASK(15, 0)

drivers/mmc/host/dw_mmc-bluefield.c

19

#define UHS_REG_EXT_SAMPLE_MASK GENMASK(22, 16)

drivers/mmc/host/dw_mmc-bluefield.c

20

#define UHS_REG_EXT_DRIVE_MASK GENMASK(29, 23)

drivers/mmc/host/dw_mmc-k3.c

39

#define GPIO_CLK_DIV_MASK GENMASK(11, 8)

drivers/mmc/host/dw_mmc-k3.c

40

#define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13)

drivers/mmc/host/dw_mmc-k3.c

41

#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)

drivers/mmc/host/dw_mmc-k3.c

42

#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21)

drivers/mmc/host/dw_mmc-k3.c

43

#define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26)

drivers/mmc/host/dw_mmc-rockchip.c

155

FIELD_PREP_WM16(GENMASK(11, 1), raw_value));

drivers/mmc/host/dw_mmc-rockchip.c

158

FIELD_PREP_WM16(GENMASK(11, 1), raw_value));

drivers/mmc/host/dw_mmc-starfive.c

24

#define STARFIVE_SMPL_PHASE GENMASK(20, 16)

drivers/mmc/host/loongson2-mmc.c

107

#define LOONGSON2_MMC_DCNT_BNUM GENMASK(11, 0)

drivers/mmc/host/loongson2-mmc.c

108

#define LOONGSON2_MMC_DCNT_BYTE GENMASK(23, 12)

drivers/mmc/host/loongson2-mmc.c

151

#define LOONGSON2_MMC_IEN_ALL GENMASK(9, 0)

drivers/mmc/host/loongson2-mmc.c

152

#define LOONGSON2_MMC_INT_CLEAR GENMASK(9, 0)

drivers/mmc/host/loongson2-mmc.c

158

#define LOONGSON2_MMC_DLLCTL_TIME GENMASK(7, 0)

drivers/mmc/host/loongson2-mmc.c

159

#define LOONGSON2_MMC_DLLCTL_INCRE GENMASK(15, 8)

drivers/mmc/host/loongson2-mmc.c

160

#define LOONGSON2_MMC_DLLCTL_START GENMASK(23, 16)

drivers/mmc/host/loongson2-mmc.c

163

#define LOONGSON2_MMC_DLLCTL_TIME_BPASS GENMASK(29, 26)

drivers/mmc/host/loongson2-mmc.c

165

#define LOONGSON2_MMC_DELAY_PAD GENMASK(7, 0)

drivers/mmc/host/loongson2-mmc.c

166

#define LOONGSON2_MMC_DELAY_RD GENMASK(15, 8)

drivers/mmc/host/loongson2-mmc.c

183

#define LOONGSON2_MMC_DMA_DESC_ADDR_LOW GENMASK(31, 1)

drivers/mmc/host/loongson2-mmc.c

193

#define LS2K1000_SDIO_DMA_MASK GENMASK(17, 15)

drivers/mmc/host/loongson2-mmc.c

201

#define LS2K0500_SDIO_DMA_MASK GENMASK(15, 14)

drivers/mmc/host/loongson2-mmc.c

510

pad_delay = FIELD_GET(GENMASK(7, 1), val);

drivers/mmc/host/loongson2-mmc.c

65

#define LOONGSON2_MMC_PRE GENMASK(9, 0)

drivers/mmc/host/loongson2-mmc.c

69

#define LOONGSON2_MMC_CCTL_INDEX GENMASK(5, 0)

drivers/mmc/host/loongson2-mmc.c

80

#define LOONGSON2_MMC_CSTS_INDEX GENMASK(7, 0)

drivers/mmc/host/loongson2-mmc.c

90

#define LOONGSON2_MMC_DTIMR GENMASK(23, 0)

drivers/mmc/host/loongson2-mmc.c

93

#define LOONGSON2_MMC_BSIZE GENMASK(11, 0)

drivers/mmc/host/loongson2-mmc.c

96

#define LOONGSON2_MMC_DCTL_BNUM GENMASK(11, 0)

drivers/mmc/host/meson-gx-mmc.c

182

#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)

drivers/mmc/host/meson-gx-mmc.c

186

#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)

drivers/mmc/host/meson-gx-mmc.c

195

#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)

drivers/mmc/host/meson-gx-mmc.c

199

#define CMD_DATA_MASK GENMASK(31, 2)

drivers/mmc/host/meson-gx-mmc.c

202

#define CMD_RESP_MASK GENMASK(31, 1)

drivers/mmc/host/meson-gx-mmc.c

34

#define CLK_DIV_MASK GENMASK(5, 0)

drivers/mmc/host/meson-gx-mmc.c

35

#define CLK_SRC_MASK GENMASK(7, 6)

drivers/mmc/host/meson-gx-mmc.c

36

#define CLK_CORE_PHASE_MASK GENMASK(9, 8)

drivers/mmc/host/meson-gx-mmc.c

37

#define CLK_TX_PHASE_MASK GENMASK(11, 10)

drivers/mmc/host/meson-gx-mmc.c

38

#define CLK_RX_PHASE_MASK GENMASK(13, 12)

drivers/mmc/host/meson-gx-mmc.c

41

#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)

drivers/mmc/host/meson-gx-mmc.c

42

#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)

drivers/mmc/host/meson-gx-mmc.c

46

#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)

drivers/mmc/host/meson-gx-mmc.c

47

#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)

drivers/mmc/host/meson-gx-mmc.c

58

#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)

drivers/mmc/host/meson-gx-mmc.c

70

#define START_DESC_ADDR_MASK GENMASK(31, 2)

drivers/mmc/host/meson-gx-mmc.c

73

#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)

drivers/mmc/host/meson-gx-mmc.c

78

#define CFG_BLK_LEN_MASK GENMASK(7, 4)

drivers/mmc/host/meson-gx-mmc.c

79

#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)

drivers/mmc/host/meson-gx-mmc.c

80

#define CFG_RC_CC_MASK GENMASK(15, 12)

drivers/mmc/host/meson-gx-mmc.c

90

#define STATUS_DATI GENMASK(23, 16)

drivers/mmc/host/meson-gx-mmc.c

93

#define IRQ_RXD_ERR_MASK GENMASK(7, 0)

drivers/mmc/host/meson-mx-sdhc.h

107

#define MESON_SDHC_ISTA_ALL_IRQS GENMASK(14, 0)

drivers/mmc/host/meson-mx-sdhc.h

118

#define MESON_SDHC_ESTA_11_13 GENMASK(13, 11)

drivers/mmc/host/meson-mx-sdhc.h

124

#define MESON_SDHC_ENHC_MESON8M2_DEBUG GENMASK(5, 3)

drivers/mmc/host/meson-mx-sdhc.h

125

#define MESON_SDHC_ENHC_MESON6_RX_TIMEOUT GENMASK(7, 0)

drivers/mmc/host/meson-mx-sdhc.h

128

#define MESON_SDHC_ENHC_SDIO_IRQ_PERIOD GENMASK(15, 8)

drivers/mmc/host/meson-mx-sdhc.h

129

#define MESON_SDHC_ENHC_RXFIFO_TH GENMASK(24, 18)

drivers/mmc/host/meson-mx-sdhc.h

130

#define MESON_SDHC_ENHC_TXFIFO_TH GENMASK(31, 25)

drivers/mmc/host/meson-mx-sdhc.h

133

#define MESON_SDHC_CLK2_RX_CLK_PHASE GENMASK(11, 0)

drivers/mmc/host/meson-mx-sdhc.h

134

#define MESON_SDHC_CLK2_SD_CLK_PHASE GENMASK(23, 12)

drivers/mmc/host/meson-mx-sdhc.h

14

#define MESON_SDHC_SEND_CMD_INDEX GENMASK(5, 0)

drivers/mmc/host/meson-mx-sdhc.h

22

#define MESON_SDHC_SEND_TOTAL_PACK GENMASK(31, 16)

drivers/mmc/host/meson-mx-sdhc.h

25

#define MESON_SDHC_CTRL_DAT_TYPE GENMASK(1, 0)

drivers/mmc/host/meson-mx-sdhc.h

28

#define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)

drivers/mmc/host/meson-mx-sdhc.h

29

#define MESON_SDHC_CTRL_RX_TIMEOUT GENMASK(19, 13)

drivers/mmc/host/meson-mx-sdhc.h

30

#define MESON_SDHC_CTRL_RX_PERIOD GENMASK(23, 20)

drivers/mmc/host/meson-mx-sdhc.h

31

#define MESON_SDHC_CTRL_RX_ENDIAN GENMASK(26, 24)

drivers/mmc/host/meson-mx-sdhc.h

34

#define MESON_SDHC_CTRL_TX_ENDIAN GENMASK(31, 29)

drivers/mmc/host/meson-mx-sdhc.h

38

#define MESON_SDHC_STAT_DAT3_0 GENMASK(4, 1)

drivers/mmc/host/meson-mx-sdhc.h

40

#define MESON_SDHC_STAT_RXFIFO_CNT GENMASK(12, 6)

drivers/mmc/host/meson-mx-sdhc.h

41

#define MESON_SDHC_STAT_TXFIFO_CNT GENMASK(19, 13)

drivers/mmc/host/meson-mx-sdhc.h

42

#define MESON_SDHC_STAT_DAT7_4 GENMASK(23, 20)

drivers/mmc/host/meson-mx-sdhc.h

45

#define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0)

drivers/mmc/host/meson-mx-sdhc.h

47

#define MESON_SDHC_CLKC_MEM_PWR_OFF GENMASK(26, 25)

drivers/mmc/host/meson-mx-sdhc.h

53

#define MESON_SDHC_PDMA_PIO_RDRESP GENMASK(3, 1)

drivers/mmc/host/meson-mx-sdhc.h

55

#define MESON_SDHC_PDMA_WR_BURST GENMASK(9, 5)

drivers/mmc/host/meson-mx-sdhc.h

56

#define MESON_SDHC_PDMA_RD_BURST GENMASK(14, 10)

drivers/mmc/host/meson-mx-sdhc.h

57

#define MESON_SDHC_PDMA_RXFIFO_TH GENMASK(21, 15)

drivers/mmc/host/meson-mx-sdhc.h

58

#define MESON_SDHC_PDMA_TXFIFO_TH GENMASK(28, 22)

drivers/mmc/host/meson-mx-sdhc.h

59

#define MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH GENMASK(30, 29)

drivers/mmc/host/meson-mx-sdhc.h

63

#define MESON_SDHC_MISC_WCRC_ERR_PATT GENMASK(6, 4)

drivers/mmc/host/meson-mx-sdhc.h

64

#define MESON_SDHC_MISC_WCRC_OK_PATT GENMASK(9, 7)

drivers/mmc/host/meson-mx-sdhc.h

65

#define MESON_SDHC_MISC_BURST_NUM GENMASK(21, 16)

drivers/mmc/host/meson-mx-sdhc.h

66

#define MESON_SDHC_MISC_THREAD_ID GENMASK(27, 22)

drivers/mmc/host/meson-mx-sdhc.h

68

#define MESON_SDHC_MISC_TXSTART_THRES GENMASK(31, 29)

drivers/mmc/host/meson-mx-sdhc.h

88

#define MESON_SDHC_ICTL_ALL_IRQS GENMASK(14, 0)

drivers/mmc/host/meson-mx-sdhc.h

89

#define MESON_SDHC_ICTL_DAT1_IRQ_DELAY GENMASK(17, 16)

drivers/mmc/host/meson-mx-sdio.c

34

#define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)

drivers/mmc/host/meson-mx-sdio.c

35

#define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)

drivers/mmc/host/meson-mx-sdio.c

42

#define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)

drivers/mmc/host/meson-mx-sdio.c

49

#define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)

drivers/mmc/host/meson-mx-sdio.c

53

#define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)

drivers/mmc/host/meson-mx-sdio.c

54

#define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)

drivers/mmc/host/meson-mx-sdio.c

55

#define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)

drivers/mmc/host/meson-mx-sdio.c

58

#define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)

drivers/mmc/host/meson-mx-sdio.c

65

#define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)

drivers/mmc/host/meson-mx-sdio.c

69

#define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)

drivers/mmc/host/meson-mx-sdio.c

74

#define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)

drivers/mmc/host/meson-mx-sdio.c

77

#define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)

drivers/mmc/host/meson-mx-sdio.c

83

#define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)

drivers/mmc/host/meson-mx-sdio.c

91

#define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)

drivers/mmc/host/meson-mx-sdio.c

96

#define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)

drivers/mmc/host/mmci.c

274

.stm32_idmabsize_mask = GENMASK(12, 5),

drivers/mmc/host/mmci.c

302

.stm32_idmabsize_mask = GENMASK(16, 5),

drivers/mmc/host/mmci.c

331

.stm32_idmabsize_mask = GENMASK(16, 6),

drivers/mmc/host/mmci.h

224

#define MMCI_STM32_THR_MASK GENMASK(3, 0)

drivers/mmc/host/mmci.h

239

#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)

drivers/mmc/host/mmci.h

59

#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)

drivers/mmc/host/mmci.h

66

#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)

drivers/mmc/host/mmci.h

96

#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)

drivers/mmc/host/mmci_qcom_dml.c

15

#define PRODUCER_CRCI_MSK GENMASK(1, 0)

drivers/mmc/host/mmci_qcom_dml.c

19

#define CONSUMER_CRCI_MSK GENMASK(3, 2)

drivers/mmc/host/mmci_qcom_dml.c

35

#define PRODUCER_PIPE_ID_MSK GENMASK(4, 0)

drivers/mmc/host/mmci_qcom_dml.c

37

#define CONSUMER_PIPE_ID_MSK GENMASK(20, 16)

drivers/mmc/host/mmci_stm32_sdmmc.c

24

#define DLYB_CFGR_SEL_MASK GENMASK(3, 0)

drivers/mmc/host/mmci_stm32_sdmmc.c

25

#define DLYB_CFGR_UNIT_MASK GENMASK(14, 8)

drivers/mmc/host/mmci_stm32_sdmmc.c

26

#define DLYB_CFGR_LNG_MASK GENMASK(27, 16)

drivers/mmc/host/mmci_stm32_sdmmc.c

38

#define DLYBSD_CR_RXTAPSEL_MASK GENMASK(6, 1)

drivers/mmc/host/mmci_stm32_sdmmc.c

41

#define DLYBSD_BYP_CMD GENMASK(21, 17)

drivers/mmc/host/mtk-sd.c

113

#define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */

drivers/mmc/host/mtk-sd.c

114

#define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */

drivers/mmc/host/mtk-sd.c

117

#define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */

drivers/mmc/host/mtk-sd.c

118

#define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */

drivers/mmc/host/mtk-sd.c

136

#define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */

drivers/mmc/host/mtk-sd.c

141

#define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */

drivers/mmc/host/mtk-sd.c

142

#define MSDC_PS_DAT GENMASK(23, 16) /* R */

drivers/mmc/host/mtk-sd.c

191

#define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */

drivers/mmc/host/mtk-sd.c

192

#define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */

drivers/mmc/host/mtk-sd.c

198

#define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */

drivers/mmc/host/mtk-sd.c

199

#define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */

drivers/mmc/host/mtk-sd.c

203

#define SDC_CFG_DTOC GENMASK(31, 24) /* RW */

drivers/mmc/host/mtk-sd.c

219

#define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */

drivers/mmc/host/mtk-sd.c

227

#define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */

drivers/mmc/host/mtk-sd.c

241

#define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)

drivers/mmc/host/mtk-sd.c

242

#define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)

drivers/mmc/host/mtk-sd.c

245

#define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */

drivers/mmc/host/mtk-sd.c

246

#define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */

drivers/mmc/host/mtk-sd.c

254

#define MSDC_PB1_WRDAT_CRC_TACNTR GENMASK(2, 0) /* RW */

drivers/mmc/host/mtk-sd.c

255

#define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */

drivers/mmc/host/mtk-sd.c

257

#define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */

drivers/mmc/host/mtk-sd.c

260

#define MSDC_PB1_RSVD20 GENMASK(18, 17) /* RW */

drivers/mmc/host/mtk-sd.c

266

#define MSDC_PB1_MSDC_CLK_ENFEAT GENMASK(31, 24) /* RW */

drivers/mmc/host/mtk-sd.c

272

#define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */

drivers/mmc/host/mtk-sd.c

273

#define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */

drivers/mmc/host/mtk-sd.c

274

#define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */

drivers/mmc/host/mtk-sd.c

276

#define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */

drivers/mmc/host/mtk-sd.c

278

#define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */

drivers/mmc/host/mtk-sd.c

279

#define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */

drivers/mmc/host/mtk-sd.c

280

#define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */

drivers/mmc/host/mtk-sd.c

281

#define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */

drivers/mmc/host/mtk-sd.c

282

#define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */

drivers/mmc/host/mtk-sd.c

283

#define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */

drivers/mmc/host/mtk-sd.c

284

#define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */

drivers/mmc/host/mtk-sd.c

293

#define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */

drivers/mmc/host/mtk-sd.c

294

#define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */

drivers/mmc/host/mtk-sd.c

295

#define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */

drivers/mmc/host/mtk-sd.c

297

#define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */

drivers/mmc/host/mtk-sd.c

300

#define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */

drivers/mmc/host/mtk-sd.c

311

#define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */

drivers/mmc/host/mtk-sd.c

313

#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */

drivers/mmc/host/mtk-sd.c

325

#define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */

drivers/mmc/host/mtk-sd.c

326

#define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */

drivers/mmc/host/mtk-sd.c

333

#define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */

drivers/mmc/host/mtk-sd.c

334

#define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */

drivers/mmc/host/mtk-sd.c

337

#define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */

drivers/mmc/host/mtk-sd.c

342

#define PAD_DS_DLY1 GENMASK(14, 10) /* RW */

drivers/mmc/host/mtk-sd.c

343

#define PAD_DS_DLY3 GENMASK(4, 0) /* RW */

drivers/mmc/host/mtk-sd.c

378

#define GPDMA_DESC_CHECKSUM GENMASK(15, 8)

drivers/mmc/host/mtk-sd.c

380

#define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)

drivers/mmc/host/mtk-sd.c

381

#define GPDMA_DESC_PTR_H4 GENMASK(31, 28)

drivers/mmc/host/mtk-sd.c

385

#define GPDMA_DESC_BUFLEN GENMASK(15, 0)

drivers/mmc/host/mtk-sd.c

386

#define GPDMA_DESC_EXTLEN GENMASK(23, 16)

drivers/mmc/host/mtk-sd.c

395

#define BDMA_DESC_CHECKSUM GENMASK(15, 8)

drivers/mmc/host/mtk-sd.c

398

#define BDMA_DESC_NEXT_H4 GENMASK(27, 24)

drivers/mmc/host/mtk-sd.c

399

#define BDMA_DESC_PTR_H4 GENMASK(31, 28)

drivers/mmc/host/mtk-sd.c

403

#define BDMA_DESC_BUFLEN GENMASK(15, 0)

drivers/mmc/host/mtk-sd.c

404

#define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)

drivers/mmc/host/owl-mmc.c

59

#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)

drivers/mmc/host/sdhci-acpi.c

246

#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)

drivers/mmc/host/sdhci-brcmstb.c

40

#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12)

drivers/mmc/host/sdhci-cadence.c

24

#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)

drivers/mmc/host/sdhci-cadence.c

25

#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)

drivers/mmc/host/sdhci-cadence.c

26

#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)

drivers/mmc/host/sdhci-cadence.c

30

#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)

drivers/mmc/host/sdhci-cadence.c

31

#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)

drivers/mmc/host/sdhci-cadence.c

403

writel(GENMASK(7, 3), priv->ctl_addr);

drivers/mmc/host/sdhci-cadence.c

416

u32 shift = reg & GENMASK(1, 0);

drivers/mmc/host/sdhci-cadence.c

420

byte_enables = GENMASK(1, 0) << shift;

drivers/mmc/host/sdhci-cadence.c

430

u32 shift = reg & GENMASK(1, 0);

drivers/mmc/host/sdhci-esdhc-imx.c

113

#define ESDHC_TUNING_WINDOW_MASK GENMASK(22, 20)

drivers/mmc/host/sdhci-esdhc-imx.c

33

#define ESDHC_SYS_CTRL_DTOCV_MASK GENMASK(19, 16)

drivers/mmc/host/sdhci-esdhc-imx.c

86

#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK GENMASK(30, 16)

drivers/mmc/host/sdhci-esdhc-imx.c

87

#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK GENMASK(30, 24)

drivers/mmc/host/sdhci-esdhc-imx.c

88

#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK GENMASK(14, 8)

drivers/mmc/host/sdhci-esdhc-imx.c

89

#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK GENMASK(7, 4)

drivers/mmc/host/sdhci-esdhc-imx.c

90

#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK GENMASK(3, 0)

drivers/mmc/host/sdhci-of-arasan.c

340

HIWORD_UPDATE(val, GENMASK(width, 0),

drivers/mmc/host/sdhci-of-arasan.c

344

GENMASK(shift + width, shift),

drivers/mmc/host/sdhci-of-arasan.c

52

#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)

drivers/mmc/host/sdhci-of-arasan.c

56

#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)

drivers/mmc/host/sdhci-of-arasan.c

58

#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)

drivers/mmc/host/sdhci-of-arasan.c

60

#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24)

drivers/mmc/host/sdhci-of-arasan.c

65

#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)

drivers/mmc/host/sdhci-of-aspeed.c

24

#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21)

drivers/mmc/host/sdhci-of-aspeed.c

25

#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16)

drivers/mmc/host/sdhci-of-aspeed.c

26

#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11)

drivers/mmc/host/sdhci-of-aspeed.c

28

#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8)

drivers/mmc/host/sdhci-of-aspeed.c

29

#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3)

drivers/mmc/host/sdhci-of-aspeed.c

31

#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0)

drivers/mmc/host/sdhci-of-dwcmshc.c

129

#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */

drivers/mmc/host/sdhci-of-dwcmshc.c

132

#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */

drivers/mmc/host/sdhci-of-dwcmshc.c

155

#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */

drivers/mmc/host/sdhci-of-dwcmshc.c

159

#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */

drivers/mmc/host/sdhci-of-dwcmshc.c

161

#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */

drivers/mmc/host/sdhci-of-dwcmshc.c

181

#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */

drivers/mmc/host/sdhci-of-dwcmshc.c

192

#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */

drivers/mmc/host/sdhci-of-dwcmshc.c

202

#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */

drivers/mmc/host/sdhci-of-dwcmshc.c

33

#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)

drivers/mmc/host/sdhci-of-dwcmshc.c

40

#define DWCMSHC_AREA1_MASK GENMASK(11, 0)

drivers/mmc/host/sdhci-of-dwcmshc.c

54

#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */

drivers/mmc/host/sdhci-of-dwcmshc.c

57

#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */

drivers/mmc/host/sdhci-of-dwcmshc.c

59

#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */

drivers/mmc/host/sdhci-of-dwcmshc.c

61

#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */

drivers/mmc/host/sdhci-of-dwcmshc.c

72

#define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)

drivers/mmc/host/sdhci-of-dwcmshc.c

73

#define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)

drivers/mmc/host/sdhci-of-dwcmshc.c

75

#define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)

drivers/mmc/host/sdhci-of-dwcmshc.c

76

#define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)

drivers/mmc/host/sdhci-of-k1.c

45

#define SDHC_DLL_PREDLY_NUM GENMASK(3, 2)

drivers/mmc/host/sdhci-of-k1.c

46

#define SDHC_DLL_FULLDLY_RANGE GENMASK(5, 4)

drivers/mmc/host/sdhci-of-k1.c

47

#define SDHC_DLL_VREG_CTRL GENMASK(7, 6)

drivers/mmc/host/sdhci-of-k1.c

51

#define SDHC_DLL_REG1_CTRL GENMASK(7, 0)

drivers/mmc/host/sdhci-of-k1.c

52

#define SDHC_DLL_REG2_CTRL GENMASK(15, 8)

drivers/mmc/host/sdhci-of-k1.c

53

#define SDHC_DLL_REG3_CTRL GENMASK(23, 16)

drivers/mmc/host/sdhci-of-k1.c

54

#define SDHC_DLL_REG4_CTRL GENMASK(31, 24)

drivers/mmc/host/sdhci-of-k1.c

60

#define SDHC_PHY_DRIVE_SEL GENMASK(2, 0)

drivers/mmc/host/sdhci-of-ma35d1.c

40

#define MA35_SDHCI_INCR_MSK GENMASK(3, 0)

drivers/mmc/host/sdhci-of-sparx5.c

23

#define MSHC_DLY_CC_MASK GENMASK(16, 13)

drivers/mmc/host/sdhci-pci-core.c

406

#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)

drivers/mmc/host/sdhci-pci-core.c

746

#define INTEL_LTR_SCALE_MASK GENMASK(11, 10)

drivers/mmc/host/sdhci-pci-core.c

749

#define INTEL_LTR_VALUE_MASK GENMASK(9, 0)

drivers/mmc/host/sdhci-pci-core.c

997

#define GLK_PATH_PLL GENMASK(13, 8)

drivers/mmc/host/sdhci-pci-core.c

998

#define GLK_DLY GENMASK(6, 0)

drivers/mmc/host/sdhci-pci-gli.c

107

#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)

drivers/mmc/host/sdhci-pci-gli.c

114

#define GLI_9763E_HS400_RXDLY GENMASK(31, 28)

drivers/mmc/host/sdhci-pci-gli.c

128

#define PCI_GLI_9755_LFCLK GENMASK(14, 12)

drivers/mmc/host/sdhci-pci-gli.c

134

#define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)

drivers/mmc/host/sdhci-pci-gli.c

138

#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)

drivers/mmc/host/sdhci-pci-gli.c

139

#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)

drivers/mmc/host/sdhci-pci-gli.c

141

#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)

drivers/mmc/host/sdhci-pci-gli.c

145

#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)

drivers/mmc/host/sdhci-pci-gli.c

150

#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28)

drivers/mmc/host/sdhci-pci-gli.c

152

#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30)

drivers/mmc/host/sdhci-pci-gli.c

156

#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8)

drivers/mmc/host/sdhci-pci-gli.c

164

#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0)

drivers/mmc/host/sdhci-pci-gli.c

168

#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4)

drivers/mmc/host/sdhci-pci-gli.c

172

#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24)

drivers/mmc/host/sdhci-pci-gli.c

174

#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28)

drivers/mmc/host/sdhci-pci-gli.c

182

#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GENMASK(21, 16)

drivers/mmc/host/sdhci-pci-gli.c

185

#define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE GENMASK(23, 22)

drivers/mmc/host/sdhci-pci-gli.c

193

#define GLI_9767_VHS_REV GENMASK(19, 16)

drivers/mmc/host/sdhci-pci-gli.c

209

#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)

drivers/mmc/host/sdhci-pci-gli.c

210

#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)

drivers/mmc/host/sdhci-pci-gli.c

212

#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)

drivers/mmc/host/sdhci-pci-gli.c

229

#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29)

drivers/mmc/host/sdhci-pci-gli.c

236

#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)

drivers/mmc/host/sdhci-pci-gli.c

237

#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)

drivers/mmc/host/sdhci-pci-gli.c

240

#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)

drivers/mmc/host/sdhci-pci-gli.c

243

#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)

drivers/mmc/host/sdhci-pci-gli.c

252

#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)

drivers/mmc/host/sdhci-pci-gli.c

256

#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21)

drivers/mmc/host/sdhci-pci-gli.c

273

#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7)

drivers/mmc/host/sdhci-pci-gli.c

275

#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11)

drivers/mmc/host/sdhci-pci-gli.c

277

#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15)

drivers/mmc/host/sdhci-pci-gli.c

279

#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17)

drivers/mmc/host/sdhci-pci-gli.c

285

#define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0)

drivers/mmc/host/sdhci-pci-gli.c

30

#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)

drivers/mmc/host/sdhci-pci-gli.c

34

#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)

drivers/mmc/host/sdhci-pci-gli.c

35

#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)

drivers/mmc/host/sdhci-pci-gli.c

43

#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)

drivers/mmc/host/sdhci-pci-gli.c

44

#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)

drivers/mmc/host/sdhci-pci-gli.c

47

#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)

drivers/mmc/host/sdhci-pci-gli.c

50

#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)

drivers/mmc/host/sdhci-pci-gli.c

54

#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)

drivers/mmc/host/sdhci-pci-gli.c

57

#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)

drivers/mmc/host/sdhci-pci-gli.c

63

#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)

drivers/mmc/host/sdhci-pci-gli.c

72

#define SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT GENMASK(17, 16)

drivers/mmc/host/sdhci-pci-gli.c

79

#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)

drivers/mmc/host/sdhci-pci-gli.c

84

#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)

drivers/mmc/host/sdhci-pci-gli.c

93

#define GLI_9763E_VHS_REV GENMASK(19, 16)

drivers/mmc/host/sdhci-pci-o2micro.c

61

#define O2_SD_PHASE_MASK GENMASK(23, 20)

drivers/mmc/host/sdhci-sprd.c

26

#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)

drivers/mmc/host/sdhci-sprd.c

77

#define SDHCI_SPRD_CMD_DLY_MASK GENMASK(15, 8)

drivers/mmc/host/sdhci-sprd.c

78

#define SDHCI_SPRD_POSRD_DLY_MASK GENMASK(23, 16)

drivers/mmc/host/sdhci-sprd.c

79

#define SDHCI_SPRD_CPST_EN GENMASK(27, 24)

drivers/mmc/host/sdhci-tegra.c

1643

tegra_sdhci_writel(host, FIELD_PREP(GENMASK(15, 8), tegra_host->stream_id) |

drivers/mmc/host/sdhci-tegra.c

1644

FIELD_PREP(GENMASK(7, 0), tegra_host->stream_id),

drivers/mmc/host/sdhci-uhs2.h

117

#define SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK GENMASK(11, 8)

drivers/mmc/host/sdhci-uhs2.h

125

#define SDHCI_UHS2_PHY_N_LSS_SYN_MASK GENMASK(19, 16)

drivers/mmc/host/sdhci-uhs2.h

126

#define SDHCI_UHS2_PHY_N_LSS_DIR_MASK GENMASK(23, 20)

drivers/mmc/host/sdhci-uhs2.h

128

#define SDHCI_UHS2_TRAN_N_FCU_MASK GENMASK(15, 8)

drivers/mmc/host/sdhci-uhs2.h

129

#define SDHCI_UHS2_TRAN_RETRY_CNT_MASK GENMASK(17, 16)

drivers/mmc/host/sdhci-uhs2.h

130

#define SDHCI_UHS2_TRAN_1_N_DAT_GAP_MASK GENMASK(7, 0)

drivers/mmc/host/sdhci-uhs2.h

134

#define SDHCI_UHS2_CAPS_DAP_MASK GENMASK(3, 0)

drivers/mmc/host/sdhci-uhs2.h

135

#define SDHCI_UHS2_CAPS_GAP_MASK GENMASK(7, 4)

drivers/mmc/host/sdhci-uhs2.h

137

#define SDHCI_UHS2_CAPS_LANE_MASK GENMASK(13, 8)

drivers/mmc/host/sdhci-uhs2.h

144

#define SDHCI_UHS2_CAPS_DEV_TYPE_MASK GENMASK(17, 16)

drivers/mmc/host/sdhci-uhs2.h

148

#define SDHCI_UHS2_CAPS_NUM_DEV_MASK GENMASK(21, 18)

drivers/mmc/host/sdhci-uhs2.h

149

#define SDHCI_UHS2_CAPS_BUS_TOPO_MASK GENMASK(23, 22)

drivers/mmc/host/sdhci-uhs2.h

157

#define SDHCI_UHS2_CAPS_PHY_REV_MASK GENMASK(5, 0)

drivers/mmc/host/sdhci-uhs2.h

158

#define SDHCI_UHS2_CAPS_PHY_RANGE_MASK GENMASK(7, 6)

drivers/mmc/host/sdhci-uhs2.h

161

#define SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK GENMASK(19, 16)

drivers/mmc/host/sdhci-uhs2.h

162

#define SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK GENMASK(23, 20)

drivers/mmc/host/sdhci-uhs2.h

164

#define SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK GENMASK(5, 0)

drivers/mmc/host/sdhci-uhs2.h

165

#define SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK GENMASK(15, 8)

drivers/mmc/host/sdhci-uhs2.h

166

#define SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK GENMASK(18, 16)

drivers/mmc/host/sdhci-uhs2.h

167

#define SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK GENMASK(31, 20)

drivers/mmc/host/sdhci-uhs2.h

170

#define SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK GENMASK(7, 0)

drivers/mmc/host/sdhci-uhs2.h

44

#define SDHCI_UHS2_CMD_DORMANT GENMASK(7, 6)

drivers/mmc/host/sdhci-uhs2.h

45

#define SDHCI_UHS2_CMD_PACK_LEN_MASK GENMASK(12, 8)

drivers/mmc/host/sdhci-uhs2.h

61

#define SDHCI_UHS2_DEV_SEL_MASK GENMASK(3, 0)

drivers/mmc/host/sdhci-uhs2.h

71

#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK GENMASK(7, 4)

drivers/mmc/host/sdhci.h

252

#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)

drivers/mmc/host/sdhci.h

255

#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)

drivers/mmc/host/sdhci.h

257

#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)

drivers/mmc/host/sdhci.h

281

#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)

drivers/mmc/host/sdhci.h

283

#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)

drivers/mmc/host/sdhci.h

284

#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)

drivers/mmc/host/sdhci.h

290

#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)

drivers/mmc/host/sdhci.h

291

#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)

drivers/mmc/host/sdhci.h

292

#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)

drivers/mmc/host/sdhci.h

293

#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)

drivers/mmc/host/sdhci.h

295

#define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */

drivers/mmc/host/sdhci.h

323

#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)

drivers/mmc/host/sdhci.h

325

#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)

drivers/mmc/host/sdhci_am654.c

25

#define SLOTTYPE_MASK GENMASK(31, 30)

drivers/mmc/host/sdhci_am654.c

44

#define OTAPDLYSEL_MASK GENMASK(15, 12)

drivers/mmc/host/sdhci_am654.c

46

#define STRBSEL_4BIT_MASK GENMASK(27, 24)

drivers/mmc/host/sdhci_am654.c

47

#define STRBSEL_8BIT_MASK GENMASK(31, 24)

drivers/mmc/host/sdhci_am654.c

53

#define FREQSEL_MASK GENMASK(10, 8)

drivers/mmc/host/sdhci_am654.c

55

#define CLKBUFSEL_MASK GENMASK(2, 0)

drivers/mmc/host/sdhci_am654.c

57

#define DLL_TRIM_ICP_MASK GENMASK(7, 4)

drivers/mmc/host/sdhci_am654.c

59

#define DR_TY_MASK GENMASK(22, 20)

drivers/mmc/host/sdhci_am654.c

75

#define ITAPDLYSEL_MASK GENMASK(4, 0)

drivers/mmc/host/sunplus-mmc.c

120

#define SPMMC_CRCTOKEN_CHECK_RESULT GENMASK(6, 4)

drivers/mmc/host/sunplus-mmc.c

128

#define SPMMC_TX_DUMMY_NUM GENMASK(8, 0)

drivers/mmc/host/sunplus-mmc.c

132

#define SPMMC_SD_CLOCK_DELAY GENMASK(2, 0)

drivers/mmc/host/sunplus-mmc.c

133

#define SPMMC_SD_WRITE_DATA_DELAY GENMASK(6, 4)

drivers/mmc/host/sunplus-mmc.c

134

#define SPMMC_SD_WRITE_COMMAND_DELAY GENMASK(10, 8)

drivers/mmc/host/sunplus-mmc.c

135

#define SPMMC_SD_READ_RESPONSE_DELAY GENMASK(14, 12)

drivers/mmc/host/sunplus-mmc.c

136

#define SPMMC_SD_READ_DATA_DELAY GENMASK(18, 16)

drivers/mmc/host/sunplus-mmc.c

137

#define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20)

drivers/mmc/host/sunplus-mmc.c

34

#define SPMMC_MEDIA_TYPE GENMASK(2, 0)

drivers/mmc/host/sunplus-mmc.c

35

#define SPMMC_DMA_SOURCE GENMASK(6, 4)

drivers/mmc/host/sunplus-mmc.c

36

#define SPMMC_DMA_DESTINATION GENMASK(10, 8)

drivers/mmc/host/sunplus-mmc.c

78

#define SPMMC_SD_TRANS_MODE GENMASK(5, 4)

drivers/mmc/host/sunplus-mmc.c

88

#define SPMMC_CLOCK_DIVISION GENMASK(31, 20)

drivers/mmc/host/uniphier-sd.c

30

#define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)

drivers/mmc/host/uniphier-sd.c

35

#define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)

drivers/mmc/host/uniphier-sd.c

38

#define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)

drivers/mtd/devices/mtd_intel_dg.c

261

((to ^ (to + len_s)) & GENMASK(31, 10))) {

drivers/mtd/devices/mtd_intel_dg.c

336

((from ^ (from + len_s)) & GENMASK(31, 10))) {

drivers/mtd/devices/mtd_intel_dg.c

64

#define NVM_MAP_ADDR_MASK GENMASK(7, 0)

drivers/mtd/devices/mtd_intel_dg.c

78

#define NVM_FREG_BASE_MASK GENMASK(15, 0)

drivers/mtd/devices/mtd_intel_dg.c

79

#define NVM_FREG_ADDR_MASK GENMASK(31, 16)

drivers/mtd/nand/bbt.c

111

unsigned long val = status & GENMASK(bits_per_block - 1, 0);

drivers/mtd/nand/bbt.c

116

pos[0] &= ~GENMASK(offs + bits_per_block - 1, offs);

drivers/mtd/nand/bbt.c

122

pos[1] &= ~GENMASK(rbits - 1, 0);

drivers/mtd/nand/bbt.c

87

return status & GENMASK(bits_per_block - 1, 0);

drivers/mtd/nand/ecc-mtk.c

43

#define ECC_ERRMASK_MT7622 GENMASK(4, 0)

drivers/mtd/nand/ecc-mtk.c

44

#define ECC_ERRMASK_MT2701 GENMASK(5, 0)

drivers/mtd/nand/ecc-mtk.c

45

#define ECC_ERRMASK_MT2712 GENMASK(6, 0)

drivers/mtd/nand/ecc-mxic.c

29

#define ECC_TYP(idx) (((idx) << 3) & GENMASK(6, 3))

drivers/mtd/nand/ecc-mxic.c

59

#define META_SZ(reg) ((reg) & GENMASK(7, 0))

drivers/mtd/nand/ecc-mxic.c

60

#define PARITY_SZ(reg) (((reg) & GENMASK(15, 8)) >> 8)

drivers/mtd/nand/ecc-mxic.c

61

#define RSV_SZ(reg) (((reg) & GENMASK(23, 16)) >> 16)

drivers/mtd/nand/ecc-realtek.c

63

#define RTL_ECC_BURST_128 GENMASK(1, 0)

drivers/mtd/nand/ecc-realtek.c

70

#define RTL_ECC_CORR_COUNT GENMASK(19, 12)

drivers/mtd/nand/raw/arasan-nand-controller.c

104

#define DIFACE_SDR_MODE(x) FIELD_PREP(GENMASK(2, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

105

#define DIFACE_DDR_MODE(x) FIELD_PREP(GENMASK(5, 3), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

30

#define PKT_SIZE(x) FIELD_PREP(GENMASK(10, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

31

#define PKT_STEPS(x) FIELD_PREP(GENMASK(23, 12), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

36

#define ADDR2_STRENGTH(x) FIELD_PREP(GENMASK(27, 25), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

37

#define ADDR2_CS(x) FIELD_PREP(GENMASK(31, 30), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

40

#define CMD_1(x) FIELD_PREP(GENMASK(7, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

41

#define CMD_2(x) FIELD_PREP(GENMASK(15, 8), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

42

#define CMD_PAGE_SIZE(x) FIELD_PREP(GENMASK(25, 23), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

44

#define CMD_NADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

66

#define EVENT_MASK GENMASK(7, 0)

drivers/mtd/nand/raw/arasan-nand-controller.c

81

#define DQS_BUFF_SEL_IN(x) FIELD_PREP(GENMASK(6, 3), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

82

#define DQS_BUFF_SEL_OUT(x) FIELD_PREP(GENMASK(18, 15), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

87

#define ECC_CONF_COL(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

88

#define ECC_CONF_LEN(x) FIELD_PREP(GENMASK(26, 16), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

92

#define GET_PKT_ERR_CNT(x) FIELD_GET(GENMASK(7, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

93

#define GET_PAGE_ERR_CNT(x) FIELD_GET(GENMASK(16, 8), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

96

#define ECC_SP_CMD1(x) FIELD_PREP(GENMASK(7, 0), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

97

#define ECC_SP_CMD2(x) FIELD_PREP(GENMASK(15, 8), (x))

drivers/mtd/nand/raw/arasan-nand-controller.c

98

#define ECC_SP_ADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))

drivers/mtd/nand/raw/atmel/nand-controller.c

71

#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)

drivers/mtd/nand/raw/atmel/nand-controller.c

73

#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)

drivers/mtd/nand/raw/atmel/nand-controller.c

78

#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)

drivers/mtd/nand/raw/atmel/nand-controller.c

94

#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)

drivers/mtd/nand/raw/atmel/pmecc.c

129

#define PMERRLOC_ERR_NUM_MASK GENMASK(12, 8)

drivers/mtd/nand/raw/atmel/pmecc.c

72

#define PMECC_CFG_BCH_STRENGTH_MASK GENMASK(2, 0)

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1024

return GENMASK(7, 0);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1026

return GENMASK(6, 0);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1028

return GENMASK(5, 0);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1030

return GENMASK(4, 0);

drivers/mtd/nand/raw/brcmnand/brcmnand.c

112

#define EDU_DONE_MASK GENMASK(1, 0)

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1823

LLOP_DATA_MASK = GENMASK(15, 0),

drivers/mtd/nand/raw/brcmnand/brcmnand.c

627

INTFC_FLASH_STATUS = GENMASK(7, 0),

drivers/mtd/nand/raw/cadence-nand-controller.c

106

#define TRAN_CFG_0_OFFSET GENMASK(31, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

108

#define TRAN_CFG_0_SEC_CNT GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

116

#define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

118

#define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

123

#define ECC_CONFIG_0_CORR_STR GENMASK(10, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

150

#define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

154

#define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

157

#define CTRL_VERSION_REV GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

168

#define CTRL_FEATURES_N_BANKS GENMASK(25, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

176

#define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

177

#define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

178

#define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

179

#define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

183

#define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

184

#define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

185

#define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

186

#define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

190

#define BCH_CFG_2_SECT_0 GENMASK(15, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

191

#define BCH_CFG_2_SECT_1 GENMASK(31, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

195

#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

208

#define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

209

#define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

212

#define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

219

#define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

220

#define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

221

#define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

222

#define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

225

#define SYNC_TCKWR GENMASK(21, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

226

#define SYNC_TWRCK GENMASK(13, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

227

#define SYNC_TCAD GENMASK(5, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

230

#define TIMINGS0_TADL GENMASK(31, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

231

#define TIMINGS0_TCCS GENMASK(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

232

#define TIMINGS0_TWHR GENMASK(15, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

233

#define TIMINGS0_TRHW GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

236

#define TIMINGS1_TRHZ GENMASK(31, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

237

#define TIMINGS1_TWB GENMASK(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

238

#define TIMINGS1_TCWAW GENMASK(15, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

239

#define TIMINGS1_TVDLY GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

242

#define TIMINGS2_TFEAT GENMASK(25, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

243

#define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

244

#define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

251

#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

252

#define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

256

#define PHY_DQ_TIMING_OE_END GENMASK(2, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

257

#define PHY_DQ_TIMING_OE_START GENMASK(6, 4)

drivers/mtd/nand/raw/cadence-nand-controller.c

258

#define PHY_DQ_TIMING_TSEL_END GENMASK(11, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

259

#define PHY_DQ_TIMING_TSEL_START GENMASK(15, 12)

drivers/mtd/nand/raw/cadence-nand-controller.c

263

#define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

264

#define PHY_DQS_TIMING_DQS_SEL_OE_START GENMASK(7, 4)

drivers/mtd/nand/raw/cadence-nand-controller.c

265

#define PHY_DQS_TIMING_DQS_SEL_TSEL_END GENMASK(11, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

271

#define PHY_GATE_LPBK_CTRL_GATE_CFG GENMASK(3, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

272

#define PHY_GATE_LPBK_CTRL_GATE_CFG_CLOSE GENMASK(5, 4)

drivers/mtd/nand/raw/cadence-nand-controller.c

273

#define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19)

drivers/mtd/nand/raw/cadence-nand-controller.c

284

#define PHY_IE_TIMING_DQS_IE_START GENMASK(10, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

285

#define PHY_IE_TIMING_DQ_IE_START GENMASK(18, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

291

#define PHY_CTRL_PHONY_DQS GENMASK(9, 4)

drivers/mtd/nand/raw/cadence-nand-controller.c

351

#define CDMA_CFPTR_MEM GENMASK(26, 24)

drivers/mtd/nand/raw/cadence-nand-controller.c

379

#define CDMA_CS_MAXERR GENMASK(9, 2)

drivers/mtd/nand/raw/cadence-nand-controller.c

49

#define CMD_REG0_CT GENMASK(31, 30)

drivers/mtd/nand/raw/cadence-nand-controller.c

55

#define CMD_REG0_TN GENMASK(27, 24)

drivers/mtd/nand/raw/denali.c

1340

iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED);

drivers/mtd/nand/raw/denali.c

456

*uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);

drivers/mtd/nand/raw/denali.h

103

#define ECC_CORRECTION__VALUE GENMASK(4, 0)

drivers/mtd/nand/raw/denali.h

104

#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)

drivers/mtd/nand/raw/denali.h

107

#define READ_MODE__VALUE GENMASK(3, 0)

drivers/mtd/nand/raw/denali.h

110

#define WRITE_MODE__VALUE GENMASK(3, 0)

drivers/mtd/nand/raw/denali.h

113

#define COPYBACK_MODE__VALUE GENMASK(3, 0)

drivers/mtd/nand/raw/denali.h

116

#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)

drivers/mtd/nand/raw/denali.h

119

#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)

drivers/mtd/nand/raw/denali.h

122

#define MAX_RD_DELAY__VALUE GENMASK(3, 0)

drivers/mtd/nand/raw/denali.h

125

#define CS_SETUP_CNT__VALUE GENMASK(4, 0)

drivers/mtd/nand/raw/denali.h

126

#define CS_SETUP_CNT__TWB GENMASK(17, 12)

drivers/mtd/nand/raw/denali.h

129

#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

132

#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

135

#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)

drivers/mtd/nand/raw/denali.h

138

#define DIE_MASK__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

141

#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

147

#define RE_2_RE__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

150

#define MANUFACTURER_ID__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

153

#define DEVICE_ID__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

156

#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

159

#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

162

#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

165

#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

168

#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

171

#define REVISION__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

174

#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

177

#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

180

#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

183

#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

186

#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

190

#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

193

#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

196

#define FEATURES__N_BANKS GENMASK(1, 0)

drivers/mtd/nand/raw/denali.h

197

#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)

drivers/mtd/nand/raw/denali.h

206

#define TRANSFER_MODE__VALUE GENMASK(1, 0)

drivers/mtd/nand/raw/denali.h

235

#define ECC_THRESHOLD__VALUE GENMASK(9, 0)

drivers/mtd/nand/raw/denali.h

238

#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

24

#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

241

#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)

drivers/mtd/nand/raw/denali.h

242

#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)

drivers/mtd/nand/raw/denali.h

245

#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)

drivers/mtd/nand/raw/denali.h

246

#define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)

drivers/mtd/nand/raw/denali.h

249

#define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)

drivers/mtd/nand/raw/denali.h

250

#define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)

drivers/mtd/nand/raw/denali.h

256

#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)

drivers/mtd/nand/raw/denali.h

27

#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

283

#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

286

#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

30

#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

33

#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

55

#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)

drivers/mtd/nand/raw/denali.h

67

#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

68

#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)

drivers/mtd/nand/raw/denali.h

72

#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)

drivers/mtd/nand/raw/denali.h

73

#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)

drivers/mtd/nand/raw/denali.h

76

#define RE_2_WE__VALUE GENMASK(5, 0)

drivers/mtd/nand/raw/denali.h

79

#define ACC_CLKS__VALUE GENMASK(3, 0)

drivers/mtd/nand/raw/denali.h

82

#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)

drivers/mtd/nand/raw/denali.h

85

#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

88

#define DEVICE_WIDTH__VALUE GENMASK(1, 0)

drivers/mtd/nand/raw/denali.h

91

#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/denali.h

94

#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1469

eccbuf[0] |= GENMASK(bitoffset - 1, 0);

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1473

eccbuf[eccbytes - 1] |= GENMASK(7, bitoffset);

drivers/mtd/nand/raw/loongson-nand-controller.c

263

host->addr_cs_field = GENMASK(17, 16);

drivers/mtd/nand/raw/loongson-nand-controller.c

280

mask &= GENMASK(chip->page_shift, 0);

drivers/mtd/nand/raw/loongson-nand-controller.c

46

#define LOONGSON_NAND_MAP_CS1_SEL GENMASK(11, 8)

drivers/mtd/nand/raw/loongson-nand-controller.c

47

#define LOONGSON_NAND_MAP_RDY1_SEL GENMASK(15, 12)

drivers/mtd/nand/raw/loongson-nand-controller.c

48

#define LOONGSON_NAND_MAP_CS2_SEL GENMASK(19, 16)

drivers/mtd/nand/raw/loongson-nand-controller.c

49

#define LOONGSON_NAND_MAP_RDY2_SEL GENMASK(23, 20)

drivers/mtd/nand/raw/loongson-nand-controller.c

50

#define LOONGSON_NAND_MAP_CS3_SEL GENMASK(27, 24)

drivers/mtd/nand/raw/loongson-nand-controller.c

51

#define LOONGSON_NAND_MAP_RDY3_SEL GENMASK(31, 28)

drivers/mtd/nand/raw/loongson-nand-controller.c

63

#define LOONGSON_NAND_WAIT_CYCLE_MASK GENMASK(7, 0)

drivers/mtd/nand/raw/loongson-nand-controller.c

64

#define LOONGSON_NAND_HOLD_CYCLE_MASK GENMASK(15, 8)

drivers/mtd/nand/raw/loongson-nand-controller.c

669

host->addr_cs_field = GENMASK(15, 14);

drivers/mtd/nand/raw/loongson-nand-controller.c

67

#define LOONGSON_NAND_CELL_SIZE_MASK GENMASK(11, 8)

drivers/mtd/nand/raw/loongson-nand-controller.c

672

host->addr_cs_field = GENMASK(16, 15);

drivers/mtd/nand/raw/loongson-nand-controller.c

675

host->addr_cs_field = GENMASK(17, 16);

drivers/mtd/nand/raw/loongson-nand-controller.c

678

host->addr_cs_field = GENMASK(18, 17);

drivers/mtd/nand/raw/loongson-nand-controller.c

681

host->addr_cs_field = GENMASK(19, 18);

drivers/mtd/nand/raw/loongson-nand-controller.c

688

host->addr_cs_field = GENMASK(17, 16);

drivers/mtd/nand/raw/loongson-nand-controller.c

691

host->addr_cs_field = GENMASK(18, 17);

drivers/mtd/nand/raw/loongson-nand-controller.c

694

host->addr_cs_field = GENMASK(19, 18);

drivers/mtd/nand/raw/loongson-nand-controller.c

697

host->addr_cs_field = GENMASK(20, 19);

drivers/mtd/nand/raw/loongson-nand-controller.c

703

host->addr_cs_field = GENMASK(20, 19);

drivers/mtd/nand/raw/loongson-nand-controller.c

710

host->addr_cs_field = GENMASK(20, 19);

drivers/mtd/nand/raw/loongson-nand-controller.c

713

host->addr_cs_field = GENMASK(21, 20);

drivers/mtd/nand/raw/loongson-nand-controller.c

716

host->addr_cs_field = GENMASK(22, 21);

drivers/mtd/nand/raw/loongson-nand-controller.c

78

#define LS2K1000_NAND_DMA_MASK GENMASK(2, 0)

drivers/mtd/nand/raw/loongson-nand-controller.c

947

.status_field = GENMASK(15, 8),

drivers/mtd/nand/raw/loongson-nand-controller.c

956

.id_cycle_field = GENMASK(14, 12),

drivers/mtd/nand/raw/loongson-nand-controller.c

957

.status_field = GENMASK(23, 16),

drivers/mtd/nand/raw/loongson-nand-controller.c

958

.op_scope_field = GENMASK(29, 16),

drivers/mtd/nand/raw/loongson-nand-controller.c

967

.id_cycle_field = GENMASK(14, 12),

drivers/mtd/nand/raw/loongson-nand-controller.c

968

.status_field = GENMASK(23, 16),

drivers/mtd/nand/raw/loongson-nand-controller.c

969

.op_scope_field = GENMASK(29, 16),

drivers/mtd/nand/raw/loongson-nand-controller.c

978

.id_cycle_field = GENMASK(14, 12),

drivers/mtd/nand/raw/loongson-nand-controller.c

979

.status_field = GENMASK(23, 16),

drivers/mtd/nand/raw/loongson-nand-controller.c

980

.op_scope_field = GENMASK(29, 16),

drivers/mtd/nand/raw/marvell_nand.c

126

#define NDCR_ALL_INT GENMASK(11, 0)

drivers/mtd/nand/raw/meson_nand.c

111

#define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0))

drivers/mtd/nand/raw/meson_nand.c

112

#define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0))

drivers/mtd/nand/raw/meson_nand.c

117

#define NFC_CMD_RAW_LEN GENMASK(13, 0)

drivers/mtd/nand/raw/meson_nand.c

43

#define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))

drivers/mtd/nand/raw/mtk_nand.c

70

#define CNTR_MASK GENMASK(16, 12)

drivers/mtd/nand/raw/mtk_nand.c

82

#define STROBE_MASK GENMASK(4, 3)

drivers/mtd/nand/raw/mxc_nand.c

51

#define NFC_V1_V2_ECC_STATUS_RESULT_ERM GENMASK(3, 2)

drivers/mtd/nand/raw/mxic_nand.c

45

#define INT_STS_ALL GENMASK(31, 0)

drivers/mtd/nand/raw/nand_base.c

141

tmp = (*src >> src_off) & GENMASK(n - 1, 0);

drivers/mtd/nand/raw/nand_base.c

142

*dst &= ~GENMASK(n - 1 + dst_off, dst_off);

drivers/mtd/nand/raw/nand_micron.c

401

#define MICRON_ID_INTERNAL_ECC_MASK GENMASK(1, 0)

drivers/mtd/nand/raw/nand_samsung.c

109

(chip->id.data[4] & GENMASK(1, 0)) == 0x1)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

39

#define PSIZE_8K GENMASK(17, 16)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

40

#define PSIZE_MASK GENMASK(17, 16)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

45

#define BCH_MASK GENMASK(22, 18)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

66

#define ECC_STATUS_MASK GENMASK(1, 0)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

67

#define ECC_ERR_CNT_MASK GENMASK(4, 0)

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

84

#define PREFIX_RA_IS_EMPTY(reg) FIELD_GET(GENMASK(31, 16), (reg))

drivers/mtd/nand/raw/renesas-nand-controller.c

114

#define MEM_CTRL_CS(cs) FIELD_PREP(GENMASK(1, 0), (cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

115

#define MEM_CTRL_DIS_WP(cs) FIELD_PREP(GENMASK(11, 8), BIT((cs)))

drivers/mtd/nand/raw/renesas-nand-controller.c

118

#define DATA_SIZE(x) FIELD_PREP(GENMASK(14, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

121

#define TIMINGS_ASYN_TRWP(x) FIELD_PREP(GENMASK(3, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

122

#define TIMINGS_ASYN_TRWH(x) FIELD_PREP(GENMASK(7, 4), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

125

#define TIM_SEQ0_TCCS(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

126

#define TIM_SEQ0_TADL(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

127

#define TIM_SEQ0_TRHW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

128

#define TIM_SEQ0_TWHR(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

131

#define TIM_SEQ1_TWB(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

132

#define TIM_SEQ1_TRR(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

133

#define TIM_SEQ1_TWW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

136

#define TIM_GEN_SEQ0_D0(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

137

#define TIM_GEN_SEQ0_D1(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

138

#define TIM_GEN_SEQ0_D2(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

139

#define TIM_GEN_SEQ0_D3(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

142

#define TIM_GEN_SEQ1_D4(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

143

#define TIM_GEN_SEQ1_D5(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

144

#define TIM_GEN_SEQ1_D6(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

145

#define TIM_GEN_SEQ1_D7(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

148

#define TIM_GEN_SEQ2_D8(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

149

#define TIM_GEN_SEQ2_D9(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

150

#define TIM_GEN_SEQ2_D10(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

151

#define TIM_GEN_SEQ2_D11(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

168

#define GEN_SEQ_COL_A0(x) FIELD_PREP(GENMASK(5, 4), min((x), 2U))

drivers/mtd/nand/raw/renesas-nand-controller.c

169

#define GEN_SEQ_COL_A1(x) FIELD_PREP(GENMASK(7, 6), min((x), 2U))

drivers/mtd/nand/raw/renesas-nand-controller.c

170

#define GEN_SEQ_ROW_A0(x) FIELD_PREP(GENMASK(9, 8), min((x), 3U))

drivers/mtd/nand/raw/renesas-nand-controller.c

171

#define GEN_SEQ_ROW_A1(x) FIELD_PREP(GENMASK(11, 10), min((x), 3U))

drivers/mtd/nand/raw/renesas-nand-controller.c

173

#define GEN_SEQ_DELAY_EN(x) FIELD_PREP(GENMASK(14, 13), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

177

#define GEN_SEQ_COMMAND_3(x) FIELD_PREP(GENMASK(26, 16), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

180

#define DMA_TLVL(x) FIELD_PREP(GENMASK(7, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

184

#define TIM_GEN_SEQ3_D12(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)

drivers/mtd/nand/raw/renesas-nand-controller.c

187

#define ECC_CNT(cs, reg) FIELD_GET(GENMASK(5, 0), (reg) >> ((cs) * 8))

drivers/mtd/nand/raw/renesas-nand-controller.c

23

#define COMMAND_SEQ(x) FIELD_PREP(GENMASK(5, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

36

#define COMMAND_0(x) FIELD_PREP(GENMASK(15, 8), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

37

#define COMMAND_1(x) FIELD_PREP(GENMASK(23, 16), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

38

#define COMMAND_2(x) FIELD_PREP(GENMASK(31, 24), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

42

#define CONTROL_ECC_BLOCK_SIZE(x) FIELD_PREP(GENMASK(2, 1), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

48

#define CONTROL_BLOCK_SIZE(x) FIELD_PREP(GENMASK(7, 6), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

55

#define MEM_RDY(cs, reg) (FIELD_GET(GENMASK(3, 0), (reg)) & BIT(cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

59

#define ECC_CTRL_CAP(x) FIELD_PREP(GENMASK(2, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

66

#define ECC_CTRL_ERR_THRESHOLD(x) FIELD_PREP(GENMASK(13, 8), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

72

#define INT_MEM_RDY(cs) FIELD_PREP(GENMASK(11, 8), BIT(cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

74

#define MEM_IS_RDY(cs, reg) (FIELD_GET(GENMASK(11, 8), (reg)) & BIT(cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

78

#define ECC_OFFSET(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

81

#define ECC_STAT_CORRECTABLE(cs, reg) (FIELD_GET(GENMASK(3, 0), (reg)) & BIT(cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

82

#define ECC_STAT_UNCORRECTABLE(cs, reg) (FIELD_GET(GENMASK(11, 8), (reg)) & BIT(cs))

drivers/mtd/nand/raw/renesas-nand-controller.c

85

#define ADDR0_COL(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

88

#define ADDR0_ROW(x) FIELD_PREP(GENMASK(23, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

91

#define ADDR1_COL(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/mtd/nand/raw/renesas-nand-controller.c

94

#define ADDR1_ROW(x) FIELD_PREP(GENMASK(23, 0), (x))

drivers/mtd/nand/raw/stm32_fmc2_nand.c

100

#define FMC2_PCR_TAR GENMASK(16, 13)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

102

#define FMC2_PCR_ECCSS GENMASK(19, 17)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

112

#define FMC2_PMEM_MEMSET GENMASK(7, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

113

#define FMC2_PMEM_MEMWAIT GENMASK(15, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

114

#define FMC2_PMEM_MEMHOLD GENMASK(23, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

115

#define FMC2_PMEM_MEMHIZ GENMASK(31, 24)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

119

#define FMC2_PATT_ATTSET GENMASK(7, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

120

#define FMC2_PATT_ATTWAIT GENMASK(15, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

121

#define FMC2_PATT_ATTHOLD GENMASK(23, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

122

#define FMC2_PATT_ATTHIZ GENMASK(31, 24)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

137

#define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

138

#define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

139

#define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

147

#define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

148

#define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

153

#define FMC2_CSQCFGR3_SNBR GENMASK(13, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

164

#define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

165

#define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

166

#define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

167

#define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

170

#define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

171

#define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

172

#define FMC2_CSQCAR2_SAO GENMASK(31, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

178

#define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

181

#define FMC2_CSQEMSR_SEM GENMASK(15, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

188

#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

193

#define FMC2_BCHDSR0_DEN GENMASK(7, 4)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

196

#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

197

#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

200

#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

201

#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

204

#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

205

#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

208

#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

209

#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

93

#define FMC2_PCR_PWID GENMASK(5, 4)

drivers/mtd/nand/raw/stm32_fmc2_nand.c

98

#define FMC2_PCR_TCLR GENMASK(12, 9)

drivers/mtd/nand/raw/sunxi_nand.c

112

#define NFC_RB_STATE_MSK GENMASK(11, 8)

drivers/mtd/nand/raw/sunxi_nand.c

140

#define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)

drivers/mtd/nand/raw/sunxi_nand.c

141

#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) /* 15-10 reserved on H6 */

drivers/mtd/nand/raw/sunxi_nand.c

142

#define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8)

drivers/mtd/nand/raw/sunxi_nand.c

144

#define NFC_ADR_NUM_MSK GENMASK(18, 16)

drivers/mtd/nand/raw/sunxi_nand.c

158

#define NFC_CMD_TYPE_MSK GENMASK(31, 30)

drivers/mtd/nand/raw/sunxi_nand.c

164

#define NFC_READ_CMD_MSK GENMASK(7, 0)

drivers/mtd/nand/raw/sunxi_nand.c

165

#define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)

drivers/mtd/nand/raw/sunxi_nand.c

166

#define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)

drivers/mtd/nand/raw/sunxi_nand.c

167

#define NFC_RND_READ_CMD2_MSK GENMASK(31, 24)

drivers/mtd/nand/raw/sunxi_nand.c

170

#define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)

drivers/mtd/nand/raw/sunxi_nand.c

171

#define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)

drivers/mtd/nand/raw/sunxi_nand.c

172

#define NFC_READ_CMD0_MSK GENMASK(23, 16)

drivers/mtd/nand/raw/sunxi_nand.c

173

#define NFC_READ_CMD1_MSK GENMASK(31, 24)

drivers/mtd/nand/raw/sunxi_nand.c

188

#define NFC_RANDOM_SEED_MSK GENMASK(30, 16)

drivers/mtd/nand/raw/sunxi_nand.c

2384

.ecc_mode_mask = GENMASK(15, 12),

drivers/mtd/nand/raw/sunxi_nand.c

2385

.ecc_err_mask = GENMASK(15, 0),

drivers/mtd/nand/raw/sunxi_nand.c

2386

.pat_found_mask = GENMASK(31, 16),

drivers/mtd/nand/raw/sunxi_nand.c

2405

.ecc_mode_mask = GENMASK(15, 12),

drivers/mtd/nand/raw/sunxi_nand.c

2406

.ecc_err_mask = GENMASK(15, 0),

drivers/mtd/nand/raw/sunxi_nand.c

2407

.pat_found_mask = GENMASK(31, 16),

drivers/mtd/nand/raw/sunxi_nand.c

2427

.ecc_mode_mask = GENMASK(15, 8),

drivers/mtd/nand/raw/sunxi_nand.c

2428

.ecc_err_mask = GENMASK(31, 0),

drivers/mtd/nand/raw/sunxi_nand.c

2429

.pat_found_mask = GENMASK(31, 0),

drivers/mtd/nand/raw/sunxi_nand.c

94

#define NFC_CE_SEL_MSK GENMASK(26, 24)

drivers/mtd/nand/raw/sunxi_nand.c

97

#define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)

drivers/mtd/nand/raw/technologic-nand-controller.c

63

unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0);

drivers/mtd/nand/raw/tegra_nand.c

710

if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {

drivers/mtd/nand/raw/vf610_nfc.c

67

#define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1)

drivers/mtd/nand/spi/gigadevice.c

32

#define GD_ECCSR_LAST_PAGE(eccsr) FIELD_GET(GENMASK(3, 0), eccsr)

drivers/mtd/nand/spi/gigadevice.c

33

#define GD_ECCSR_ACCUMULATED(eccsr) FIELD_GET(GENMASK(7, 4), eccsr)

drivers/mtd/nand/spi/macronix.c

14

#define MACRONIX_ECCSR_BF_LAST_PAGE(eccsr) FIELD_GET(GENMASK(3, 0), eccsr)

drivers/mtd/nand/spi/macronix.c

15

#define MACRONIX_ECCSR_BF_ACCUMULATED_PAGES(eccsr) FIELD_GET(GENMASK(7, 4), eccsr)

drivers/mtd/nand/spi/macronix.c

24

#define CFG_BFT(x) FIELD_PREP(GENMASK(7, 4), (x))

drivers/mtd/nand/spi/micron.c

17

#define MICRON_STATUS_ECC_MASK GENMASK(6, 4)

drivers/mtd/nand/spi/xtx.c

14

#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2)

drivers/mtd/nand/spi/xtx.c

19

#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6)

drivers/mtd/parsers/sharpslpart.c

163

return (us >> 1) & GENMASK(9, 0);

drivers/mtd/spi-nor/atmel.c

11

#define ATMEL_SR_GLOBAL_PROTECT_MASK GENMASK(5, 2)

drivers/mtd/spi-nor/controllers/hisi-sfc.c

26

#define FMC_ECC_TYPE_MASK GENMASK(7, 5)

drivers/mtd/spi-nor/controllers/hisi-sfc.c

51

#define FMC_DATA_NUM_CNT(cnt) ((cnt) & GENMASK(13, 0))

drivers/mtd/spi-nor/controllers/hisi-sfc.c

61

#define FMC_DMA_LEN_SET(len) ((len) & GENMASK(27, 0))

drivers/mtd/spi-nor/sfdp.c

103

#define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)

drivers/mtd/spi-nor/sfdp.c

109

#define SMPT_MAP_ID_MASK GENMASK(15, 8)

drivers/mtd/spi-nor/sfdp.c

114

#define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)

drivers/mtd/spi-nor/sfdp.c

1173

#define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)

drivers/mtd/spi-nor/sfdp.c

1174

#define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)

drivers/mtd/spi-nor/sfdp.c

1175

#define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)

drivers/mtd/spi-nor/sfdp.c

1176

#define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)

drivers/mtd/spi-nor/sfdp.c

1177

#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)

drivers/mtd/spi-nor/sfdp.c

120

#define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)

drivers/mtd/spi-nor/sfdp.c

81

#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)

drivers/mtd/spi-nor/sfdp.c

87

#define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)

drivers/mtd/spi-nor/sfdp.c

93

#define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)

drivers/mtd/spi-nor/sfdp.c

98

#define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)

drivers/mtd/spi-nor/sfdp.h

101

#define BFPT_DWORD16_EX4B_MASK GENMASK(18, 14)

drivers/mtd/spi-nor/sfdp.h

121

#define BFPT_DWORD17_RD_1_1_8_CMD GENMASK(31, 24)

drivers/mtd/spi-nor/sfdp.h

122

#define BFPT_DWORD17_RD_1_1_8_MODE_CLOCKS GENMASK(23, 21)

drivers/mtd/spi-nor/sfdp.h

123

#define BFPT_DWORD17_RD_1_1_8_WAIT_STATES GENMASK(20, 16)

drivers/mtd/spi-nor/sfdp.h

124

#define BFPT_DWORD17_RD_1_8_8_CMD GENMASK(15, 8)

drivers/mtd/spi-nor/sfdp.h

125

#define BFPT_DWORD17_RD_1_8_8_MODE_CLOCKS GENMASK(7, 5)

drivers/mtd/spi-nor/sfdp.h

126

#define BFPT_DWORD17_RD_1_8_8_WAIT_STATES GENMASK(4, 0)

drivers/mtd/spi-nor/sfdp.h

128

#define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)

drivers/mtd/spi-nor/sfdp.h

35

#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)

drivers/mtd/spi-nor/sfdp.h

50

#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)

drivers/mtd/spi-nor/sfdp.h

85

#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)

drivers/mtd/spi-nor/sfdp.h

93

#define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24)

drivers/mtd/spi-nor/spansion.c

33

#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)

drivers/mux/mmio.c

134

if (mask != GENMASK(field.msb, field.lsb)) {

drivers/net/can/at91_can.c

101

#define AT91_MCR_MDLC_MASK GENMASK(19, 16)

drivers/net/can/at91_can.c

72

#define AT91_BR_PHASE2_MASK GENMASK(2, 0)

drivers/net/can/at91_can.c

73

#define AT91_BR_PHASE1_MASK GENMASK(6, 4)

drivers/net/can/at91_can.c

74

#define AT91_BR_PROPAG_MASK GENMASK(10, 8)

drivers/net/can/at91_can.c

75

#define AT91_BR_SJW_MASK GENMASK(13, 12)

drivers/net/can/at91_can.c

76

#define AT91_BR_BRP_MASK GENMASK(22, 16)

drivers/net/can/at91_can.c

79

#define AT91_TIM_TIMER_MASK GENMASK(15, 0)

drivers/net/can/at91_can.c

81

#define AT91_ECR_REC_MASK GENMASK(8, 0)

drivers/net/can/at91_can.c

82

#define AT91_ECR_TEC_MASK GENMASK(23, 16)

drivers/net/can/at91_can.c

86

#define AT91_MMR_MTIMEMARK_MASK GENMASK(15, 0)

drivers/net/can/at91_can.c

87

#define AT91_MMR_PRIOR_MASK GENMASK(19, 16)

drivers/net/can/at91_can.c

88

#define AT91_MMR_MOT_MASK GENMASK(26, 24)

drivers/net/can/at91_can.c

90

#define AT91_MID_MIDVB_MASK GENMASK(17, 0)

drivers/net/can/at91_can.c

91

#define AT91_MID_MIDVA_MASK GENMASK(28, 18)

drivers/net/can/at91_can.c

94

#define AT91_MSR_MTIMESTAMP_MASK GENMASK(15, 0)

drivers/net/can/at91_can.c

95

#define AT91_MSR_MDLC_MASK GENMASK(19, 16)

drivers/net/can/bxcan.c

100

#define BXCAN_TDTxR_DLC_MASK GENMASK(3, 0)

drivers/net/can/bxcan.c

103

#define BXCAN_RIxR_STID_MASK GENMASK(31, 21)

drivers/net/can/bxcan.c

104

#define BXCAN_RIxR_EXID_MASK GENMASK(31, 3)

drivers/net/can/bxcan.c

109

#define BXCAN_RDTxR_TIME_MASK GENMASK(31, 16)

drivers/net/can/bxcan.c

110

#define BXCAN_RDTxR_DLC_MASK GENMASK(3, 0)

drivers/net/can/bxcan.c

123

#define BXCAN_FMR_CANSB_MASK GENMASK(13, 8)

drivers/net/can/bxcan.c

58

#define BXCAN_RF0R_FMP0_MASK GENMASK(1, 0)

drivers/net/can/bxcan.c

77

#define BXCAN_ESR_REC_MASK GENMASK(31, 24)

drivers/net/can/bxcan.c

78

#define BXCAN_ESR_TEC_MASK GENMASK(23, 16)

drivers/net/can/bxcan.c

79

#define BXCAN_ESR_LEC_MASK GENMASK(6, 4)

drivers/net/can/bxcan.c

87

#define BXCAN_BTR_SJW_MASK GENMASK(25, 24)

drivers/net/can/bxcan.c

88

#define BXCAN_BTR_TS2_MASK GENMASK(22, 20)

drivers/net/can/bxcan.c

89

#define BXCAN_BTR_TS1_MASK GENMASK(19, 16)

drivers/net/can/bxcan.c

90

#define BXCAN_BTR_BRP_MASK GENMASK(9, 0)

drivers/net/can/bxcan.c

93

#define BXCAN_TIxR_STID_MASK GENMASK(31, 21)

drivers/net/can/bxcan.c

94

#define BXCAN_TIxR_EXID_MASK GENMASK(31, 3)

drivers/net/can/c_can/c_can_main.c

1240

priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0);

drivers/net/can/c_can/c_can_main.c

801

return pend & ~GENMASK(lasts - 1, 0);

drivers/net/can/ctucanfd/ctucanfd_kframe.h

41

#define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

47

#define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

50

#define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

51

#define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

54

#define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

57

#define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

60

#define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

61

#define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

62

#define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

63

#define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

66

#define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

67

#define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

68

#define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

69

#define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

72

#define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

73

#define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

74

#define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16)

drivers/net/can/ctucanfd/ctucanfd_kframe.h

75

#define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

100

#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

115

#define REG_MODE_RTRTH GENMASK(20, 17)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

159

#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

162

#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

165

#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

168

#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

171

#define REG_BTR_PROP GENMASK(6, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

172

#define REG_BTR_PH1 GENMASK(12, 7)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

173

#define REG_BTR_PH2 GENMASK(18, 13)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

174

#define REG_BTR_BRP GENMASK(26, 19)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

175

#define REG_BTR_SJW GENMASK(31, 27)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

178

#define REG_BTR_FD_PROP_FD GENMASK(5, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

179

#define REG_BTR_FD_PH1_FD GENMASK(11, 7)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

180

#define REG_BTR_FD_PH2_FD GENMASK(17, 13)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

181

#define REG_BTR_FD_BRP_FD GENMASK(26, 19)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

182

#define REG_BTR_FD_SJW_FD GENMASK(31, 27)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

185

#define REG_EWL_EW_LIMIT GENMASK(7, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

186

#define REG_EWL_ERP_LIMIT GENMASK(15, 8)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

192

#define REG_REC_REC_VAL GENMASK(8, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

193

#define REG_REC_TEC_VAL GENMASK(24, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

196

#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

197

#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

200

#define REG_CTR_PRES_CTPV GENMASK(8, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

207

#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

210

#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

213

#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

216

#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

219

#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

222

#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

225

#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

228

#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

253

#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

254

#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

257

#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

258

#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

264

#define REG_RX_STATUS_RXFRC GENMASK(14, 4)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

268

#define REG_RX_DATA_RX_DATA GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

271

#define REG_TX_STATUS_TX1S GENMASK(3, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

272

#define REG_TX_STATUS_TX2S GENMASK(7, 4)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

273

#define REG_TX_STATUS_TX3S GENMASK(11, 8)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

274

#define REG_TX_STATUS_TX4S GENMASK(15, 12)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

275

#define REG_TX_STATUS_TX5S GENMASK(19, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

276

#define REG_TX_STATUS_TX6S GENMASK(23, 20)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

277

#define REG_TX_STATUS_TX7S GENMASK(27, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

278

#define REG_TX_STATUS_TX8S GENMASK(31, 28)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

292

#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

295

#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

296

#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

297

#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

298

#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

299

#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

300

#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

301

#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

302

#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

305

#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

306

#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

307

#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

308

#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

309

#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

310

#define REG_ERR_CAPT_TS_BITS GENMASK(29, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

313

#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

314

#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

315

#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

318

#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

321

#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

324

#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

325

#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

341

#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

344

#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

347

#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

98

#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)

drivers/net/can/ctucanfd/ctucanfd_kregs.h

99

#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)

drivers/net/can/esd/esdacc.c

14

#define ACC_ID_ID_MASK GENMASK(28, 0)

drivers/net/can/esd/esdacc.c

18

#define ACC_DLC_DLC_MASK GENMASK(3, 0)

drivers/net/can/esd/esdacc.h

46

#define ACC_OV_REG_MODE_MASK_TIMER GENMASK(6, 4)

drivers/net/can/esd/esdacc.h

47

#define ACC_OV_REG_MODE_MASK_TS_SRC GENMASK(8, 7)

drivers/net/can/esd/esdacc.h

88

#define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0)

drivers/net/can/esd/esdacc.h

89

#define ACC_REG_BTR_CL_MASK_TSEG1 GENMASK(3, 0)

drivers/net/can/esd/esdacc.h

90

#define ACC_REG_BTR_CL_MASK_TSEG2 GENMASK(18, 16)

drivers/net/can/esd/esdacc.h

91

#define ACC_REG_BTR_CL_MASK_SJW GENMASK(25, 24)

drivers/net/can/esd/esdacc.h

94

#define ACC_REG_BRP_FD_MASK_BRP GENMASK(7, 0)

drivers/net/can/esd/esdacc.h

95

#define ACC_REG_BTR_FD_MASK_TSEG1 GENMASK(7, 0)

drivers/net/can/esd/esdacc.h

96

#define ACC_REG_BTR_FD_MASK_TSEG2 GENMASK(22, 16)

drivers/net/can/esd/esdacc.h

97

#define ACC_REG_BTR_FD_MASK_SJW GENMASK(30, 24)

drivers/net/can/flexcan/flexcan-core.c

149

#define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)

drivers/net/can/flexcan/flexcan-core.c

150

#define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)

drivers/net/can/flexcan/flexcan-core.c

151

#define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)

drivers/net/can/flexcan/flexcan-core.c

152

#define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)

drivers/net/can/flexcan/flexcan-core.c

153

#define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)

drivers/net/can/flexcan/flexcan-core.c

157

#define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)

drivers/net/can/flexcan/flexcan-core.c

158

#define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)

drivers/net/can/flexcan/flexcan-core.c

165

#define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)

drivers/net/can/flexcan/flexcan-core.c

166

#define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)

drivers/net/can/flexcan/flexcan-core.c

169

#define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)

drivers/net/can/flexcan/flexcan-core.c

170

#define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)

drivers/net/can/flexcan/flexcan-core.c

171

#define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)

drivers/net/can/flexcan/flexcan-core.c

172

#define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)

drivers/net/can/flexcan/flexcan-core.c

173

#define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

1011

iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

119

#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

125

#define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

130

#define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

132

#define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

163

#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

165

#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

168

#define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

204

#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

205

#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

206

#define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

207

#define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

210

#define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

211

#define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

225

#define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

226

#define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

227

#define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

232

#define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

240

#define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

253

#define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

254

#define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

336

.all = GENMASK(4, 0),

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

342

.all = GENMASK(19, 16) | BIT(4),

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

348

.all = GENMASK(23, 16) | BIT(4),

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

569

iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

57

#define KVASER_PCIEFD_SF2_DMA_LSB_MASK GENMASK(31, 12)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

60

#define KVASER_PCIEFD_XILINX_DMA_LSB_MASK GENMASK(31, 12)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

604

iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

619

iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

93

#define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

94

#define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

95

#define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)

drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c

96

#define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)

drivers/net/can/m_can/m_can.c

115

#define CCCR_CMR_MASK GENMASK(11, 10)

drivers/net/can/m_can/m_can.c

119

#define CCCR_CME_MASK GENMASK(9, 8)

drivers/net/can/m_can/m_can.c

135

#define NBTP_NSJW_MASK GENMASK(31, 25)

drivers/net/can/m_can/m_can.c

136

#define NBTP_NBRP_MASK GENMASK(24, 16)

drivers/net/can/m_can/m_can.c

137

#define NBTP_NTSEG1_MASK GENMASK(15, 8)

drivers/net/can/m_can/m_can.c

138

#define NBTP_NTSEG2_MASK GENMASK(6, 0)

drivers/net/can/m_can/m_can.c

141

#define TSCC_TCP_MASK GENMASK(19, 16)

drivers/net/can/m_can/m_can.c

142

#define TSCC_TSS_MASK GENMASK(1, 0)

drivers/net/can/m_can/m_can.c

148

#define TSCV_TSC_MASK GENMASK(15, 0)

drivers/net/can/m_can/m_can.c

152

#define ECR_REC_MASK GENMASK(14, 8)

drivers/net/can/m_can/m_can.c

153

#define ECR_TEC_MASK GENMASK(7, 0)

drivers/net/can/m_can/m_can.c

159

#define PSR_LEC_MASK GENMASK(2, 0)

drivers/net/can/m_can/m_can.c

160

#define PSR_DLEC_MASK GENMASK(10, 8)

drivers/net/can/m_can/m_can.c

228

#define RXFC_FWM_MASK GENMASK(30, 24)

drivers/net/can/m_can/m_can.c

229

#define RXFC_FS_MASK GENMASK(22, 16)

drivers/net/can/m_can/m_can.c

234

#define RXFS_FPI_MASK GENMASK(21, 16)

drivers/net/can/m_can/m_can.c

235

#define RXFS_FGI_MASK GENMASK(13, 8)

drivers/net/can/m_can/m_can.c

236

#define RXFS_FFL_MASK GENMASK(6, 0)

drivers/net/can/m_can/m_can.c

239

#define RXESC_RBDS_MASK GENMASK(10, 8)

drivers/net/can/m_can/m_can.c

240

#define RXESC_F1DS_MASK GENMASK(6, 4)

drivers/net/can/m_can/m_can.c

241

#define RXESC_F0DS_MASK GENMASK(2, 0)

drivers/net/can/m_can/m_can.c

245

#define TXBC_TFQS_MASK GENMASK(29, 24)

drivers/net/can/m_can/m_can.c

246

#define TXBC_NDTB_MASK GENMASK(21, 16)

drivers/net/can/m_can/m_can.c

250

#define TXFQS_TFQPI_MASK GENMASK(20, 16)

drivers/net/can/m_can/m_can.c

251

#define TXFQS_TFGI_MASK GENMASK(12, 8)

drivers/net/can/m_can/m_can.c

252

#define TXFQS_TFFL_MASK GENMASK(5, 0)

drivers/net/can/m_can/m_can.c

255

#define TXESC_TBDS_MASK GENMASK(2, 0)

drivers/net/can/m_can/m_can.c

259

#define TXEFC_EFWM_MASK GENMASK(29, 24)

drivers/net/can/m_can/m_can.c

260

#define TXEFC_EFS_MASK GENMASK(21, 16)

drivers/net/can/m_can/m_can.c

265

#define TXEFS_EFGI_MASK GENMASK(12, 8)

drivers/net/can/m_can/m_can.c

266

#define TXEFS_EFFL_MASK GENMASK(5, 0)

drivers/net/can/m_can/m_can.c

269

#define TXEFA_EFAI_MASK GENMASK(4, 0)

drivers/net/can/m_can/m_can.c

294

#define RX_BUF_RXTS_MASK GENMASK(15, 0)

drivers/net/can/m_can/m_can.c

305

#define TX_BUF_MM_MASK GENMASK(31, 24)

drivers/net/can/m_can/m_can.c

306

#define TX_BUF_DLC_MASK GENMASK(19, 16)

drivers/net/can/m_can/m_can.c

310

#define TX_EVENT_MM_MASK GENMASK(31, 24)

drivers/net/can/m_can/m_can.c

311

#define TX_EVENT_TXTS_MASK GENMASK(15, 0)

drivers/net/can/m_can/m_can.c

86

#define CREL_REL_MASK GENMASK(31, 28)

drivers/net/can/m_can/m_can.c

87

#define CREL_STEP_MASK GENMASK(27, 24)

drivers/net/can/m_can/m_can.c

88

#define CREL_SUBSTEP_MASK GENMASK(23, 20)

drivers/net/can/m_can/m_can.c

92

#define DBTP_DBRP_MASK GENMASK(20, 16)

drivers/net/can/m_can/m_can.c

93

#define DBTP_DTSEG1_MASK GENMASK(12, 8)

drivers/net/can/m_can/m_can.c

94

#define DBTP_DTSEG2_MASK GENMASK(7, 4)

drivers/net/can/m_can/m_can.c

95

#define DBTP_DSJW_MASK GENMASK(3, 0)

drivers/net/can/m_can/m_can.c

98

#define TDCR_TDCO_MASK GENMASK(14, 8)

drivers/net/can/m_can/m_can.c

99

#define TDCR_TDCF_MASK GENMASK(6, 0)

drivers/net/can/rcar/rcar_can.c

118

#define RCAR_CAN_CTLR_BOM GENMASK(12, 11) /* Bus-Off Recovery Mode Bits */

drivers/net/can/rcar/rcar_can.c

122

#define RCAR_CAN_CTLR_CANM GENMASK(9, 8) /* Operating Mode Select Bit */

drivers/net/can/rcar/rcar_can.c

128

#define RCAR_CAN_CTLR_IDFM GENMASK(2, 1) /* ID Format Mode Select Bits */

drivers/net/can/rcar/rcar_can.c

146

#define RCAR_CAN_TFCR_TFUST GENMASK(3, 1) /* Transmit FIFO Unsent Message */

drivers/net/can/rcar/rcar_can.c

155

#define RCAR_CAN_BCR_TSEG1 GENMASK(23, 20)

drivers/net/can/rcar/rcar_can.c

156

#define RCAR_CAN_BCR_BRP GENMASK(17, 8)

drivers/net/can/rcar/rcar_can.c

157

#define RCAR_CAN_BCR_SJW GENMASK(5, 4)

drivers/net/can/rcar/rcar_can.c

158

#define RCAR_CAN_BCR_TSEG2 GENMASK(2, 0)

drivers/net/can/rcar/rcar_can.c

163

#define RCAR_CAN_SID GENMASK(28, 18) /* Standard ID */

drivers/net/can/rcar/rcar_can.c

164

#define RCAR_CAN_EID GENMASK(28, 0) /* Extended ID */

drivers/net/can/rcar/rcar_canfd.c

106

#define RCANFD_CFG_SJW GENMASK(25, 24)

drivers/net/can/rcar/rcar_canfd.c

107

#define RCANFD_CFG_TSEG2 GENMASK(22, 20)

drivers/net/can/rcar/rcar_canfd.c

108

#define RCANFD_CFG_TSEG1 GENMASK(19, 16)

drivers/net/can/rcar/rcar_canfd.c

109

#define RCANFD_CFG_BRP GENMASK(9, 0)

drivers/net/can/rcar/rcar_canfd.c

112

#define RCANFD_NCFG_NBRP GENMASK(9, 0)

drivers/net/can/rcar/rcar_canfd.c

172

#define RCANFD_DCFG_DBRP GENMASK(7, 0)

drivers/net/can/rcar/rcar_canfd.c

177

#define RCANFD_FDCFG_TDCO GENMASK(23, 16)

drivers/net/can/rcar/rcar_canfd.c

182

#define RCANFD_FDSTS_SOC GENMASK(31, 24)

drivers/net/can/rcar/rcar_canfd.c

183

#define RCANFD_FDSTS_EOC GENMASK(23, 16)

drivers/net/can/rcar/rcar_canfd.c

185

#define RCANFD_GEN4_FDSTS_PNSTS GENMASK(13, 12)

drivers/net/can/rcar/rcar_canfd.c

189

#define RCANFD_FDSTS_TDCR GENMASK(7, 0)

drivers/net/can/rcar/rcar_canfd.c

78

#define RCANFD_GERFL_EEF GENMASK(23, 16)

drivers/net/can/rockchip/rockchip_canfd.h

103

#define RKCANFD_REG_BITTIMING_SJW GENMASK(15, 14)

drivers/net/can/rockchip/rockchip_canfd.h

104

#define RKCANFD_REG_BITTIMING_BRP GENMASK(13, 8)

drivers/net/can/rockchip/rockchip_canfd.h

105

#define RKCANFD_REG_BITTIMING_TSEG2 GENMASK(6, 4)

drivers/net/can/rockchip/rockchip_canfd.h

106

#define RKCANFD_REG_BITTIMING_TSEG1 GENMASK(3, 0)

drivers/net/can/rockchip/rockchip_canfd.h

109

#define RKCANFD_REG_ARBITFAIL_ARBIT_FAIL_CODE GENMASK(6, 0)

drivers/net/can/rockchip/rockchip_canfd.h

114

#define RKCANFD_REG_ERROR_CODE_TYPE GENMASK(28, 26)

drivers/net/can/rockchip/rockchip_canfd.h

121

#define RKCANFD_REG_ERROR_CODE_TX GENMASK(24, 16)

drivers/net/can/rockchip/rockchip_canfd.h

131

#define RKCANFD_REG_ERROR_CODE_RX GENMASK(15, 0)

drivers/net/can/rockchip/rockchip_canfd.h

156

#define RKCANFD_REG_RXERRORCNT_RX_ERR_CNT GENMASK(7, 0)

drivers/net/can/rockchip/rockchip_canfd.h

159

#define RKCANFD_REG_TXERRORCNT_TX_ERR_CNT GENMASK(8, 0)

drivers/net/can/rockchip/rockchip_canfd.h

162

#define RKCANFD_REG_IDCODE_STANDARD_FRAME_ID GENMASK(10, 0)

drivers/net/can/rockchip/rockchip_canfd.h

163

#define RKCANFD_REG_IDCODE_EXTENDED_FRAME_ID GENMASK(28, 0)

drivers/net/can/rockchip/rockchip_canfd.h

170

#define RKCANFD_REG_FRAMEINFO_DATA_LENGTH GENMASK(3, 0)

drivers/net/can/rockchip/rockchip_canfd.h

173

#define RKCANFD_REG_TXID_TX_ID GENMASK(28, 0)

drivers/net/can/rockchip/rockchip_canfd.h

183

#define RKCANFD_REG_RTL_VERSION_MAJOR GENMASK(7, 4)

drivers/net/can/rockchip/rockchip_canfd.h

184

#define RKCANFD_REG_RTL_VERSION_MINOR GENMASK(3, 0)

drivers/net/can/rockchip/rockchip_canfd.h

188

#define RKCANFD_REG_FD_NOMINAL_BITTIMING_SJW GENMASK(30, 24)

drivers/net/can/rockchip/rockchip_canfd.h

189

#define RKCANFD_REG_FD_NOMINAL_BITTIMING_BRP GENMASK(23, 16)

drivers/net/can/rockchip/rockchip_canfd.h

190

#define RKCANFD_REG_FD_NOMINAL_BITTIMING_TSEG2 GENMASK(14, 8)

drivers/net/can/rockchip/rockchip_canfd.h

191

#define RKCANFD_REG_FD_NOMINAL_BITTIMING_TSEG1 GENMASK(7, 0)

drivers/net/can/rockchip/rockchip_canfd.h

195

#define RKCANFD_REG_FD_DATA_BITTIMING_SJW GENMASK(20, 17)

drivers/net/can/rockchip/rockchip_canfd.h

196

#define RKCANFD_REG_FD_DATA_BITTIMING_BRP GENMASK(16, 9)

drivers/net/can/rockchip/rockchip_canfd.h

197

#define RKCANFD_REG_FD_DATA_BITTIMING_TSEG2 GENMASK(8, 5)

drivers/net/can/rockchip/rockchip_canfd.h

198

#define RKCANFD_REG_FD_DATA_BITTIMING_TSEG1 GENMASK(4, 0)

drivers/net/can/rockchip/rockchip_canfd.h

201

#define RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET GENMASK(6, 1)

drivers/net/can/rockchip/rockchip_canfd.h

206

#define RKCANFD_REG_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE GENMASK(5, 1)

drivers/net/can/rockchip/rockchip_canfd.h

212

#define RKCANFD_REG_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT GENMASK(8, 5)

drivers/net/can/rockchip/rockchip_canfd.h

213

#define RKCANFD_REG_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK GENMASK(4, 1)

drivers/net/can/rockchip/rockchip_canfd.h

217

#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT GENMASK(6, 4)

drivers/net/can/rockchip/rockchip_canfd.h

218

#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK GENMASK(3, 1)

drivers/net/can/rockchip/rockchip_canfd.h

244

#define RKCANFD_REG_FD_FRAMEINFO_DATA_LENGTH GENMASK(3, 0)

drivers/net/can/rockchip/rockchip_canfd.h

247

#define RKCANFD_REG_FD_ID_EFF GENMASK(28, 0)

drivers/net/can/rockchip/rockchip_canfd.h

248

#define RKCANFD_REG_FD_ID_SFF GENMASK(11, 0)

drivers/net/can/spi/mcp251x.c

423

GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)

drivers/net/can/spi/mcp251x.c

425

GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)

drivers/net/can/spi/mcp251x.c

62

# define BFPCTRL_BFM_MASK GENMASK(1, 0)

drivers/net/can/spi/mcp251x.c

66

# define BFPCTRL_BFE_MASK GENMASK(3, 2)

drivers/net/can/spi/mcp251x.c

70

# define BFPCTRL_BFS_MASK GENMASK(5, 4)

drivers/net/can/spi/mcp251x.c

76

# define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)

drivers/net/can/spi/mcp251x.c

81

# define TXRTSCTRL_RTS_MASK GENMASK(5, 3)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

144

#define MCP251XFD_REG_TREC_TEC_MASK GENMASK(15, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

145

#define MCP251XFD_REG_TREC_REC_MASK GENMASK(7, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

148

#define MCP251XFD_REG_BDIAG0_DTERRCNT_MASK GENMASK(31, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

149

#define MCP251XFD_REG_BDIAG0_DRERRCNT_MASK GENMASK(23, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

150

#define MCP251XFD_REG_BDIAG0_NTERRCNT_MASK GENMASK(15, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

151

#define MCP251XFD_REG_BDIAG0_NRERRCNT_MASK GENMASK(7, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

176

#define MCP251XFD_REG_BDIAG1_EFMSGCNT_MASK GENMASK(15, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

179

#define MCP251XFD_REG_TEFCON_FSIZE_MASK GENMASK(28, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

197

#define MCP251XFD_REG_TXQCON_PLSIZE_MASK GENMASK(31, 29)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

206

#define MCP251XFD_REG_TXQCON_FSIZE_MASK GENMASK(28, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

210

#define MCP251XFD_REG_TXQCON_TXAT_MASK GENMASK(22, 21)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

211

#define MCP251XFD_REG_TXQCON_TXPRI_MASK GENMASK(20, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

221

#define MCP251XFD_REG_TXQSTA_TXQCI_MASK GENMASK(12, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

232

#define MCP251XFD_REG_FIFOCON_PLSIZE_MASK GENMASK(31, 29)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

241

#define MCP251XFD_REG_FIFOCON_FSIZE_MASK GENMASK(28, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

242

#define MCP251XFD_REG_FIFOCON_TXAT_MASK GENMASK(22, 21)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

246

#define MCP251XFD_REG_FIFOCON_TXPRI_MASK GENMASK(20, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

260

#define MCP251XFD_REG_FIFOSTA_FIFOCI_MASK GENMASK(12, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

274

#define MCP251XFD_REG_FLTCON_F3BP_MASK GENMASK(28, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

276

#define MCP251XFD_REG_FLTCON_F2BP_MASK GENMASK(20, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

278

#define MCP251XFD_REG_FLTCON_F1BP_MASK GENMASK(12, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

280

#define MCP251XFD_REG_FLTCON_F0BP_MASK GENMASK(4, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

282

#define MCP251XFD_REG_FLTCON_FLT_MASK(x) (GENMASK(7, 0) << (8 * ((x) & 0x3)))

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

288

#define MCP251XFD_REG_FLTOBJ_EID_MASK GENMASK(28, 11)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

289

#define MCP251XFD_REG_FLTOBJ_SID_MASK GENMASK(10, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

294

#define MCP251XFD_REG_MASK_MEID_MASK GENMASK(28, 11)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

295

#define MCP251XFD_REG_MASK_MSID_MASK GENMASK(10, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

303

#define MCP251XFD_OBJ_ID_EID_MASK GENMASK(28, 11)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

304

#define MCP251XFD_OBJ_ID_SID_MASK GENMASK(10, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

305

#define MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK GENMASK(31, 9)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

306

#define MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK GENMASK(15, 9)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

31

#define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

313

#define MCP251XFD_OBJ_FLAGS_DLC_MASK GENMASK(3, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

315

#define MCP251XFD_REG_FRAME_EFF_SID_MASK GENMASK(28, 18)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

316

#define MCP251XFD_REG_FRAME_EFF_EID_MASK GENMASK(17, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

327

#define MCP251XFD_REG_OSC_CLKODIV_MASK GENMASK(6, 5)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

33

#define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

343

#define MCP251XFD_REG_IOCON_GPIO_MASK GENMASK(17, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

347

#define MCP251XFD_REG_IOCON_LAT_MASK GENMASK(9, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

358

#define MCP251XFD_REG_CRC_IF_MASK GENMASK(17, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

359

#define MCP251XFD_REG_CRC_MASK GENMASK(15, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

362

#define MCP251XFD_REG_ECCCON_PARITY_MASK GENMASK(14, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

368

#define MCP251XFD_REG_ECCSTAT_ERRADDR_MASK GENMASK(27, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

369

#define MCP251XFD_REG_ECCSTAT_IF_MASK GENMASK(2, 1)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

374

#define MCP251XFD_REG_DEVID_ID_MASK GENMASK(7, 4)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

375

#define MCP251XFD_REG_DEVID_REV_MASK GENMASK(3, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

384

#define MCP251XFD_SPI_ADDRESS_MASK GENMASK(11, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

42

#define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

50

#define MCP251XFD_REG_CON_WFT_MASK GENMASK(10, 9)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

58

#define MCP251XFD_REG_CON_DNCNT_MASK GENMASK(4, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

61

#define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

62

#define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

63

#define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

64

#define MCP251XFD_REG_NBTCFG_SJW_MASK GENMASK(6, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

67

#define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

68

#define MCP251XFD_REG_DBTCFG_TSEG1_MASK GENMASK(20, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

69

#define MCP251XFD_REG_DBTCFG_TSEG2_MASK GENMASK(11, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

70

#define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

75

#define MCP251XFD_REG_TDC_TDCMOD_MASK GENMASK(17, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

79

#define MCP251XFD_REG_TDC_TDCO_MASK GENMASK(14, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

80

#define MCP251XFD_REG_TDC_TDCV_MASK GENMASK(5, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

88

#define MCP251XFD_REG_TSCON_TBCPRE_MASK GENMASK(9, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

91

#define MCP251XFD_REG_VEC_RXCODE_MASK GENMASK(30, 24)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

92

#define MCP251XFD_REG_VEC_TXCODE_MASK GENMASK(22, 16)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

93

#define MCP251XFD_REG_VEC_FILHIT_MASK GENMASK(12, 8)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

94

#define MCP251XFD_REG_VEC_ICODE_MASK GENMASK(6, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

97

#define MCP251XFD_REG_INT_IF_MASK GENMASK(15, 0)

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

98

#define MCP251XFD_REG_INT_IE_MASK GENMASK(31, 16)

drivers/net/can/usb/esd_usb.c

57

#define ESD_USB_IDMASK GENMASK(28, 0)

drivers/net/can/usb/esd_usb.c

65

#define ESD_USB_NO_BAUDRATE GENMASK(30, 0) /* bit rate unconfigured */

drivers/net/can/usb/esd_usb.c

748

msg->filter.mask[i] = cpu_to_le32(GENMASK(31, 0));

drivers/net/can/usb/esd_usb.c

82

#define ESD_USB_SJA1000_ECC_SEG GENMASK(4, 0)

drivers/net/can/usb/esd_usb.c

88

#define ESD_USB_SJA1000_ECC_MASK GENMASK(7, 6)

drivers/net/can/usb/esd_usb.c

91

#define ESD_USB_BUSSTATE_MASK GENMASK(7, 6)

drivers/net/can/usb/esd_usb.c

94

#define ESD_USB_BUSSTATE_BUSOFF GENMASK(7, 6)

drivers/net/can/usb/etas_es58x/es58x_fd.c

72

const u32 mask = GENMASK(BITS_PER_TYPE(mask) - 1,

drivers/net/can/usb/f81604.c

32

#define F81604_DLC_LEN_MASK GENMASK(3, 0)

drivers/net/can/usb/f81604.c

39

#define F81604_BRP_MASK GENMASK(5, 0)

drivers/net/can/usb/f81604.c

40

#define F81604_SJW_MASK GENMASK(7, 6)

drivers/net/can/usb/f81604.c

42

#define F81604_SEG1_MASK GENMASK(3, 0)

drivers/net/can/usb/f81604.c

43

#define F81604_SEG2_MASK GENMASK(6, 4)

drivers/net/can/usb/gs_usb.c

187

#define GS_CAN_FEATURE_MASK GENMASK(13, 0)

drivers/net/can/usb/kvaser_usb/kvaser_usb.h

51

#define KVASER_USB_SW_VERSION_MAJOR_MASK GENMASK(31, 24)

drivers/net/can/usb/kvaser_usb/kvaser_usb.h

52

#define KVASER_USB_SW_VERSION_MINOR_MASK GENMASK(23, 16)

drivers/net/can/usb/kvaser_usb/kvaser_usb.h

53

#define KVASER_USB_SW_VERSION_BUILD_MASK GENMASK(15, 0)

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c

229

#define KVASER_USB_HYDRA_LED_IDX_MASK GENMASK(31, 1)

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c

350

GENMASK(KVASER_USB_KCAN_DATA_DLC_BITS - 1 + \

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c

459

GENMASK(KVASER_USB_HYDRA_TRANSID_BITS - 1, 0)

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c

460

#define KVASER_USB_HYDRA_HE_ADDR_SRC_MASK GENMASK(7, 6)

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c

461

#define KVASER_USB_HYDRA_HE_ADDR_DEST_MASK GENMASK(5, 0)

drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c

126

#define KVASER_USB_USBCAN_CLK_OVERFLOW_MASK GENMASK(31, 16)

drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c

185

#define KVASER_USB_LEAF_LED_IDX_MASK GENMASK(31, 1)

drivers/net/can/usb/nct6694_canfd.c

35

#define NCT6694_CANFD_SETTING_NBTP_NTSEG2 GENMASK(6, 0)

drivers/net/can/usb/nct6694_canfd.c

36

#define NCT6694_CANFD_SETTING_NBTP_NTSEG1 GENMASK(15, 8)

drivers/net/can/usb/nct6694_canfd.c

37

#define NCT6694_CANFD_SETTING_NBTP_NBRP GENMASK(24, 16)

drivers/net/can/usb/nct6694_canfd.c

38

#define NCT6694_CANFD_SETTING_NBTP_NSJW GENMASK(31, 25)

drivers/net/can/usb/nct6694_canfd.c

39

#define NCT6694_CANFD_SETTING_DBTP_DSJW GENMASK(3, 0)

drivers/net/can/usb/nct6694_canfd.c

40

#define NCT6694_CANFD_SETTING_DBTP_DTSEG2 GENMASK(7, 4)

drivers/net/can/usb/nct6694_canfd.c

41

#define NCT6694_CANFD_SETTING_DBTP_DTSEG1 GENMASK(12, 8)

drivers/net/can/usb/nct6694_canfd.c

42

#define NCT6694_CANFD_SETTING_DBTP_DBRP GENMASK(20, 16)

drivers/net/can/usb/nct6694_canfd.c

54

#define NCT6694_CANFD_EVENT_MASK GENMASK(5, 0)

drivers/net/can/xilinx_can.c

101

#define XCAN_BRPR_TDCO_MASK GENMASK(12, 8) /* TDCO */

drivers/net/can/xilinx_can.c

102

#define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */

drivers/net/can/xilinx_can.c

116

#define XCAN_SR_TDCV_MASK GENMASK(22, 16) /* TDCV Value */

drivers/net/can/xilinx_can.c

163

#define XCAN_ECC_1BIT_CNT_MASK GENMASK(15, 0) /* FIFO ECC 1bit count mask */

drivers/net/can/xilinx_can.c

164

#define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mask */

drivers/net/dsa/b53/b53_mmap.c

56

.ephy_port_mask = GENMASK((ARRAY_SIZE(bcm6318_ephy_offsets) - 1), 0),

drivers/net/dsa/b53/b53_mmap.c

65

.ephy_port_mask = GENMASK((ARRAY_SIZE(bcm6368_ephy_offsets) - 1), 0),

drivers/net/dsa/b53/b53_mmap.c

74

.ephy_enable_mask = GENMASK(4, 0),

drivers/net/dsa/b53/b53_mmap.c

75

.ephy_port_mask = GENMASK((ARRAY_SIZE(bcm63268_ephy_offsets) - 1), 0),

drivers/net/dsa/b53/b53_regs.h

348

#define ARLTBL_DATA_PORT_ID_MASK_89 GENMASK(8, 0)

drivers/net/dsa/b53/b53_regs.h

349

#define ARLTBL_TC_MASK_89 GENMASK(12, 10)

drivers/net/dsa/b53/b53_regs.h

373

#define ARL_ADDR_MASK GENMASK(14, 0)

drivers/net/dsa/b53/b53_regs.h

402

#define ARL_SRST_PORT_ID_MASK_63XX GENMASK(9, 1)

drivers/net/dsa/b53/b53_regs.h

403

#define ARL_SRST_TC_MASK_63XX GENMASK(13, 11)

drivers/net/dsa/bcm_sf2_cfp.c

133

return GENMASK(num_udf - 1, 0) >> (UDFS_PER_SLICE - 1);

drivers/net/dsa/bcm_sf2_cfp.c

138

return (u8)GENMASK(num_udf - 1, 0);

drivers/net/dsa/hirschmann/hellcreek.h

104

#define HR_FDBMDRD_PORTMASK_MASK GENMASK(3, 0)

drivers/net/dsa/hirschmann/hellcreek.h

106

#define HR_FDBMDRD_AGE_MASK GENMASK(7, 4)

drivers/net/dsa/hirschmann/hellcreek.h

111

#define HR_FDBMDRD_REPRIO_TC_MASK GENMASK(14, 12)

drivers/net/dsa/hirschmann/hellcreek.h

119

#define HR_FDBWRM0_PORTMASK_MASK GENMASK(3, 0)

drivers/net/dsa/hirschmann/hellcreek.h

123

#define HR_FDBWRM0_REPRIO_TC_MASK GENMASK(14, 12)

drivers/net/dsa/hirschmann/hellcreek.h

133

#define HR_SWCFG_LAS_MODE_MASK GENMASK(13, 12)

drivers/net/dsa/hirschmann/hellcreek.h

152

#define HR_VIDCFG_VID_MASK GENMASK(11, 0)

drivers/net/dsa/hirschmann/hellcreek.h

157

#define HR_VIDMBRCFG_P0MBR_MASK GENMASK(1, 0)

drivers/net/dsa/hirschmann/hellcreek.h

159

#define HR_VIDMBRCFG_P1MBR_MASK GENMASK(3, 2)

drivers/net/dsa/hirschmann/hellcreek.h

161

#define HR_VIDMBRCFG_P2MBR_MASK GENMASK(5, 4)

drivers/net/dsa/hirschmann/hellcreek.h

163

#define HR_VIDMBRCFG_P3MBR_MASK GENMASK(7, 6)

drivers/net/dsa/hirschmann/hellcreek.h

167

#define HR_FEABITS0_FDBBINS_MASK GENMASK(7, 4)

drivers/net/dsa/hirschmann/hellcreek.h

169

#define HR_FEABITS0_PCNT_MASK GENMASK(11, 8)

drivers/net/dsa/hirschmann/hellcreek.h

171

#define HR_FEABITS0_MCNT_MASK GENMASK(15, 12)

drivers/net/dsa/hirschmann/hellcreek.h

175

#define TR_TGDVER_REV_MIN_MASK GENMASK(7, 0)

drivers/net/dsa/hirschmann/hellcreek.h

177

#define TR_TGDVER_REV_MAJ_MASK GENMASK(15, 8)

drivers/net/dsa/hirschmann/hellcreek.h

180

#define TR_TGDSEL_TDGSEL_MASK GENMASK(1, 0)

drivers/net/dsa/hirschmann/hellcreek.h

186

#define TR_TGDCTRL_ADMINGATESTATES_MASK GENMASK(15, 8)

drivers/net/dsa/hirschmann/hellcreek.h

193

#define TR_ESTCMD_ESTSEC_MASK GENMASK(2, 0)

drivers/net/dsa/hirschmann/hellcreek.h

209

#define TR_GCLDAT_GCLWRGATES_MASK GENMASK(7, 0)

drivers/net/dsa/hirschmann/hellcreek.h

216

#define TR_GCLCMD_GCLWRADR_MASK GENMASK(7, 0)

drivers/net/dsa/hirschmann/hellcreek.h

218

#define TR_GCLCMD_INIT_GATE_STATES_MASK GENMASK(15, 8)

drivers/net/dsa/hirschmann/hellcreek.h

57

#define HR_PSEL_PTWSEL_MASK GENMASK(5, 4)

drivers/net/dsa/hirschmann/hellcreek.h

59

#define HR_PSEL_PRTCWSEL_MASK GENMASK(2, 0)

drivers/net/dsa/hirschmann/hellcreek.h

68

#define HR_PTCFG_PPRIO_MASK GENMASK(6, 4)

drivers/net/dsa/hirschmann/hellcreek.h

76

#define HR_PRTCCFG_PCP_TC_MAP_MASK GENMASK(2, 0)

drivers/net/dsa/hirschmann/hellcreek.h

82

#define HR_PTPRTCCFG_MAXSDU_MASK GENMASK(10, 0)

drivers/net/dsa/hirschmann/hellcreek.h

86

#define HR_CSEL_MASK GENMASK(7, 0)

drivers/net/dsa/hirschmann/hellcreek_ptp.h

37

#define PR_SETTINGS_C_TS_SRC_TK_MASK GENMASK(9, 8)

drivers/net/dsa/lan9303-core.c

1415

chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1, 0);

drivers/net/dsa/lantiq/lantiq_gswip.h

116

#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)

drivers/net/dsa/lantiq/lantiq_gswip.h

138

#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)

drivers/net/dsa/lantiq/lantiq_gswip.h

139

#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)

drivers/net/dsa/lantiq/lantiq_gswip.h

144

#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)

drivers/net/dsa/lantiq/lantiq_gswip.h

164

#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)

drivers/net/dsa/lantiq/lantiq_gswip.h

170

#define GSWIP_PCE_VCTRL_VINR GENMASK(2, 1) /* VLAN Ingress Tag Rule */

drivers/net/dsa/lantiq/lantiq_gswip.h

203

#define GSWIP_MAC_CTRL_4_GWAIT_MASK GENMASK(14, 8) /* LPI Wait Time 1G */

drivers/net/dsa/lantiq/lantiq_gswip.h

205

#define GSWIP_MAC_CTRL_4_WAIT_MASK GENMASK(6, 0) /* LPI Wait Time 100M */

drivers/net/dsa/lantiq/lantiq_gswip.h

212

#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */

drivers/net/dsa/lantiq/lantiq_gswip.h

228

#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */

drivers/net/dsa/lantiq/lantiq_gswip.h

229

#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */

drivers/net/dsa/lantiq/lantiq_gswip.h

83

#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)

drivers/net/dsa/lantiq/lantiq_gswip.h

84

#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)

drivers/net/dsa/lantiq/lantiq_gswip.h

95

#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)

drivers/net/dsa/lantiq/lantiq_gswip.h

96

#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)

drivers/net/dsa/lantiq/mxl-gsw1xx.c

414

FIELD_GET(GENMASK(15, 8), txaneg));

drivers/net/dsa/lantiq/mxl-gsw1xx.c

418

FIELD_GET(GENMASK(7, 0), txaneg));

drivers/net/dsa/lantiq/mxl-gsw1xx.c

53

smdio_badr = reg & ~GENMASK(3, 0);

drivers/net/dsa/lantiq/mxl-gsw1xx.h

114

#define GSW1XX_SHELL_MANU_ID_PNUML GENMASK(15, 12)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

115

#define GSW1XX_SHELL_MANU_ID_MANID GENMASK(11, 1)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

119

#define GSW1XX_SHELL_PNUM_ID_VER GENMASK(15, 12)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

120

#define GSW1XX_SHELL_PNUM_ID_PNUMM GENMASK(11, 0)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

132

#define GSW1XX_SGMII_HSP_MASK GENMASK(3, 2)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

34

#define GSW1XX_SGMII_TBI_ANEGCTL_LT GENMASK(1, 0)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

43

#define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE GENMASK(7, 6)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

61

#define GSW1XX_SGMII_TBI_LPSTAT_SPEED GENMASK(6, 5)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

79

#define GSW1XX_SGMII_PHY_RX0_CFG2_EQ GENMASK(2, 0)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

84

#define GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT GENMASK(12, 6)

drivers/net/dsa/lantiq/mxl-gsw1xx.h

89

#define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL GENMASK(11, 9)

drivers/net/dsa/microchip/ksz8_reg.h

233

#define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5)

drivers/net/dsa/microchip/ksz8_reg.h

713

#define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13)

drivers/net/dsa/microchip/ksz8_reg.h

720

#define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0)

drivers/net/dsa/microchip/ksz9477_acl.c

102

#define KSZ9477_ACL_PM_M GENMASK(7, 6)

drivers/net/dsa/microchip/ksz9477_acl.c

107

#define KSZ9477_ACL_P_M GENMASK(5, 3)

drivers/net/dsa/microchip/ksz9477_acl.c

114

#define KSZ9477_ACL_INDEX_M GENMASK(3, 0)

drivers/net/dsa/microchip/ksz9477_acl.c

75

#define KSZ9477_ACL_MD_MASK GENMASK(5, 4)

drivers/net/dsa/microchip/ksz9477_acl.c

81

#define KSZ9477_ACL_ENB_MASK GENMASK(3, 2)

drivers/net/dsa/microchip/ksz9477_reg.h

1158

#define PMAVBC_MASK GENMASK(26, 16)

drivers/net/dsa/microchip/ksz9477_reg.h

152

#define REG_SW_MTU_MASK GENMASK(13, 0)

drivers/net/dsa/microchip/ksz9477_reg.h

167

#define SW_AGE_CNT_M GENMASK(5, 3)

drivers/net/dsa/microchip/ksz9477_reg.h

202

#define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)

drivers/net/dsa/microchip/ksz9477_reg.h

819

#define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0)

drivers/net/dsa/microchip/ksz9477_reg.h

831

#define PORT_INTF_SPEED_MASK GENMASK(4, 3)

drivers/net/dsa/microchip/ksz9477_reg.h

832

#define PORT_INTF_SPEED_NONE GENMASK(1, 0)

drivers/net/dsa/microchip/ksz_common.c

585

[VLAN_TABLE_FID] = GENMASK(15, 12),

drivers/net/dsa/microchip/ksz_common.c

586

[VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),

drivers/net/dsa/microchip/ksz_common.c

590

[STATIC_MAC_TABLE_FID] = GENMASK(25, 22),

drivers/net/dsa/microchip/ksz_common.c

592

[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),

drivers/net/dsa/microchip/ksz_common.c

593

[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),

drivers/net/dsa/microchip/ksz_common.c

596

[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),

drivers/net/dsa/microchip/ksz_common.c

597

[DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),

drivers/net/dsa/microchip/ksz_common.c

598

[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),

drivers/net/dsa/microchip/ksz_common.c

599

[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),

drivers/net/dsa/microchip/ksz_common.c

645

[VLAN_TABLE_FID] = GENMASK(6, 0),

drivers/net/dsa/microchip/ksz_common.c

646

[VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),

drivers/net/dsa/microchip/ksz_common.c

650

[STATIC_MAC_TABLE_FID] = GENMASK(30, 24),

drivers/net/dsa/microchip/ksz_common.c

652

[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),

drivers/net/dsa/microchip/ksz_common.c

653

[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),

drivers/net/dsa/microchip/ksz_common.c

656

[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),

drivers/net/dsa/microchip/ksz_common.c

657

[DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),

drivers/net/dsa/microchip/ksz_common.c

658

[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),

drivers/net/dsa/microchip/ksz_common.c

659

[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),

drivers/net/dsa/microchip/ksz_common.c

718

[VLAN_TABLE_FID] = GENMASK(15, 12),

drivers/net/dsa/microchip/ksz_common.c

719

[VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),

drivers/net/dsa/microchip/ksz_common.c

723

[STATIC_MAC_TABLE_FID] = GENMASK(25, 22),

drivers/net/dsa/microchip/ksz_common.c

725

[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),

drivers/net/dsa/microchip/ksz_common.c

726

[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),

drivers/net/dsa/microchip/ksz_common.c

729

[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),

drivers/net/dsa/microchip/ksz_common.c

730

[DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),

drivers/net/dsa/microchip/ksz_common.c

731

[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),

drivers/net/dsa/microchip/ksz_common.c

732

[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),

drivers/net/dsa/microchip/ksz_common.c

772

[VLAN_TABLE_FID] = GENMASK(6, 0),

drivers/net/dsa/microchip/ksz_common.c

773

[VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),

drivers/net/dsa/microchip/ksz_common.c

777

[STATIC_MAC_TABLE_FID] = GENMASK(30, 24),

drivers/net/dsa/microchip/ksz_common.c

779

[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),

drivers/net/dsa/microchip/ksz_common.c

780

[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),

drivers/net/dsa/microchip/ksz_common.c

783

[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),

drivers/net/dsa/microchip/ksz_common.c

784

[DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),

drivers/net/dsa/microchip/ksz_common.c

785

[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),

drivers/net/dsa/microchip/ksz_common.c

786

[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),

drivers/net/dsa/microchip/ksz_common.h

779

#define SW_FAMILY_ID_M GENMASK(15, 8)

drivers/net/dsa/microchip/ksz_common.h

788

#define SW_CHIP_ID_M GENMASK(7, 4)

drivers/net/dsa/microchip/ksz_common.h

799

#define SW_REV_ID_M GENMASK(7, 4)

drivers/net/dsa/microchip/ksz_common.h

908

#define MTI_SCHEDULE_MODE_M GENMASK(7, 6)

drivers/net/dsa/microchip/ksz_common.h

911

#define MTI_SHAPING_M GENMASK(5, 4)

drivers/net/dsa/microchip/ksz_dcb.c

128

*mask = GENMASK(1, 0);

drivers/net/dsa/microchip/ksz_dcb.c

132

*mask = GENMASK(1, 0);

drivers/net/dsa/microchip/ksz_dcb.c

138

*mask = GENMASK(2, 0);

drivers/net/dsa/microchip/ksz_dcb.c

22

#define KSZ8_PORT_BASED_PRIO_M GENMASK(4, 3)

drivers/net/dsa/microchip/ksz_dcb.c

30

#define KSZ9477_SW_TOS_DSCP_DEFAULT_PRIO_M GENMASK(5, 3)

drivers/net/dsa/microchip/ksz_dcb.c

44

#define KSZ9477_PORT_BASED_PRIO_M GENMASK(2, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

102

#define TRIG_CYCLE_WIDTH_M GENMASK(31, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

106

#define TRIG_CYCLE_CNT_M GENMASK(31, 16)

drivers/net/dsa/microchip/ksz_ptp_reg.h

107

#define TRIG_BIT_PATTERN_M GENMASK(15, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

113

#define TRIG_PULSE_WIDTH_M GENMASK(23, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

54

#define PTP_GPIO_INDEX GENMASK(19, 16)

drivers/net/dsa/microchip/ksz_ptp_reg.h

56

#define PTP_TOU_INDEX GENMASK(1, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

60

#define TRIG_ERROR_M GENMASK(18, 16)

drivers/net/dsa/microchip/ksz_ptp_reg.h

61

#define TRIG_DONE_M GENMASK(2, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

65

#define TRIG_INT_M GENMASK(18, 16)

drivers/net/dsa/microchip/ksz_ptp_reg.h

66

#define TS_INT_M GENMASK(1, 0)

drivers/net/dsa/microchip/ksz_ptp_reg.h

86

#define TRIG_CASCADE_UPS_M GENMASK(29, 26)

drivers/net/dsa/microchip/ksz_ptp_reg.h

90

#define TRIG_PATTERN_M GENMASK(22, 20)

drivers/net/dsa/microchip/ksz_ptp_reg.h

98

#define TRIG_GPO_M GENMASK(19, 16)

drivers/net/dsa/microchip/ksz_ptp_reg.h

99

#define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0)

drivers/net/dsa/microchip/lan937x_reg.h

173

#define PORT_TUNE_ADJ GENMASK(13, 7)

drivers/net/dsa/microchip/lan937x_reg.h

59

#define SW_AGE_CNT_M GENMASK(5, 3)

drivers/net/dsa/microchip/lan937x_reg.h

77

#define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)

drivers/net/dsa/microchip/lan937x_reg.h

80

#define SW_AGE_PERIOD_19_8_M GENMASK(19, 8)

drivers/net/dsa/mt7530.h

103

#define PAE_EG_TAG_MASK GENMASK(24, 22)

drivers/net/dsa/mt7530.h

105

#define PAE_PORT_FW_MASK GENMASK(18, 16)

drivers/net/dsa/mt7530.h

107

#define BPDU_EG_TAG_MASK GENMASK(8, 6)

drivers/net/dsa/mt7530.h

109

#define BPDU_PORT_FW_MASK GENMASK(2, 0)

drivers/net/dsa/mt7530.h

114

#define R02_EG_TAG_MASK GENMASK(24, 22)

drivers/net/dsa/mt7530.h

116

#define R02_PORT_FW_MASK GENMASK(18, 16)

drivers/net/dsa/mt7530.h

119

#define R01_EG_TAG_MASK GENMASK(8, 6)

drivers/net/dsa/mt7530.h

121

#define R01_PORT_FW_MASK GENMASK(2, 0)

drivers/net/dsa/mt7530.h

126

#define R0E_EG_TAG_MASK GENMASK(24, 22)

drivers/net/dsa/mt7530.h

128

#define R0E_PORT_FW_MASK GENMASK(18, 16)

drivers/net/dsa/mt7530.h

131

#define R03_EG_TAG_MASK GENMASK(8, 6)

drivers/net/dsa/mt7530.h

133

#define R03_PORT_FW_MASK GENMASK(2, 0)

drivers/net/dsa/mt7530.h

248

#define AGE_CNT_MASK GENMASK(19, 12)

drivers/net/dsa/mt7530.h

252

#define AGE_UNIT_MASK GENMASK(11, 0)

drivers/net/dsa/mt7530.h

257

#define ERLCR_CIR_MASK GENMASK(31, 16)

drivers/net/dsa/mt7530.h

259

#define ERLCR_EXP_MASK GENMASK(11, 8)

drivers/net/dsa/mt7530.h

261

#define ERLCR_MANT_MASK GENMASK(6, 0)

drivers/net/dsa/mt7530.h

264

#define EGR_BC_MASK GENMASK(7, 0)

drivers/net/dsa/mt7530.h

321

#define ACC_FRM_MASK GENMASK(1, 0)

drivers/net/dsa/mt7530.h

350

#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)

drivers/net/dsa/mt7530.h

395

#define WAKEUP_TIME_1000_MASK GENMASK(31, 24)

drivers/net/dsa/mt7530.h

397

#define WAKEUP_TIME_100_MASK GENMASK(23, 16)

drivers/net/dsa/mt7530.h

399

#define LPI_THRESH_MASK GENMASK(15, 4)

drivers/net/dsa/mt7530.h

422

#define MAX_RX_JUMBO_MASK GENMASK(5, 2)

drivers/net/dsa/mt7530.h

423

#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)

drivers/net/dsa/mt7530.h

43

#define BC_FFP_MASK GENMASK(31, 24)

drivers/net/dsa/mt7530.h

45

#define UNM_FFP_MASK GENMASK(23, 16)

drivers/net/dsa/mt7530.h

47

#define UNU_FFP_MASK GENMASK(15, 8)

drivers/net/dsa/mt7530.h

50

#define MT7530_CPU_PORT_MASK GENMASK(6, 4)

drivers/net/dsa/mt7530.h

53

#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)

drivers/net/dsa/mt7530.h

546

#define CLK_SKEW_OUT_MASK GENMASK(9, 8)

drivers/net/dsa/mt7530.h

548

#define CLK_SKEW_IN_MASK GENMASK(7, 6)

drivers/net/dsa/mt7530.h

552

#define GP_MODE_MASK GENMASK(2, 1)

drivers/net/dsa/mt7530.h

56

#define MT7531_QRY_FFP_MASK GENMASK(7, 0)

drivers/net/dsa/mt7530.h

62

#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)

drivers/net/dsa/mt7530.h

65

#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)

drivers/net/dsa/mt7530.h

668

#define MT7531_GPIO0_MASK GENMASK(3, 0)

drivers/net/dsa/mt7530.h

672

#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)

drivers/net/dsa/mt7530.h

674

#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)

drivers/net/dsa/mt7530.h

684

#define AN7583_CSR_ETHER_AFE_PWD GENMASK(28, 24)

drivers/net/dsa/mv88e6xxx/chip.c

194

ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);

drivers/net/dsa/mv88e6xxx/chip.c

218

u16 mask = GENMASK(chip->g1_irq.nirqs, 0);

drivers/net/dsa/mv88e6xxx/chip.c

270

mask &= ~GENMASK(chip->g1_irq.nirqs, 0);

drivers/net/dsa/mv88e6xxx/chip.c

316

mask &= ~GENMASK(chip->g1_irq.nirqs, 0);

drivers/net/dsa/mv88e6xxx/chip.c

330

mask &= ~GENMASK(chip->g1_irq.nirqs, 0);

drivers/net/dsa/mv88e6xxx/chip.c

3860

bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +

drivers/net/dsa/mv88e6xxx/chip.h

799

return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);

drivers/net/dsa/mv88e6xxx/port.h

315

#define MV88E6XXX_PORT_LED_CONTROL_POINTER_MASK GENMASK(14, 12)

drivers/net/dsa/mv88e6xxx/port.h

319

#define MV88E6XXX_PORT_LED_CONTROL_DATA_MASK GENMASK(10, 0)

drivers/net/dsa/mv88e6xxx/port.h

321

#define MV88E6XXX_PORT_LED_CONTROL_LED0_SEL_MASK GENMASK(3, 0)

drivers/net/dsa/mv88e6xxx/port.h

322

#define MV88E6XXX_PORT_LED_CONTROL_LED1_SEL_MASK GENMASK(7, 4)

drivers/net/dsa/mv88e6xxx/serdes.h

75

#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)

drivers/net/dsa/mxl862xx/mxl862xx-host.c

104

if (WARN_ON(ret & GENMASK(31, 16)))

drivers/net/dsa/ocelot/felix.c

126

outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0);

drivers/net/dsa/ocelot/felix.c

128

outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0);

drivers/net/dsa/ocelot/felix_vsc9959.c

1618

rate = clamp_t(u32, rate, 1, GENMASK(14, 0));

drivers/net/dsa/ocelot/felix_vsc9959.c

1622

burst = clamp_t(u32, burst, 1, GENMASK(5, 0));

drivers/net/dsa/ocelot/felix_vsc9959.c

2599

val = GENMASK(7, 0) & ~mm->active_preemptible_tcs;

drivers/net/dsa/ocelot/felix_vsc9959.c

943

WARN_ON(wm & ~GENMASK(8, 0));

drivers/net/dsa/ocelot/felix_vsc9959.c

946

return (wm & GENMASK(7, 0)) * 16;

drivers/net/dsa/ocelot/felix_vsc9959.c

953

*inuse = (val & GENMASK(23, 12)) >> 12;

drivers/net/dsa/ocelot/felix_vsc9959.c

954

*maxuse = val & GENMASK(11, 0);

drivers/net/dsa/ocelot/seville_vsc9953.c

856

WARN_ON(wm & ~GENMASK(9, 0));

drivers/net/dsa/ocelot/seville_vsc9953.c

859

return (wm & GENMASK(8, 0)) * 16;

drivers/net/dsa/ocelot/seville_vsc9953.c

866

*inuse = (val & GENMASK(25, 13)) >> 13;

drivers/net/dsa/ocelot/seville_vsc9953.c

867

*maxuse = val & GENMASK(12, 0);

drivers/net/dsa/qca/ar9331.c

106

#define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0)

drivers/net/dsa/qca/ar9331.c

114

#define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30)

drivers/net/dsa/qca/ar9331.c

119

#define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16)

drivers/net/dsa/qca/ar9331.c

150

#define AR9331_SW_ADDR_PAGE GENMASK(18, 9)

drivers/net/dsa/qca/ar9331.c

164

#define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)

drivers/net/dsa/qca/ar9331.c

165

#define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)

drivers/net/dsa/qca/ar9331.c

167

#define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)

drivers/net/dsa/qca/ar9331.c

171

#define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)

drivers/net/dsa/qca/ar9331.c

65

#define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)

drivers/net/dsa/qca/ar9331.c

71

#define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)

drivers/net/dsa/qca/ar9331.c

72

#define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)

drivers/net/dsa/qca/ar9331.c

73

#define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)

drivers/net/dsa/qca/ar9331.c

871

*(u32 *)val_buf = GENMASK(9, 0);

drivers/net/dsa/qca/ar9331.c

91

#define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)

drivers/net/dsa/qca/ar9331.c

985

.selector_mask = GENMASK(9, 0),

drivers/net/dsa/qca/qca8k.h

109

#define QCA8K_LED_CTRL_MASK GENMASK(15, 0)

drivers/net/dsa/qca/qca8k.h

110

#define QCA8K_LED_RULE_MASK GENMASK(13, 0)

drivers/net/dsa/qca/qca8k.h

111

#define QCA8K_LED_BLINK_FREQ_MASK GENMASK(1, 0)

drivers/net/dsa/qca/qca8k.h

127

#define QCA8K_LED_PATTERN_EN_MASK GENMASK(15, 14)

drivers/net/dsa/qca/qca8k.h

138

#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)

drivers/net/dsa/qca/qca8k.h

152

#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)

drivers/net/dsa/qca/qca8k.h

153

#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)

drivers/net/dsa/qca/qca8k.h

163

#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)

drivers/net/dsa/qca/qca8k.h

184

#define QCA8K_TRUNK_HASH_MASK GENMASK(3, 0)

drivers/net/dsa/qca/qca8k.h

188

#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)

drivers/net/dsa/qca/qca8k.h

190

#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)

drivers/net/dsa/qca/qca8k.h

200

#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)

drivers/net/dsa/qca/qca8k.h

201

#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)

drivers/net/dsa/qca/qca8k.h

202

#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)

drivers/net/dsa/qca/qca8k.h

203

#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)

drivers/net/dsa/qca/qca8k.h

205

#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)

drivers/net/dsa/qca/qca8k.h

206

#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)

drivers/net/dsa/qca/qca8k.h

207

#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)

drivers/net/dsa/qca/qca8k.h

209

#define QCA8K_ATU_VID_MASK GENMASK(19, 8)

drivers/net/dsa/qca/qca8k.h

210

#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)

drivers/net/dsa/qca/qca8k.h

217

#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)

drivers/net/dsa/qca/qca8k.h

227

#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)

drivers/net/dsa/qca/qca8k.h

228

#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))

drivers/net/dsa/qca/qca8k.h

239

#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)

drivers/net/dsa/qca/qca8k.h

242

#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)

drivers/net/dsa/qca/qca8k.h

246

#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)

drivers/net/dsa/qca/qca8k.h

248

#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)

drivers/net/dsa/qca/qca8k.h

249

#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)

drivers/net/dsa/qca/qca8k.h

250

#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)

drivers/net/dsa/qca/qca8k.h

251

#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)

drivers/net/dsa/qca/qca8k.h

253

#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)

drivers/net/dsa/qca/qca8k.h

254

#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)

drivers/net/dsa/qca/qca8k.h

260

#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)

drivers/net/dsa/qca/qca8k.h

278

#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK GENMASK(6, 0)

drivers/net/dsa/qca/qca8k.h

282

#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK GENMASK(3, 0)

drivers/net/dsa/qca/qca8k.h

284

#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK GENMASK(2, 0)

drivers/net/dsa/qca/qca8k.h

293

#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)

drivers/net/dsa/qca/qca8k.h

295

#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)

drivers/net/dsa/qca/qca8k.h

299

#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)

drivers/net/dsa/qca/qca8k.h

301

#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)

drivers/net/dsa/qca/qca8k.h

303

#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)

drivers/net/dsa/qca/qca8k.h

305

#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)

drivers/net/dsa/qca/qca8k.h

307

#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)

drivers/net/dsa/qca/qca8k.h

309

#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)

drivers/net/dsa/qca/qca8k.h

311

#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)

drivers/net/dsa/qca/qca8k.h

315

#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)

drivers/net/dsa/qca/qca8k.h

324

#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))

drivers/net/dsa/qca/qca8k.h

330

#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)

drivers/net/dsa/qca/qca8k.h

43

#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)

drivers/net/dsa/qca/qca8k.h

45

#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)

drivers/net/dsa/qca/qca8k.h

54

#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)

drivers/net/dsa/qca/qca8k.h

56

#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)

drivers/net/dsa/qca/qca8k.h

72

#define QCA8K_MIB_FUNC GENMASK(26, 24)

drivers/net/dsa/qca/qca8k.h

81

#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)

drivers/net/dsa/qca/qca8k.h

83

#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)

drivers/net/dsa/qca/qca8k.h

85

#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)

drivers/net/dsa/qca/qca8k.h

98

#define QCA8K_LED_PHY123_PATTERN_EN_MASK GENMASK(1, 0)

drivers/net/dsa/realtek/rtl8365mb.c

180

#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)

drivers/net/dsa/realtek/rtl8365mb.c

181

#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)

drivers/net/dsa/realtek/rtl8365mb.c

182

#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)

drivers/net/dsa/realtek/rtl8366rb.c

114

#define RTL8366RB_STP_MASK GENMASK(1, 0)

drivers/net/dsa/realtek/rtl8366rb.c

285

#define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)

drivers/net/dsa/realtek/rtl8366rb.c

302

#define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)

drivers/net/dsa/realtek/rtl8366rb.c

66

#define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)

drivers/net/dsa/realtek/rtl8366rb.c

68

#define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)

drivers/net/dsa/realtek/rtl8366rb.c

70

#define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)

drivers/net/dsa/realtek/rtl8366rb.h

42

#define RTL8366RB_LED_0_X_CTRL_MASK GENMASK(5, 0)

drivers/net/dsa/realtek/rtl8366rb.h

43

#define RTL8366RB_LED_X_1_CTRL_MASK GENMASK(11, 6)

drivers/net/dsa/realtek/rtl8366rb.h

44

#define RTL8366RB_LED_2_X_CTRL_MASK GENMASK(5, 0)

drivers/net/dsa/realtek/rtl8366rb.h

45

#define RTL8366RB_LED_X_3_CTRL_MASK GENMASK(11, 6)

drivers/net/dsa/rzn1_a5psw.h

106

#define A5PSW_LK_LEARNCOUNT_COUNT GENMASK(13, 0)

drivers/net/dsa/rzn1_a5psw.h

107

#define A5PSW_LK_LEARNCOUNT_MODE GENMASK(31, 30)

drivers/net/dsa/rzn1_a5psw.h

113

#define A5PSW_MGMT_TAG_CFG_TAGFIELD GENMASK(31, 16)

drivers/net/dsa/rzn1_a5psw.h

118

#define A5PSW_LK_AGETIME_MASK GENMASK(23, 0)

drivers/net/dsa/rzn1_a5psw.h

121

#define A5PSW_MDIO_CFG_STATUS_CLKDIV GENMASK(15, 7)

drivers/net/dsa/rzn1_a5psw.h

128

#define A5PSW_MDIO_COMMAND_PHY_ADDR GENMASK(9, 5)

drivers/net/dsa/rzn1_a5psw.h

129

#define A5PSW_MDIO_COMMAND_REG_ADDR GENMASK(4, 0)

drivers/net/dsa/rzn1_a5psw.h

132

#define A5PSW_MDIO_DATA_MASK GENMASK(15, 0)

drivers/net/dsa/rzn1_a5psw.h

146

#define A5PSW_FRM_LENGTH_MASK GENMASK(13, 0)

drivers/net/dsa/rzn1_a5psw.h

47

#define A5PSW_VLAN_IN_MODE_PORT(port) (GENMASK(1, 0) << \

drivers/net/dsa/rzn1_a5psw.h

55

#define A5PSW_VLAN_OUT_MODE_PORT(port) (GENMASK(1, 0) << \

drivers/net/dsa/rzn1_a5psw.h

74

#define A5PSW_VLAN_RES_VLANID GENMASK(16, 5)

drivers/net/dsa/rzn1_a5psw.h

75

#define A5PSW_VLAN_RES_PORTMASK GENMASK(4, 0)

drivers/net/dsa/rzn1_a5psw.h

98

#define A5PSW_LK_ADDR_CTRL_ADDRESS GENMASK(12, 0)

drivers/net/dsa/sja1105/sja1105_mdio.c

114

offset = addr & GENMASK(7, 0);

drivers/net/dsa/sja1105/sja1105_mdio.c

23

if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)

drivers/net/dsa/sja1105/sja1105_mdio.c

25

if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)

drivers/net/dsa/sja1105/sja1105_mdio.c

26

return NXP_SJA1105_XPCS_ID & GENMASK(15, 0);

drivers/net/dsa/sja1105/sja1105_mdio.c

67

if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)

drivers/net/dsa/sja1105/sja1105_mdio.c

69

if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)

drivers/net/dsa/sja1105/sja1105_mdio.c

70

return NXP_SJA1110_XPCS_ID & GENMASK(15, 0);

drivers/net/dsa/sja1105/sja1105_mdio.c

73

offset = addr & GENMASK(7, 0);

drivers/net/dsa/vitesse-vsc73xx-core.c

124

#define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

137

#define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19)

drivers/net/dsa/vitesse-vsc73xx-core.c

140

#define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4)

drivers/net/dsa/vitesse-vsc73xx-core.c

156

#define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1)

drivers/net/dsa/vitesse-vsc73xx-core.c

166

#define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12)

drivers/net/dsa/vitesse-vsc73xx-core.c

167

#define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

200

#define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

202

#define VSC73XX_MACHDATA_VID GENMASK(27, 16)

drivers/net/dsa/vitesse-vsc73xx-core.c

203

#define VSC73XX_MACHDATA_MAC0 GENMASK(15, 8)

drivers/net/dsa/vitesse-vsc73xx-core.c

204

#define VSC73XX_MACHDATA_MAC1 GENMASK(7, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

205

#define VSC73XX_MACLDATA_MAC2 GENMASK(31, 24)

drivers/net/dsa/vitesse-vsc73xx-core.c

206

#define VSC73XX_MACLDATA_MAC3 GENMASK(23, 16)

drivers/net/dsa/vitesse-vsc73xx-core.c

207

#define VSC73XX_MACLDATA_MAC4 GENMASK(15, 8)

drivers/net/dsa/vitesse-vsc73xx-core.c

208

#define VSC73XX_MACLDATA_MAC5 GENMASK(7, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

210

#define VSC73XX_HASH0_VID_FROM_MASK GENMASK(5, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

211

#define VSC73XX_HASH0_MAC0_FROM_MASK GENMASK(7, 4)

drivers/net/dsa/vitesse-vsc73xx-core.c

212

#define VSC73XX_HASH1_MAC0_FROM_MASK GENMASK(3, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

213

#define VSC73XX_HASH1_MAC1_FROM_MASK GENMASK(7, 1)

drivers/net/dsa/vitesse-vsc73xx-core.c

215

#define VSC73XX_HASH2_MAC2_FROM_MASK GENMASK(7, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

216

#define VSC73XX_HASH2_MAC3_FROM_MASK GENMASK(7, 6)

drivers/net/dsa/vitesse-vsc73xx-core.c

217

#define VSC73XX_HASH3_MAC3_FROM_MASK GENMASK(5, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

218

#define VSC73XX_HASH3_MAC4_FROM_MASK GENMASK(7, 3)

drivers/net/dsa/vitesse-vsc73xx-core.c

219

#define VSC73XX_HASH4_MAC4_FROM_MASK GENMASK(2, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

221

#define VSC73XX_HASH0_VID_TO_MASK GENMASK(9, 4)

drivers/net/dsa/vitesse-vsc73xx-core.c

222

#define VSC73XX_HASH0_MAC0_TO_MASK GENMASK(3, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

223

#define VSC73XX_HASH1_MAC0_TO_MASK GENMASK(10, 7)

drivers/net/dsa/vitesse-vsc73xx-core.c

224

#define VSC73XX_HASH1_MAC1_TO_MASK GENMASK(6, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

226

#define VSC73XX_HASH2_MAC2_TO_MASK GENMASK(9, 2)

drivers/net/dsa/vitesse-vsc73xx-core.c

227

#define VSC73XX_HASH2_MAC3_TO_MASK GENMASK(1, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

228

#define VSC73XX_HASH3_MAC3_TO_MASK GENMASK(10, 5)

drivers/net/dsa/vitesse-vsc73xx-core.c

229

#define VSC73XX_HASH3_MAC4_TO_MASK GENMASK(4, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

230

#define VSC73XX_HASH4_MAC4_TO_MASK GENMASK(10, 8)

drivers/net/dsa/vitesse-vsc73xx-core.c

233

#define VSC73XX_MACTINDX_BUCKET_MSK GENMASK(12, 11)

drivers/net/dsa/vitesse-vsc73xx-core.c

234

#define VSC73XX_MACTINDX_INDEX_MSK GENMASK(10, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

242

#define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3)

drivers/net/dsa/vitesse-vsc73xx-core.c

243

#define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

256

#define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2)

drivers/net/dsa/vitesse-vsc73xx-core.c

258

#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

276

#define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21)

drivers/net/dsa/vitesse-vsc73xx-core.c

277

#define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16)

drivers/net/dsa/vitesse-vsc73xx-core.c

278

#define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

281

#define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

284

#define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0)

drivers/net/dsa/vitesse-vsc73xx-core.c

321

#define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8)

drivers/net/dsa/vitesse-vsc73xx-core.c

83

#define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19)

drivers/net/dsa/vitesse-vsc73xx-core.c

91

#define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6)

drivers/net/dsa/vitesse-vsc73xx-core.c

97

#define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0)

drivers/net/dsa/xrs700x/xrs700x.c

628

val = GENMASK(ds->num_ports - 1, 0);

drivers/net/dsa/xrs700x/xrs700x.c

696

val = GENMASK(ds->num_ports - 1, 0);

drivers/net/dsa/xrs700x/xrs700x_mdio.c

32

uval = (u16)FIELD_GET(GENMASK(31, 16), reg);

drivers/net/dsa/xrs700x/xrs700x_mdio.c

40

uval = (u16)((reg & GENMASK(15, 1)) | XRS_IB_READ);

drivers/net/dsa/xrs700x/xrs700x_mdio.c

73

uval = (u16)FIELD_GET(GENMASK(31, 16), reg);

drivers/net/dsa/xrs700x/xrs700x_mdio.c

81

uval = (u16)((reg & GENMASK(15, 1)) | XRS_IB_WRITE);

drivers/net/dsa/yt921x.c

110

#define YT921X_PORT_MASK_INT0_n(n) GENMASK((n) - 1, 0)

drivers/net/dsa/yt921x.c

3119

ctrl = GENMASK(10, 0);

drivers/net/dsa/yt921x.c

527

mbus->phy_mask = (u32)~GENMASK(YT921X_PORT_NUM - 1, 0);

drivers/net/dsa/yt921x.h

105

#define YT921X_PORT_SPEED_M GENMASK(2, 0)

drivers/net/dsa/yt921x.h

11

#define YT921X_SMI_SWITCHID_M GENMASK(3, 2)

drivers/net/dsa/yt921x.h

120

#define YT921X_MDIO_POLLING_SPEED_M GENMASK(2, 0)

drivers/net/dsa/yt921x.h

131

#define YT921X_CHIP_MODE_MODE GENMASK(1, 0)

drivers/net/dsa/yt921x.h

135

#define YT921X_XMII_MODE_M GENMASK(31, 29)

drivers/net/dsa/yt921x.h

146

#define YT921X_XMII_RGMII_TX_DELAY_150PS_M GENMASK(16, 13)

drivers/net/dsa/yt921x.h

152

#define YT921X_XMII_RGMII_RX_DELAY_150PS_M GENMASK(6, 3)

drivers/net/dsa/yt921x.h

159

#define YT921X_MAC_FRAME_SIZE_M GENMASK(21, 8)

drivers/net/dsa/yt921x.h

170

#define YT921X_MIB_CTRL_PORT_M GENMASK(6, 3)

drivers/net/dsa/yt921x.h

232

#define YT921X_EDATA_CTRL_ADDR_M GENMASK(15, 8)

drivers/net/dsa/yt921x.h

234

#define YT921X_EDATA_CTRL_OP_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

238

#define YT921X_EDATA_DATA_DATA_M GENMASK(31, 24)

drivers/net/dsa/yt921x.h

239

#define YT921X_EDATA_DATA_STATUS_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

248

#define YT921X_MBUS_CTRL_PORT_M GENMASK(25, 21)

drivers/net/dsa/yt921x.h

250

#define YT921X_MBUS_CTRL_REG_M GENMASK(20, 16)

drivers/net/dsa/yt921x.h

252

#define YT921X_MBUS_CTRL_TYPE_M GENMASK(11, 8) /* wild guess */

drivers/net/dsa/yt921x.h

255

#define YT921X_MBUS_CTRL_OP_M GENMASK(3, 2) /* wild guess */

drivers/net/dsa/yt921x.h

265

#define YT921X_PORT_EGR_TPID_CTAG_M GENMASK(5, 4)

drivers/net/dsa/yt921x.h

267

#define YT921X_PORT_EGR_TPID_STAG_M GENMASK(3, 2)

drivers/net/dsa/yt921x.h

270

#define YT921X_TPID_EGR_TPID_M GENMASK(15, 0)

drivers/net/dsa/yt921x.h

274

#define YT921X_IPM_PRIO_M GENMASK(4, 2)

drivers/net/dsa/yt921x.h

276

#define YT921X_IPM_COLOR_M GENMASK(1, 0)

drivers/net/dsa/yt921x.h

28

#define YT921X_CHIP_ID_MAJOR GENMASK(31, 16)

drivers/net/dsa/yt921x.h

284

#define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1)

drivers/net/dsa/yt921x.h

288

#define YT921X_PORT_PRIO_ORD_APPm_M(m) GENMASK(3 * (m) + 2, 3 * (m))

drivers/net/dsa/yt921x.h

310

#define YT921X_STP_PORTn_M(port) GENMASK(2 * (port) + 1, 2 * (port))

drivers/net/dsa/yt921x.h

32

#define YT921X_EXT_CPU_PORT_PORT_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

324

#define YT921X_PORT_LEARN_LIMIT_M GENMASK(15, 8)

drivers/net/dsa/yt921x.h

327

#define YT921X_PORT_LEARN_MODE_M GENMASK(1, 0)

drivers/net/dsa/yt921x.h

333

#define YT921X_AGEING_INTERVAL_M GENMASK(15, 0)

drivers/net/dsa/yt921x.h

338

#define YT921X_FDB_OP_INDEX_M GENMASK(22, 11)

drivers/net/dsa/yt921x.h

342

#define YT921X_FDB_OP_FLUSH_M GENMASK(8, 7)

drivers/net/dsa/yt921x.h

349

#define YT921X_FDB_OP_NEXT_TYPE_M GENMASK(5, 4)

drivers/net/dsa/yt921x.h

35

#define YT921X_CPU_TAG_TPID_TPID_M GENMASK(15, 0)

drivers/net/dsa/yt921x.h

355

#define YT921X_FDB_OP_OP_M GENMASK(3, 1)

drivers/net/dsa/yt921x.h

367

#define YT921X_FDB_RESULT_INDEX_M GENMASK(11, 0)

drivers/net/dsa/yt921x.h

370

#define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0)

drivers/net/dsa/yt921x.h

373

#define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28)

drivers/net/dsa/yt921x.h

381

#define YT921X_FDB_IO1_FID_M GENMASK(27, 16) /* filtering ID (VID) */

drivers/net/dsa/yt921x.h

383

#define YT921X_FDB_IO1_ADDR_LO2_M GENMASK(15, 0)

drivers/net/dsa/yt921x.h

385

#define YT921X_FDB_IO2_MOVE_AGING_STATUS_M GENMASK(31, 30)

drivers/net/dsa/yt921x.h

387

#define YT921X_FDB_IO2_EGR_PORTS_M GENMASK(28, 18)

drivers/net/dsa/yt921x.h

392

#define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12)

drivers/net/dsa/yt921x.h

394

#define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0)

drivers/net/dsa/yt921x.h

400

#define YT921X_FILTER_PORTS_M GENMASK(10, 0)

drivers/net/dsa/yt921x.h

406

#define YT921X_LAG_GROUP_PORTS_M GENMASK(13, 3)

drivers/net/dsa/yt921x.h

408

#define YT921X_LAG_GROUP_MEMBER_NUM_M GENMASK(2, 0)

drivers/net/dsa/yt921x.h

411

#define YT921X_LAG_MEMBER_PORT_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

421

#define YT921X_ACT_UNK_ACTn_M(port) GENMASK(2 * (port) + 1, 2 * (port))

drivers/net/dsa/yt921x.h

452

#define YT921X_TPID_IGR_TPID_M GENMASK(15, 0)

drivers/net/dsa/yt921x.h

454

#define YT921X_PORT_IGR_TPIDn_STAG_M GENMASK(7, 4)

drivers/net/dsa/yt921x.h

456

#define YT921X_PORT_IGR_TPIDn_CTAG_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

46

#define YT9215_IO_LEVEL_NORMAL_M GENMASK(5, 4)

drivers/net/dsa/yt921x.h

471

#define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18)

drivers/net/dsa/yt921x.h

473

#define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6)

drivers/net/dsa/yt921x.h

475

#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3)

drivers/net/dsa/yt921x.h

476

#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0)

drivers/net/dsa/yt921x.h

479

#define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4)

drivers/net/dsa/yt921x.h

486

#define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16)

drivers/net/dsa/yt921x.h

489

#define YT921X_MIRROR_EGR_PORTS_M GENMASK(14, 4)

drivers/net/dsa/yt921x.h

492

#define YT921X_MIRROR_PORT_M GENMASK(3, 0)

drivers/net/dsa/yt921x.h

50

#define YT9215_IO_LEVEL_RGMII1_M GENMASK(3, 2)

drivers/net/dsa/yt921x.h

55

#define YT9215_IO_LEVEL_RGMII0_M GENMASK(1, 0)

drivers/net/dsa/yt921x.h

60

#define YT9218_IO_LEVEL_RGMII1_M GENMASK(5, 4)

drivers/net/dsa/yt921x.h

65

#define YT9218_IO_LEVEL_RGMII0_M GENMASK(3, 2)

drivers/net/dsa/yt921x.h

70

#define YT9218_IO_LEVEL_NORMAL_M GENMASK(1, 0)

drivers/net/dsa/yt921x.h

77

#define YT921X_SERDES_MODE_M GENMASK(9, 7)

drivers/net/dsa/yt921x.h

88

#define YT921X_SERDES_SPEED_M GENMASK(2, 0)

drivers/net/ethernet/actions/owl-emac.h

125

#define OWL_EMAC_MSK_MAC_CSR10_CLKDIV GENMASK(30, 28) /* Clock divider */

drivers/net/ethernet/actions/owl-emac.h

134

#define OWL_EMAC_MSK_MAC_CSR10_PHYADD GENMASK(25, 21) /* Physical layer address */

drivers/net/ethernet/actions/owl-emac.h

136

#define OWL_EMAC_MSK_MAC_CSR10_REGADD GENMASK(20, 16) /* Register address */

drivers/net/ethernet/actions/owl-emac.h

138

#define OWL_EMAC_MSK_MAC_CSR10_DATA GENMASK(15, 0) /* Register data */

drivers/net/ethernet/actions/owl-emac.h

180

#define OWL_EMAC_MSK_RDES0_FL GENMASK(29, 16) /* Frame length */

drivers/net/ethernet/actions/owl-emac.h

198

#define OWL_EMAC_MSK_RDES1_RBS1 GENMASK(10, 0) /* Buffer 1 size */

drivers/net/ethernet/actions/owl-emac.h

207

#define OWL_EMAC_MSK_TDES0_CC GENMASK(6, 3) /* Collision count */

drivers/net/ethernet/actions/owl-emac.h

221

#define OWL_EMAC_MSK_TDES1_TBS1 GENMASK(10, 0) /* Buffer 1 size */

drivers/net/ethernet/actions/owl-emac.h

47

#define OWL_EMAC_MSK_MAC_CSR5_TS GENMASK(22, 20) /* Transmit process state */

drivers/net/ethernet/actions/owl-emac.h

51

#define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */

drivers/net/ethernet/actions/owl-emac.h

76

#define OWL_EMAC_MSK_MAC_CSR6_SPEED GENMASK(17, 16) /* Eth speed selection */

drivers/net/ethernet/adi/adin1110.c

202

priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg);

drivers/net/ethernet/adi/adin1110.c

203

priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);

drivers/net/ethernet/adi/adin1110.c

248

priv->data[0] = ADIN1110_CD | ADIN1110_WRITE | FIELD_GET(GENMASK(12, 8), reg);

drivers/net/ethernet/adi/adin1110.c

249

priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);

drivers/net/ethernet/adi/adin1110.c

330

priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg);

drivers/net/ethernet/adi/adin1110.c

331

priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);

drivers/net/ethernet/adi/adin1110.c

401

priv->data[0] |= FIELD_GET(GENMASK(12, 8), ADIN1110_TX);

drivers/net/ethernet/adi/adin1110.c

402

priv->data[1] = FIELD_GET(GENMASK(7, 0), ADIN1110_TX);

drivers/net/ethernet/adi/adin1110.c

527

mii_bus->phy_mask = ~((u32)GENMASK(2, 0));

drivers/net/ethernet/adi/adin1110.c

60

#define ADIN1110_MDIO_ST GENMASK(29, 28)

drivers/net/ethernet/adi/adin1110.c

61

#define ADIN1110_MDIO_OP GENMASK(27, 26)

drivers/net/ethernet/adi/adin1110.c

62

#define ADIN1110_MDIO_PRTAD GENMASK(25, 21)

drivers/net/ethernet/adi/adin1110.c

63

#define ADIN1110_MDIO_DEVAD GENMASK(20, 16)

drivers/net/ethernet/adi/adin1110.c

64

#define ADIN1110_MDIO_DATA GENMASK(15, 0)

drivers/net/ethernet/adi/adin1110.c

645

port_rules_mask |= GENMASK(15, 0);

drivers/net/ethernet/airoha/airoha_eth.h

167

#define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6)

drivers/net/ethernet/airoha/airoha_eth.h

168

#define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0)

drivers/net/ethernet/airoha/airoha_eth.h

256

#define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_eth.h

257

#define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_eth.h

259

#define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12)

drivers/net/ethernet/airoha/airoha_eth.h

261

#define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0)

drivers/net/ethernet/airoha/airoha_eth.h

285

#define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)

drivers/net/ethernet/airoha/airoha_eth.h

286

#define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)

drivers/net/ethernet/airoha/airoha_eth.h

290

#define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28)

drivers/net/ethernet/airoha/airoha_eth.h

291

#define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25)

drivers/net/ethernet/airoha/airoha_eth.h

295

#define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20)

drivers/net/ethernet/airoha/airoha_eth.h

296

#define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16)

drivers/net/ethernet/airoha/airoha_eth.h

298

#define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)

drivers/net/ethernet/airoha/airoha_eth.h

300

#define AIROHA_FOE_IB2_DSCP GENMASK(31, 24)

drivers/net/ethernet/airoha/airoha_eth.h

301

#define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13)

drivers/net/ethernet/airoha/airoha_eth.h

306

#define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5)

drivers/net/ethernet/airoha/airoha_eth.h

307

#define AIROHA_FOE_IB2_NBQ GENMASK(4, 0)

drivers/net/ethernet/airoha/airoha_eth.h

309

#define AIROHA_FOE_ACTDP GENMASK(31, 24)

drivers/net/ethernet/airoha/airoha_eth.h

310

#define AIROHA_FOE_SHAPER_ID GENMASK(23, 16)

drivers/net/ethernet/airoha/airoha_eth.h

311

#define AIROHA_FOE_CHANNEL GENMASK(15, 11)

drivers/net/ethernet/airoha/airoha_eth.h

312

#define AIROHA_FOE_QID GENMASK(10, 8)

drivers/net/ethernet/airoha/airoha_eth.h

315

#define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0)

drivers/net/ethernet/airoha/airoha_eth.h

317

#define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_eth.h

318

#define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9)

drivers/net/ethernet/airoha/airoha_eth.h

319

#define AIROHA_FOE_METER_GRP3 GENMASK(8, 5)

drivers/net/ethernet/airoha/airoha_eth.h

320

#define AIROHA_FOE_METER_GRP2 GENMASK(4, 0)

drivers/net/ethernet/airoha/airoha_eth.h

551

#define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_eth.h

552

#define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_npu.c

120

#define MBOX_MSG_FUNC_ID GENMASK(14, 11)

drivers/net/ethernet/airoha/airoha_npu.c

122

#define MBOX_MSG_STATUS GENMASK(4, 2)

drivers/net/ethernet/airoha/airoha_regs.h

100

#define PSE_IQ_RES2_P4_MASK GENMASK(7, 0)

drivers/net/ethernet/airoha/airoha_regs.h

107

#define PATN_TYPE_MASK GENMASK(3, 1)

drivers/net/ethernet/airoha/airoha_regs.h

111

#define PATN_DP_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

112

#define PATN_SP_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

115

#define CDM_VLAN_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

118

#define CDM_OAM_QSEL_MASK GENMASK(31, 27)

drivers/net/ethernet/airoha/airoha_regs.h

119

#define CDM_VIP_QSEL_MASK GENMASK(24, 20)

drivers/net/ethernet/airoha/airoha_regs.h

123

GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))

drivers/net/ethernet/airoha/airoha_regs.h

132

#define GDM_UCFQ_MASK GENMASK(15, 12)

drivers/net/ethernet/airoha/airoha_regs.h

133

#define GDM_BCFQ_MASK GENMASK(11, 8)

drivers/net/ethernet/airoha/airoha_regs.h

134

#define GDM_MCFQ_MASK GENMASK(7, 4)

drivers/net/ethernet/airoha/airoha_regs.h

135

#define GDM_OCFQ_MASK GENMASK(3, 0)

drivers/net/ethernet/airoha/airoha_regs.h

142

#define GDM_SHORT_LEN_MASK GENMASK(13, 0)

drivers/net/ethernet/airoha/airoha_regs.h

143

#define GDM_LONG_LEN_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

146

#define LPBK_GAP_MASK GENMASK(31, 24)

drivers/net/ethernet/airoha/airoha_regs.h

147

#define LPBK_LEN_MASK GENMASK(23, 10)

drivers/net/ethernet/airoha/airoha_regs.h

148

#define LPBK_CHAN_MASK GENMASK(8, 4)

drivers/net/ethernet/airoha/airoha_regs.h

149

#define LPBK_MODE_MASK GENMASK(3, 1)

drivers/net/ethernet/airoha/airoha_regs.h

156

#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25)

drivers/net/ethernet/airoha/airoha_regs.h

157

#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17)

drivers/net/ethernet/airoha/airoha_regs.h

175

#define FE_TX_MIB_ID_MASK GENMASK(15, 8)

drivers/net/ethernet/airoha/airoha_regs.h

176

#define FE_RX_MIB_ID_MASK GENMASK(7, 0)

drivers/net/ethernet/airoha/airoha_regs.h

218

#define GDM_SPORT_OFF2_MASK GENMASK(19, 16)

drivers/net/ethernet/airoha/airoha_regs.h

219

#define GDM_SPORT_OFF1_MASK GENMASK(15, 12)

drivers/net/ethernet/airoha/airoha_regs.h

220

#define GDM_SPORT_OFF0_MASK GENMASK(11, 8)

drivers/net/ethernet/airoha/airoha_regs.h

270

#define PPE_IP_PROTO_CHK_IPV4_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

271

#define PPE_IP_PROTO_CHK_IPV6_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

274

#define PPE_SRAM_TB_NUM_ENTRY_MASK GENMASK(26, 24)

drivers/net/ethernet/airoha/airoha_regs.h

275

#define PPE_TB_CFG_KEEPALIVE_MASK GENMASK(13, 12)

drivers/net/ethernet/airoha/airoha_regs.h

282

#define PPE_TB_CFG_SEARCH_MISS_MASK GENMASK(5, 4)

drivers/net/ethernet/airoha/airoha_regs.h

284

#define PPE_DRAM_TB_NUM_ENTRY_MASK GENMASK(2, 0)

drivers/net/ethernet/airoha/airoha_regs.h

289

#define PPE_BIND_RATE_L2B_BIND_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

290

#define PPE_BIND_RATE_BIND_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

293

#define PPE_BIND_LIMIT0_HALF_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

294

#define PPE_BIND_LIMIT0_QUARTER_MASK GENMASK(13, 0)

drivers/net/ethernet/airoha/airoha_regs.h

297

#define PPE_BIND_LIMIT1_NON_L4_MASK GENMASK(23, 16)

drivers/net/ethernet/airoha/airoha_regs.h

298

#define PPE_BIND_LIMIT1_FULL_MASK GENMASK(13, 0)

drivers/net/ethernet/airoha/airoha_regs.h

301

#define PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)

drivers/net/ethernet/airoha/airoha_regs.h

302

#define PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)

drivers/net/ethernet/airoha/airoha_regs.h

305

#define PPE_UNBIND_AGE_MIN_PACKETS_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

306

#define PPE_UNBIND_AGE_DELTA_MASK GENMASK(7, 0)

drivers/net/ethernet/airoha/airoha_regs.h

309

#define PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)

drivers/net/ethernet/airoha/airoha_regs.h

310

#define PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)

drivers/net/ethernet/airoha/airoha_regs.h

316

#define DFT_CPORT_MASK(_n) GENMASK(3 + ((_n) << 2), ((_n) << 2))

drivers/net/ethernet/airoha/airoha_regs.h

321

#define PPE_DRAM_HASH1_MODE_MASK GENMASK(31, 28)

drivers/net/ethernet/airoha/airoha_regs.h

323

#define PPE_DRAM_HASH0_MODE_MASK GENMASK(23, 20)

drivers/net/ethernet/airoha/airoha_regs.h

325

#define PPE_SRAM_HASH1_MODE_MASK GENMASK(15, 12)

drivers/net/ethernet/airoha/airoha_regs.h

327

#define PPE_SRAM_HASH0_MODE_MASK GENMASK(7, 4)

drivers/net/ethernet/airoha/airoha_regs.h

332

#define FP1_EGRESS_MTU_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

333

#define FP0_EGRESS_MTU_MASK GENMASK(13, 0)

drivers/net/ethernet/airoha/airoha_regs.h

338

#define PPE_SRAM_CTRL_ENTRY_MASK GENMASK(23, 8)

drivers/net/ethernet/airoha/airoha_regs.h

34

#define FE_DMA_GLO_L2_SPACE_MASK GENMASK(7, 4)

drivers/net/ethernet/airoha/airoha_regs.h

348

#define PPE_UPDMEM_ADDR_MASK GENMASK(11, 8)

drivers/net/ethernet/airoha/airoha_regs.h

349

#define PPE_UPDMEM_OFFSET_MASK GENMASK(7, 4)

drivers/net/ethernet/airoha/airoha_regs.h

350

#define PPE_UPDMEM_SEL_MASK GENMASK(3, 2)

drivers/net/ethernet/airoha/airoha_regs.h

357

#define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21)

drivers/net/ethernet/airoha/airoha_regs.h

358

#define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

359

#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)

drivers/net/ethernet/airoha/airoha_regs.h

360

#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)

drivers/net/ethernet/airoha/airoha_regs.h

367

#define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16)

drivers/net/ethernet/airoha/airoha_regs.h

368

#define MC_VLAN_CFG_PORT_ID_MASK GENMASK(11, 8)

drivers/net/ethernet/airoha/airoha_regs.h

375

#define SP_CPORT_DFT_MASK GENMASK(2, 0)

drivers/net/ethernet/airoha/airoha_regs.h

376

#define SP_CPORT_MASK(_n) GENMASK(3 + ((_n) << 2), ((_n) << 2))

drivers/net/ethernet/airoha/airoha_regs.h

379

#define FC_ID_OF_SRC_PORT27_MASK GENMASK(28, 24)

drivers/net/ethernet/airoha/airoha_regs.h

380

#define FC_ID_OF_SRC_PORT26_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

381

#define FC_ID_OF_SRC_PORT25_MASK GENMASK(12, 8)

drivers/net/ethernet/airoha/airoha_regs.h

382

#define FC_ID_OF_SRC_PORT24_MASK GENMASK(4, 0)

drivers/net/ethernet/airoha/airoha_regs.h

389

#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29)

drivers/net/ethernet/airoha/airoha_regs.h

403

#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8)

drivers/net/ethernet/airoha/airoha_regs.h

406

#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4)

drivers/net/ethernet/airoha/airoha_regs.h

416

#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28)

drivers/net/ethernet/airoha/airoha_regs.h

417

#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)

drivers/net/ethernet/airoha/airoha_regs.h

418

#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

46

#define WAN1_MASK GENMASK(12, 8)

drivers/net/ethernet/airoha/airoha_regs.h

47

#define WAN0_MASK GENMASK(4, 0)

drivers/net/ethernet/airoha/airoha_regs.h

66

#define PSE_CFG_PORT_ID_MASK GENMASK(27, 24)

drivers/net/ethernet/airoha/airoha_regs.h

67

#define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

688

#define TX_IRQ_THR_MASK GENMASK(27, 16)

drivers/net/ethernet/airoha/airoha_regs.h

689

#define TX_IRQ_DEPTH_MASK GENMASK(11, 0)

drivers/net/ethernet/airoha/airoha_regs.h

692

#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0)

drivers/net/ethernet/airoha/airoha_regs.h

695

#define IRQ_ENTRY_LEN_MASK GENMASK(27, 16)

drivers/net/ethernet/airoha/airoha_regs.h

696

#define IRQ_HEAD_IDX_MASK GENMASK(11, 0)

drivers/net/ethernet/airoha/airoha_regs.h

713

#define TX_RING_CPU_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

718

#define TX_RING_DMA_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

72

#define PSE_CFG_OQ_RSV_MASK GENMASK(13, 0)

drivers/net/ethernet/airoha/airoha_regs.h

720

#define IRQ_RING_IDX_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

721

#define IRQ_DESC_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

729

#define RX_RING_THR_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

730

#define RX_RING_SIZE_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

735

#define RX_RING_CPU_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

746

#define RX_DELAY_INT_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

748

#define RX_RING_DMA_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

75

#define PSE_FQ_LIMIT_MASK GENMASK(14, 0)

drivers/net/ethernet/airoha/airoha_regs.h

755

#define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

756

#define INGRESS_FAST_TICK_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

769

#define CNTR_SRC_MASK GENMASK(27, 24)

drivers/net/ethernet/airoha/airoha_regs.h

770

#define CNTR_DSCP_RING_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

771

#define CNTR_CHAN_MASK GENMASK(7, 3)

drivers/net/ethernet/airoha/airoha_regs.h

772

#define CNTR_QUEUE_MASK GENMASK(2, 0)

drivers/net/ethernet/airoha/airoha_regs.h

779

#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20)

drivers/net/ethernet/airoha/airoha_regs.h

78

#define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

780

#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)

drivers/net/ethernet/airoha/airoha_regs.h

783

#define FWD_DSCP_LOW_THR_MASK GENMASK(17, 0)

drivers/net/ethernet/airoha/airoha_regs.h

788

#define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12)

drivers/net/ethernet/airoha/airoha_regs.h

789

#define EGRESS_RATE_METER_TIMESLICE_MASK GENMASK(10, 0)

drivers/net/ethernet/airoha/airoha_regs.h

79

#define PSE_ALLRSV_MASK GENMASK(14, 0)

drivers/net/ethernet/airoha/airoha_regs.h

794

#define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

795

#define EGRESS_FAST_TICK_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

799

#define TRTCM_PARAM_TYPE_MASK GENMASK(29, 28)

drivers/net/ethernet/airoha/airoha_regs.h

800

#define TRTCM_METER_GROUP_MASK GENMASK(27, 26)

drivers/net/ethernet/airoha/airoha_regs.h

801

#define TRTCM_PARAM_INDEX_MASK GENMASK(23, 17)

drivers/net/ethernet/airoha/airoha_regs.h

810

#define RATE_LIMIT_PARAM_TYPE_MASK GENMASK(29, 28)

drivers/net/ethernet/airoha/airoha_regs.h

811

#define RATE_LIMIT_METER_GROUP_MASK GENMASK(27, 26)

drivers/net/ethernet/airoha/airoha_regs.h

812

#define RATE_LIMIT_PARAM_INDEX_MASK GENMASK(23, 16)

drivers/net/ethernet/airoha/airoha_regs.h

82

#define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16)

drivers/net/ethernet/airoha/airoha_regs.h

821

#define TWRR_CHAN_IDX_MASK GENMASK(23, 19)

drivers/net/ethernet/airoha/airoha_regs.h

822

#define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)

drivers/net/ethernet/airoha/airoha_regs.h

823

#define TWRR_VALUE_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

829

#define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2)

drivers/net/ethernet/airoha/airoha_regs.h

83

#define PSE_SHARE_USED_HTHD_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

834

#define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

835

#define GLB_FAST_TICK_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

844

#define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16)

drivers/net/ethernet/airoha/airoha_regs.h

845

#define SLA_FAST_TICK_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

853

#define QDMA_DESC_LEN_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

855

#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

858

#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14)

drivers/net/ethernet/airoha/airoha_regs.h

865

#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3)

drivers/net/ethernet/airoha/airoha_regs.h

866

#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0)

drivers/net/ethernet/airoha/airoha_regs.h

869

#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */

drivers/net/ethernet/airoha/airoha_regs.h

870

#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20)

drivers/net/ethernet/airoha/airoha_regs.h

871

#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15)

drivers/net/ethernet/airoha/airoha_regs.h

875

#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */

drivers/net/ethernet/airoha/airoha_regs.h

876

#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */

drivers/net/ethernet/airoha/airoha_regs.h

879

#define QDMA_ETH_RXMSG_SPTAG GENMASK(21, 14)

drivers/net/ethernet/airoha/airoha_regs.h

887

#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21)

drivers/net/ethernet/airoha/airoha_regs.h

888

#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)

drivers/net/ethernet/airoha/airoha_regs.h

889

#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

904

#define QDMA_FWD_DESC_RING_MASK GENMASK(30, 28)

drivers/net/ethernet/airoha/airoha_regs.h

905

#define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16)

drivers/net/ethernet/airoha/airoha_regs.h

906

#define QDMA_FWD_DESC_LEN_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

908

#define QDMA_FWD_DESC_FIRST_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/airoha/airoha_regs.h

910

#define QDMA_FWD_DESC_MORE_PKT_NUM_MASK GENMASK(2, 0)

drivers/net/ethernet/airoha/airoha_regs.h

96

#define PSE_IQ_RES1_P2_MASK GENMASK(23, 16)

drivers/net/ethernet/airoha/airoha_regs.h

99

#define PSE_IQ_RES2_P5_MASK GENMASK(15, 8)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1236

#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1245

#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1248

#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1253

#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1254

#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1256

#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1262

#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1265

#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1297

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1298

#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1311

#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1313

#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1315

#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1317

#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1318

#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1320

#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

1322

#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

278

#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

280

#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

291

#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

297

#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

307

#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

308

#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

310

#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

313

#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

317

#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

332

#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

333

#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

335

#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

337

#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

339

#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

354

#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

356

#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

358

#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

379

#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

381

#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)

drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h

386

#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)

drivers/net/ethernet/amd/xgbe/xgbe-pps.c

15

return GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x));

drivers/net/ethernet/amd/xgbe/xgbe-pps.c

20

return (val & GENMASK(3, 0)) << PPS_MINIDX(x);

drivers/net/ethernet/amd/xgbe/xgbe-pps.c

25

return (val & GENMASK(1, 0)) << (PPS_MAXIDX(x) - 2);

drivers/net/ethernet/amd/xgbe/xgbe.h

267

#define XGBE_GEN_HI_MASK GENMASK(31, 16)

drivers/net/ethernet/amd/xgbe/xgbe.h

268

#define XGBE_GEN_LO_MASK GENMASK(15, 0)

drivers/net/ethernet/apm/xgene-v2/mac.h

62

u32 mask = GENMASK(pos + len, pos);

drivers/net/ethernet/apm/xgene-v2/mac.h

70

u32 mask = GENMASK(pos + len, pos);

drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c

225

mask = GENMASK(gstrings_extd_stats[i].mask - 1, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

113

ring_id_val = ring->id & GENMASK(9, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

116

ring_id_buf = (ring->num << 9) & GENMASK(18, 9);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

167

#define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0))

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

168

#define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16))

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

180

#define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20))

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

23

u32 mask = GENMASK(end, start);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

31

return (val & GENMASK(end, start)) >> start;

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

313

#define DATALEN_MASK GENMASK(11, 0)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

61

#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

71

#define RING_OWNER_MASK GENMASK(9, 6)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

72

#define RING_BUFNUM_MASK GENMASK(5, 0)

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

1270

return (owner << 6) | (bufnum & GENMASK(5, 0));

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

136

bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

47

mask = GENMASK(13, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

49

} else if (!(hw_len & GENMASK(13, 12))) {

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

50

mask = GENMASK(11, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

53

mask = GENMASK(11, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c

105

ring_id_val = ring->id & GENMASK(9, 0);

drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c

108

ring_id_buf = (ring->num << 9) & GENMASK(18, 9);

drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c

166

data |= (count & GENMASK(16, 0));

drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h

12

#define PHY_ADDR(src) (((src)<<8) & GENMASK(12, 8))

drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h

13

#define REG_ADDR(src) ((src) & GENMASK(4, 0))

drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h

14

#define PHY_CONTROL(src) ((src) & GENMASK(15, 0))

drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h

15

#define LINK_SPEED(src) (((src) & GENMASK(11, 10)) >> 10)

drivers/net/ethernet/atheros/ag71xx.c

245

{ 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

246

{ 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

247

{ 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

248

{ 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

249

{ 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

250

{ 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", },

drivers/net/ethernet/atheros/ag71xx.c

251

{ 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", },

drivers/net/ethernet/atheros/ag71xx.c

252

{ 0x009C, GENMASK(23, 0), "Rx Byte", },

drivers/net/ethernet/atheros/ag71xx.c

253

{ 0x00A0, GENMASK(17, 0), "Rx Packet", },

drivers/net/ethernet/atheros/ag71xx.c

254

{ 0x00A4, GENMASK(11, 0), "Rx FCS Error", },

drivers/net/ethernet/atheros/ag71xx.c

255

{ 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", },

drivers/net/ethernet/atheros/ag71xx.c

256

{ 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", },

drivers/net/ethernet/atheros/ag71xx.c

257

{ 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", },

drivers/net/ethernet/atheros/ag71xx.c

258

{ 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", },

drivers/net/ethernet/atheros/ag71xx.c

259

{ 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", },

drivers/net/ethernet/atheros/ag71xx.c

260

{ 0x00BC, GENMASK(11, 0), "Rx Alignment Error", },

drivers/net/ethernet/atheros/ag71xx.c

261

{ 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", },

drivers/net/ethernet/atheros/ag71xx.c

262

{ 0x00C4, GENMASK(11, 0), "Rx Code Error", },

drivers/net/ethernet/atheros/ag71xx.c

263

{ 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", },

drivers/net/ethernet/atheros/ag71xx.c

264

{ 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", },

drivers/net/ethernet/atheros/ag71xx.c

265

{ 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", },

drivers/net/ethernet/atheros/ag71xx.c

266

{ 0x00D4, GENMASK(11, 0), "Rx Fragments", },

drivers/net/ethernet/atheros/ag71xx.c

267

{ 0x00D8, GENMASK(11, 0), "Rx Jabber", },

drivers/net/ethernet/atheros/ag71xx.c

268

{ 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", },

drivers/net/ethernet/atheros/ag71xx.c

269

{ 0x00E0, GENMASK(23, 0), "Tx Byte", },

drivers/net/ethernet/atheros/ag71xx.c

270

{ 0x00E4, GENMASK(17, 0), "Tx Packet", },

drivers/net/ethernet/atheros/ag71xx.c

271

{ 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", },

drivers/net/ethernet/atheros/ag71xx.c

272

{ 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", },

drivers/net/ethernet/atheros/ag71xx.c

273

{ 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", },

drivers/net/ethernet/atheros/ag71xx.c

274

{ 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", },

drivers/net/ethernet/atheros/ag71xx.c

275

{ 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", },

drivers/net/ethernet/atheros/ag71xx.c

276

{ 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", },

drivers/net/ethernet/atheros/ag71xx.c

277

{ 0x0100, GENMASK(11, 0), "Tx Multiple Collision", },

drivers/net/ethernet/atheros/ag71xx.c

278

{ 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", },

drivers/net/ethernet/atheros/ag71xx.c

279

{ 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", },

drivers/net/ethernet/atheros/ag71xx.c

280

{ 0x010C, GENMASK(12, 0), "Tx Total Collision", },

drivers/net/ethernet/atheros/ag71xx.c

281

{ 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", },

drivers/net/ethernet/atheros/ag71xx.c

282

{ 0x0114, GENMASK(11, 0), "Tx Drop Frame", },

drivers/net/ethernet/atheros/ag71xx.c

283

{ 0x0118, GENMASK(11, 0), "Tx Jabber Frame", },

drivers/net/ethernet/atheros/ag71xx.c

284

{ 0x011C, GENMASK(11, 0), "Tx FCS Error", },

drivers/net/ethernet/atheros/ag71xx.c

285

{ 0x0120, GENMASK(11, 0), "Tx Control Frame", },

drivers/net/ethernet/atheros/ag71xx.c

286

{ 0x0124, GENMASK(11, 0), "Tx Oversize Frame", },

drivers/net/ethernet/atheros/ag71xx.c

287

{ 0x0128, GENMASK(11, 0), "Tx Undersize Frame", },

drivers/net/ethernet/atheros/ag71xx.c

288

{ 0x012C, GENMASK(11, 0), "Tx Fragment", },

drivers/net/ethernet/broadcom/asp2/bcmasp.c

295

match_val &= ~GENMASK(shift + 7, shift);

drivers/net/ethernet/broadcom/asp2/bcmasp.c

296

mask_val &= ~GENMASK(shift + 7, shift);

drivers/net/ethernet/broadcom/asp2/bcmasp.h

156

#define ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE GENMASK(4, 0)

drivers/net/ethernet/broadcom/asp2/bcmasp_intf_defs.h

155

#define RGMII_PORT_MODE_MASK GENMASK(2, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

100

#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK GENMASK(3, 1)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

110

#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK GENMASK(11, 9)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

118

#define RX_CMPL_ERRORS_PKT_ERROR_MASK GENMASK(15, 12)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

129

#define RX_CMPL_CFA_CODE_MASK GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

131

#define RX_CMPL_METADATA0_TCI_MASK GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

132

#define RX_CMPL_METADATA0_VID_MASK GENMASK(27, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

142

#define RX_AGG_CMP_TYPE GENMASK(5, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

143

#define RX_AGG_CMP_LEN GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

146

#define RX_AGG_CMP_AGG_ID GENMASK(25, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

15

#define TX_BD_HSIZE GENMASK(23, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

18

#define TX_BD_CFA_ACTION GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

201

#define RSS_PROFILE_ID_MASK GENMASK(4, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

214

#define RX_TPA_START_CMP_TYPE GENMASK(5, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

215

#define RX_TPA_START_CMP_FLAGS GENMASK(15, 6)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

218

#define RX_TPA_START_CMP_FLAGS_PLACEMENT GENMASK(9, 7)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

226

#define RX_TPA_START_CMP_FLAGS_ITYPES GENMASK(15, 12)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

229

#define RX_TPA_START_CMP_LEN GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

23

#define TX_BD_CFA_META_PRI_MASK GENMASK(15, 12)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

232

#define RX_TPA_START_CMP_RSS_HASH_TYPE GENMASK(15, 9)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

234

#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE GENMASK(15, 7)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

236

#define RX_TPA_START_CMP_AGG_ID GENMASK(25, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

238

#define RX_TPA_START_CMP_METADATA1 GENMASK(31, 28)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

240

#define RX_TPA_START_METADATA1_TPID_SEL GENMASK(30, 28)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

25

#define TX_BD_CFA_META_TPID_MASK GENMASK(17, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

27

#define TX_BD_CFA_META_KEY GENMASK(31, 28)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

288

#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT GENMASK(11, 10)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

292

#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

295

#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK GENMASK(3, 1)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

300

#define RX_TPA_START_CMP_CFA_CODE GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

302

#define RX_TPA_START_CMP_METADATA0_TCI_MASK GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

303

#define RX_TPA_START_CMP_METADATA0_VID_MASK GENMASK(27, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

331

#define RX_TPA_END_CMP_TYPE GENMASK(5, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

332

#define RX_TPA_END_CMP_FLAGS GENMASK(15, 6)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

334

#define RX_TPA_END_CMP_FLAGS_PLACEMENT GENMASK(9, 7)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

341

#define RX_TPA_END_CMP_FLAGS_ITYPES GENMASK(15, 12)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

344

#define RX_TPA_END_CMP_LEN GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

347

#define RX_TPA_END_CMP_TPA_SEGS GENMASK(15, 8)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

349

#define RX_TPA_END_CMP_AGG_ID GENMASK(25, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

380

#define RX_TPA_END_CMP_TPA_DUP_ACKS GENMASK(3, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

381

#define RX_TPA_END_CMP_PAYLOAD_OFFSET GENMASK(23, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

383

#define RX_TPA_END_CMP_AGG_BUFS GENMASK(31, 24)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

385

#define RX_TPA_END_CMP_TPA_SEG_LEN GENMASK(15, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

387

#define RX_TPA_END_CMP_ERRORS GENMASK(2, 1)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

41

#define RX_CMP_CMP_TYPE GENMASK(5, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

43

#define RX_CMP_FLAGS_PLACEMENT GENMASK(9, 7)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

56

#define RX_CMP_LEN GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

60

#define RX_CMP_AGG_BUFS GENMASK(5, 1)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

62

#define RX_CMP_RSS_HASH_TYPE GENMASK(15, 9)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

64

#define RX_CMP_V3_RSS_EXT_OP_LEGACY GENMASK(15, 12)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

66

#define RX_CMP_V3_RSS_EXT_OP_NEW GENMASK(11, 8)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

68

#define RX_CMP_PAYLOAD_OFFSET GENMASK(23, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

70

#define RX_CMP_SUB_NS_TS GENMASK(19, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

72

#define RX_CMP_METADATA1 GENMASK(31, 28)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

74

#define RX_CMP_METADATA1_TPID_SEL GENMASK(30, 28)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

92

#define RX_CMP_FLAGS2_METADATA_TCI_MASK GENMASK(15, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

93

#define RX_CMP_FLAGS2_METADATA_VID_MASK GENMASK(11, 0)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

94

#define RX_CMP_FLAGS2_METADATA_TPID_MASK GENMASK(31, 16)

drivers/net/ethernet/broadcom/bnge/bnge_hw_def.h

98

#define RX_CMPL_ERRORS_MASK GENMASK(15, 1)

drivers/net/ethernet/broadcom/genet/bcmgenet.c

3565

reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);

drivers/net/ethernet/cadence/macb.h

1433

return DIV_ROUND_UP(GENMASK(GEM_ON_TIME_SIZE - 1, 0) *

drivers/net/ethernet/cadence/macb_main.c

4248

if (start_time_sec > GENMASK(GEM_START_TIME_SEC_SIZE - 1, 0)) {

drivers/net/ethernet/cisco/enic/enic_wq.c

10

#define ENET_CQ_DESC_COMP_NDX_MASK GENMASK(ENET_CQ_DESC_COMP_NDX_BITS - 1, 0)

drivers/net/ethernet/davicom/dm9051.c

1062

hash_val = ether_crc_le(ETH_ALEN, ha->addr) & GENMASK(5, 0);

drivers/net/ethernet/davicom/dm9051.c

753

if ((rxbyte & GENMASK(7, 0)) != DM9051_PKT_RDY)

drivers/net/ethernet/freescale/dpaa2/dpmac-cmd.h

33

GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \

drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h

107

GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \

drivers/net/ethernet/freescale/dpaa2/dpsw-cmd.h

102

GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \

drivers/net/ethernet/freescale/dpaa2/dpsw-cmd.h

109

(((var) >> (bit)) & GENMASK(0, 0))

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

101

#define PSICFGR2_NUM_MSIX GENMASK(5, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

117

#define PMCAPR_FP GENMASK(10, 9)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

128

#define PCR_PSPEED GENMASK(29, 16)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

146

#define PTCTMSDUR_MAXSDU GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

147

#define PTCTMSDUR_SDU_TYPE GENMASK(17, 16)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

160

#define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

19

#define SILSOSFMR0_TCP_MID_SEG GENMASK(27, 16)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

195

#define PM_SINGLE_STEP_OFFSET GENMASK(15, 7)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

20

#define SILSOSFMR0_TCP_1ST_SEG GENMASK(11, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

201

#define PM_IF_MODE_IFMODE GENMASK(2, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

209

#define PM_IF_MODE_SSP GENMASK(14, 13)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

25

#define SILSOSFMR1_TCP_LAST_SEG GENMASK(11, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

49

#define ECAPR1_NUM_TCS GENMASK(6, 4)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

50

#define ECAPR1_NUM_MCH GENMASK(9, 8)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

51

#define ECAPR1_NUM_UCH GENMASK(11, 10)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

52

#define ECAPR1_NUM_MSIX GENMASK(22, 12)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

53

#define ECAPR1_NUM_VSI GENMASK(27, 24)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

57

#define ECAPR2_NUM_TX_BDR GENMASK(9, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

58

#define ECAPR2_NUM_RX_BDR GENMASK(25, 16)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

80

#define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0)

drivers/net/ethernet/freescale/enetc/enetc4_hw.h

84

#define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

1041

#define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

143

#define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

167

#define ENETC_PMR_EN GENMASK(18, 16)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

168

#define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

212

#define ENETC_CBS_BW_MASK GENMASK(6, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

236

#define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */

drivers/net/ethernet/freescale/enetc/enetc_hw.h

239

#define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */

drivers/net/ethernet/freescale/enetc/enetc_hw.h

241

#define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */

drivers/net/ethernet/freescale/enetc/enetc_hw.h

245

#define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */

drivers/net/ethernet/freescale/enetc/enetc_hw.h

248

#define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */

drivers/net/ethernet/freescale/enetc/enetc_hw.h

292

#define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

297

#define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

301

#define ENETC_PSIDCAPR_MSK GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

303

#define ENETC_PSFCAPR_MSK GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

305

#define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

306

#define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

308

#define ENETC_PFMCAPR_MSK GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

378

#define EIPBRR0_REVISION GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

48

#define SICVLANR_ETYPE GENMASK(15, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

571

#define ENETC_TX_BD_L3_START GENMASK(6, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

574

#define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

577

#define ENETC_TX_BD_L4T GENMASK(7, 5)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

59

#define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

616

#define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

618

#define ENETC_TXBD_TSTAMP GENMASK(29, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

671

#define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

97

#define ENETC_PSIIER_MR_MASK GENMASK(2, 1)

drivers/net/ethernet/freescale/enetc/enetc_hw.h

978

#define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)

drivers/net/ethernet/freescale/enetc/enetc_mdio.c

20

#define MDIO_CFG_HOLD(x) (((x) << 2) & GENMASK(4, 2))

drivers/net/ethernet/freescale/enetc/enetc_qos.c

395

FILTER_ACTION_TYPE_BOTH = GENMASK(1, 0),

drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c

35

#define CFG_LINK_MII_PORT_0 GENMASK(3, 0)

drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c

36

#define CFG_LINK_MII_PORT_1 GENMASK(7, 4)

drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c

54

#define NETC_LINK_CFG_MII_PROT GENMASK(3, 0)

drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c

55

#define NETC_LINK_CFG_IO_VAR GENMASK(19, 16)

drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c

75

#define FAUXR_LDID GENMASK(3, 0)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

20

#define NTMP_RESP_LEN GENMASK(19, 0)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

21

#define NTMP_REQ_LEN GENMASK(31, 20)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

31

#define NTMP_ACCESS_METHOD GENMASK(7, 4)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

38

#define NTMP_HDR_VERSION GENMASK(5, 0)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

51

#define NTMP_RESP_ERROR GENMASK(11, 0)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

68

#define NTMP_QUERY_ACT GENMASK(3, 0)

drivers/net/ethernet/freescale/enetc/ntmp_private.h

69

#define NTMP_TBL_VER GENMASK(7, 4)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

144

#define HBG_REG_FIFO_THRSLD_FULL_M GENMASK(25, 16)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

145

#define HBG_REG_FIFO_THRSLD_EMPTY_M GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

147

#define HBG_REG_CFG_FIFO_THRSLD_TX_FULL_M GENMASK(31, 24)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

148

#define HBG_REG_CFG_FIFO_THRSLD_TX_EMPTY_M GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

149

#define HBG_REG_CFG_FIFO_THRSLD_RX_FULL_M GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

150

#define HBG_REG_CFG_FIFO_THRSLD_RX_EMPTY_M GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

176

#define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

183

#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

184

#define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M GENMASK(24, 16)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

197

#define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

199

#define HBG_REG_BUS_CTRL_ENDIAN_M GENMASK(2, 1)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

201

#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M GENMASK(31, 28)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

203

#define HBG_REG_RX_CTRL_RX_ALIGN_NUM_M GENMASK(18, 17)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

204

#define HBG_REG_RX_CTRL_PORT_NUM GENMASK(16, 13)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

206

#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

208

#define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

23

#define HBG_REG_MSG_HEADER_OPCODE_M GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

238

#define HBG_TX_DESC_W0_IP_OFF_M GENMASK(30, 26)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

24

#define HBG_REG_MSG_HEADER_STATUS_M GENMASK(11, 8)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

242

#define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

25

#define HBG_REG_MSG_HEADER_DATA_NUM_M GENMASK(19, 12)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

253

#define HBG_RX_DESC_W2_PKT_LEN_M GENMASK(31, 16)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

254

#define HBG_RX_DESC_W2_PORT_NUM_M GENMASK(15, 12)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

255

#define HBG_RX_DESC_W3_IP_OFFSET_M GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

256

#define HBG_RX_DESC_W3_VLAN_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

257

#define HBG_RX_DESC_W4_IP_TCP_UDP_M GENMASK(31, 30)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

26

#define HBG_REG_MSG_HEADER_RESP_CODE_M GENMASK(27, 20)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

260

#define HBG_RX_DESC_W4_L4_ERR_CODE_M GENMASK(26, 23)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

271

#define HBG_RX_DESC_W4_L3_ERR_CODE_M GENMASK(12, 9)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

274

#define HBG_RX_DESC_W4_PARSE_MODE_M GENMASK(6, 5)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

275

#define HBG_RX_DESC_W5_VALID_SIZE_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

36

#define HBG_REG_MDIO_COMMAND_ST_M GENMASK(13, 12)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

37

#define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

38

#define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

39

#define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

42

#define HBG_REG_MDIO_WDATA_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h

56

#define HBG_REG_PORT_MODE_M GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hisi_femac.c

28

#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)

drivers/net/ethernet/hisilicon/hisi_femac.c

40

#define RX_FRAME_LEN_MASK GENMASK(11, 0)

drivers/net/ethernet/hisilicon/hisi_femac.c

45

#define TX_CNT_INUSE_MASK GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hisi_femac.c

64

#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hisi_femac.c

77

#define MACFLT_HI16_MASK GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

360

#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

365

#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

367

#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

369

#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

371

#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

374

#define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

376

#define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

378

#define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hns3/hnae3.h

380

#define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

15

#define HCLGE_COMM_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

16

#define HCLGE_COMM_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

28

#define HCLGE_COMM_RSS_TC_OFFSET_M GENMASK(10, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

31

#define HCLGE_COMM_RSS_TC_SIZE_M GENMASK(14, 12)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

51

#define HCLGE_COMM_RSS_SET_BITMAP_MSK GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h

52

#define HCLGE_COMM_RSS_HASH_ALGO_MASK GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

122

#define HNS3_RXD_PTYPE_M GENMASK(11, 4)

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

199

#define HNS3_VECTOR_GL_MASK GENMASK(11, 0)

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

205

#define HNS3_VECTOR_QL_MASK GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

188

#define HCLGE_CFG_OFFSET_M GENMASK(19, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

190

#define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

195

#define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

197

#define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

199

#define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

201

#define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

203

#define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

205

#define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

207

#define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

209

#define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

211

#define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

213

#define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

215

#define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

217

#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

219

#define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

221

#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

246

#define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

249

#define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

315

#define HCLGE_CFG_SPEED_M GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

360

#define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

413

#define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

415

#define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

605

#define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

608

#define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

63

#define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

67

#define HCLGE_INT_TYPE_M GENMASK(1, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

673

#define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

69

#define HCLGE_TQP_ID_M GENMASK(12, 2)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

71

#define HCLGE_INT_GL_IDX_M GENMASK(14, 13)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

732

#define HCLGE_FD_AD_QID_L_M GENMASK(11, 2)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

735

#define HCLGE_FD_AD_COUNTER_NUM_L_M GENMASK(19, 13)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

738

#define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

741

#define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

744

#define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

75

#define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

765

#define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

958

#define HCLGE_MAC_SPEED_MASK GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

100

#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

101

#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

109

#define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

61

#define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

62

#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

63

#define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

64

#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

65

#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

66

#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

67

#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

72

#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

73

#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

74

#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

75

#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

76

#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

77

#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

78

#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

79

#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

82

#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

83

#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

86

#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

87

#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

89

#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

91

#define HCLGE_IGU_INT_MASK GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

92

#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

93

#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

94

#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

99

#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

5810

GENMASK(cur_pos + tuple_size, cur_pos),

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

116

#define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

138

#define HCLGE_PF_ID_M GENMASK(2, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

140

#define HCLGE_VF_ID_M GENMASK(10, 3)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

143

#define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

153

#define HCLGE_RESET_INT_M GENMASK(7, 5)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

645

#define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

646

#define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

647

#define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

113

#define HCLGE_PTP_UDP_EN_MASK GENMASK(4, 3)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

115

#define HCLGE_PTP_MSG_TYPE_MASK GENMASK(9, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

117

#define HCLGE_PTP_MSG1_MASK GENMASK(19, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

119

#define HCLGE_PTP_MSG0_MASK GENMASK(27, 24)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

18

#define HCLGE_PTP_TX_TS_NSEC_MASK GENMASK(29, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

21

#define HCLGE_PTP_TX_TS_SEC_H_MASK GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

25

#define HCLGE_PTP_TIME_SEC_H_MASK GENMASK(15, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

35

#define HCLGE_PTP_CYCLE_QUO_MASK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h

46

#define HCLGE_PTP_SEC_L_MASK GENMASK(31, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

106

#define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

108

#define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

110

#define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

112

#define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

114

#define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

154

#define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

156

#define HCLGE_BP_GRP_ID_M GENMASK(9, 5)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

160

#define HCLGE_BP_EXT_GRP_ID_M GENMASK(10, 5)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

57

#define HCLGE_TM_QS_ID_L_MSK GENMASK(9, 0)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

59

#define HCLGE_TM_QS_ID_H_MSK GENMASK(14, 10)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

62

#define HCLGE_TM_QS_ID_H_EXT_MSK GENMASK(15, 11)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

30

#define CMDQ_WQE_HDR_BUFDESC_LEN_MASK GENMASK(7, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

34

#define CMDQ_WQE_HDR_COMPLETE_SECT_LEN_MASK GENMASK(28, 27)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

35

#define CMDQ_WQE_HDR_CTRL_LEN_MASK GENMASK(30, 29)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

42

#define CMDQ_CTRL_PI_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

43

#define CMDQ_CTRL_CMD_MASK GENMASK(23, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

44

#define CMDQ_CTRL_MOD_MASK GENMASK(28, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

51

#define CMDQ_WQE_ERRCODE_VAL_MASK GENMASK(30, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

55

#define CMDQ_DB_INFO_HI_PROD_IDX_MASK GENMASK(7, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

60

#define CMDQ_DB_HEAD_CMDQ_TYPE_MASK GENMASK(26, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

64

#define CMDQ_CEQE_TYPE_MASK GENMASK(2, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_csr.h

44

#define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK GENMASK(31, 22)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

12

#define AEQ_CTRL_0_INTR_IDX_MASK GENMASK(9, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

13

#define AEQ_CTRL_0_DMA_ATTR_MASK GENMASK(17, 12)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

14

#define AEQ_CTRL_0_PCI_INTF_IDX_MASK GENMASK(22, 20)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

19

#define AEQ_CTRL_1_LEN_MASK GENMASK(20, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

20

#define AEQ_CTRL_1_ELEM_SIZE_MASK GENMASK(25, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

21

#define AEQ_CTRL_1_PAGE_SIZE_MASK GENMASK(31, 28)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

25

#define CEQ_CTRL_0_INTR_IDX_MASK GENMASK(9, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

26

#define CEQ_CTRL_0_DMA_ATTR_MASK GENMASK(17, 12)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

27

#define CEQ_CTRL_0_LIMIT_KICK_MASK GENMASK(23, 20)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

28

#define CEQ_CTRL_0_PCI_INTF_IDX_MASK GENMASK(25, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

29

#define CEQ_CTRL_0_PAGE_SIZE_MASK GENMASK(30, 27)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

34

#define CEQ_CTRL_1_LEN_MASK GENMASK(19, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

38

#define CEQE_TYPE_MASK GENMASK(25, 23)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

42

#define CEQE_DATA_MASK GENMASK(25, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

45

#define EQ_ELEM_DESC_TYPE_MASK GENMASK(6, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

47

#define EQ_ELEM_DESC_SIZE_MASK GENMASK(15, 8)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

52

#define EQ_CI_SIMPLE_INDIR_CI_MASK GENMASK(20, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

54

#define EQ_CI_SIMPLE_INDIR_AEQ_IDX_MASK GENMASK(31, 30)

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

55

#define EQ_CI_SIMPLE_INDIR_CEQ_IDX_MASK GENMASK(31, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

18

#define HINIC3_DMA_ATTR_INDIR_IDX_MASK GENMASK(9, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

22

#define HINIC3_DMA_ATTR_ENTRY_ST_MASK GENMASK(7, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

23

#define HINIC3_DMA_ATTR_ENTRY_AT_MASK GENMASK(9, 8)

drivers/net/ethernet/huawei/hinic3/hinic3_hwdev.c

24

#define HINIC3_DMA_ATTR_ENTRY_PH_MASK GENMASK(11, 10)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

27

#define HINIC3_AF0_FUNC_GLOBAL_IDX_MASK GENMASK(11, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

28

#define HINIC3_AF0_P2P_IDX_MASK GENMASK(16, 12)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

29

#define HINIC3_AF0_PCI_INTF_IDX_MASK GENMASK(19, 17)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

34

#define HINIC3_AF1_PPF_IDX_MASK GENMASK(5, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

35

#define HINIC3_AF1_AEQS_PER_FUNC_MASK GENMASK(9, 8)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

40

#define HINIC3_AF2_CEQS_PER_FUNC_MASK GENMASK(8, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

41

#define HINIC3_AF2_IRQS_PER_FUNC_MASK GENMASK(26, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

45

#define HINIC3_AF3_GLOBAL_VF_ID_OF_PF_MASK GENMASK(27, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

59

#define HINIC3_AF6_PF_STATUS_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

60

#define HINIC3_AF6_FUNC_MAX_SQ_MASK GENMASK(31, 23)

drivers/net/ethernet/huawei/hinic3/hinic3_hwif.c

67

#define HINIC3_PPF_ELECTION_IDX_MASK GENMASK(5, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

12

#define MBOX_INT_DST_AEQN_MASK GENMASK(11, 10)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

13

#define MBOX_INT_SRC_RESP_AEQN_MASK GENMASK(13, 12)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

14

#define MBOX_INT_STAT_DMA_MASK GENMASK(19, 14)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

16

#define MBOX_INT_TX_SIZE_MASK GENMASK(24, 20)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

18

#define MBOX_INT_STAT_DMA_SO_RO_MASK GENMASK(26, 25)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

25

#define MBOX_CTRL_DST_FUNC_MASK GENMASK(28, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

68

#define MBOX_MQ_SYNC_CI_MASK GENMASK(7, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c

69

#define MBOX_MQ_ASYNC_CI_MASK GENMASK(15, 8)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

120

#define SQ_CTXT_PI_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

121

#define SQ_CTXT_CI_IDX_MASK GENMASK(31, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

130

#define SQ_CTXT_WQ_PAGE_HI_PFN_MASK GENMASK(19, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

135

#define SQ_CTXT_PKT_DROP_THD_ON_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

136

#define SQ_CTXT_PKT_DROP_THD_OFF_MASK GENMASK(31, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

140

#define SQ_CTXT_GLOBAL_SQ_ID_MASK GENMASK(12, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

144

#define SQ_CTXT_VLAN_INSERT_MODE_MASK GENMASK(20, 19)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

149

#define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK GENMASK(13, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

150

#define SQ_CTXT_PREF_CACHE_MAX_MASK GENMASK(24, 14)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

151

#define SQ_CTXT_PREF_CACHE_MIN_MASK GENMASK(31, 25)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

153

#define SQ_CTXT_PREF_CI_HI_MASK GENMASK(3, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

156

#define SQ_CTXT_PREF_WQ_PFN_HI_MASK GENMASK(19, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

157

#define SQ_CTXT_PREF_CI_LOW_MASK GENMASK(31, 20)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

161

#define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK GENMASK(22, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

168

#define RQ_CTXT_PI_IDX_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

169

#define RQ_CTXT_CI_IDX_MASK GENMASK(31, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

173

#define RQ_CTXT_CEQ_ATTR_INTR_MASK GENMASK(30, 21)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

178

#define RQ_CTXT_WQ_PAGE_HI_PFN_MASK GENMASK(19, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

179

#define RQ_CTXT_WQ_PAGE_WQE_TYPE_MASK GENMASK(29, 28)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

184

#define RQ_CTXT_CQE_LEN_MASK GENMASK(29, 28)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

188

#define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK GENMASK(13, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

189

#define RQ_CTXT_PREF_CACHE_MAX_MASK GENMASK(24, 14)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

190

#define RQ_CTXT_PREF_CACHE_MIN_MASK GENMASK(31, 25)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

192

#define RQ_CTXT_PREF_CI_HI_MASK GENMASK(3, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

195

#define RQ_CTXT_PREF_WQ_PFN_HI_MASK GENMASK(19, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

196

#define RQ_CTXT_PREF_CI_LOW_MASK GENMASK(31, 20)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

200

#define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK GENMASK(22, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

58

#define DB_INFO_QID_MASK GENMASK(12, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

60

#define DB_INFO_COS_MASK GENMASK(26, 24)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

61

#define DB_INFO_TYPE_MASK GENMASK(31, 27)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

11

#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK GENMASK(4, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

12

#define RQ_CQE_OFFOLAD_TYPE_IP_TYPE_MASK GENMASK(6, 5)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

13

#define RQ_CQE_OFFOLAD_TYPE_TUNNEL_PKT_FORMAT_MASK GENMASK(11, 8)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

18

#define RQ_CQE_SGE_VLAN_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

19

#define RQ_CQE_SGE_LEN_MASK GENMASK(31, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

23

#define RQ_CQE_STATUS_CSUM_ERR_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_rx.h

24

#define RQ_CQE_STATUS_NUM_LRO_MASK GENMASK(23, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

44

#define SQ_CTRL_BUFDESC_NUM_MASK GENMASK(26, 19)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

52

#define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK GENMASK(9, 2)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

55

#define SQ_CTRL_QUEUE_INFO_MSS_MASK GENMASK(26, 13)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

73

#define SQ_TASK_INFO3_VLAN_TAG_MASK GENMASK(15, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_tx.h

74

#define SQ_TASK_INFO3_VLAN_TPID_MASK GENMASK(18, 16)

drivers/net/ethernet/intel/i40e/i40e.h

59

#define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0)

drivers/net/ethernet/intel/i40e/i40e.h

60

#define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12)

drivers/net/ethernet/intel/i40e/i40e.h

61

#define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8)

drivers/net/ethernet/intel/i40e/i40e.h

62

#define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0)

drivers/net/ethernet/intel/i40e/i40e.h

63

#define I40E_OEM_VER_MASK GENMASK(31, 24)

drivers/net/ethernet/intel/i40e/i40e.h

64

#define I40E_OEM_GEN_MASK GENMASK(31, 24)

drivers/net/ethernet/intel/i40e/i40e.h

65

#define I40E_OEM_SNAP_MASK GENMASK(23, 16)

drivers/net/ethernet/intel/i40e/i40e.h

66

#define I40E_OEM_RELEASE_MASK GENMASK(15, 0)

drivers/net/ethernet/intel/iavf/iavf_ethtool.c

861

#define IAVF_USERDEF_FLEX_WORD_M GENMASK(15, 0)

drivers/net/ethernet/intel/iavf/iavf_ethtool.c

863

#define IAVF_USERDEF_FLEX_OFFS_M GENMASK(31, IAVF_USERDEF_FLEX_OFFS_S)

drivers/net/ethernet/intel/iavf/iavf_ethtool.c

864

#define IAVF_USERDEF_FLEX_FLTR_M GENMASK(31, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1513

#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1541

#define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1546

#define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1550

#define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1560

#define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1563

#define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1670

#define ICE_AQC_NVM_SDP_AC_PTR_M GENMASK(14, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1673

#define ICE_AQC_NVM_SDP_AC_SDP_NUM_M GENMASK(2, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1675

#define ICE_AQC_NVM_SDP_AC_PIN_M GENMASK(15, 6)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1794

#define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

1957

ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4),

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

2067

#define ICE_AQC_Q_CFG_MODE_M GENMASK(7, 6)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

2222

#define ICE_AQC_GET_CGU_MAX_PHASE_ADJ GENMASK(30, 0)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

412

#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

800

#define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

802

#define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4)

drivers/net/ethernet/intel/ice/ice_common.h

43

#define ICE_CGU_R9_TIME_REF_FREQ_SEL GENMASK(2, 0)

drivers/net/ethernet/intel/ice/ice_common.h

48

#define ICE_CGU_R9_ONE_PPS_OUT_AMP GENMASK(19, 18)

drivers/net/ethernet/intel/ice/ice_common.h

51

#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ GENMASK(31, 24)

drivers/net/ethernet/intel/ice/ice_common.h

54

#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_common.h

55

#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 GENMASK(9, 0)

drivers/net/ethernet/intel/ice/ice_common.h

56

#define ICE_CGU_R19_TSPLL_NDIVRATIO GENMASK(19, 16)

drivers/net/ethernet/intel/ice/ice_common.h

59

#define ICE_CGU_R22_TIME1588CLK_DIV GENMASK(23, 20)

drivers/net/ethernet/intel/ice/ice_common.h

64

#define ICE_CGU_R24_FBDIV_FRAC GENMASK(21, 0)

drivers/net/ethernet/intel/ice/ice_common.h

66

#define ICE_CGU_R23_R24_REF1588_CK_DIV GENMASK(30, 27)

drivers/net/ethernet/intel/ice/ice_common.h

70

#define ICE_CGU_BW_TDC_PLLLOCK_SEL GENMASK(30, 29)

drivers/net/ethernet/intel/ice/ice_dpll.h

162

#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)

drivers/net/ethernet/intel/ice/ice_dpll.h

163

#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)

drivers/net/ethernet/intel/ice/ice_dpll.h

166

#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)

drivers/net/ethernet/intel/ice/ice_dpll.h

167

#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)

drivers/net/ethernet/intel/ice/ice_dpll.h

170

#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)

drivers/net/ethernet/intel/ice/ice_dpll.h

173

#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)

drivers/net/ethernet/intel/ice/ice_flow.c

1635

#define HI_BYTE_IN_WORD GENMASK(15, 8)

drivers/net/ethernet/intel/ice/ice_flow.c

1636

#define LO_BYTE_IN_WORD GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

193

#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M GENMASK(1, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

278

#define PFLAN_TX_QALLOC_FIRSTQ_M GENMASK(13, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

308

#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

310

#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

365

#define E800_GL_MNG_FWSM_FW_MODES_M GENMASK(2, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

366

#define E830_GL_MNG_FWSM_FW_MODES_M GENMASK(1, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

384

#define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M GENMASK(13, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

385

#define GLCOMM_QTX_CNTX_CTL_CMD_M GENMASK(18, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

404

#define E800_GLQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

405

#define E830_GLQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

407

#define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

408

#define E830_GLQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

411

#define E800_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(14, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

412

#define E830_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

414

#define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

415

#define E830_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(31, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

438

#define E800_PFQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

439

#define E830_PFQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

440

#define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

441

#define E830_PFQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

541

#define E800_VSIQF_FD_CNT_FD_GCNT_M GENMASK(13, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

542

#define E830_VSIQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

544

#define E800_VSIQF_FD_CNT_FD_BCNT_M GENMASK(29, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

545

#define E830_VSIQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

560

#define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

562

#define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

346

#define ICE_RX_FLEX_DESC_HDR_LEN_M GENMASK(10, 0)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

488

#define ICE_TX_GCS_DESC_START_M GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

489

#define ICE_TX_GCS_DESC_OFFSET_M GENMASK(11, 8)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

490

#define ICE_TX_GCS_DESC_TYPE_M GENMASK(14, 12)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

575

#define ICE_TXTIME_TX_DESC_IDX_M GENMASK(12, 0)

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

576

#define ICE_TXTIME_STAMP_M GENMASK(31, 13)

drivers/net/ethernet/intel/ice/ice_parser.c

1275

#define ICE_BST_NPKB_OPC GENMASK(1, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

1276

#define ICE_BST_NPKB_S_R0 GENMASK(9, 2)

drivers/net/ethernet/intel/ice/ice_parser.c

1277

#define ICE_BST_NPKB_L_R1 GENMASK(17, 10)

drivers/net/ethernet/intel/ice/ice_parser.c

1299

#define ICE_BT_PGP_M GENMASK(361 - ICE_BT_PGP_S, 360 - ICE_BT_PGP_S)

drivers/net/ethernet/intel/ice/ice_parser.c

1588

#define ICE_PO_PID GENMASK(8, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

1589

#define ICE_PO_OFF GENMASK(21, 12)

drivers/net/ethernet/intel/ice/ice_parser.c

1663

#define ICE_FRT_IFID GENMASK(6, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

244

#define ICE_IM_BKB_PRIO GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

258

#define ICE_IM_NPKB_OPC GENMASK(1, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

259

#define ICE_IM_NPKB_S_R0 GENMASK(9, 2)

drivers/net/ethernet/intel/ice/ice_parser.c

260

#define ICE_IM_NPKB_L_R1 GENMASK(17, 10)

drivers/net/ethernet/intel/ice/ice_parser.c

369

#define ICE_IMEM_PGP GENMASK(15, 14)

drivers/net/ethernet/intel/ice/ice_protocol_type.h

297

#define ICE_MDID_SOURCE_VSI_MASK GENMASK(9, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

130

#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

131

#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

498

#define P_REG_40B_LOW_M GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

617

#define PHY_EXT_40B_LOW_M GENMASK(31, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

619

#define PHY_40B_LOW_M GENMASK(7, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

631

#define REG_LL_PROXY_H_PHY_TMR_CMD_M GENMASK(7, 6)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

634

#define REG_LL_PROXY_H_TS_HIGH GENMASK(23, 16)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

636

#define REG_LL_PROXY_H_TS_IDX GENMASK(29, 24)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

745

#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

746

#define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

748

#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

776

#define PHY_GPCS_CONFIG_REG0_TX_THR_M GENMASK(27, 24)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

779

#define PHY_PTP_1STEP_T1S_UP64_M GENMASK(7, 4)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

780

#define PHY_PTP_1STEP_T1S_DELTA_M GENMASK(11, 8)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

783

#define PHY_PTP_1STEP_PD_DELAY_M GENMASK(30, 1)

drivers/net/ethernet/intel/ice/ice_type.h

401

#define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)

drivers/net/ethernet/intel/idpf/idpf.h

31

#define GETMAXVAL(num_bits) GENMASK((num_bits) - 1, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

103

#define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

108

#define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

110

#define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

112

#define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

124

#define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

24

#define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

35

#define PF_FW_ARQH_ARQH_M GENMASK(12, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

42

#define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

53

#define PF_FW_ATQH_ATQH_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

57

#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M GENMASK(1, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

70

#define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

91

#define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_pf_regs.h

96

#define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

173

IDPF_TX_DESC_CMD_IIPT_IPV4_CSUM = GENMASK(6, 5),

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

177

IDPF_TX_DESC_CMD_L4T_EOFT_UDP = GENMASK(9, 8),

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

230

#define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

232

#define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

249

#define IDPF_TXD_FLEX_FLOW_DTYPE_M GENMASK(4, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

261

#define IDPF_TXD_FLEX_FLOW_BUFSIZE_M GENMASK(13, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

275

IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI = GENMASK(10, 9),

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

281

#define IDPF_TXD_FLEX_CTX_TLEN_M GENMASK(17, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

284

#define IDPF_TXD_FLEX_CTX_MSS_RT_M GENMASK(13, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

10

#define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

114

#define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

19

#define VF_ATQLEN_ATQLEN_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

30

#define VF_ATQH_ATQH_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

37

#define VF_ARQLEN_ARQLEN_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

48

#define VF_ARQH_ARQH_M GENMASK(12, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

70

#define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3)

drivers/net/ethernet/intel/idpf/idpf_lan_vf_regs.h

80

#define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3)

drivers/net/ethernet/intel/idpf/idpf_txrx.h

117

#define IDPF_RFL_BI_BUFID_M GENMASK(15, 0)

drivers/net/ethernet/intel/idpf/idpf_virtchnl.h

10

#define IDPF_VC_XN_IDX_M GENMASK(7, 0)

drivers/net/ethernet/intel/idpf/idpf_virtchnl.h

11

#define IDPF_VC_XN_SALT_M GENMASK(15, 8)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

113

VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_RSVD_M = GENMASK(1, 0),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

125

#define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

128

#define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M GENMASK(13, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

152

VIRTCHNL2_RX_FLEX_DESC_STATUS1_CPM_M = GENMASK(3, 0),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

179

VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD_M = GENMASK(7, 5),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

181

VIRTCHNL2_RX_BASE_DESC_STATUS_UMBCAST_M = GENMASK(10, 9),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

183

VIRTCHNL2_RX_BASE_DESC_STATUS_FLTSTAT_M = GENMASK(13, 12),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

186

VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD1_M = GENMASK(17, 16),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

195

VIRTCHNL2_RX_BASE_DESC_ERROR_L3L4E_M = GENMASK(5, 3),

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

204

#define VIRTCHNL2_RX_BASE_DESC_FLTSTAT_RSS_HASH_M GENMASK(13, 12)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

60

#define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M GENMASK(3, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

61

#define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M GENMASK(7, 6)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

62

#define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

66

#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M GENMASK(15, 13)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

67

#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M GENMASK(13, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

74

#define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M GENMASK(9, 0)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

82

#define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M GENMASK(14, 12)

drivers/net/ethernet/intel/idpf/xdp.c

245

if (unlikely((val & GENMASK(IDPF_TXD_COMPLQ_GEN_S - 1, 0)) !=

drivers/net/ethernet/intel/igb/igb_ptp.c

67

#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)

drivers/net/ethernet/intel/igbvf/netdev.c

993

adapter->eims_enable_mask = GENMASK(vector - 1, 0);

drivers/net/ethernet/intel/igc/igc.h

425

#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */

drivers/net/ethernet/intel/igc/igc.h

496

#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0)

drivers/net/ethernet/intel/igc/igc.h

497

#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8)

drivers/net/ethernet/intel/igc/igc.h

498

#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16)

drivers/net/ethernet/intel/igc/igc.h

499

#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25)

drivers/net/ethernet/intel/igc/igc.h

500

#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26)

drivers/net/ethernet/intel/igc/igc.h

501

#define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27)

drivers/net/ethernet/intel/igc/igc_base.h

90

#define IGC_SRRCTL_BSIZEPKT_MASK GENMASK(6, 0)

drivers/net/ethernet/intel/igc/igc_base.h

93

#define IGC_SRRCTL_BSIZEHDR_MASK GENMASK(13, 8)

drivers/net/ethernet/intel/igc/igc_base.h

96

#define IGC_SRRCTL_DESCTYPE_MASK GENMASK(27, 25)

drivers/net/ethernet/intel/igc/igc_defines.h

37

#define IGC_WUFC_FILTER_MASK GENMASK(23, 14)

drivers/net/ethernet/intel/igc/igc_defines.h

394

#define IGC_MRQC_DEFAULT_QUEUE_MASK GENMASK(5, 3)

drivers/net/ethernet/intel/igc/igc_defines.h

409

#define IGC_RXPBSIZE_EXP_MASK GENMASK(5, 0)

drivers/net/ethernet/intel/igc/igc_defines.h

410

#define IGC_BMC2OSPBSIZE_MASK GENMASK(11, 6)

drivers/net/ethernet/intel/igc/igc_defines.h

411

#define IGC_RXPBSIZE_BE_MASK GENMASK(17, 12)

drivers/net/ethernet/intel/igc/igc_defines.h

413

#define IGC_RXPBS_CFG_TS_EN_MASK GENMASK(31, 31)

drivers/net/ethernet/intel/igc/igc_defines.h

429

#define IGC_TXPB0SIZE_MASK GENMASK(5, 0)

drivers/net/ethernet/intel/igc/igc_defines.h

430

#define IGC_TXPB1SIZE_MASK GENMASK(11, 6)

drivers/net/ethernet/intel/igc/igc_defines.h

431

#define IGC_TXPB2SIZE_MASK GENMASK(17, 12)

drivers/net/ethernet/intel/igc/igc_defines.h

432

#define IGC_TXPB3SIZE_MASK GENMASK(23, 18)

drivers/net/ethernet/intel/igc/igc_defines.h

434

#define IGC_OS2BMCPBSIZE_MASK GENMASK(29, 24)

drivers/net/ethernet/intel/igc/igc_defines.h

606

#define IGC_TXARB_TXQ_PRIO_0_MASK GENMASK(1, 0)

drivers/net/ethernet/intel/igc/igc_defines.h

607

#define IGC_TXARB_TXQ_PRIO_1_MASK GENMASK(3, 2)

drivers/net/ethernet/intel/igc/igc_defines.h

608

#define IGC_TXARB_TXQ_PRIO_2_MASK GENMASK(5, 4)

drivers/net/ethernet/intel/igc/igc_defines.h

609

#define IGC_TXARB_TXQ_PRIO_3_MASK GENMASK(7, 6)

drivers/net/ethernet/intel/igc/igc_defines.h

648

#define IGC_PTM_STAT_ALL GENMASK(5, 0) /* Used to clear all status */

drivers/net/ethernet/intel/igc/igc_defines.h

88

#define IGC_WUFC_EXT_FILTER_MASK GENMASK(31, 8)

drivers/net/ethernet/intel/igc/igc_leds.c

15

#define IGC_LEDCTL_LED0_MODE_MASK GENMASK(3, 0)

drivers/net/ethernet/intel/igc/igc_leds.c

18

#define IGC_LEDCTL_LED1_MODE_MASK GENMASK(11, 8)

drivers/net/ethernet/intel/igc/igc_leds.c

21

#define IGC_LEDCTL_LED2_MODE_MASK GENMASK(19, 16)

drivers/net/ethernet/intel/igc/igc_main.c

3683

tmp &= ~GENMASK(7, 0);

drivers/net/ethernet/intel/igc/igc_regs.h

80

#define IGC_FHFT_LENGTH_MASK GENMASK(7, 0)

drivers/net/ethernet/intel/igc/igc_regs.h

82

#define IGC_FHFT_QUEUE_MASK GENMASK(10, 8)

drivers/net/ethernet/intel/igc/igc_regs.h

84

#define IGC_FHFT_PRIO_MASK GENMASK(18, 16)

drivers/net/ethernet/intel/igc/igc_regs.h

90

#define IGC_FHFTSL_FTSL_MASK GENMASK(1, 0)

drivers/net/ethernet/intel/igc/igc_tsn.c

186

queue |= GENMASK(offset + count - 1, offset);

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

3781

IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), GENMASK(18, 17));

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

781

#define IXGBE_CAPS_VALID_FUNCS_M GENMASK(7, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4652

IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

4654

IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

1080

bus->phy_mask = GENMASK(31, 0);

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

697

hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

706

data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

744

data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

771

hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

2766

#define IXGBE_16VFS_BITMASK GENMASK(IXGBE_16VFS_QUEUES - 1, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

2767

#define IXGBE_32VFS_BITMASK GENMASK(IXGBE_32VFS_QUEUES - 1, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

2768

#define IXGBE_64VFS_BITMASK GENMASK(IXGBE_64VFS_QUEUES - 1, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

3003

#define IXGBE_ADVTXD_MSS_MASK GENMASK(31, IXGBE_ADVTXD_MSS_SHIFT)

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

3004

#define IXGBE_ADVTXD_HEADER_LEN_MASK GENMASK(8, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

103

#define IXGBE_SR_CTRL_WORD_1_M GENMASK(7, 6)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

17

#define IXGBE_E610_SR_PBA_BLOCK_MASK GENMASK(15, 8)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

21

#define IXGBE_E610_NVM_VER_LO_MASK GENMASK(7, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

22

#define IXGBE_E610_NVM_VER_HI_MASK GENMASK(15, 12)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

249

#define IXGBE_ACI_REPORT_MODE_M GENMASK(3, 1)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

316

#define IXGBE_ACI_PHY_CAPS_MASK GENMASK(7, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

417

#define IXGBE_ACI_LSE_M GENMASK(1, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

481

#define IXGBE_ACI_FEC_MASK GENMASK(2, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

483

#define IXGBE_ACI_CFG_PACING_M GENMASK(6, 3)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

489

#define IXGBE_ACI_PWR_CLASS_M GENMASK(5, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

497

#define IXGBE_ACI_LINK_SPEED_M GENMASK(10, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

563

#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M GENMASK(3, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

577

#define IXGBE_ACI_LINK_TOPO_NODE_CTX_M GENMASK(7, 4)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

661

#define IXGBE_ACI_SFF_I2CBUS_7BIT_M GENMASK(6, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

662

#define IXGBE_ACI_SFF_I2CBUS_10BIT_M GENMASK(9, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

688

#define IXGBE_ACI_NVM_OFFSET_HI_A_MASK GENMASK(15, 8)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

689

#define IXGBE_ACI_NVM_OFFSET_HI_U_MASK GENMASK(23, 16)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

700

#define IXGBE_ACI_NVM_RESET_LVL_M GENMASK(1, 0) /* Write reply only */

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

827

#define IXGBE_MGMT_MODE_PASS_THRU_MODE_M GENMASK(3, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

828

#define IXGBE_MGMT_MODE_CTL_INTERFACE_M GENMASK(7, 4)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

829

#define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M GENMASK(11, 8)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

91

#define GLNVM_GENS_SR_SIZE_M GENMASK(7, 5)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

920

#define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M GENMASK(15, 8)

drivers/net/ethernet/marvell/mvmdio.c

156

return val & GENMASK(15, 0);

drivers/net/ethernet/marvell/mvmdio.c

213

return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

435

#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

485

#define MVPP2_GMAC_LPI_CTRL0_TS_MASK GENMASK(15, 8)

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

488

#define MVPP2_GMAC_LPI_CTRL1_TW_MASK GENMASK(15, 4)

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

87

#define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0)

drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c

48

GENMASK(sizeof(msg->hdr.s.msg_id) * BITS_PER_BYTE, 0);

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1726

#define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1727

#define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1729

#define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

1730

#define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

1304

rsp->cstm_etype[idx] = val & GENMASK(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

1310

rsp->cstm_etype[idx] = (val >> 0x1) & GENMASK(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

619

req->data0 &= GENMASK(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

657

req->data2 &= GENMASK(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

320

#define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)

drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c

837

free_dis = FIELD_GET(GENMASK(15, 0), intr_val);

drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c

855

alloc_dis = FIELD_GET(GENMASK(31, 16), intr_val);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5827

#define NIX_BW_PROF_HI_MASK GENMASK(10, 7)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

6034

aq_req->prof_mask.band_prof_id = GENMASK(6, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

6036

aq_req->prof_mask.band_prof_id_h = GENMASK(3, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

6045

#define NIX_RQ_PROF_HI_MASK GENMASK(13, 10)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

619

bpid = cfg & GENMASK(8, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

328

GENMASK(31, 0), 0, intf);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

345

GENMASK(31, 0), 0, intf);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

98

field_hash &= FIELD_GET(GENMASK(63, 32), rsp.hash_ctrl[intf][hash_idx]);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

99

field_hash += FIELD_GET(GENMASK(31, 0), rsp.hash_ctrl[intf][hash_idx]);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

342

aq->rq_mask.band_prof_id = GENMASK(9, 0);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

348

aq->rq_mask.band_prof_id_h = GENMASK(3, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

434

lso->field_mask = GENMASK(18, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c

168

cn10k_sq_aq->sq_mask.smq = GENMASK(9, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c

183

sq_aq->sq_mask.smq = GENMASK(8, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c

364

aq->cq_mask.bpid = GENMASK(8, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c

379

npa_aq->aura_mask.nix0_bpid = GENMASK(8, 0);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

1457

sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

1478

mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

1488

snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

30

#define OTX2_UNSUPP_LSE_DEPTH GENMASK(6, 4)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

11

#define PRESTERA_DSA_W0_CMD GENMASK(31, 30)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

13

#define PRESTERA_DSA_W0_DEV_NUM GENMASK(28, 24)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

14

#define PRESTERA_DSA_W0_PORT_NUM GENMASK(23, 19)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

15

#define PRESTERA_DSA_W0_VPT GENMASK(15, 13)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

17

#define PRESTERA_DSA_W0_VID GENMASK(11, 0)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

21

#define PRESTERA_DSA_W1_PORT_NUM GENMASK(11, 10)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

22

#define PRESTERA_DSA_W1_MASK_CPU_CODE GENMASK(7, 0)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

27

#define PRESTERA_DSA_W3_VID GENMASK(30, 27)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

28

#define PRESTERA_DSA_W3_DST_EPORT GENMASK(23, 7)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

29

#define PRESTERA_DSA_W3_DEV_NUM GENMASK(6, 0)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

31

#define PRESTERA_DSA_VID GENMASK(15, 12)

drivers/net/ethernet/marvell/prestera/prestera_dsa.c

32

#define PRESTERA_DSA_DEV_NUM GENMASK(11, 5)

drivers/net/ethernet/marvell/prestera/prestera_pci.c

167

#define PRESTERA_FW_EVT_CTL_STATUS_MASK GENMASK(1, 0)

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

139

u32p_replace_bits(&word, PRESTERA_SDMA_BUFF_SIZE_MAX, GENMASK(15, 0));

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

28

((le32_to_cpu((desc)->word2) >> 16) & GENMASK(13, 0))

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

283

qmask = GENMASK(qnum - 1, 0);

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

326

GENMASK(9, 2));

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

340

GENMASK(15, 8));

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

376

GENMASK(15, 8));

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

423

GENMASK(7, 0));

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c

448

u32p_replace_bits(&word, len + ETH_FCS_LEN, GENMASK(30, 16));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

2354

unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4018

oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4019

!(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4020

!(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4034

gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4035

gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4036

gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4037

gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4052

oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4053

cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));

drivers/net/ethernet/mediatek/mtk_eth_soc.c

4054

adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&

drivers/net/ethernet/mediatek/mtk_eth_soc.h

210

#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

215

#define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

252

#define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

255

#define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

257

#define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

258

#define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

259

#define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

26

#define MTK_DSA_PORT_MASK GENMASK(2, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

261

#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

262

#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

345

#define TX_DMA_PQID GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

346

#define TX_DMA_ADDR64_MASK GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

366

#define RX_DMA_ADDR64_MASK GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

381

#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

382

#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

383

#define MTK_RXD4_SRC_PORT GENMASK(21, 19)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

384

#define MTK_RXD4_ALG GENMASK(31, 22)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

392

#define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

393

#define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

394

#define MTK_RXD5_SRC_PORT GENMASK(29, 26)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

405

#define PPSC_MDC_CFG GENMASK(29, 24)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

413

#define PHY_IAC_REG_MASK GENMASK(29, 25)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

415

#define PHY_IAC_ADDR_MASK GENMASK(24, 20)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

417

#define PHY_IAC_CMD_MASK GENMASK(19, 18)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

422

#define PHY_IAC_START_MASK GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

425

#define PHY_IAC_DATA_MASK GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

441

#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

446

#define GSWTX_IPG_MASK GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

448

#define GSWRX_IPG_MASK GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

454

#define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

479

#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

480

#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

481

#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

500

#define DQSI0(x) ((x << 0) & GENMASK(6, 0))

drivers/net/ethernet/mediatek/mtk_eth_soc.h

501

#define DQSI1(x) ((x << 8) & GENMASK(14, 8))

drivers/net/ethernet/mediatek/mtk_eth_soc.h

502

#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))

drivers/net/ethernet/mediatek/mtk_eth_soc.h

512

#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))

drivers/net/ethernet/mediatek/mtk_eth_soc.h

565

#define SYSCFG0_SGMII_MASK GENMASK(9, 7)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

609

#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)

drivers/net/ethernet/mediatek/mtk_eth_soc.h

613

#define QPHY_SEL_MASK GENMASK(1, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

16

#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

17

#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)

drivers/net/ethernet/mediatek/mtk_ppe.h

20

#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

22

#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16)

drivers/net/ethernet/mediatek/mtk_ppe.h

30

#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25)

drivers/net/ethernet/mediatek/mtk_ppe.h

31

#define MTK_FOE_IB1_STATE GENMASK(29, 28)

drivers/net/ethernet/mediatek/mtk_ppe.h

36

#define MTK_FOE_IB1_BIND_TIMESTAMP_V2 GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

37

#define MTK_FOE_IB1_BIND_VLAN_LAYER_V2 GENMASK(16, 14)

drivers/net/ethernet/mediatek/mtk_ppe.h

42

#define MTK_FOE_IB1_PACKET_TYPE_V2 GENMASK(27, 23)

drivers/net/ethernet/mediatek/mtk_ppe.h

54

#define MTK_FOE_IB2_QID GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

56

#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)

drivers/net/ethernet/mediatek/mtk_ppe.h

60

#define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)

drivers/net/ethernet/mediatek/mtk_ppe.h

65

#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12)

drivers/net/ethernet/mediatek/mtk_ppe.h

67

#define MTK_FOE_IB2_RX_IDX GENMASK(18, 17)

drivers/net/ethernet/mediatek/mtk_ppe.h

68

#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18)

drivers/net/ethernet/mediatek/mtk_ppe.h

70

#define MTK_FOE_IB2_DSCP GENMASK(31, 24)

drivers/net/ethernet/mediatek/mtk_ppe.h

73

#define MTK_FOE_IB2_QID_V2 GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

76

#define MTK_FOE_IB2_DEST_PORT_V2 GENMASK(12, 9)

drivers/net/ethernet/mediatek/mtk_ppe.h

79

#define MTK_FOE_IB2_PORT_AG_V2 GENMASK(23, 20)

drivers/net/ethernet/mediatek/mtk_ppe.h

81

#define MTK_FOE_VLAN2_WINFO_BSS GENMASK(5, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

82

#define MTK_FOE_VLAN2_WINFO_WCID GENMASK(13, 6)

drivers/net/ethernet/mediatek/mtk_ppe.h

83

#define MTK_FOE_VLAN2_WINFO_RING GENMASK(15, 14)

drivers/net/ethernet/mediatek/mtk_ppe.h

85

#define MTK_FOE_WINFO_BSS GENMASK(5, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

86

#define MTK_FOE_WINFO_WCID GENMASK(15, 6)

drivers/net/ethernet/mediatek/mtk_ppe.h

88

#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_ppe.h

89

#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

91

#define MTK_FOE_WINFO_AMSDU_USR_INFO GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe.h

92

#define MTK_FOE_WINFO_AMSDU_TID GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

100

#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

101

#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

104

#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

105

#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

106

#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

109

#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

110

#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

113

#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

114

#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

117

#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

118

#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

123

#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

130

#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

131

#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

134

#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

135

#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

144

#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

154

#define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

157

#define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

160

#define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

161

#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

164

#define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

43

#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

44

#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

47

#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

49

#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

56

#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

57

#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

58

#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

59

#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

64

#define MTK_PPE_NTU_KEEPALIVE GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

89

#define MTK_PPE_TB_USED_NUM GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

92

#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

93

#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

96

#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_ppe_regs.h

97

#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16)

drivers/net/ethernet/mediatek/mtk_star_emac.c

145

#define MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS GENMASK(26, 16)

drivers/net/ethernet/mediatek/mtk_star_emac.c

156

#define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_star_emac.c

194

#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_star_emac.c

212

#define MTK_STAR_DESC_MSK_LEN GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_star_emac.c

50

#define MTK_STAR_MSK_PHY_CTRL0_PREG GENMASK(12, 8)

drivers/net/ethernet/mediatek/mtk_star_emac.c

52

#define MTK_STAR_MSK_PHY_CTRL0_RWDATA GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_star_emac.c

70

#define MTK_STAR_VAL_MAC_CFG_IPG_96BIT GENMASK(4, 0)

drivers/net/ethernet/mediatek/mtk_star_emac.c

82

#define MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_star_emac.c

96

#define MTK_STAR_MSK_HASH_CTRL_HASH_BIT_ADDR GENMASK(8, 0)

drivers/net/ethernet/mediatek/mtk_wed.c

1980

u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));

drivers/net/ethernet/mediatek/mtk_wed.c

2032

GENMASK(1, 0));

drivers/net/ethernet/mediatek/mtk_wed.c

65

.reset_idx_tx_mask = GENMASK(3, 0),

drivers/net/ethernet/mediatek/mtk_wed.c

66

.reset_idx_rx_mask = GENMASK(17, 16),

drivers/net/ethernet/mediatek/mtk_wed.c

78

.reset_idx_tx_mask = GENMASK(1, 0),

drivers/net/ethernet/mediatek/mtk_wed.c

79

.reset_idx_rx_mask = GENMASK(7, 6),

drivers/net/ethernet/mediatek/mtk_wed.c

92

.reset_idx_tx_mask = GENMASK(1, 0),

drivers/net/ethernet/mediatek/mtk_wed.c

93

.reset_idx_rx_mask = GENMASK(7, 6),

drivers/net/ethernet/mediatek/mtk_wed_regs.h

109

#define MTK_WED_STATUS_TX GENMASK(15, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

112

#define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

115

#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

116

#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

12

#define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

123

#define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

126

#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

127

#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

132

#define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

133

#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

138

#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

139

#define MTK_WED_TX_BM_DYN_THR_LO_V2 GENMASK(8, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

140

#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

141

#define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

144

#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

145

#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

149

#define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

151

#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

152

#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

155

#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

156

#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

160

#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

173

#define MTK_WED_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

178

#define MTK_WED_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

180

#define MTK_WED_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

181

#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

190

#define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

204

#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

211

#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

216

#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

218

#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

219

#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

232

#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

243

#define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

244

#define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

252

#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

259

#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

262

#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

267

#define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG GENMASK(6, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

270

#define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG GENMASK(14, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

275

#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

286

#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

287

#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

310

#define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

311

#define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

314

#define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

316

#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

327

#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

328

#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

349

#define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

350

#define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

365

#define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

382

#define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

384

#define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

387

#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

390

#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

393

#define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

394

#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

400

#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

401

#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

402

#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

403

#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

410

#define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

414

#define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

420

#define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

421

#define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

441

#define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

442

#define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

447

#define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

448

#define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

489

#define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

490

#define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

507

#define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

508

#define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

521

#define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

558

#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

582

#define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

589

#define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

597

#define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

598

#define MTK_WED_RROQM_MIOD_MOD_DW GENMASK(13, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

599

#define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

615

#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

616

#define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

625

#define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

626

#define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

629

#define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

630

#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

631

#define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

635

#define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

636

#define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

640

#define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

641

#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

642

#define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

646

#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

649

#define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

659

#define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

687

#define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

691

#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

697

#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

700

#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

705

#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

708

#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

711

#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

714

#define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

720

#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

723

#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

724

#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

725

#define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

730

#define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

745

#define MTK_WED_AMSDU_STA_MAX_AMSDU_LEN GENMASK(7, 2)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

746

#define MTK_WED_AMSDU_STA_MAX_AMSDU_NUM GENMASK(11, 8)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

754

#define MTK_WED_AMSDU_HIFTXD_SRC GENMASK(16, 15)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

765

#define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

766

#define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

769

#define MTK_WED_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

770

#define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

771

#define MTK_WED_AMSDU_ENG_MAX_MSDU_MERGED GENMASK(28, 24)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

776

#define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

777

#define MTK_WED_AMSDU_QMEM_SP_QCNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

778

#define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

779

#define MTK_WED_AMSDU_QMEM_TID1_QCNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

780

#define MTK_WED_AMSDU_QMEM_TID2_QCNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

781

#define MTK_WED_AMSDU_QMEM_TID3_QCNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

782

#define MTK_WED_AMSDU_QMEM_TID4_QCNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

783

#define MTK_WED_AMSDU_QMEM_TID5_QCNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

784

#define MTK_WED_AMSDU_QMEM_TID6_QCNT GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

785

#define MTK_WED_AMSDU_QMEM_TID7_QCNT GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

788

#define MTK_WED_AMSDU_QMEM_FQ_HEAD GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

789

#define MTK_WED_AMSDU_QMEM_SP_QHEAD GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

790

#define MTK_WED_AMSDU_QMEM_TID0_QHEAD GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

791

#define MTK_WED_AMSDU_QMEM_TID1_QHEAD GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

792

#define MTK_WED_AMSDU_QMEM_TID2_QHEAD GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

793

#define MTK_WED_AMSDU_QMEM_TID3_QHEAD GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

794

#define MTK_WED_AMSDU_QMEM_TID4_QHEAD GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

795

#define MTK_WED_AMSDU_QMEM_TID5_QHEAD GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

796

#define MTK_WED_AMSDU_QMEM_TID6_QHEAD GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

797

#define MTK_WED_AMSDU_QMEM_TID7_QHEAD GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

798

#define MTK_WED_AMSDU_QMEM_FQ_TAIL GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

799

#define MTK_WED_AMSDU_QMEM_SP_QTAIL GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

8

#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

800

#define MTK_WED_AMSDU_QMEM_TID0_QTAIL GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

801

#define MTK_WED_AMSDU_QMEM_TID1_QTAIL GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

802

#define MTK_WED_AMSDU_QMEM_TID2_QTAIL GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

803

#define MTK_WED_AMSDU_QMEM_TID3_QTAIL GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

804

#define MTK_WED_AMSDU_QMEM_TID4_QTAIL GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

805

#define MTK_WED_AMSDU_QMEM_TID5_QTAIL GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

806

#define MTK_WED_AMSDU_QMEM_TID6_QTAIL GENMASK(27, 16)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

807

#define MTK_WED_AMSDU_QMEM_TID7_QTAIL GENMASK(11, 0)

drivers/net/ethernet/mediatek/mtk_wed_regs.h

9

#define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_wed_wo.h

129

#define MTK_WED_WO_CCIF_RCHNUM_MASK GENMASK(7, 0)

drivers/net/ethernet/mediatek/mtk_wed_wo.h

151

#define MTK_WED_WO_CTL_SD_LEN1 GENMASK(13, 0)

drivers/net/ethernet/mediatek/mtk_wed_wo.h

155

#define MTK_WED_WO_CTL_SD_LEN0 GENMASK(29, 16)

drivers/net/ethernet/mediatek/mtk_wed_wo.h

158

#define MTK_WED_WO_INFO_WINFO GENMASK(15, 0)

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c

192

#define RSS_L4 GENMASK(1, 0)

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c

193

#define RSS_L3 GENMASK(3, 2) /* Same as CQE_RSS_HTYPE_IP */

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h

44

#define MLX5_IPSEC_METADATA_SYNDROM(metadata) (((metadata) >> 24) & GENMASK(5, 0))

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h

45

#define MLX5_IPSEC_METADATA_HANDLE(metadata) ((metadata) & GENMASK(23, 0))

drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h

15

#define MLX5_PSP_METADATA_SYNDROME(metadata) (((metadata) >> 23) & GENMASK(6, 0))

drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h

16

#define MLX5_PSP_METADATA_HANDLE(metadata) ((metadata) & GENMASK(22, 0))

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

194

u32 max_mask = GENMASK(match_len - 1, 0);

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

241

u32 max_mask = GENMASK(match_len - 1, 0);

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

141

#define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

170

#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

172

#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

174

#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

256

#define MLX5_REG_MAPPING_MASK(reg_id) (GENMASK(mlx5e_tc_attr_to_reg_mappings[reg_id].mlen - 1, 0))

drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c

1337

if (!(bond_status & GENMASK(ldev->ports - 1, 0)))

drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c

1351

bond_status == GENMASK(ldev->ports - 1, 0);

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

140

#define MLXBF_GIGE_RX_CQE_PKT_LEN_MASK GENMASK(10, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

141

#define MLXBF_GIGE_RX_CQE_VALID_MASK GENMASK(11, 11)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

142

#define MLXBF_GIGE_RX_CQE_PKT_STATUS_MASK GENMASK(15, 12)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

143

#define MLXBF_GIGE_RX_CQE_PKT_STATUS_MAC_ERR GENMASK(12, 12)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

144

#define MLXBF_GIGE_RX_CQE_PKT_STATUS_TRUNCATED GENMASK(13, 13)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

145

#define MLXBF_GIGE_RX_CQE_CHKSUM_MASK GENMASK(31, 16)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

150

#define MLXBF_GIGE_TX_WQE_PKT_LEN_MASK GENMASK(10, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

151

#define MLXBF_GIGE_TX_WQE_UPDATE_MASK GENMASK(31, 31)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

152

#define MLXBF_GIGE_TX_WQE_CHKSUM_LEN_MASK GENMASK(42, 32)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

153

#define MLXBF_GIGE_TX_WQE_CHKSUM_START_MASK GENMASK(55, 48)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

154

#define MLXBF_GIGE_TX_WQE_CHKSUM_OFFSET_MASK GENMASK(63, 56)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c

102

#define MLXBF_GIGE_MDIO_CORE_F_MASK GENMASK(25, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c

104

#define MLXBF_GIGE_MDIO_CORE_R_MASK GENMASK(31, 26)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c

106

#define MLXBF_GIGE_MDIO_CORE_OD_MASK GENMASK(3, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

25

#define MLXBF2_GIGE_MDIO_GW_AD_MASK GENMASK(15, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

26

#define MLXBF2_GIGE_MDIO_GW_DEVAD_MASK GENMASK(20, 16)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

27

#define MLXBF2_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

28

#define MLXBF2_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

29

#define MLXBF2_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

30

#define MLXBF2_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

40

#define MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

41

#define MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK GENMASK(2, 2)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

42

#define MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(4, 4)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

43

#define MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(15, 8)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

44

#define MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(23, 16)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf2.h

45

#define MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(31, 24)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

28

#define MLXBF3_GIGE_MDIO_GW_ST1_MASK GENMASK(1, 1)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

29

#define MLXBF3_GIGE_MDIO_GW_OPCODE_MASK GENMASK(3, 2)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

30

#define MLXBF3_GIGE_MDIO_GW_PARTAD_MASK GENMASK(8, 4)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

31

#define MLXBF3_GIGE_MDIO_GW_DEVAD_MASK GENMASK(13, 9)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

33

#define MLXBF3_GIGE_MDIO_GW_DATA_MASK GENMASK(29, 14)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

34

#define MLXBF3_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

36

#define MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK GENMASK(15, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

48

#define MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

49

#define MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(2, 2)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

50

#define MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(7, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

51

#define MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(7, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio_bf3.h

52

#define MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(15, 8)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h

86

#define MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK GENMASK(11, 0)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h

87

#define MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK GENMASK(15, 14)

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h

90

#define MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK GENMASK(25, 24)

drivers/net/ethernet/mellanox/mlxsw/i2c.c

123

GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/i2c.c

124

mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,

drivers/net/ethernet/mellanox/mlxsw/i2c.c

130

GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/i2c.c

131

mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,

drivers/net/ethernet/mellanox/mlxsw/item.h

121

tmp &= GENMASK(item->size.bits - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/item.h

133

u32 mask = GENMASK(item->size.bits - 1, 0) << item->shift;

drivers/net/ethernet/mellanox/mlxsw/item.h

242

tmp &= GENMASK(item->element_size - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/item.h

252

u8 mask = GENMASK(item->element_size - 1, 0) << shift;

drivers/net/ethernet/mellanox/mlxsw/item.h

53

tmp &= GENMASK(item->size.bits - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/item.h

65

u8 mask = GENMASK(item->size.bits - 1, 0) << item->shift;

drivers/net/ethernet/mellanox/mlxsw/item.h

87

tmp &= GENMASK(item->size.bits - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/item.h

99

u16 mask = GENMASK(item->size.bits - 1, 0) << item->shift;

drivers/net/ethernet/mellanox/mlxsw/reg.h

9489

((s16)((GENMASK(15, 0) + (v_) + 1) \

drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c

146

key->vrid, GENMASK(11, 0));

drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c

160

key->vrid, GENMASK(3, 0));

drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c

162

key->vrid >> 4, GENMASK(3, 0));

drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c

165

key->vrid >> 8, GENMASK(3, 0));

drivers/net/ethernet/meta/fbnic/fbnic_csr.h

10

#define CSR_GENMASK(h, l) GENMASK(h, l)

drivers/net/ethernet/microchip/fdma/fdma_api.h

49

#define FDMA_DCB_INFO_DATAL(x) ((x) & GENMASK(15, 0))

drivers/net/ethernet/microchip/fdma/fdma_api.h

52

#define FDMA_DCB_INFO_SW(x) (((x) << 24) & GENMASK(31, 24))

drivers/net/ethernet/microchip/fdma/fdma_api.h

54

#define FDMA_DCB_STATUS_BLOCKL(x) ((x) & GENMASK(15, 0))

drivers/net/ethernet/microchip/fdma/fdma_api.h

59

#define FDMA_DCB_STATUS_BLOCKO(x) (((x) << 20) & GENMASK(31, 20))

drivers/net/ethernet/microchip/lan743x_main.h

123

#define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28)

drivers/net/ethernet/microchip/lan743x_main.h

126

#define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

128

#define HS_E2P_DATA_MASK_ GENMASK(7, 0)

drivers/net/ethernet/microchip/lan743x_main.h

130

#define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)

drivers/net/ethernet/microchip/lan743x_main.h

132

#define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)

drivers/net/ethernet/microchip/lan743x_main.h

328

#define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16)

drivers/net/ethernet/microchip/lan743x_main.h

331

#define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

334

#define SGMII_DATA_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

341

#define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4)

drivers/net/ethernet/microchip/lan743x_main.h

369

#define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)

drivers/net/ethernet/microchip/lan743x_main.h

373

#define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)

drivers/net/ethernet/microchip/lan743x_main.h

382

#define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)

drivers/net/ethernet/microchip/lan743x_main.h

388

#define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)

drivers/net/ethernet/microchip/lan743x_main.h

396

#define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)

drivers/net/ethernet/microchip/lan743x_main.h

398

#define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)

drivers/net/ethernet/microchip/lan743x_main.h

501

#define PTP_INT_IO_FE_MASK_ GENMASK(31, 24)

drivers/net/ethernet/microchip/lan743x_main.h

504

#define PTP_INT_IO_RE_MASK_ GENMASK(23, 16)

drivers/net/ethernet/microchip/lan743x_main.h

539

#define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

541

#define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24)

drivers/net/ethernet/microchip/lan743x_main.h

542

#define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16)

drivers/net/ethernet/microchip/lan743x_main.h

543

#define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)

drivers/net/ethernet/microchip/lan743x_main.h

544

#define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)

drivers/net/ethernet/microchip/lan743x_main.h

546

#define PTP_IO_SEL_MASK_ GENMASK(10, 8)

drivers/net/ethernet/microchip/lan743x_main.h

555

#define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0)

drivers/net/ethernet/microchip/lan743x_main.h

575

#define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)

drivers/net/ethernet/microchip/lan743x_main.h

577

#define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16)

drivers/net/ethernet/microchip/lan743x_main.h

579

#define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)

drivers/net/ethernet/microchip/lan743x_main.h

581

#define PTP_TX_SDOID_MASK_ GENMASK(23, 16)

drivers/net/ethernet/microchip/lan743x_main.h

583

#define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)

drivers/net/ethernet/microchip/lan743x_main.h

599

#define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

602

#define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)

drivers/net/ethernet/microchip/lan743x_main.h

605

#define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

616

#define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)

drivers/net/ethernet/microchip/lan743x_main.h

65

#define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)

drivers/net/ethernet/microchip/lan966x/lan966x_cbs.c

34

if (cir > GENMASK(15, 0) ||

drivers/net/ethernet/microchip/lan966x/lan966x_cbs.c

35

cbs > GENMASK(6, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_lag.c

9

u32 visited = GENMASK(lan966x->num_phys_ports - 1, 0);

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

1005

lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

1010

lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

1014

lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

1019

lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

1024

lan_rmw(ANA_PGID_PGID_SET(BIT(CPU_PORT) | GENMASK(lan966x->num_phys_ports - 1, 0)),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

898

GENMASK(1, 0),

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

906

~(GENMASK(1, 0)),

drivers/net/ethernet/microchip/lan966x/lan966x_police.c

31

if (pol->rate > GENMASK(15, 0) ||

drivers/net/ethernet/microchip/lan966x/lan966x_police.c

32

pol->burst > GENMASK(6, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_police.c

66

lan_wr(ANA_POL_PIR_CFG_PIR_RATE_SET(GENMASK(14, 0)) |

drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c

119

if (mask == GENMASK(lan966x->num_phys_ports, 0)) {

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1000

#define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1033

#define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1048

#define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1057

#define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

106

#define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1066

#define PTP_DOM_CFG_ENA GENMASK(11, 9)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1072

#define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1084

#define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1090

#define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1096

#define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1102

#define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1111

#define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1123

#define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1133

#define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1134

#define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1135

#define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1141

#define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1142

#define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1143

#define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

115

#define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1166

#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1181

#define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1190

#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

121

#define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1214

#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1232

#define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1250

#define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1259

#define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1265

#define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

127

#define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1289

#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1301

#define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1307

#define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1316

#define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1331

#define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1337

#define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1346

#define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

136

#define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1364

#define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1372

#define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1381

#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1387

#define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1399

#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1408

#define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1417

#define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

142

#define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1426

#define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1432

#define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1441

#define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1453

#define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1465

#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1474

#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

148

#define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1483

#define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1492

#define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1498

#define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1504

#define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1513

#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1519

#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1531

#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

154

#define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1540

#define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1546

#define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1555

#define REW_TAG_CFG_TAG_CFG GENMASK(8, 7)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1561

#define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1567

#define REW_TAG_CFG_TAG_PCP_CFG GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1573

#define REW_TAG_CFG_TAG_DEI_CFG GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1597

#define REW_DSCP_CFG_DSCP_REWR_CFG GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1612

#define REW_PCP_DEI_CFG_PCP_QOS_VAL GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1621

#define REW_STAT_CFG_STAT_MODE GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

163

#define ANA_PGID_PGID GENMASK(8, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1639

#define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1645

#define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1672

#define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1681

#define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1687

#define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1708

#define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1714

#define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1738

#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1759

#define VCAP_UPDATE_CTRL_UPDATE_CMD GENMASK(24, 22)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1783

#define VCAP_UPDATE_CTRL_UPDATE_ADDR GENMASK(18, 3)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1810

#define VCAP_MV_CFG_MV_NUM_POS GENMASK(31, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1816

#define VCAP_MV_CFG_MV_SIZE GENMASK(15, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1843

#define VCAP_CORE_IDX_CORE_IDX GENMASK(3, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1852

#define VCAP_CORE_MAP_CORE_MAP GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

205

#define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

211

#define ANA_MACACCESS_DEST_IDX GENMASK(9, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

217

#define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

226

#define ANA_MACTINDX_BUCKET GENMASK(12, 11)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

232

#define ANA_MACTINDX_M_INDEX GENMASK(10, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

241

#define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

250

#define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

265

#define ANA_VLANTIDX_V_INDEX GENMASK(11, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

280

#define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

286

#define ANA_VLAN_CFG_VLAN_PCP GENMASK(15, 13)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

298

#define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

340

#define ANA_QOS_CFG_QOS_DEFAULT_VAL GENMASK(7, 5)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

358

#define ANA_QOS_CFG_DSCP_REWR_CFG GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

37

#define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

376

#define ANA_VCAP_S1_CFG_KEY_RT_CFG GENMASK(11, 9)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

382

#define ANA_VCAP_S1_CFG_KEY_IP6_CFG GENMASK(8, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

388

#define ANA_VCAP_S1_CFG_KEY_IP4_CFG GENMASK(5, 3)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

394

#define ANA_VCAP_S1_CFG_KEY_OTHER_CFG GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

403

#define ANA_VCAP_S2_CFG_ISDX_ENA GENMASK(20, 19)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

409

#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA GENMASK(18, 17)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

415

#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA GENMASK(16, 15)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

427

#define ANA_VCAP_S2_CFG_SNAP_DIS GENMASK(13, 12)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

433

#define ANA_VCAP_S2_CFG_ARP_DIS GENMASK(11, 10)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

439

#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS GENMASK(9, 8)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

445

#define ANA_VCAP_S2_CFG_IP_OTHER_DIS GENMASK(7, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

451

#define ANA_VCAP_S2_CFG_IP6_CFG GENMASK(5, 2)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

457

#define ANA_VCAP_S2_CFG_OAM_DIS GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

472

#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL GENMASK(2, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

52

#define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

535

#define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

544

#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL GENMASK(5, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

559

#define ANA_POL_CFG_POL_ORDER GENMASK(8, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

568

#define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

628

#define ANA_DSCP_CFG_QOS_DSCP_VAL GENMASK(10, 8)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

649

#define ANA_POL_PIR_CFG_PIR_RATE GENMASK(20, 6)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

655

#define ANA_POL_PIR_CFG_PIR_BURST GENMASK(5, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

676

#define ANA_POL_MODE_IPG_SIZE GENMASK(9, 5)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

682

#define ANA_POL_MODE_FRM_MODE GENMASK(4, 3)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

697

#define ANA_POL_PIR_STATE_PIR_LVL GENMASK(21, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

745

#define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

778

#define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

802

#define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

808

#define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

814

#define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

823

#define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

877

#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

88

#define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

904

#define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

943

#define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

952

#define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

961

#define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

97

#define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

970

#define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0)

drivers/net/ethernet/microchip/lan966x/lan966x_tbf.c

38

if (cir > GENMASK(15, 0) ||

drivers/net/ethernet/microchip/lan966x/lan966x_tbf.c

39

cbs > GENMASK(6, 0))

drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c

362

port->chip_port, GENMASK(4, 0));

drivers/net/ethernet/microchip/lan966x/lan966x_vlan.c

321

GENMASK(lan966x->num_phys_ports - 1, 0) | BIT(CPU_PORT);

drivers/net/ethernet/microchip/lan966x/lan966x_vlan.c

325

GENMASK(lan966x->num_phys_ports - 1, 0) | BIT(CPU_PORT);

drivers/net/ethernet/microchip/lan966x/lan966x_vlan.c

337

lan_wr(GENMASK(lan966x->num_phys_ports, 0),

drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c

107

spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5,

drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c

56

spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5,

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1016

GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1027

#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1038

#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1056

GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1067

#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

109

#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1091

GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1102

#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1113

#define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1119

#define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1131

GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1138

GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1149

#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

115

#define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1155

#define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1173

GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1196

#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

121

#define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1213

#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1231

#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1237

#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1249

#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

127

#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

133

#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1371

#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1377

#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

139

#define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1407

#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1419

#define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1431

#define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1442

#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1453

#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1459

#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1476

#define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1482

#define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1530

#define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1536

#define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1569

#define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1575

#define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1581

#define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1587

#define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1593

#define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1599

#define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1616

#define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1627

#define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1633

#define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1639

#define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1662

#define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1673

#define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1697

#define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1774

#define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1786

GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1798

GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1820

#define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1826

#define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

219

#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2347

#define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2358

#define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2369

#define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2380

#define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2391

#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2402

#define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2413

#define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2424

#define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

249

GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2493

#define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2499

#define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2539

#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2545

#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2557

#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

261

GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

267

#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2684

#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2703

#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2737

#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2748

#define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2759

#define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2870

#define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2876

#define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2882

#define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

290

#define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

2956

#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3026

#define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

303

GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3032

#define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3038

#define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3113

#define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3200

#define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

321

GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3211

#define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3223

#define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3240

#define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3246

#define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3274

#define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3280

#define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3286

#define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3303

#define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3321

#define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

338

#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3401

#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3453

#define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3482

#define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3558

#define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3564

#define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3576

#define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3611

#define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

365

#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

3685

#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

371

#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

383

#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4138

#define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4154

#define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4170

#define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4186

#define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4202

#define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4218

#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4234

#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4250

#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4273

#define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4279

#define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4285

#define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

434

#define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4359

#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4382

#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4416

#define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4445

#define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4456

#define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4467

#define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4473

#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4479

#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4485

#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4523

#define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4529

#define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4668

#define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4679

#define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4690

#define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

471

#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4743

GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4760

#define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4771

#define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4777

#define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4823

#define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

483

#define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4834

#define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4845

#define FDMA_INTR_DB_INTR_DB GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4856

#define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4867

#define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4873

#define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4884

#define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4890

#define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4896

#define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4902

#define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4908

#define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4914

#define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4920

#define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4926

#define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4937

#define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

495

#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4959

#define GCB_CHIP_ID_REV_ID GENMASK(31, 28)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4965

#define GCB_CHIP_ID_PART_ID GENMASK(27, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

4971

#define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5032

GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5043

#define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5049

#define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5060

#define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5066

#define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5077

#define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5083

#define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5095

GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5107

#define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5113

#define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

512

GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5131

GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5142

#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5149

GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5178

#define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5184

#define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5196

GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5202

#define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5208

#define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5220

#define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5231

#define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5243

GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5279

GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5298

GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

534

#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5344

#define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5366

#define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5377

#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5388

#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

540

#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5423

#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5439

#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5452

GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5458

#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5474

#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5480

#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5506

#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5530

#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5536

#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5554

#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5560

#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5571

GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5581

#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5587

#define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5593

#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

562

#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5647

#define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5675

#define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5681

#define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5691

#define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5697

#define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5713

#define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5719

#define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5731

#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5754

GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5760

#define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5771

#define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5777

#define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5836

#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

584

#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5842

#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5858

#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5864

#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5885

#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5891

#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

5914

#define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

601

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6014

#define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

607

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6114

#define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

613

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

619

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

625

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

631

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

637

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

643

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

649

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

655

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6566

GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6578

GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6590

GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6601

#define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6607

#define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

661

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6613

#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6619

#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6635

#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6646

#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6662

#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

667

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6679

GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION])

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6686

GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC])

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6700

GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6706

#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6712

#define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6718

#define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

673

#define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6730

#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6741

#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6757

#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6768

#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6784

#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6795

#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6806

#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6812

#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6839

#define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

684

#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6845

#define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6886

#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

690

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6903

#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6914

#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6931

#define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6937

#define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

696

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6984

GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

6995

GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7006

GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7017

GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7027

#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7053

#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7063

#define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7073

#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7093

#define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7117

#define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7127

#define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7133

#define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7139

#define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7151

GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7158

GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7182

GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

719

#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7193

#define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7211

GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7222

#define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7233

#define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7239

#define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

725

#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7273

#define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7285

GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7291

#define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7349

#define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

736

#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7361

#define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7372

#define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7383

#define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7422

#define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7428

#define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7434

#define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7440

#define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7446

#define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

748

#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7498

#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7515

#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7526

#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7547

#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7558

#define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7564

#define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

759

#define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7591

#define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7615

#define VCAP_ES0_CTRL_UPDATE_ADDR GENMASK(18, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7643

#define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7649

#define VCAP_ES0_CFG_MV_SIZE GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7683

#define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7693

#define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7753

#define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7777

#define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7805

#define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7811

#define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

782

#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7845

#define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7855

#define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

788

#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7915

#define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7939

#define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

794

#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7967

#define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

7973

#define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

800

#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8007

#define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8017

#define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

806

#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8101

#define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8108

GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8120

#define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8132

GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8144

GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8156

GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8168

GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8183

#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8211

#define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8223

#define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8240

#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8246

#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

8252

#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

946

#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

957

#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

963

#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

98

#define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

986

#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

992

#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_packet.c

46

info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1),

drivers/net/ethernet/microchip/sparx5/sparx5_packet.c

54

((u64)(xtr_hdr[2] & GENMASK(5, 0)) << 24) |

drivers/net/ethernet/microchip/vcap/vcap_api.c

134

u8 bidx = idx & GENMASK(2, 0);

drivers/net/ethernet/mscc/ocelot.c

2280

unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);

drivers/net/ethernet/mscc/ocelot.c

2288

ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),

drivers/net/ethernet/mscc/ocelot.c

3269

u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));

drivers/net/ethernet/mscc/ocelot.c

899

unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);

drivers/net/ethernet/mscc/ocelot_devlink.c

478

int all_tcs = GENMASK(OCELOT_NUM_TC - 1, 0);

drivers/net/ethernet/mscc/ocelot_devlink.c

508

return (wm & GENMASK(7, 0)) * 16;

drivers/net/ethernet/mscc/ocelot_devlink.c

516

*inuse = (val & GENMASK(23, 12)) >> 12;

drivers/net/ethernet/mscc/ocelot_devlink.c

517

*maxuse = val & GENMASK(11, 0);

drivers/net/ethernet/mscc/ocelot_fdma.h

12

#define MSCC_FDMA_DCB_STAT_BLOCKO(x) (((x) << 20) & GENMASK(31, 20))

drivers/net/ethernet/mscc/ocelot_fdma.h

13

#define MSCC_FDMA_DCB_STAT_BLOCKO_M GENMASK(31, 20)

drivers/net/ethernet/mscc/ocelot_fdma.h

14

#define MSCC_FDMA_DCB_STAT_BLOCKO_X(x) (((x) & GENMASK(31, 20)) >> 20)

drivers/net/ethernet/mscc/ocelot_fdma.h

19

#define MSCC_FDMA_DCB_STAT_BLOCKL_M GENMASK(15, 0)

drivers/net/ethernet/mscc/ocelot_fdma.h

20

#define MSCC_FDMA_DCB_STAT_BLOCKL(x) ((x) & GENMASK(15, 0))

drivers/net/ethernet/mscc/ocelot_flower.c

596

filter->ingress_port.mask = GENMASK(key_length - 1, 0);

drivers/net/ethernet/mscc/ocelot_flower.c

847

filter->egress_port.mask = GENMASK(key_length - 1, 0);

drivers/net/ethernet/mscc/ocelot_net.c

733

val = GENMASK(ocelot->num_phys_ports - 1, 0);

drivers/net/ethernet/mscc/ocelot_police.c

104

if (pir > GENMASK(15, 0)) {

drivers/net/ethernet/mscc/ocelot_police.c

107

pol_ix, pir, GENMASK(15, 0));

drivers/net/ethernet/mscc/ocelot_police.c

111

if (cir > GENMASK(15, 0)) {

drivers/net/ethernet/mscc/ocelot_police.c

114

pol_ix, cir, GENMASK(15, 0));

drivers/net/ethernet/mscc/ocelot_police.c

146

(pir_discard ? GENMASK(22, 0) : 0),

drivers/net/ethernet/mscc/ocelot_police.c

155

(cir_discard ? GENMASK(22, 0) : 0),

drivers/net/ethernet/mscc/ocelot_police.c

41

ipg = min_t(u8, GENMASK(4, 0), conf->ipg);

drivers/net/ethernet/mscc/ocelot_police.c

81

pbs_max = GENMASK(6, 0); /* Limit burst size */

drivers/net/ethernet/mscc/ocelot_police.c

98

pir = GENMASK(15, 0);

drivers/net/ethernet/mscc/ocelot_qs.h

24

#define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))

drivers/net/ethernet/mscc/ocelot_qs.h

25

#define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)

drivers/net/ethernet/mscc/ocelot_qs.h

26

#define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

drivers/net/ethernet/mscc/ocelot_qs.h

34

#define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5))

drivers/net/ethernet/mscc/ocelot_qs.h

35

#define QS_XTR_CFG_DP_WM_M GENMASK(7, 5)

drivers/net/ethernet/mscc/ocelot_qs.h

36

#define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5)

drivers/net/ethernet/mscc/ocelot_qs.h

37

#define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2))

drivers/net/ethernet/mscc/ocelot_qs.h

38

#define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)

drivers/net/ethernet/mscc/ocelot_qs.h

39

#define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2)

drivers/net/ethernet/mscc/ocelot_qs.h

40

#define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0))

drivers/net/ethernet/mscc/ocelot_qs.h

41

#define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0)

drivers/net/ethernet/mscc/ocelot_qs.h

45

#define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))

drivers/net/ethernet/mscc/ocelot_qs.h

46

#define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2)

drivers/net/ethernet/mscc/ocelot_qs.h

47

#define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

drivers/net/ethernet/mscc/ocelot_qs.h

54

#define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21))

drivers/net/ethernet/mscc/ocelot_qs.h

55

#define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21)

drivers/net/ethernet/mscc/ocelot_qs.h

56

#define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21)

drivers/net/ethernet/mscc/ocelot_qs.h

60

#define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16))

drivers/net/ethernet/mscc/ocelot_qs.h

61

#define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16)

drivers/net/ethernet/mscc/ocelot_qs.h

62

#define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16)

drivers/net/ethernet/mscc/ocelot_qs.h

64

#define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4))

drivers/net/ethernet/mscc/ocelot_qs.h

65

#define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4)

drivers/net/ethernet/mscc/ocelot_qs.h

66

#define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4)

drivers/net/ethernet/mscc/ocelot_qs.h

67

#define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2))

drivers/net/ethernet/mscc/ocelot_qs.h

68

#define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2)

drivers/net/ethernet/mscc/ocelot_qs.h

69

#define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2)

drivers/net/ethernet/mscc/ocelot_qs.h

70

#define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0))

drivers/net/ethernet/mscc/ocelot_qs.h

71

#define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0)

drivers/net/ethernet/mscc/ocelot_rew.h

13

#define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16))

drivers/net/ethernet/mscc/ocelot_rew.h

14

#define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16)

drivers/net/ethernet/mscc/ocelot_rew.h

15

#define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16)

drivers/net/ethernet/mscc/ocelot_rew.h

17

#define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12))

drivers/net/ethernet/mscc/ocelot_rew.h

18

#define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12)

drivers/net/ethernet/mscc/ocelot_rew.h

19

#define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)

drivers/net/ethernet/mscc/ocelot_rew.h

20

#define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0))

drivers/net/ethernet/mscc/ocelot_rew.h

21

#define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0)

drivers/net/ethernet/mscc/ocelot_rew.h

25

#define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7))

drivers/net/ethernet/mscc/ocelot_rew.h

26

#define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7)

drivers/net/ethernet/mscc/ocelot_rew.h

27

#define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7)

drivers/net/ethernet/mscc/ocelot_rew.h

28

#define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5))

drivers/net/ethernet/mscc/ocelot_rew.h

29

#define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5)

drivers/net/ethernet/mscc/ocelot_rew.h

30

#define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5)

drivers/net/ethernet/mscc/ocelot_rew.h

32

#define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2))

drivers/net/ethernet/mscc/ocelot_rew.h

33

#define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2)

drivers/net/ethernet/mscc/ocelot_rew.h

34

#define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)

drivers/net/ethernet/mscc/ocelot_rew.h

35

#define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0))

drivers/net/ethernet/mscc/ocelot_rew.h

36

#define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0)

drivers/net/ethernet/mscc/ocelot_rew.h

41

#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3))

drivers/net/ethernet/mscc/ocelot_rew.h

42

#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3)

drivers/net/ethernet/mscc/ocelot_rew.h

43

#define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3)

drivers/net/ethernet/mscc/ocelot_rew.h

54

#define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0))

drivers/net/ethernet/mscc/ocelot_rew.h

55

#define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0)

drivers/net/ethernet/mscc/ocelot_rew.h

60

#define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3))

drivers/net/ethernet/mscc/ocelot_rew.h

61

#define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3)

drivers/net/ethernet/mscc/ocelot_rew.h

62

#define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3)

drivers/net/ethernet/mscc/ocelot_vcap.c

133

mask = GENMASK(width, 0);

drivers/net/ethernet/mscc/ocelot_vcap.c

169

data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0);

drivers/net/ethernet/mscc/ocelot_vcap.c

203

data->tg_mask |= GENMASK(offset + width - 1, offset);

drivers/net/ethernet/netronome/nfp/abm/ctrl.c

392

abm->dscp_mask = GENMASK(7, 8 - order_base_2(abm->num_prios));

drivers/net/ethernet/netronome/nfp/abm/main.h

24

#define NFP_ABM_PORTID_TYPE GENMASK(23, 16)

drivers/net/ethernet/netronome/nfp/abm/main.h

25

#define NFP_ABM_PORTID_ID GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/bpf/jit.c

3634

wrp_immed(nfp_prog, plen_reg(nfp_prog), GENMASK(13, 0));

drivers/net/ethernet/netronome/nfp/bpf/jit.c

909

mask = size < 4 ? GENMASK(size - 1, 0) : 0;

drivers/net/ethernet/netronome/nfp/ccm.h

72

#define NFP_NET_MBOX_TLV_TYPE GENMASK(31, 16)

drivers/net/ethernet/netronome/nfp/ccm.h

73

#define NFP_NET_MBOX_TLV_LEN GENMASK(15, 0)

drivers/net/ethernet/netronome/nfp/crypto/fw.h

30

#define NFP_NET_TLS_IPVER GENMASK(15, 12)

drivers/net/ethernet/netronome/nfp/crypto/fw.h

31

#define NFP_NET_TLS_VLAN GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

104

#define NFP_FL_TUNNEL_TYPE GENMASK(7, 4)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

105

#define NFP_FL_PRE_TUN_INDEX GENMASK(2, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

32

#define NFP_FLOWER_MASK_VLAN_PRIO GENMASK(15, 13)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

34

#define NFP_FLOWER_MASK_VLAN_VID GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

36

#define NFP_FLOWER_MASK_MPLS_LB GENMASK(31, 12)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

37

#define NFP_FLOWER_MASK_MPLS_TC GENMASK(11, 9)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

615

#define NFP_FLOWER_CMSG_MAC_REPR_NBI GENMASK(1, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

660

#define NFP_FLOWER_CMSG_PORT_TYPE GENMASK(31, 28)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

661

#define NFP_FLOWER_CMSG_PORT_SYS_ID GENMASK(27, 24)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

662

#define NFP_FLOWER_CMSG_PORT_NFP_ID GENMASK(23, 22)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

663

#define NFP_FLOWER_CMSG_PORT_PCI GENMASK(15, 14)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

664

#define NFP_FLOWER_CMSG_PORT_VNIC_TYPE GENMASK(13, 12)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

665

#define NFP_FLOWER_CMSG_PORT_VNIC GENMASK(11, 6)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

666

#define NFP_FLOWER_CMSG_PORT_PCIE_Q GENMASK(5, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

667

#define NFP_FLOWER_CMSG_PORT_PHYS_PORT_NUM GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

94

#define NFP_FL_OUT_FLAGS_TYPE_IDX GENMASK(2, 0)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

96

#define NFP_FL_PUSH_VLAN_PRIO GENMASK(15, 13)

drivers/net/ethernet/netronome/nfp/flower/cmsg.h

97

#define NFP_FL_PUSH_VLAN_VID GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/flower/conntrack.c

168

#define NFP_IPV4_TOS_MASK GENMASK(23, 16)

drivers/net/ethernet/netronome/nfp/flower/conntrack.c

169

#define NFP_IPV4_TTL_MASK GENMASK(31, 24)

drivers/net/ethernet/netronome/nfp/flower/conntrack.c

170

#define NFP_IPV6_TCLASS_MASK GENMASK(27, 20)

drivers/net/ethernet/netronome/nfp/flower/conntrack.c

171

#define NFP_IPV6_HLIMIT_MASK GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/flower/lag_conf.c

72

#define NFP_FL_LAG_PKT_NUMBER_MASK GENMASK(30, 0)

drivers/net/ethernet/netronome/nfp/flower/lag_conf.c

73

#define NFP_FL_LAG_VERSION_MASK GENMASK(22, 0)

drivers/net/ethernet/netronome/nfp/flower/main.h

26

#define NFP_FL_STAT_ID_MU_NUM GENMASK(31, 22)

drivers/net/ethernet/netronome/nfp/flower/main.h

27

#define NFP_FL_STAT_ID_STAT GENMASK(21, 0)

drivers/net/ethernet/netronome/nfp/nfd3/nfd3.h

13

#define NFD3_DESC_TX_OFFSET_MASK GENMASK(6, 0)

drivers/net/ethernet/netronome/nfp/nfd3/nfd3.h

14

#define NFD3_DESC_TX_MSS_MASK GENMASK(13, 0)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

24

#define NFDK_DESC_TX_MSS_MASK GENMASK(13, 0)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

31

#define NFDK_DESC_TX_DMA_LEN_HEAD GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

32

#define NFDK_DESC_TX_TYPE_HEAD GENMASK(15, 12)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

33

#define NFDK_DESC_TX_DMA_LEN GENMASK(13, 0)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

40

#define NFDK_META_LEN GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

41

#define NFDK_META_FIELDS GENMASK(31, 8)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

257

#define CMD_OVE_DATA GENMASK(5, 3)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

259

#define CMD_OV_LEN GENMASK(12, 8)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

286

#define NN_REG_TYPE GENMASK(31, 24)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

287

#define NN_REG_LM_IDX GENMASK(23, 22)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

290

#define NN_REG_LM_MOD GENMASK(21, 20)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

291

#define NN_REG_VAL GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/nfp_asm.h

401

#define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0)

drivers/net/ethernet/netronome/nfp/nfp_net.h

197

#define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0)

drivers/net/ethernet/netronome/nfp/nfp_net.h

253

#define NFP_NET_META_FIELD_MASK GENMASK(NFP_NET_META_FIELD_SIZE - 1, 0)

drivers/net/ethernet/netronome/nfp/nfp_net_common.c

1837

#define NFP_FS_QUEUE_ID GENMASK(22, 16)

drivers/net/ethernet/netronome/nfp/nfp_net_common.c

1838

#define NFP_FS_ACT GENMASK(15, 0)

drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h

39

#define NFP_NET_META_VLAN_TPID_MASK GENMASK(19, 16)

drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h

40

#define NFP_NET_META_VLAN_TCI_MASK GENMASK(15, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c

27

#define NFP_PL_DEVICE_ID_MASK GENMASK(7, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c

28

#define NFP_PL_DEVICE_PART_MASK GENMASK(31, 16)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

13

.qc_idx_mask = GENMASK(8, 0),

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

25

.qc_idx_mask = GENMASK(8, 0),

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

32

.qc_idx_mask = GENMASK(7, 0),

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_dev.c

44

.qc_idx_mask = GENMASK(7, 0),

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

64

#define NSP_CODE_MAJOR GENMASK(15, 12)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

65

#define NSP_CODE_MINOR GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

67

#define NFP_FW_LOAD_RET_MAJOR GENMASK(15, 8)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

68

#define NFP_FW_LOAD_RET_MINOR GENMASK(23, 16)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

70

#define NFP_HWINFO_LOOKUP_SIZE GENMASK(11, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

72

#define NFP_VERSIONS_SIZE GENMASK(11, 0)

drivers/net/ethernet/oa_tc6.c

38

#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8)

drivers/net/ethernet/oa_tc6.c

39

#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0)

drivers/net/ethernet/oa_tc6.c

55

#define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24)

drivers/net/ethernet/oa_tc6.c

56

#define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8)

drivers/net/ethernet/oa_tc6.c

57

#define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1)

drivers/net/ethernet/oa_tc6.c

64

#define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16)

drivers/net/ethernet/oa_tc6.c

66

#define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8)

drivers/net/ethernet/oa_tc6.c

73

#define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24)

drivers/net/ethernet/oa_tc6.c

76

#define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16)

drivers/net/ethernet/oa_tc6.c

78

#define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8)

drivers/net/ethernet/oa_tc6.c

79

#define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1)

drivers/net/ethernet/qualcomm/emac/emac-mac.h

42

#define BITS_GET(val, lo, hi) ((le32_to_cpu(val) & GENMASK((hi), (lo))) >> lo)

drivers/net/ethernet/qualcomm/emac/emac-mac.h

44

val = cpu_to_le32((le32_to_cpu(val) & (~GENMASK((hi), (lo)))) | \

drivers/net/ethernet/qualcomm/emac/emac-mac.h

45

(((new_val) << (lo)) & GENMASK((hi), (lo))))

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1403

val = FIELD_GET(GENMASK(2, 0), port_cfg.ceil);

drivers/net/ethernet/qualcomm/ppe/ppe_config.c

1405

val = FIELD_GET(GENMASK(10, 3), port_cfg.ceil);

drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c

165

*drop_cnt = FIELD_PREP(GENMASK(23, 0), value);

drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c

169

*drop_cnt |= FIELD_PREP(GENMASK(31, 24), value);

drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c

23

#define PPE_W0_PKT_CNT GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c

24

#define PPE_W2_DROP_PKT_CNT_LOW GENMASK(31, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c

25

#define PPE_W3_DROP_PKT_CNT_HIGH GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

105

#define PPE_SERVICE_W0_BYPASS_BITMAP GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

118

#define PPE_PORT_EG_VLAN_TBL_CTAG_MODE GENMASK(2, 1)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

119

#define PPE_PORT_EG_VLAN_TBL_STAG_MODE GENMASK(4, 3)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

133

#define PPE_EG_SERVICE_W0_UPDATE_ACTION GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

134

#define PPE_EG_SERVICE_W1_NEXT_SERVCODE GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

135

#define PPE_EG_SERVICE_W1_HW_SERVICE GENMASK(13, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

15

#define PPE_BM_SCH_CTRL_SCH_DEPTH GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

16

#define PPE_BM_SCH_CTRL_SCH_OFFSET GENMASK(14, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

162

#define PPE_MC_MTU_CTRL_TBL_MTU GENMASK(13, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

163

#define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

170

#define PPE_VSI_W0_MEMBER_PORT_BITMAP GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

171

#define PPE_VSI_W0_UUC_BITMAP GENMASK(15, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

172

#define PPE_VSI_W0_UMC_BITMAP GENMASK(23, 16)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

173

#define PPE_VSI_W0_BC_BITMAP GENMASK(31, 24)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

175

#define PPE_VSI_W1_NEW_ADDR_FWD_CMD GENMASK(2, 1)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

177

#define PPE_VSI_W1_STATION_MOVE_FWD_CMD GENMASK(5, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

200

#define PPE_MRU_MTU_CTRL_W0_MRU GENMASK(13, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

201

#define PPE_MRU_MTU_CTRL_W0_MRU_CMD GENMASK(15, 14)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

202

#define PPE_MRU_MTU_CTRL_W0_MTU GENMASK(29, 16)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

203

#define PPE_MRU_MTU_CTRL_W0_MTU_CMD GENMASK(31, 30)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

206

#define PPE_MRU_MTU_CTRL_W1_SRC_PROFILE GENMASK(3, 2)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

208

#define PPE_MRU_MTU_CTRL_W2_INNER_PREC_HIGH GENMASK(1, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

228

#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID GENMASK(4, 1)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

230

#define PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP GENMASK(29, 6)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

239

#define PPE_L2_VP_PORT_W0_DST_INFO GENMASK(9, 2)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

295

#define PPE_TL_SERVICE_TBL_BYPASS_BITMAP GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

300

#define PPE_PSCH_SCH_DEPTH_CFG_SCH_DEPTH GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

306

#define PPE_L0_FLOW_MAP_TBL_FLOW_ID GENMASK(5, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

307

#define PPE_L0_FLOW_MAP_TBL_C_PRI GENMASK(8, 6)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

308

#define PPE_L0_FLOW_MAP_TBL_E_PRI GENMASK(11, 9)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

309

#define PPE_L0_FLOW_MAP_TBL_C_NODE_WT GENMASK(21, 12)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

310

#define PPE_L0_FLOW_MAP_TBL_E_NODE_WT GENMASK(31, 22)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

315

#define PPE_L0_C_FLOW_CFG_TBL_NODE_ID GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

321

#define PPE_L0_E_FLOW_CFG_TBL_NODE_ID GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

327

#define PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

332

#define PPE_L0_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

333

#define PPE_L0_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

350

#define PPE_L1_FLOW_MAP_TBL_FLOW_ID GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

351

#define PPE_L1_FLOW_MAP_TBL_C_PRI GENMASK(6, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

352

#define PPE_L1_FLOW_MAP_TBL_E_PRI GENMASK(9, 7)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

353

#define PPE_L1_FLOW_MAP_TBL_C_NODE_WT GENMASK(19, 10)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

354

#define PPE_L1_FLOW_MAP_TBL_E_NODE_WT GENMASK(29, 20)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

359

#define PPE_L1_C_FLOW_CFG_TBL_NODE_ID GENMASK(5, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

365

#define PPE_L1_E_FLOW_CFG_TBL_NODE_ID GENMASK(5, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

371

#define PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

376

#define PPE_L1_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

377

#define PPE_L1_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

383

#define PPE_PSCH_SCH_CFG_TBL_DES_PORT GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

384

#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT GENMASK(7, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

385

#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT_BITMAP GENMASK(15, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

387

#define PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT GENMASK(20, 17)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

401

#define PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID GENMASK(1, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

407

#define PPE_BM_USED_CNT_VAL GENMASK(10, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

413

#define PPE_BM_REACT_CNT_VAL GENMASK(8, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

418

#define PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT GENMASK(10, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

423

#define PPE_BM_PORT_FC_W0_REACT_LIMIT GENMASK(8, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

424

#define PPE_BM_PORT_FC_W0_RESUME_THRESHOLD GENMASK(17, 9)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

425

#define PPE_BM_PORT_FC_W0_RESUME_OFFSET GENMASK(28, 18)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

426

#define PPE_BM_PORT_FC_W0_CEILING_LOW GENMASK(31, 29)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

427

#define PPE_BM_PORT_FC_W1_CEILING_HIGH GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

428

#define PPE_BM_PORT_FC_W1_WEIGHT GENMASK(10, 8)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

430

#define PPE_BM_PORT_FC_W1_PRE_ALLOC GENMASK(22, 12)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

455

#define PPE_UCAST_QUEUE_MAP_TBL_PROFILE_ID GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

456

#define PPE_UCAST_QUEUE_MAP_TBL_QUEUE_ID GENMASK(11, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

462

#define PPE_UCAST_HASH_MAP_TBL_HASH GENMASK(7, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

468

#define PPE_UCAST_PRIORITY_MAP_TBL_CLASS GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

478

#define PPE_AC_UNICAST_QUEUE_CFG_W0_GRP_ID GENMASK(5, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

479

#define PPE_AC_UNICAST_QUEUE_CFG_W0_PRE_LIMIT GENMASK(16, 6)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

481

#define PPE_AC_UNICAST_QUEUE_CFG_W0_WEIGHT GENMASK(20, 18)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

482

#define PPE_AC_UNICAST_QUEUE_CFG_W0_THRESHOLD GENMASK(31, 21)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

483

#define PPE_AC_UNICAST_QUEUE_CFG_W3_GRN_RESUME GENMASK(23, 13)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

507

#define PPE_AC_MULTICAST_QUEUE_CFG_W0_GRP_ID GENMASK(4, 3)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

508

#define PPE_AC_MULTICAST_QUEUE_CFG_W0_PRE_LIMIT GENMASK(15, 5)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

509

#define PPE_AC_MULTICAST_QUEUE_CFG_W0_THRESHOLD GENMASK(26, 16)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

510

#define PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME GENMASK(17, 7)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

530

#define PPE_AC_GRP_W0_THRESHOLD_LOW GENMASK(31, 25)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

531

#define PPE_AC_GRP_W1_THRESHOLD_HIGH GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

532

#define PPE_AC_GRP_W1_BUF_LIMIT GENMASK(14, 4)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

533

#define PPE_AC_GRP_W2_RESUME_GRN GENMASK(15, 5)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

534

#define PPE_AC_GRP_W2_PRE_ALLOC GENMASK(26, 16)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

54

#define PPE_RSS_HASH_MASK_HASH_MASK GENMASK(20, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

543

#define PPE_AC_UNICAST_QUEUE_CNT_TBL_PEND_CNT GENMASK(12, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

549

#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_PEND_CNT GENMASK(12, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

58

#define PPE_RSS_HASH_SEED_VAL GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

63

#define PPE_RSS_HASH_MIX_VAL GENMASK(4, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

68

#define PPE_RSS_HASH_FIN_INNER GENMASK(4, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

69

#define PPE_RSS_HASH_FIN_OUTER GENMASK(9, 5)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

72

#define PPE_RSS_HASH_MASK_IPV4_HASH_MASK GENMASK(20, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

76

#define PPE_RSS_HASH_SEED_IPV4_VAL GENMASK(31, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

81

#define PPE_RSS_HASH_MIX_IPV4_VAL GENMASK(4, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

86

#define PPE_RSS_HASH_FIN_IPV4_INNER GENMASK(4, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

87

#define PPE_RSS_HASH_FIN_IPV4_OUTER GENMASK(9, 5)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

92

#define PPE_BM_SCH_CFG_TBL_PORT_NUM GENMASK(3, 0)

drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

96

#define PPE_BM_SCH_CFG_TBL_SECOND_PORT GENMASK(11, 8)

drivers/net/ethernet/realtek/r8169_main.c

4803

pkt_size = status & GENMASK(13, 0);

drivers/net/ethernet/realtek/r8169_main.c

5442

new_bus->phy_mask = GENMASK(31, 1);

drivers/net/ethernet/realtek/rtase/rtase.h

260

#define RTASE_VLAN_TAG_MASK GENMASK(15, 0)

drivers/net/ethernet/realtek/rtase/rtase.h

261

#define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0)

drivers/net/ethernet/realtek/rtase/rtase.h

267

#define RTASE_IDLESLOPE_INT_MASK GENMASK(31, 25)

drivers/net/ethernet/realtek/rtase/rtase.h

31

#define RTASE_MULTICAST_FILTER_MASK GENMASK(30, 26)

drivers/net/ethernet/realtek/rtase/rtase.h

358

#define RTASE_TCPHO_MASK GENMASK(24, 18)

drivers/net/ethernet/realtek/rtase/rtase.h

360

#define RTASE_MSS_MASK GENMASK(28, 18)

drivers/net/ethernet/realtek/rtase/rtase.h

42

#define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0)

drivers/net/ethernet/realtek/rtase/rtase.h

43

#define RTASE_MITI_TIME_UNIT_MASK GENMASK(7, 4)

drivers/net/ethernet/realtek/rtase/rtase.h

46

#define RTASE_MITI_PKT_NUM_COUNT_MASK GENMASK(11, 8)

drivers/net/ethernet/realtek/rtase/rtase.h

47

#define RTASE_MITI_PKT_NUM_UNIT_MASK GENMASK(13, 12)

drivers/net/ethernet/renesas/ravb.h

427

EIS_RESERVED = (GENMASK(31, 17) | GENMASK(15, 11)),

drivers/net/ethernet/renesas/ravb.h

472

RIS0_RESERVED = GENMASK(31, 18),

drivers/net/ethernet/renesas/ravb.h

529

RIS2_RESERVED = GENMASK(30, 18),

drivers/net/ethernet/renesas/ravb.h

546

TIS_RESERVED = (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))

drivers/net/ethernet/renesas/ravb.h

620

GIS_RESERVED = GENMASK(15, 10),

drivers/net/ethernet/renesas/rswitch.h

734

#define MPIC_PIS GENMASK(2, 0)

drivers/net/ethernet/renesas/rswitch.h

737

#define MPIC_LSC GENMASK(5, 3)

drivers/net/ethernet/renesas/rswitch.h

741

#define MPIC_PSMCS GENMASK(22, 16)

drivers/net/ethernet/renesas/rswitch.h

742

#define MPIC_PSMHT GENMASK(26, 24)

drivers/net/ethernet/renesas/rswitch.h

748

#define MPSM_PDA GENMASK(7, 3)

drivers/net/ethernet/renesas/rswitch.h

749

#define MPSM_PRA GENMASK(12, 8)

drivers/net/ethernet/renesas/rswitch.h

750

#define MPSM_POP GENMASK(14, 13)

drivers/net/ethernet/renesas/rswitch.h

755

#define MPSM_PRD GENMASK(31, 16)

drivers/net/ethernet/renesas/rswitch.h

777

#define GWMDNC_TSDMN(num) (((num) << 16) & GENMASK(17, 16))

drivers/net/ethernet/renesas/rswitch.h

778

#define GWMDNC_TXDMN(num) (((num) << 8) & GENMASK(12, 8))

drivers/net/ethernet/renesas/rswitch.h

779

#define GWMDNC_RXDMN(num) ((num) & GENMASK(4, 0))

drivers/net/ethernet/renesas/rswitch.h

782

#define GWDCC_DCP_MASK GENMASK(18, 16)

drivers/net/ethernet/renesas/rswitch.h

825

#define FWCP1_LTHFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)

drivers/net/ethernet/renesas/rswitch.h

829

#define FWCP2_LTWFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)

drivers/net/ethernet/renesas/rswitch.h

830

#define FWCP2_LTWFW_MASK GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)

drivers/net/ethernet/renesas/rswitch.h

833

#define FWPBFC_PBDV GENMASK(RSWITCH_NUM_AGENTS - 1, 0)

drivers/net/ethernet/renesas/rswitch.h

837

#define FWMACHEC_MACHMUE_MASK GENMASK(26, 16)

drivers/net/ethernet/renesas/rswitch.h

842

#define FWMACAGUSPC_MACAGUSP GENMASK(9, 0)

drivers/net/ethernet/renesas/rswitch.h

843

#define FWMACAGC_MACAGT GENMASK(15, 0)

drivers/net/ethernet/renesas/rswitch.h

911

#define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0))

drivers/net/ethernet/renesas/rswitch.h

912

#define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8)

drivers/net/ethernet/renesas/rswitch.h

913

#define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16)

drivers/net/ethernet/renesas/rswitch_l2.c

69

fwd_mask = GENMASK(RSWITCH_NUM_AGENTS - 1, 0);

drivers/net/ethernet/renesas/rswitch_main.c

120

u32 all_ports_mask = GENMASK(RSWITCH_NUM_AGENTS - 1, 0);

drivers/net/ethernet/renesas/rtsn.h

326

#define MPIC_PIS_MASK GENMASK(1, 0)

drivers/net/ethernet/renesas/rtsn.h

332

#define MPIC_LSC_MASK GENMASK(3, MPIC_LSC_SHIFT)

drivers/net/ethernet/renesas/rtsn.h

337

#define MPIC_PSMCS_MASK GENMASK(21, MPIC_PSMCS_SHIFT)

drivers/net/ethernet/renesas/rtsn.h

340

#define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)

drivers/net/ethernet/renesas/rtsn.h

350

#define MPSM_PDA_MASK GENMASK(7, 3)

drivers/net/ethernet/renesas/rtsn.h

353

#define MPSM_PRA_MASK GENMASK(12, 8)

drivers/net/ethernet/socionext/sni_ave.c

1027

writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0,

drivers/net/ethernet/socionext/sni_ave.c

120

#define AVE_RXCR_MPSIZ_MASK GENMASK(10, 0)

drivers/net/ethernet/socionext/sni_ave.c

130

#define AVE_DESCC_STATUS_MASK GENMASK(31, 16)

drivers/net/ethernet/socionext/sni_ave.c

136

#define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */

drivers/net/ethernet/socionext/sni_ave.c

137

#define AVE_TXDC_ADDR GENMASK(11, 0) /* Start address */

drivers/net/ethernet/socionext/sni_ave.c

141

#define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */

drivers/net/ethernet/socionext/sni_ave.c

142

#define AVE_RXDC0_ADDR GENMASK(14, 0) /* Start address */

drivers/net/ethernet/socionext/sni_ave.c

147

#define AVE_IIRQC_BSCK GENMASK(15, 0) /* Interval count unit */

drivers/net/ethernet/socionext/sni_ave.c

159

#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)

drivers/net/ethernet/socionext/sni_ave.c

163

#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)

drivers/net/ethernet/socionext/sni_ave.c

166

#define AVE_PFMBYTE_MASK0 (GENMASK(31, 8) | GENMASK(5, 0))

drivers/net/ethernet/socionext/sni_ave.c

167

#define AVE_PFMBYTE_MASK1 GENMASK(25, 0)

drivers/net/ethernet/socionext/sni_ave.c

168

#define AVE_PFMBIT_MASK GENMASK(15, 0)

drivers/net/ethernet/socionext/sni_ave.c

389

major = (vr & GENMASK(15, 8)) >> 8;

drivers/net/ethernet/socionext/sni_ave.c

390

minor = (vr & GENMASK(7, 0));

drivers/net/ethernet/socionext/sni_ave.c

517

return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0);

drivers/net/ethernet/spacemit/k1_emac.h

159

#define MREGBIT_BURST_LENGTH GENMASK(7, 1)

drivers/net/ethernet/spacemit/k1_emac.h

160

#define MREGBIT_DESCRIPTOR_SKIP_LENGTH GENMASK(12, 8)

drivers/net/ethernet/spacemit/k1_emac.h

184

#define MREGBIT_TRANSMIT_DMA_STATE GENMASK(18, 16)

drivers/net/ethernet/spacemit/k1_emac.h

185

#define MREGBIT_RECEIVE_DMA_STATE GENMASK(23, 20)

drivers/net/ethernet/spacemit/k1_emac.h

198

#define MREGBIT_RECEIVE_IRQ_FRAME_COUNTER_MASK GENMASK(7, 0)

drivers/net/ethernet/spacemit/k1_emac.h

199

#define MREGBIT_RECEIVE_IRQ_TIMEOUT_COUNTER_MASK GENMASK(27, 8)

drivers/net/ethernet/spacemit/k1_emac.h

204

#define MREGBIT_SPEED GENMASK(1, 0)

drivers/net/ethernet/spacemit/k1_emac.h

219

#define MREGBIT_IFG_LEN GENMASK(6, 4)

drivers/net/ethernet/spacemit/k1_emac.h

220

#define MREGBIT_PREAMBLE_LENGTH GENMASK(9, 7)

drivers/net/ethernet/spacemit/k1_emac.h

232

#define MREGBIT_MAX_FRAME_SIZE GENMASK(13, 0)

drivers/net/ethernet/spacemit/k1_emac.h

235

#define MREGBIT_TRANSMIT_JABBER_SIZE GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

238

#define MREGBIT_RECEIVE_JABBER_SIZE GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

262

#define MREGBIT_MAC_FC_PAUSE_TIME GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

265

#define MREGBIT_PHY_ADDRESS GENMASK(4, 0)

drivers/net/ethernet/spacemit/k1_emac.h

266

#define MREGBIT_REGISTER_ADDRESS GENMASK(9, 5)

drivers/net/ethernet/spacemit/k1_emac.h

271

#define MREGBIT_MDIO_DATA GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

274

#define MREGBIT_RX_COUNTER_NUMBER GENMASK(4, 0)

drivers/net/ethernet/spacemit/k1_emac.h

278

#define MREGBIT_RX_STATCTR_DATA_HIGH GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

280

#define MREGBIT_RX_STATCTR_DATA_LOW GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

283

#define MREGBIT_TX_COUNTER_NUMBER GENMASK(4, 0)

drivers/net/ethernet/spacemit/k1_emac.h

287

#define MREGBIT_TX_STATCTR_DATA_HIGH GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

289

#define MREGBIT_TX_STATCTR_DATA_LOW GENMASK(15, 0)

drivers/net/ethernet/spacemit/k1_emac.h

292

#define MREGBIT_TX_FIFO_AF GENMASK(13, 0)

drivers/net/ethernet/spacemit/k1_emac.h

295

#define MREGBIT_TX_PACKET_START_THRESHOLD GENMASK(13, 0)

drivers/net/ethernet/spacemit/k1_emac.h

298

#define MREGBIT_RX_PACKET_START_THRESHOLD GENMASK(13, 0)

drivers/net/ethernet/spacemit/k1_emac.h

310

#define RX_DESC_0_FRAME_PACKET_LENGTH_MASK GENMASK(13, 0)

drivers/net/ethernet/spacemit/k1_emac.h

330

#define RX_DESC_1_BUFFER_SIZE_1_MASK GENMASK(11, 0)

drivers/net/ethernet/spacemit/k1_emac.h

331

#define RX_DESC_1_BUFFER_SIZE_2_MASK GENMASK(23, 12)

drivers/net/ethernet/spacemit/k1_emac.h

345

#define TX_DESC_1_BUFFER_SIZE_1_MASK GENMASK(11, 0)

drivers/net/ethernet/spacemit/k1_emac.h

346

#define TX_DESC_1_BUFFER_SIZE_2_MASK GENMASK(23, 12)

drivers/net/ethernet/spacemit/k1_emac.h

53

#define EMAC_RX_DLINE_STEP_MASK GENMASK(5, 4)

drivers/net/ethernet/spacemit/k1_emac.h

54

#define EMAC_RX_DLINE_CODE_MASK GENMASK(15, 8)

drivers/net/ethernet/spacemit/k1_emac.h

57

#define EMAC_TX_DLINE_STEP_MASK GENMASK(21, 20)

drivers/net/ethernet/spacemit/k1_emac.h

58

#define EMAC_TX_DLINE_CODE_MASK GENMASK(31, 24)

drivers/net/ethernet/stmicro/stmmac/common.h

565

#define DMA_AXI_BLEN_MASK GENMASK(7, 1)

drivers/net/ethernet/stmicro/stmmac/descs.h

106

#define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22)

drivers/net/ethernet/stmicro/stmmac/descs.h

115

#define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)

drivers/net/ethernet/stmicro/stmmac/descs.h

116

#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)

drivers/net/ethernet/stmicro/stmmac/descs.h

119

#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(6, 2)

drivers/net/ethernet/stmicro/stmmac/descs.h

125

#define ERDES4_MSG_TYPE_MASK GENMASK(11, 8)

drivers/net/ethernet/stmicro/stmmac/descs.h

131

#define ERDES4_VLAN_TAG_PRI_VAL_MASK GENMASK(20, 18)

drivers/net/ethernet/stmicro/stmmac/descs.h

134

#define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)

drivers/net/ethernet/stmicro/stmmac/descs.h

34

#define RDES0_FRAME_LEN_MASK GENMASK(29, 16)

drivers/net/ethernet/stmicro/stmmac/descs.h

38

#define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)

drivers/net/ethernet/stmicro/stmmac/descs.h

39

#define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)

drivers/net/ethernet/stmicro/stmmac/descs.h

50

#define ERDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)

drivers/net/ethernet/stmicro/stmmac/descs.h

53

#define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)

drivers/net/ethernet/stmicro/stmmac/descs.h

61

#define TDES0_COLLISION_COUNT_MASK GENMASK(6, 3)

drivers/net/ethernet/stmicro/stmmac/descs.h

75

#define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)

drivers/net/ethernet/stmicro/stmmac/descs.h

76

#define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)

drivers/net/ethernet/stmicro/stmmac/descs.h

82

#define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)

drivers/net/ethernet/stmicro/stmmac/descs.h

92

#define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3)

drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

34

#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c

35

#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

25

#define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

26

#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

31

#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

40

#define CTRL_SPEED_MASK GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

23

#define MACPHYC_TXCLK_SEL_MASK GENMASK(31, 31)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

26

#define MACPHYC_MODE_SEL_MASK GENMASK(31, 31)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

28

#define MACPHYC_TX_SEL_MASK GENMASK(19, 19)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

31

#define MACPHYC_TX_DELAY_MASK GENMASK(18, 12)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

32

#define MACPHYC_RX_SEL_MASK GENMASK(11, 11)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

35

#define MACPHYC_RX_DELAY_MASK GENMASK(10, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

36

#define MACPHYC_SOFT_RST_MASK GENMASK(3, 3)

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

37

#define MACPHYC_PHY_INFT_MASK GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

20

#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

21

#define SERDES_RATE_MASK GENMASK(9, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

22

#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

23

#define SERDES_LINK_MODE_MASK GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

58

#define B_PCH_FIA_PCR_L0O GENMASK(3, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

101

#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

103

#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

91

#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

93

#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

95

#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

97

#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

99

#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22)

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c

374

mac->mii.clk_csr_mask = GENMASK(5, 2);

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c

40

#define PHY_INTF_SELI GENMASK(30, 28)

drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c

24

# define LPC18XX_CREG_CREG6_ETHMODE_MASK GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

26

#define ETH_DLY_GTXC_STAGES GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

29

#define ETH_DLY_TXC_STAGES GENMASK(18, 14)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

32

#define ETH_DLY_RXC_STAGES GENMASK(11, 7)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

43

#define MT8195_ETH_INTF_SEL GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

48

#define MT8195_DLY_GTXC_STAGES GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

53

#define MT8195_DLY_RXC_STAGES GENMASK(17, 13)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

56

#define MT8195_DLY_TXC_STAGES GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

61

#define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13)

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

64

#define MT8195_DLY_RMII_TXC_STAGES GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

28

#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

31

#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

37

#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

62

#define PRG_ETH0_ADJ_DELAY GENMASK(19, 15)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

67

#define PRG_ETH0_ADJ_SKEW GENMASK(24, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

77

#define PRG_ETH1_CFG_RXCLK_DLY GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

141

mac[0] = FIELD_GET(GENMASK(15, 8), maca0hr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

142

mac[1] = FIELD_GET(GENMASK(7, 0), maca0hr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

143

mac[2] = FIELD_GET(GENMASK(31, 24), maca0lr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

144

mac[3] = FIELD_GET(GENMASK(23, 16), maca0lr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

145

mac[4] = FIELD_GET(GENMASK(15, 8), maca0lr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

146

mac[5] = FIELD_GET(GENMASK(7, 0), maca0lr);

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

34

#define INT_MODERATION_RX GENMASK(11, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

35

#define INT_MODERATION_TX GENMASK(27, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

37

#define EFUSE_OP_MODE GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

40

#define EFUSE_OP_ADDR GENMASK(15, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c

43

#define EFUSE_OP_RD_DATA GENMASK(31, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

29

#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

30

#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

31

#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

32

#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

33

#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

38

#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

43

#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

44

#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

490

BIT(12) | GENMASK(9, 8),

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

50

#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

54

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

55

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

568

rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

57

#define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

58

#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

62

#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

63

#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

71

#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

64

#define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6)

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

69

#define ENMII_MASK GENMASK(5, 5)

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

71

#define EN_MASK GENMASK(1, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c

82

#define MII_PHY_SEL_MASK GENMASK(4, 2)

drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

25

#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

50

#define SYSCFG_PMCR_PHY_INTF_SEL_MASK GENMASK(23, 21)

drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

55

#define SYSCFG_MP2_ETH_MASK GENMASK(31, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

57

#define SYSCFG_ETHCR_ETH_SEL_MASK GENMASK(6, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c

31

#define SYSCON_ETXDC_MASK GENMASK(12, 10)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c

32

#define SYSCON_ERXDC_MASK GENMASK(9, 5)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c

35

#define SYSCON_ETCS_MASK GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

1059

mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

1067

mac->mii.reg_mask = GENMASK(8, 4);

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

1069

mac->mii.addr_mask = GENMASK(16, 12);

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

1071

mac->mii.clk_csr_mask = GENMASK(22, 20);

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

186

#define EMAC_RX_TH_MASK GENMASK(5, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

197

#define EMAC_TX_TH_MASK GENMASK(10, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

267

#define SYSCON_ETCS_MASK GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c

29

#define GMAC_RXCLK_DELAY GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c

33

#define GMAC_TXCLK_DELAY GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c

36

#define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac100.h

46

#define MAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */

drivers/net/ethernet/stmicro/stmmac/dwmac100.h

54

#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

114

#define GMAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

125

#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

131

#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

137

#define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

142

#define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

149

#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

156

#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

167

#define DMA_BUS_MODE_RPBL_MASK GENMASK(22, 17) /* Rx-Programmable Burst Len */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

261

#define GMAC3_X_ATSNS GENMASK(29, 25)

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

74

#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

504

mac->mii.clk_csr_mask = GENMASK(5, 2);

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

192

mac->mii.clk_csr_mask = GENMASK(5, 2);

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

144

#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

150

#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

155

#define GMAC_CONFIG_SARC GENMASK(30, 28)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

157

#define GMAC_CONFIG_IPG GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

172

#define GMAC_CONFIG_EIPG GENMASK(29, 25)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

174

#define GMAC_CONFIG_HDSMS GENMASK(22, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

196

#define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

197

#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

201

#define GMAC_HW_ADDR64 GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

202

#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

203

#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

206

#define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

207

#define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

208

#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

209

#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

210

#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

211

#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

214

#define GMAC_HW_FEAT_ASP GENMASK(29, 28)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

217

#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

218

#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

220

#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

221

#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

224

#define GMAC_HW_FEAT_NRVF GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

228

#define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

237

#define GMAC_HI_DCS GENMASK(18, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

251

#define GMAC_L4DP0 GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

252

#define GMAC_L4SP0 GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

256

#define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

262

#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

302

#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

307

#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

309

#define MTL_OP_MODE_TTC_MASK GENMASK(6, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

319

#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

321

#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

323

#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

328

#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

372

#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

391

#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

410

#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

429

#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

437

#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

445

#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

450

#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

474

#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

52

#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

54

#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

56

#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

58

#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

60

#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

66

#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

81

#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

89

#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

93

#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

98

#define GMAC_TX_FLOW_CTRL_PT_MASK GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

1034

mac->mii.addr_mask = GENMASK(25, 21);

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

1036

mac->mii.reg_mask = GENMASK(20, 16);

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

1038

mac->mii.clk_csr_mask = GENMASK(11, 8);

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

100

#define RDES2_L3_L4_HEADER_SIZE_MASK GENMASK(9, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

105

#define RDES2_MAC_ADDR_MATCH_MASK GENMASK(26, 19)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

106

#define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

109

#define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

111

#define RDES2_HL GENMASK(9, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

114

#define RDES3_PACKET_SIZE_MASK GENMASK(14, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

116

#define RDES3_PACKET_LEN_TYPE_MASK GENMASK(18, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

19

#define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

20

#define TDES2_VLAN_TAG_MASK GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

21

#define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

22

#define TDES3_IVTIR_MASK GENMASK(19, 18)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

25

#define TDES2_IVT_MASK GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

29

#define TDES3_PACKET_SIZE_MASK GENMASK(14, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

30

#define TDES3_VLAN_TAG GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

32

#define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

33

#define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

35

#define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

36

#define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

37

#define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

44

#define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

70

#define TDES4_LT GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

73

#define TDES5_LT GENMASK(31, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

82

#define RDES0_VLAN_TAG_MASK GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

85

#define RDES1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

91

#define RDES1_PTP_MSG_TYPE_MASK GENMASK(11, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

97

#define RDES1_IP_TYPE1_CSUM_MASK GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

140

#define DMA_CHAN_STATUS_REB GENMASK(21, 19)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

21

#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

36

#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

37

#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

46

#define DMA_TBS_FTOS GENMASK(31, 8)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

75

#define DMA_CHAN_TX_CTRL_TXPBL_MASK GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

82

#define DMA_CHAN_RX_CTRL_RXPBL_MASK GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

83

#define DMA_RBSZ_MASK GENMASK(14, 1)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

17

#define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

20

GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

23

GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

29

#define TTSL0 GENMASK(30, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

35

#define NPE GENMASK(23, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

36

#define NVE GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

39

#define RXPEIEC GENMASK(22, 21)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

42

#define ADDR GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwmac5.h

78

#define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17)

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

130

#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

131

#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

28

#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

29

#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

109

#define XGMAC_HWFEAT_TSSTSSEL GENMASK(26, 25)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

110

#define XGMAC_HWFEAT_PHYSEL GENMASK(24, 23)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

111

#define XGMAC_HWFEAT_ADDMACADRSEL GENMASK(22, 18)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

127

#define XGMAC_HWFEAT_L3L4FNUM GENMASK(30, 27)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

128

#define XGMAC_HWFEAT_HASHTBLSZ GENMASK(25, 24)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

129

#define XGMAC_HWFEAT_NUMTC GENMASK(23, 21)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

135

#define XGMAC_HWFEAT_ADDR64 GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

139

#define XGMAC_HWFEAT_TXFIFOSIZE GENMASK(10, 6)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

141

#define XGMAC_HWFEAT_RXFIFOSIZE GENMASK(4, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

143

#define XGMAC_HWFEAT_AUXSNAPNUM GENMASK(30, 28)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

144

#define XGMAC_HWFEAT_PPSOUTNUM GENMASK(26, 24)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

145

#define XGMAC_HWFEAT_TXCHCNT GENMASK(21, 18)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

146

#define XGMAC_HWFEAT_RXCHCNT GENMASK(15, 12)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

147

#define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

148

#define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

150

#define XGMAC_HWFEAT_TBSCH GENMASK(31, 28)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

154

#define XGMAC_HWFEAT_ESTWID GENMASK(24, 23)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

155

#define XGMAC_HWFEAT_ESTDEP GENMASK(22, 20)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

157

#define XGMAC_HWFEAT_TTSFD GENMASK(18, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

158

#define XGMAC_HWFEAT_ASP GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

160

#define XGMAC_HWFEAT_FRPES GENMASK(12, 11)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

161

#define XGMAC_HWFEAT_FRPPB GENMASK(10, 9)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

163

#define XGMAC_HWFEAT_FRPPIPE GENMASK(7, 5)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

166

#define XGMAC_HWFEAT_NRVF GENMASK(2, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

169

#define XGMAC_HWFEAT_PCSEL GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

18

#define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

182

#define XGMAC_DCS GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

185

#define XGMAC_IDDR GENMASK(16, 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

186

#define XGMAC_IDDR_FNUM_MASK GENMASK(7, 4) /* FNUM within IDDR */

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

187

#define XGMAC_IDDR_REG_MASK GENMASK(3, 0) /* REG within IDDR */

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

197

#define XGMAC_L3HDBM0 GENMASK(15, 11)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

198

#define XGMAC_L3HSBM0 GENMASK(10, 6)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

205

#define XGMAC_L4DP0 GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

206

#define XGMAC_L4SP0 GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

224

#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

227

#define XGMAC_TXTSSTSLO GENMASK(30, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

233

GENMASK(XGMAC_PPS_MAXIDX(x), XGMAC_PPS_MINIDX(x))

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

235

GENMASK(XGMAC_PPS_MAXIDX(x) - 1, XGMAC_PPS_MAXIDX(x) - 2) & \

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

238

GENMASK(XGMAC_PPS_MINIDX(x) + 3, XGMAC_PPS_MINIDX(x)) & \

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

252

#define XGMAC_ETSALG GENMASK(6, 5)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

26

#define XGMAC_CONFIG_SARC GENMASK(22, 20)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

260

#define XGMAC_QxMDMACH(x) GENMASK((x) * 8 + 7, (x) * 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

265

#define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

269

#define XGMAC_NPE GENMASK(23, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

270

#define XGMAC_NVE GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

274

#define XGMAC_ADDR GENMASK(9, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

289

#define XGMAC_TQS GENMASK(25, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

290

#define XGMAC_Q2TCMAP GENMASK(10, 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

291

#define XGMAC_TTC GENMASK(6, 4)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

292

#define XGMAC_TXQEN GENMASK(3, 2)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

300

#define XGMAC_TSA GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

305

#define XGMAC_RQS GENMASK(25, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

308

#define XGMAC_RTC GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

310

#define XGMAC_RFD GENMASK(31, 17)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

311

#define XGMAC_RFA GENMASK(15, 1)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

32

#define XGMAC_CONFIG_GPSL GENMASK(29, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

324

#define XGMAC_WR_OSR_LMT GENMASK(29, 24)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

325

#define XGMAC_RD_OSR_LMT GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

33

#define XGMAC_CONFIG_HDSMS GENMASK(14, 12)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

333

#define XGMAC_TDPS GENMASK(29, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

335

#define XGMAC_RDPS GENMASK(29, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

340

#define XGMAC_FTOS GENMASK(31, 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

359

#define XGMAC_TxPBL GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

364

#define XGMAC_RxPBL GENMASK(21, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

365

#define XGMAC_RBSZ GENMASK(14, 1)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

387

#define XGMAC_RWT GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

407

#define XGMAC_TDES0_LT GENMASK(7, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

408

#define XGMAC_TDES1_LT GENMASK(31, 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

409

#define XGMAC_TDES2_IVT GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

412

#define XGMAC_TDES2_B2L GENMASK(29, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

413

#define XGMAC_TDES2_VTIR GENMASK(15, 14)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

414

#define XGMAC_TDES2_B1L GENMASK(13, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

419

#define XGMAC_TDES3_CPC GENMASK(27, 26)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

421

#define XGMAC_TDES3_SAIC GENMASK(25, 23)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

423

#define XGMAC_TDES3_THL GENMASK(22, 19)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

424

#define XGMAC_TDES3_IVTIR GENMASK(19, 18)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

427

#define XGMAC_TDES3_CIC GENMASK(17, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

428

#define XGMAC_TDES3_TPL GENMASK(17, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

430

#define XGMAC_TDES3_VT GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

431

#define XGMAC_TDES3_FL GENMASK(14, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

432

#define XGMAC_RDES2_HL GENMASK(9, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

439

#define XGMAC_RDES3_L34T GENMASK(23, 20)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

440

#define XGMAC_RDES3_ET_LT GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

446

#define XGMAC_RDES3_PL GENMASK(13, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

451

#define XGMAC_RDES0_VLAN_TAG_MASK GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

61

#define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

64

#define XGMAC_AVCPQ GENMASK(31, 28)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

66

#define XGMAC_PTPQ GENMASK(27, 24)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

69

#define XGMAC_DCBCPQ GENMASK(19, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

72

#define XGMAC_MCBCQ GENMASK(11, 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

74

#define XGMAC_FPRQ GENMASK(7, 4)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

75

#define XGMAC_UPQ GENMASK(3, 0)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

79

#define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

92

#define XGMAC_PT GENMASK(31, 16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1555

mac->mii.addr_mask = GENMASK(20, 16);

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1557

mac->mii.reg_mask = GENMASK(15, 0);

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1559

mac->mii.clk_csr_mask = GENMASK(21, 19);

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1598

mac->mii.addr_mask = GENMASK(20, 16);

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1600

mac->mii.reg_mask = GENMASK(15, 0);

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

1602

mac->mii.clk_csr_mask = GENMASK(21, 19);

drivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h

11

#define XLGMAC_CONFIG_SS GENMASK(30, 28)

drivers/net/ethernet/stmicro/stmmac/mmc_core.c

417

if (tmp > GENMASK(31, 0))

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

11

#define EST_GMAC5_PTOV GENMASK(31, 24)

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

14

#define EST_XGMAC_PTOV GENMASK(31, 23)

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

22

#define EST_GMAC5_BTRL GENMASK(11, 8)

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

23

#define EST_XGMAC_BTRL GENMASK(15, 8)

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

37

#define EST_SZ_CAP_HBFS_MASK GENMASK(14, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

42

(_val > 4 ? GENMASK(18, 16) : \

drivers/net/ethernet/stmicro/stmmac/stmmac_est.h

43

_val > 2 ? GENMASK(17, 16) : \

drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c

18

#define FPE_MTL_PREEMPTION_CLASS GENMASK(15, 8)

drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c

20

#define FPE_MTL_ADD_FRAG_SZ GENMASK(1, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c

224

preemptible_txqs |= GENMASK(offset + count - 1, offset);

drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c

282

preemptible_txqs |= GENMASK(offset + count - 1, offset);

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

124

ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

28

#define MII_DATA_GD_MASK GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

44

#define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h

83

#define PTP_ACR_MASK GENMASK(7, 4) /* Aux Snapshot Mask */

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

1015

if (delta_ns > GENMASK(wid - 1, 0))

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

1017

if (gates > GENMASK(31 - wid, 0))

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

137

GENMASK(31, rem * 8);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

139

GENMASK(31, rem * 8);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

144

GENMASK(rem * 8 - 1, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

146

GENMASK(rem * 8 - 1, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

394

priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

397

priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

400

priv->plat->tx_queues_cfg[queue].high_credit = value & GENMASK(31, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c

403

priv->plat->tx_queues_cfg[queue].low_credit = value & GENMASK(31, 0);

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

24

#define VLAN_VID GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

27

#define VLAN_VLC GENMASK(17, 16)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

29

#define VLAN_VLHT GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

32

#define VLAN_TAG_VID GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

38

#define VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

40

#define VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

50

#define VLAN_TAG_DATA_VID GENMASK(15, 0)

drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.h

56

#define VLAN_HW_FEAT_NRVF GENMASK(2, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

111

#define MAC_DIS_MC2CPU GENMASK(3, 2)

drivers/net/ethernet/sunplus/spl2sw_define.h

114

#define MAC_DIS_UN2CPU GENMASK(1, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

117

#define MAC_DIS_PORT GENMASK(25, 24)

drivers/net/ethernet/sunplus/spl2sw_define.h

136

#define MAC_RMC_TB_FAULT_RULE GENMASK(26, 25)

drivers/net/ethernet/sunplus/spl2sw_define.h

137

#define MAC_LED_FLASH_TIME GENMASK(24, 23)

drivers/net/ethernet/sunplus/spl2sw_define.h

138

#define MAC_BC_STORM_PREV GENMASK(5, 4)

drivers/net/ethernet/sunplus/spl2sw_define.h

144

#define MAC_CPU_PHY_WT_DATA GENMASK(31, 16)

drivers/net/ethernet/sunplus/spl2sw_define.h

145

#define MAC_CPU_PHY_CMD GENMASK(14, 13)

drivers/net/ethernet/sunplus/spl2sw_define.h

146

#define MAC_CPU_PHY_REG_ADDR GENMASK(12, 8)

drivers/net/ethernet/sunplus/spl2sw_define.h

147

#define MAC_CPU_PHY_ADDR GENMASK(4, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

150

#define MAC_CPU_PHY_RD_DATA GENMASK(31, 16)

drivers/net/ethernet/sunplus/spl2sw_define.h

155

#define MAC_EXT_PHY1_ADDR GENMASK(28, 24)

drivers/net/ethernet/sunplus/spl2sw_define.h

156

#define MAC_EXT_PHY0_ADDR GENMASK(20, 16)

drivers/net/ethernet/sunplus/spl2sw_define.h

157

#define MAC_FORCE_RMII_LINK GENMASK(9, 8)

drivers/net/ethernet/sunplus/spl2sw_define.h

160

#define MAC_FORCE_RMII_FC GENMASK(5, 4)

drivers/net/ethernet/sunplus/spl2sw_define.h

161

#define MAC_FORCE_RMII_DPX GENMASK(3, 2)

drivers/net/ethernet/sunplus/spl2sw_define.h

162

#define MAC_FORCE_RMII_SPD GENMASK(1, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

181

#define TXD_ERR_CODE GENMASK(29, 26)

drivers/net/ethernet/sunplus/spl2sw_define.h

184

#define TXD_VLAN GENMASK(17, 12)

drivers/net/ethernet/sunplus/spl2sw_define.h

185

#define TXD_PKT_LEN GENMASK(10, 0) /* packet length */

drivers/net/ethernet/sunplus/spl2sw_define.h

188

#define TXD_BUF_LEN2 GENMASK(22, 12)

drivers/net/ethernet/sunplus/spl2sw_define.h

189

#define TXD_BUF_LEN1 GENMASK(10, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

194

#define RXD_ERR_CODE GENMASK(29, 26)

drivers/net/ethernet/sunplus/spl2sw_define.h

197

#define RXD_PROTOCOL GENMASK(21, 20)

drivers/net/ethernet/sunplus/spl2sw_define.h

200

#define RXD_ROUTE_TYPE GENMASK(17, 16)

drivers/net/ethernet/sunplus/spl2sw_define.h

201

#define RXD_PKT_SP GENMASK(14, 12) /* packet source port */

drivers/net/ethernet/sunplus/spl2sw_define.h

202

#define RXD_PKT_LEN GENMASK(10, 0) /* packet length */

drivers/net/ethernet/sunplus/spl2sw_define.h

205

#define RXD_BUF_LEN2 GENMASK(22, 12)

drivers/net/ethernet/sunplus/spl2sw_define.h

206

#define RXD_BUF_LEN1 GENMASK(10, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

53

#define MAC_HASH_LOOKUP_ADDR GENMASK(31, 22)

drivers/net/ethernet/sunplus/spl2sw_define.h

54

#define MAC_R_PORT_MAP GENMASK(13, 12)

drivers/net/ethernet/sunplus/spl2sw_define.h

55

#define MAC_R_CPU_PORT GENMASK(11, 10)

drivers/net/ethernet/sunplus/spl2sw_define.h

56

#define MAC_R_VID GENMASK(9, 7)

drivers/net/ethernet/sunplus/spl2sw_define.h

57

#define MAC_R_AGE GENMASK(6, 4)

drivers/net/ethernet/sunplus/spl2sw_define.h

64

#define MAC_W_PORT_MAP GENMASK(13, 12)

drivers/net/ethernet/sunplus/spl2sw_define.h

67

#define MAC_W_CPU_PORT GENMASK(11, 10)

drivers/net/ethernet/sunplus/spl2sw_define.h

70

#define MAC_W_VID GENMASK(9, 7)

drivers/net/ethernet/sunplus/spl2sw_define.h

71

#define MAC_W_AGE GENMASK(6, 4)

drivers/net/ethernet/sunplus/spl2sw_define.h

78

#define MAC_W_MAC_15_0 GENMASK(15, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

81

#define MAC_W_MAC_47_16 GENMASK(31, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

84

#define MAC_P1_PVID GENMASK(6, 4)

drivers/net/ethernet/sunplus/spl2sw_define.h

85

#define MAC_P0_PVID GENMASK(2, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

88

#define MAC_VLAN_MEMSET_3 GENMASK(27, 24)

drivers/net/ethernet/sunplus/spl2sw_define.h

89

#define MAC_VLAN_MEMSET_2 GENMASK(19, 16)

drivers/net/ethernet/sunplus/spl2sw_define.h

90

#define MAC_VLAN_MEMSET_1 GENMASK(11, 8)

drivers/net/ethernet/sunplus/spl2sw_define.h

91

#define MAC_VLAN_MEMSET_0 GENMASK(3, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

94

#define MAC_VLAN_MEMSET_5 GENMASK(11, 8)

drivers/net/ethernet/sunplus/spl2sw_define.h

95

#define MAC_VLAN_MEMSET_4 GENMASK(3, 0)

drivers/net/ethernet/sunplus/spl2sw_define.h

98

#define MAC_PORT_ABILITY_LINK_ST GENMASK(25, 24)

drivers/net/ethernet/synopsys/dwc-xlgmac.h

104

((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \

drivers/net/ethernet/synopsys/dwc-xlgmac.h

111

((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \

drivers/net/ethernet/synopsys/dwc-xlgmac.h

119

_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \

drivers/net/ethernet/synopsys/dwc-xlgmac.h

120

_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \

drivers/net/ethernet/synopsys/dwc-xlgmac.h

128

_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \

drivers/net/ethernet/synopsys/dwc-xlgmac.h

129

_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \

drivers/net/ethernet/tehuti/tn40.h

193

#define TN40_GET_RXD_BC(x) FIELD_GET(GENMASK(4, 0), (x))

drivers/net/ethernet/tehuti/tn40.h

194

#define TN40_GET_RXD_ERR(x) FIELD_GET(GENMASK(26, 21), (x))

drivers/net/ethernet/tehuti/tn40.h

195

#define TN40_GET_RXD_PKT_ID(x) FIELD_GET(GENMASK(30, 28), (x))

drivers/net/ethernet/tehuti/tn40.h

197

#define TN40_GET_RXD_VLAN_TCI(x) FIELD_GET(GENMASK(15, 0), (x))

drivers/net/ethernet/tehuti/tn40.h

221

GENMASK(17, 16) | \

drivers/net/ethernet/tehuti/tn40.h

222

FIELD_PREP(GENMASK(4, 0), (bc)) | \

drivers/net/ethernet/tehuti/tn40.h

223

FIELD_PREP(GENMASK(7, 5), (checksum)) | \

drivers/net/ethernet/tehuti/tn40.h

225

FIELD_PREP(GENMASK(12, 9), (lgsnd)) | \

drivers/net/ethernet/tehuti/tn40.h

226

FIELD_PREP(GENMASK(15, 13), \

drivers/net/ethernet/tehuti/tn40.h

227

FIELD_GET(GENMASK(15, 13), (vlan_id))) | \

drivers/net/ethernet/tehuti/tn40.h

228

FIELD_PREP(GENMASK(31, 20), \

drivers/net/ethernet/tehuti/tn40.h

229

FIELD_GET(GENMASK(11, 0), (vlan_id))) \

drivers/net/ethernet/tehuti/tn40.h

35

FIELD_PREP(GENMASK(14, 0), (coal)) | \

drivers/net/ethernet/tehuti/tn40.h

37

FIELD_PREP(GENMASK(19, 16), (rxf_th)) | \

drivers/net/ethernet/tehuti/tn40.h

38

FIELD_PREP(GENMASK(31, 20), (pck_th)) \

drivers/net/ethernet/tehuti/tn40_mdio.c

10

#define TN40_MDIO_DEVAD_MASK GENMASK(4, 0)

drivers/net/ethernet/tehuti/tn40_mdio.c

11

#define TN40_MDIO_PRTAD_MASK GENMASK(9, 5)

drivers/net/ethernet/tehuti/tn40_regs.h

144

#define TN40_GET_MDIO_BUSY(x) FIELD_GET(GENMASK(0, 0), (x))

drivers/net/ethernet/tehuti/tn40_regs.h

145

#define TN40_GET_MDIO_RD_ERR(x) FIELD_GET(GENMASK(1, 1), (x))

drivers/net/ethernet/ti/am65-cpsw-nuss.c

1236

#define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0)

drivers/net/ethernet/ti/am65-cpsw-nuss.c

187

#define AM65_CPSW_DSCP_MAX GENMASK(5, 0)

drivers/net/ethernet/ti/am65-cpsw-nuss.c

188

#define AM65_CPSW_PRI_MAX GENMASK(2, 0)

drivers/net/ethernet/ti/am65-cpsw-nuss.c

2722

if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) {

drivers/net/ethernet/ti/am65-cpsw-nuss.c

2901

if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask))

drivers/net/ethernet/ti/am65-cpsw-nuss.c

919

port_mask = GENMASK(common->port_num, 0) &

drivers/net/ethernet/ti/am65-cpsw-qos.c

1255

ch_msk = GENMASK(common->tx_ch_num - 1, queue);

drivers/net/ethernet/ti/am65-cpsw-qos.c

1259

ch_msk = queue ? GENMASK(queue - 1, 0) : 0;

drivers/net/ethernet/ti/am65-cpsw-qos.c

161

ch_msk = GENMASK(num_tc - 1, i);

drivers/net/ethernet/ti/am65-cpsw-qos.h

162

#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)

drivers/net/ethernet/ti/am65-cpsw-qos.h

168

#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK GENMASK(10, 8)

drivers/net/ethernet/ti/am65-cpsw-qos.h

170

#define AM65_CPSW_PN_IET_MAC_PREMPT_MASK GENMASK(23, 16)

drivers/net/ethernet/ti/am65-cpsw-qos.h

183

#define AM65_CPSW_PN_MAC_STATUS GENMASK(3, 0)

drivers/net/ethernet/ti/am65-cpsw-qos.h

190

#define AM65_CPSW_PN_MAC_VERIFY_CNT_MASK GENMASK(23, 0)

drivers/net/ethernet/ti/am65-cpsw-qos.h

198

#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)

drivers/net/ethernet/ti/am65-cpsw-qos.h

199

#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)

drivers/net/ethernet/ti/am65-cpsw-qos.h

206

#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)

drivers/net/ethernet/ti/am65-cpsw-qos.h

209

#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)

drivers/net/ethernet/ti/am65-cpsw-qos.h

76

#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)

drivers/net/ethernet/ti/am65-cpsw-qos.h

79

#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)

drivers/net/ethernet/ti/am65-cpsw-qos.h

80

#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)

drivers/net/ethernet/ti/am65-cpsw-qos.h

87

#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)

drivers/net/ethernet/ti/am65-cpsw-qos.h

90

#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)

drivers/net/ethernet/ti/am65-cpts.c

116

#define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0)

drivers/net/ethernet/ti/am65-cpts.c

118

#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16)

drivers/net/ethernet/ti/am65-cpts.c

121

#define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20)

drivers/net/ethernet/ti/am65-cpts.c

124

#define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24)

drivers/net/ethernet/ti/cpsw_ale.c

60

#define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0)

drivers/net/ethernet/ti/cpsw_ale.c

65

#define ALE_AGING_TIMER_MASK GENMASK(23, 0)

drivers/net/ethernet/ti/cpsw_priv.h

132

#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)

drivers/net/ethernet/ti/cpsw_priv.h

135

#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)

drivers/net/ethernet/ti/davinci_mdio.c

54

#define CONTROL_CLKDIV GENMASK(15, 0)

drivers/net/ethernet/ti/icssg/icss_iep.c

29

#define IEP_GLOBAL_CFG_DEFAULT_INC_MASK GENMASK(7, 4)

drivers/net/ethernet/ti/icssg/icss_iep.c

31

#define IEP_GLOBAL_CFG_COMPEN_INC_MASK GENMASK(19, 8)

drivers/net/ethernet/ti/icssg/icss_iep.c

38

#define IEP_CMP_CFG_CMP_EN(cmp) (GENMASK(16, 1) & (1 << ((cmp) + 1)))

drivers/net/ethernet/ti/icssg/icss_iep.c

43

#define IEP_SYNC_CTRL_SYNC_N_EN(n) (GENMASK(2, 1) & (BIT(1) << (n)))

drivers/net/ethernet/ti/icssg/icssg_classifier.c

33

#define FT1_LEN_MASK GENMASK(19, 16)

drivers/net/ethernet/ti/icssg/icssg_classifier.c

36

#define FT1_START_MASK GENMASK(14, 0)

drivers/net/ethernet/ti/icssg/icssg_classifier.c

38

#define FT1_MATCH_SLOT(n) (GENMASK(23, 16) & (BIT(n) << 16))

drivers/net/ethernet/ti/icssg/icssg_classifier.c

96

#define RX_CLASS_FT_FT1_MATCH_MASK GENMASK(23, 16)

drivers/net/ethernet/ti/icssg/icssg_classifier.c

98

#define RX_CLASS_FT_FT3_MATCH_MASK GENMASK(15, 0)

drivers/net/ethernet/ti/icssg/icssg_common.c

647

iepcount_lo = lo & GENMASK(19, 0);

drivers/net/ethernet/ti/icssg/icssg_common.c

648

iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20;

drivers/net/ethernet/ti/icssg/icssg_config.c

68

#define SMEM_VLAN_OFFSET_MASK GENMASK(25, 8)

drivers/net/ethernet/ti/icssg/icssg_config.c

69

#define FDB_HASH_SIZE_MASK GENMASK(6, 3)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

108

#define ICSSG_CFG_MII1_MODE GENMASK(6, 5)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

110

#define ICSSG_CFG_MII0_MODE GENMASK(4, 3)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

128

#define RGMII_CFG_SPEED_MII0 GENMASK(2, 1)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

129

#define RGMII_CFG_SPEED_MII1 GENMASK(6, 5)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

54

#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

57

#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

61

#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

69

#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

72

#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

84

#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0)

drivers/net/ethernet/ti/icssg/icssg_mii_rt.h

87

#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4)

drivers/net/ethernet/ti/icssg/icssg_prueth.c

498

sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0);

drivers/net/ethernet/ti/icssg/icssg_prueth.c

499

sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32;

drivers/net/ethernet/ti/icssm/icssm_switch.h

95

#define PRUETH_BD_PORT_MASK GENMASK(17, 16)

drivers/net/ethernet/ti/icssm/icssm_switch.h

98

#define PRUETH_BD_LENGTH_MASK GENMASK(28, 18)

drivers/net/ethernet/vertexcom/mse102x.c

38

#define CMD_MASK GENMASK(15, CMD_SHIFT)

drivers/net/ethernet/vertexcom/mse102x.c

39

#define LEN_MASK GENMASK(CMD_SHIFT - 2, 0)

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1511

wr32(wx, WX_RDM_VF_RE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

1513

wr32(wx, WX_TDM_VF_TE(reg_offset), GENMASK(31, vf_shift));

drivers/net/ethernet/wangxun/libwx/wx_hw.c

2168

#define WX_RDB_RSS_PL_2 FIELD_PREP(GENMASK(31, 29), 1)

drivers/net/ethernet/wangxun/libwx/wx_hw.c

2169

#define WX_RDB_RSS_PL_4 FIELD_PREP(GENMASK(31, 29), 2)

drivers/net/ethernet/wangxun/libwx/wx_mbx.h

35

#define WX_MBVFICR_VFREQ_MASK GENMASK(15, 0)

drivers/net/ethernet/wangxun/libwx/wx_mbx.h

36

#define WX_MBVFICR_VFACK_MASK GENMASK(31, 16)

drivers/net/ethernet/wangxun/libwx/wx_mbx.h

42

#define WX_VT_MSGINFO_MASK GENMASK(23, 16)

drivers/net/ethernet/wangxun/libwx/wx_sriov.c

885

msgbuf[1] = FIELD_PREP(GENMASK(31, 1), wx->speed) | link_up;

drivers/net/ethernet/wangxun/libwx/wx_sriov.h

8

#define WX_VF_NUM_GET(_m) FIELD_GET(GENMASK(5, 0), (_m))

drivers/net/ethernet/wangxun/libwx/wx_type.h

106

#define WX_CFG_PORT_ST_LANID GENMASK(9, 8)

drivers/net/ethernet/wangxun/libwx/wx_type.h

108

#define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */

drivers/net/ethernet/wangxun/libwx/wx_type.h

111

#define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)

drivers/net/ethernet/wangxun/libwx/wx_type.h

112

#define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)

drivers/net/ethernet/wangxun/libwx/wx_type.h

113

#define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)

drivers/net/ethernet/wangxun/libwx/wx_type.h

179

#define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16)

drivers/net/ethernet/wangxun/libwx/wx_type.h

191

#define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16)

drivers/net/ethernet/wangxun/libwx/wx_type.h

226

#define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

227

#define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)

drivers/net/ethernet/wangxun/libwx/wx_type.h

232

#define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)

drivers/net/ethernet/wangxun/libwx/wx_type.h

233

#define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)

drivers/net/ethernet/wangxun/libwx/wx_type.h

234

#define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)

drivers/net/ethernet/wangxun/libwx/wx_type.h

238

#define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))

drivers/net/ethernet/wangxun/libwx/wx_type.h

239

#define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))

drivers/net/ethernet/wangxun/libwx/wx_type.h

242

#define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)

drivers/net/ethernet/wangxun/libwx/wx_type.h

28

#define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))

drivers/net/ethernet/wangxun/libwx/wx_type.h

29

#define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))

drivers/net/ethernet/wangxun/libwx/wx_type.h

292

#define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

322

#define WX_TSC_BUF_AE_THR GENMASK(9, 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

346

#define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

368

#define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)

drivers/net/ethernet/wangxun/libwx/wx_type.h

380

#define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

385

#define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

386

#define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

388

#define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

399

#define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

462

#define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3)

drivers/net/ethernet/wangxun/libwx/wx_type.h

465

#define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)

drivers/net/ethernet/wangxun/libwx/wx_type.h

466

#define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)

drivers/net/ethernet/wangxun/libwx/wx_type.h

48

#define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

49

#define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

50

#define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)

drivers/net/ethernet/wangxun/libwx/wx_type.h

585

#define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)

drivers/net/ethernet/wangxun/libwx/wx_type.h

654

#define WX_RXD_RSCCNT_MASK GENMASK(20, 17)

drivers/net/ethernet/wangxun/libwx/wx_type.h

656

#define WX_RXD_NEXTP_MASK GENMASK(19, 4)

drivers/net/ethernet/wangxun/libwx/wx_type.h

710

#define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)

drivers/net/ethernet/wangxun/libwx/wx_vf.c

523

ret = read_poll_timeout_atomic(rd32, val, val & GENMASK(4, 1),

drivers/net/ethernet/wangxun/libwx/wx_vf.c

564

switch (msgbuf[0] & GENMASK(8, 0)) {

drivers/net/ethernet/wangxun/libwx/wx_vf.h

100

#define WX_PFLINK_SPEED(g) FIELD_GET(GENMASK(31, 1), g)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

101

#define WX_VXSTATUS_SPEED(g) FIELD_GET(GENMASK(4, 1), g)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

21

#define WX_VXMRQC_PSR_MASK GENMASK(5, 1)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

22

#define WX_VXMRQC_PSR(f) FIELD_PREP(GENMASK(5, 1), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

23

#define WX_VXMRQC_RSS_HASH(f) FIELD_PREP(GENMASK(15, 13), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

24

#define WX_VXMRQC_RSS_MASK GENMASK(31, 16)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

25

#define WX_VXMRQC_RSS(f) FIELD_PREP(GENMASK(31, 16), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

44

#define WX_VXITR_MASK GENMASK(8, 0)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

71

#define WX_VXRXDCTL_BUFLEN_MASK GENMASK(6, 1)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

72

#define WX_VXRXDCTL_BUFLEN(f) FIELD_PREP(GENMASK(6, 1), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

73

#define WX_VXRXDCTL_BUFSZ_MASK GENMASK(11, 8)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

74

#define WX_VXRXDCTL_BUFSZ(f) FIELD_PREP(GENMASK(11, 8), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

75

#define WX_VXRXDCTL_HDRSZ_MASK GENMASK(15, 12)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

76

#define WX_VXRXDCTL_HDRSZ(f) FIELD_PREP(GENMASK(15, 12), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

78

#define WX_VXRXDCTL_RSCMAX_MASK GENMASK(24, 23)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

79

#define WX_VXRXDCTL_RSCMAX(f) FIELD_PREP(GENMASK(24, 23), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

91

#define WX_VXTXDCTL_BUFLEN(f) FIELD_PREP(GENMASK(6, 1), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

92

#define WX_VXTXDCTL_PTHRESH(f) FIELD_PREP(GENMASK(11, 8), f)

drivers/net/ethernet/wangxun/libwx/wx_vf.h

93

#define WX_VXTXDCTL_WTHRESH(f) FIELD_PREP(GENMASK(22, 16), f)

drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c

172

mii_bus->phy_mask = GENMASK(31, 4);

drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c

543

mii_bus->phy_mask = GENMASK(31, 1);

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

120

#define TXGBE_RDB_FDIR_CTL_DROP_Q(v) FIELD_PREP(GENMASK(14, 8), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

121

#define TXGBE_RDB_FDIR_CTL_HASH_BITS(v) FIELD_PREP(GENMASK(23, 20), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

122

#define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v) FIELD_PREP(GENMASK(27, 24), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

123

#define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v) FIELD_PREP(GENMASK(31, 28), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

132

#define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v) FIELD_PREP(GENMASK(31, 16), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

135

#define TXGBE_RDB_FDIR_CMD_CMD_MASK GENMASK(1, 0)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

136

#define TXGBE_RDB_FDIR_CMD_CMD(v) FIELD_PREP(GENMASK(1, 0), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

142

#define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v) FIELD_PREP(GENMASK(6, 5), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

146

#define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v) FIELD_PREP(GENMASK(22, 16), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

147

#define TXGBE_RDB_FDIR_CMD_VT_POOL(v) FIELD_PREP(GENMASK(29, 24), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

159

#define TXGBE_RDB_FDIR_FLEX_CFG_FIELD0 GENMASK(7, 0)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

160

#define TXGBE_RDB_FDIR_FLEX_CFG_BASE_MAC FIELD_PREP(GENMASK(1, 0), 0)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

162

#define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v) FIELD_PREP(GENMASK(7, 3), v)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

168

#define TXGBE_AML_MAC_TX_CFG_SPEED_MASK GENMASK(30, 27)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

169

#define TXGBE_AML_MAC_TX_CFG_SPEED_40G FIELD_PREP(GENMASK(30, 27), 0)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

170

#define TXGBE_AML_MAC_TX_CFG_SPEED_25G FIELD_PREP(GENMASK(30, 27), 2)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

171

#define TXGBE_AML_MAC_TX_CFG_SPEED_10G FIELD_PREP(GENMASK(30, 27), 8)

drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

309

#define TXGBE_MAX_EITR GENMASK(11, 3)

drivers/net/ethernet/xilinx/xilinx_axienet.h

108

#define XAXIDMA_BD_CTRL_LENGTH_MASK GENMASK(25, 0) /* Requested len */

drivers/net/ethernet/xilinx/xilinx_axienet.h

133

#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK GENMASK(25, 0) /* Actual len */

drivers/net/fjes/fjes_regs.h

107

REG_ICTL_MASK_ALL = GENMASK(20, 16),

drivers/net/fjes/fjes_regs.h

112

REG_IS_MASK_EPID = GENMASK(15, 0),

drivers/net/ipa/gsi.c

1701

u32 event_bitmap = GENMASK(BITS_PER_LONG - 1, evt_ring_max);

drivers/net/ipa/gsi.c

1703

event_bitmap |= GENMASK(GSI_MHI_EVENT_ID_END, GSI_MHI_EVENT_ID_START);

drivers/net/ipa/gsi.c

918

val = (scr.data.word4 & GENMASK(31, 16)) | (val & GENMASK(15, 0));

drivers/net/ipa/gsi_trans.c

82

#define TRE_FLAGS_CHAIN_FMASK GENMASK(0, 0)

drivers/net/ipa/gsi_trans.c

83

#define TRE_FLAGS_IEOT_FMASK GENMASK(9, 9)

drivers/net/ipa/gsi_trans.c

84

#define TRE_FLAGS_BEI_FMASK GENMASK(10, 10)

drivers/net/ipa/gsi_trans.c

85

#define TRE_FLAGS_TYPE_FMASK GENMASK(23, 16)

drivers/net/ipa/ipa_cmd.c

103

#define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0)

drivers/net/ipa/ipa_cmd.c

109

#define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)

drivers/net/ipa/ipa_cmd.c

110

#define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)

drivers/net/ipa/ipa_cmd.c

121

#define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15)

drivers/net/ipa/ipa_cmd.c

124

#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0)

drivers/net/ipa/ipa_cmd.c

126

#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1)

drivers/net/ipa/ipa_cmd.c

127

#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2)

drivers/net/ipa/ipa_cmd.c

460

offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16));

drivers/net/ipa/ipa_cmd.c

69

#define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0)

drivers/net/ipa/ipa_cmd.c

70

#define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12)

drivers/net/ipa/ipa_cmd.c

75

#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)

drivers/net/ipa/ipa_cmd.c

76

#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)

drivers/net/ipa/ipa_cmd.c

88

#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11)

drivers/net/ipa/ipa_cmd.c

90

#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15)

drivers/net/ipa/ipa_cmd.c

93

#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0)

drivers/net/ipa/ipa_endpoint.c

136

return le32_get_bits(word[0], GENMASK(7, 0));

drivers/net/ipa/ipa_endpoint.c

138

return le32_get_bits(word[0], GENMASK(15, 8));

drivers/net/ipa/ipa_endpoint.c

140

return le32_get_bits(word[0], GENMASK(31, 16));

drivers/net/ipa/ipa_endpoint.c

142

return le32_get_bits(word[1], GENMASK(15, 0));

drivers/net/ipa/ipa_endpoint.c

145

return le32_get_bits(word[1], GENMASK(20, 16));

drivers/net/ipa/ipa_endpoint.c

146

return le32_get_bits(word[1], GENMASK(23, 16));

drivers/net/ipa/ipa_endpoint.c

151

return le32_get_bits(word[1], GENMASK(28, 24));

drivers/net/ipa/ipa_endpoint.c

152

return le32_get_bits(word[7], GENMASK(23, 16));

drivers/net/ipa/ipa_endpoint.c

157

return le32_get_bits(word[3], GENMASK(0, 0));

drivers/net/ipa/ipa_endpoint.c

159

return le32_get_bits(word[3], GENMASK(1, 1));

drivers/net/ipa/ipa_endpoint.c

161

return le32_get_bits(word[3], GENMASK(2, 2));

drivers/net/ipa/ipa_endpoint.c

163

return le32_get_bits(word[3], GENMASK(3, 3));

drivers/net/ipa/ipa_endpoint.c

165

return le32_get_bits(word[3], GENMASK(13, 4));

drivers/net/ipa/ipa_endpoint.c

169

return le32_get_bits(word[3], GENMASK(14, 14));

drivers/net/ipa/ipa_endpoint.c

170

return le32_get_bits(word[1], GENMASK(27, 27));

drivers/net/ipa/ipa_endpoint.c

173

return le32_get_bits(word[3], GENMASK(15, 15));

drivers/net/ipa/ipa_endpoint.c

174

return le32_get_bits(word[1], GENMASK(28, 28));

drivers/net/ipa/ipa_endpoint.c

177

return le32_get_bits(word[3], GENMASK(16, 16));

drivers/net/ipa/ipa_endpoint.c

178

return le32_get_bits(word[7], GENMASK(31, 31));

drivers/net/ipa/ipa_endpoint.c

181

return le32_get_bits(word[3], GENMASK(21, 17));

drivers/net/ipa/ipa_endpoint.c

182

return le32_get_bits(word[3], GENMASK(21, 14));

drivers/net/ipa/ipa_endpoint.c

184

return le32_get_bits(word[3], GENMASK(31, 22));

drivers/net/ipa/ipa_endpoint.c

186

return le32_get_bits(word[4], GENMASK(0, 0));

drivers/net/ipa/ipa_endpoint.c

188

return le32_get_bits(word[4], GENMASK(13, 1));

drivers/net/ipa/ipa_endpoint.c

190

return le32_get_bits(word[4], GENMASK(15, 14));

drivers/net/ipa/ipa_endpoint.c

192

return le32_get_bits(word[4], GENMASK(31, 16)) |

drivers/net/ipa/ipa_endpoint.c

193

(le32_get_bits(word[5], GENMASK(15, 0)) << 16);

drivers/net/ipa/ipa_endpoint.c

195

return le32_get_bits(word[5], GENMASK(31, 16));

drivers/net/ipa/ipa_endpoint.c

197

return le32_get_bits(word[6], GENMASK(7, 0));

drivers/net/ipa/ipa_endpoint.c

199

return le32_get_bits(word[6], GENMASK(31, 8));

drivers/net/ipa/ipa_endpoint.c

201

return le32_get_bits(word[7], GENMASK(0, 0));

drivers/net/ipa/ipa_endpoint.c

203

return le32_get_bits(word[7], GENMASK(10, 1));

drivers/net/ipa/ipa_endpoint.c

205

return le32_get_bits(word[7], GENMASK(11, 11));

drivers/net/ipa/ipa_endpoint.c

207

return le32_get_bits(word[7], GENMASK(15, 12));

drivers/net/ipa/reg/gsi_reg-v3.1.c

109

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

110

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v3.1.c

111

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

152

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

154

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

160

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

162

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

168

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

169

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v3.1.c

170

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v3.1.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.1.c

228

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v3.1.c

230

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v3.1.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v3.1.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v3.1.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

35

[CH_R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

57

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

58

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.1.c

59

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v3.1.c

60

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v3.1.c

62

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v3.1.c

63

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

64

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v3.1.c

80

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.1.c

81

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.1.c

82

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v3.1.c

85

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v3.1.c

86

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.1.c

93

[R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

109

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

110

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

111

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

152

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

154

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

160

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

162

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

168

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

169

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

170

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

177

[IRAM_SIZE] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

178

[NUM_CH_PER_EE] = GENMASK(7, 3),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

179

[NUM_EV_PER_EE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

239

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

241

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

35

[CH_R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

57

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

58

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

59

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

60

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

62

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

63

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

64

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

80

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

81

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

82

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

85

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

86

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v3.5.1.c

93

[R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

110

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

111

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.0.c

112

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

153

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

155

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

161

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

163

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

169

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

170

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v4.0.c

171

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.0.c

178

[IRAM_SIZE] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

179

[NUM_CH_PER_EE] = GENMASK(7, 3),

drivers/net/ipa/reg/gsi_reg-v4.0.c

180

[NUM_EV_PER_EE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.0.c

184

[GSI_SDMA_N_INT] = GENMASK(18, 16),

drivers/net/ipa/reg/gsi_reg-v4.0.c

185

[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),

drivers/net/ipa/reg/gsi_reg-v4.0.c

186

[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),

drivers/net/ipa/reg/gsi_reg-v4.0.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.0.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.0.c

244

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

246

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v4.0.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v4.0.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.0.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

35

[CH_R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

58

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

59

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.0.c

60

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v4.0.c

61

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v4.0.c

63

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v4.0.c

64

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

65

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v4.0.c

81

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.0.c

82

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.0.c

83

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v4.0.c

86

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.0.c

87

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.0.c

94

[R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

113

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

114

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.11.c

115

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

156

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

158

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

164

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

166

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

172

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

173

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v4.11.c

174

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.11.c

176

[GENERIC_PARAMS] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

182

[IRAM_SIZE] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

183

[NUM_CH_PER_EE] = GENMASK(7, 3),

drivers/net/ipa/reg/gsi_reg-v4.11.c

184

[NUM_EV_PER_EE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.11.c

188

[GSI_SDMA_N_INT] = GENMASK(18, 16),

drivers/net/ipa/reg/gsi_reg-v4.11.c

189

[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),

drivers/net/ipa/reg/gsi_reg-v4.11.c

190

[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),

drivers/net/ipa/reg/gsi_reg-v4.11.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.11.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.11.c

249

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v4.11.c

251

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v4.11.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.11.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

35

[CH_R_LENGTH] = GENMASK(19, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

51

[PREFETCH_MODE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.11.c

53

[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.11.c

61

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

62

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.11.c

63

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v4.11.c

64

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v4.11.c

66

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v4.11.c

67

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

68

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v4.11.c

84

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.11.c

85

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.11.c

86

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v4.11.c

89

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.11.c

90

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.11.c

97

[R_LENGTH] = GENMASK(19, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

112

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

113

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.5.c

114

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

155

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

157

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

163

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

165

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

171

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

172

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v4.5.c

173

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.5.c

180

[IRAM_SIZE] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

181

[NUM_CH_PER_EE] = GENMASK(7, 3),

drivers/net/ipa/reg/gsi_reg-v4.5.c

182

[NUM_EV_PER_EE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.5.c

186

[GSI_SDMA_N_INT] = GENMASK(18, 16),

drivers/net/ipa/reg/gsi_reg-v4.5.c

187

[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),

drivers/net/ipa/reg/gsi_reg-v4.5.c

188

[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),

drivers/net/ipa/reg/gsi_reg-v4.5.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.5.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.5.c

247

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

249

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v4.5.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v4.5.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.5.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

35

[CH_R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

51

[PREFETCH_MODE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.5.c

53

[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.5.c

60

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

61

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.5.c

62

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v4.5.c

63

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v4.5.c

65

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v4.5.c

66

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

67

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v4.5.c

83

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.5.c

84

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.5.c

85

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v4.5.c

88

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.5.c

89

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.5.c

96

[R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

113

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

114

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.9.c

115

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

156

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

158

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

164

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

166

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

172

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

173

[GENERIC_CHID] = GENMASK(9, 5),

drivers/net/ipa/reg/gsi_reg-v4.9.c

174

[GENERIC_EE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.9.c

181

[IRAM_SIZE] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

182

[NUM_CH_PER_EE] = GENMASK(7, 3),

drivers/net/ipa/reg/gsi_reg-v4.9.c

183

[NUM_EV_PER_EE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.9.c

187

[GSI_SDMA_N_INT] = GENMASK(18, 16),

drivers/net/ipa/reg/gsi_reg-v4.9.c

188

[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),

drivers/net/ipa/reg/gsi_reg-v4.9.c

189

[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),

drivers/net/ipa/reg/gsi_reg-v4.9.c

20

[CHTYPE_PROTOCOL] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

22

[CH_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.9.c

23

[CHID] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v4.9.c

248

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

25

[ERINDEX] = GENMASK(18, 14),

drivers/net/ipa/reg/gsi_reg-v4.9.c

250

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v4.9.c

27

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.9.c

28

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

35

[CH_R_LENGTH] = GENMASK(19, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

47

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

51

[PREFETCH_MODE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v4.9.c

53

[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v4.9.c

61

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

62

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.9.c

63

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v4.9.c

64

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v4.9.c

66

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v4.9.c

67

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

68

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v4.9.c

84

[EV_CHTYPE] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v4.9.c

85

[EV_EE] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v4.9.c

86

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v4.9.c

89

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v4.9.c

90

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v4.9.c

97

[R_LENGTH] = GENMASK(15, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

100

[EV_MODC] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v5.0.c

101

[EV_MOD_CNT] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

142

[CH_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

144

[CH_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

150

[EV_CHID] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

152

[EV_OPCODE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

158

[GENERIC_OPCODE] = GENMASK(4, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

159

[GENERIC_CHID] = GENMASK(12, 5),

drivers/net/ipa/reg/gsi_reg-v5.0.c

160

[GENERIC_EE] = GENMASK(16, 13),

drivers/net/ipa/reg/gsi_reg-v5.0.c

162

[GENERIC_PARAMS] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

168

[NUM_CH_PER_EE] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

169

[IRAM_SIZE] = GENMASK(12, 8),

drivers/net/ipa/reg/gsi_reg-v5.0.c

173

[GSI_SDMA_N_INT] = GENMASK(18, 16),

drivers/net/ipa/reg/gsi_reg-v5.0.c

174

[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),

drivers/net/ipa/reg/gsi_reg-v5.0.c

175

[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),

drivers/net/ipa/reg/gsi_reg-v5.0.c

183

[EV_PER_EE] = GENMASK(7, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

184

[IRAM_PROTOCOL_COUNT] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v5.0.c

20

[CHTYPE_PROTOCOL] = GENMASK(6, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

22

[CH_EE] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v5.0.c

23

[CHID] = GENMASK(19, 12),

drivers/net/ipa/reg/gsi_reg-v5.0.c

238

[ERR_ARG3] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

239

[ERR_ARG2] = GENMASK(7, 4),

drivers/net/ipa/reg/gsi_reg-v5.0.c

24

[CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v5.0.c

240

[ERR_ARG1] = GENMASK(11, 8),

drivers/net/ipa/reg/gsi_reg-v5.0.c

241

[ERR_CODE] = GENMASK(15, 12),

drivers/net/ipa/reg/gsi_reg-v5.0.c

243

[ERR_VIRT_IDX] = GENMASK(23, 19),

drivers/net/ipa/reg/gsi_reg-v5.0.c

244

[ERR_TYPE] = GENMASK(27, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

245

[ERR_EE] = GENMASK(31, 28),

drivers/net/ipa/reg/gsi_reg-v5.0.c

25

[ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

253

[INTER_EE_RESULT] = GENMASK(2, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

255

[GENERIC_EE_RESULT] = GENMASK(7, 5),

drivers/net/ipa/reg/gsi_reg-v5.0.c

32

[CH_R_LENGTH] = GENMASK(23, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

33

[CH_ERINDEX] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

44

[WRR_WEIGHT] = GENMASK(3, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

48

[PREFETCH_MODE] = GENMASK(13, 10),

drivers/net/ipa/reg/gsi_reg-v5.0.c

50

[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),

drivers/net/ipa/reg/gsi_reg-v5.0.c

71

[EV_CHTYPE] = GENMASK(6, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

73

[EV_EVCHID] = GENMASK(15, 8),

drivers/net/ipa/reg/gsi_reg-v5.0.c

74

[EV_EE] = GENMASK(19, 16),

drivers/net/ipa/reg/gsi_reg-v5.0.c

75

[EV_CHSTATE] = GENMASK(23, 20),

drivers/net/ipa/reg/gsi_reg-v5.0.c

76

[EV_ELEMENT_SIZE] = GENMASK(31, 24),

drivers/net/ipa/reg/gsi_reg-v5.0.c

83

[R_LENGTH] = GENMASK(23, 0),

drivers/net/ipa/reg/gsi_reg-v5.0.c

99

[EV_MODT] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

100

[IPA_BASE_ADDR] = GENMASK(16, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

111

[EOT_COAL_GRANULARITY] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

112

[AGGR_GRANULARITY] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v3.1.c

119

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

120

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

121

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

122

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

129

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

130

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

131

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

132

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

139

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

140

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

141

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

142

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

149

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

150

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

151

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

152

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

159

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

160

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

161

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

162

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

169

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

170

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

171

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

172

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

179

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

180

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

181

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

182

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

189

[X_MIN_LIM] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

190

[X_MAX_LIM] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

191

[Y_MIN_LIM] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

192

[Y_MAX_LIM] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v3.1.c

208

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v3.1.c

209

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v3.1.c

218

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

225

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

227

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v3.1.c

228

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v3.1.c

230

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v3.1.c

244

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v3.1.c

245

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v3.1.c

255

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

257

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v3.1.c

259

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v3.1.c

269

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

270

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v3.1.c

271

[BYTE_LIMIT] = GENMASK(9, 5),

drivers/net/ipa/reg/ipa_reg-v3.1.c

272

[TIME_LIMIT] = GENMASK(14, 10),

drivers/net/ipa/reg/ipa_reg-v3.1.c

273

[PKT_LIMIT] = GENMASK(20, 15),

drivers/net/ipa/reg/ipa_reg-v3.1.c

293

[TIMER_BASE_VALUE] = GENMASK(31, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

300

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

303

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

306

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

312

[ENDP_RSRC_GRP] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

319

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

320

[SEQ_REP_TYPE] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.1.c

328

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v3.1.c

344

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

353

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

48

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v3.1.c

50

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v3.1.c

51

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v3.1.c

60

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

61

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v3.1.c

67

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

68

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v3.1.c

75

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.1.c

76

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

105

[IPA_BASE_ADDR] = GENMASK(16, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

117

[AGGR_GRANULARITY] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

126

[PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

133

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

135

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

137

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

139

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

146

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

154

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

156

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

158

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

160

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

168

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

170

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

172

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

174

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

182

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

184

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

186

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

188

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

196

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

198

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

200

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

202

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

219

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

220

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

229

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

236

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

238

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

239

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

241

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

255

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

256

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

266

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

268

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

270

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

280

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

281

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

282

[BYTE_LIMIT] = GENMASK(9, 5),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

283

[TIME_LIMIT] = GENMASK(14, 10),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

284

[PKT_LIMIT] = GENMASK(20, 15),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

304

[TIMER_BASE_VALUE] = GENMASK(31, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

311

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

314

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

317

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

323

[ENDP_RSRC_GRP] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

330

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

331

[SEQ_REP_TYPE] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

339

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

355

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

364

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

53

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

55

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

56

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

65

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

66

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

72

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

73

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

80

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

81

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.11.c

101

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

102

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.11.c

109

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

110

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.11.c

112

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

113

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

135

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

147

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v4.11.c

148

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v4.11.c

152

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v4.11.c

161

[MAX_PIPES] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

163

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

165

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

167

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

174

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

182

[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

185

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

187

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

194

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

202

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

203

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v4.11.c

204

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v4.11.c

211

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

213

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

215

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

217

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

225

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

227

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

229

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

231

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

239

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

241

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

243

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

245

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

253

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

255

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

257

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

259

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.11.c

268

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v4.11.c

269

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v4.11.c

278

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

285

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

287

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v4.11.c

288

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v4.11.c

290

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v4.11.c

293

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v4.11.c

294

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v4.11.c

304

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v4.11.c

305

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v4.11.c

307

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

308

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v4.11.c

309

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v4.11.c

319

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

321

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.11.c

323

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v4.11.c

333

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

334

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v4.11.c

335

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v4.11.c

337

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v4.11.c

338

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v4.11.c

35

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22),

drivers/net/ipa/reg/ipa_reg-v4.11.c

358

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

368

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

371

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.11.c

374

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

380

[ENDP_RSRC_GRP] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

387

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

395

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.11.c

411

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

420

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v4.11.c

82

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.11.c

84

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v4.11.c

85

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v4.11.c

94

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.11.c

95

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

101

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

102

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.2.c

104

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

105

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

142

[IPA_BASE_ADDR] = GENMASK(16, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

154

[AGGR_GRANULARITY] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.2.c

162

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v4.2.c

163

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v4.2.c

167

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v4.2.c

177

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

179

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

181

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

183

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

190

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

198

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

200

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

202

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

204

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

212

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

214

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

216

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

218

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

226

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

228

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

230

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

232

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

240

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

242

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

244

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

246

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.2.c

255

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v4.2.c

256

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v4.2.c

265

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

272

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

274

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v4.2.c

275

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v4.2.c

277

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v4.2.c

291

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v4.2.c

292

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v4.2.c

30

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),

drivers/net/ipa/reg/ipa_reg-v4.2.c

302

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

304

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.2.c

306

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v4.2.c

316

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

317

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v4.2.c

318

[BYTE_LIMIT] = GENMASK(9, 5),

drivers/net/ipa/reg/ipa_reg-v4.2.c

319

[TIME_LIMIT] = GENMASK(14, 10),

drivers/net/ipa/reg/ipa_reg-v4.2.c

320

[PKT_LIMIT] = GENMASK(20, 15),

drivers/net/ipa/reg/ipa_reg-v4.2.c

339

[TIMER_BASE_VALUE] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

341

[TIMER_SCALE] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

349

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

352

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

355

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

368

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

369

[SEQ_REP_TYPE] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v4.2.c

377

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.2.c

74

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.2.c

76

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v4.2.c

77

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v4.2.c

86

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

87

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.2.c

93

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.2.c

94

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.5.c

103

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

104

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.5.c

106

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

107

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

129

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

141

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v4.5.c

142

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v4.5.c

146

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v4.5.c

154

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

156

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

158

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

160

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

167

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

175

[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

178

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

180

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

187

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

195

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

196

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v4.5.c

197

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v4.5.c

203

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

205

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

207

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

209

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

217

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

219

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

221

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

223

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

231

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

233

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

235

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

237

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

245

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

247

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

249

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

251

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

259

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

261

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

263

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

265

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

273

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

275

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

277

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

279

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.5.c

288

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v4.5.c

289

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v4.5.c

298

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

30

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),

drivers/net/ipa/reg/ipa_reg-v4.5.c

305

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

307

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v4.5.c

308

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v4.5.c

310

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v4.5.c

313

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v4.5.c

314

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v4.5.c

324

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v4.5.c

325

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v4.5.c

327

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

328

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v4.5.c

329

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v4.5.c

339

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

341

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.5.c

343

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v4.5.c

352

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

353

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v4.5.c

354

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v4.5.c

356

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v4.5.c

357

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v4.5.c

377

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

387

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

390

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.5.c

393

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

399

[ENDP_RSRC_GRP] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

406

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

414

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.5.c

430

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

439

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

76

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.5.c

78

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v4.5.c

79

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v4.5.c

88

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

89

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.5.c

95

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.5.c

96

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.7.c

103

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

104

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.7.c

106

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

107

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

129

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

141

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v4.7.c

142

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v4.7.c

146

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v4.7.c

155

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

157

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

159

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

161

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

168

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

176

[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

179

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

181

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

188

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

196

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

197

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v4.7.c

198

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v4.7.c

204

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

206

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

208

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

210

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

218

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

220

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

222

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

224

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

232

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

234

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

236

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

238

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

246

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

248

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

250

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

252

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.7.c

261

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v4.7.c

262

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v4.7.c

271

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

278

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

280

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v4.7.c

281

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v4.7.c

283

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v4.7.c

286

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v4.7.c

287

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v4.7.c

297

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v4.7.c

298

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v4.7.c

30

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),

drivers/net/ipa/reg/ipa_reg-v4.7.c

300

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

301

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v4.7.c

302

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v4.7.c

312

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

314

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.7.c

316

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v4.7.c

325

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

326

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v4.7.c

327

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v4.7.c

329

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v4.7.c

330

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v4.7.c

350

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

360

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

363

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.7.c

366

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

379

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

387

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.7.c

403

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

412

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

76

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.7.c

78

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v4.7.c

79

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v4.7.c

88

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

89

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.7.c

95

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.7.c

96

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.9.c

100

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

101

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.9.c

108

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

109

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v4.9.c

111

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

112

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

134

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

146

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v4.9.c

147

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v4.9.c

151

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v4.9.c

160

[MAX_PIPES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

162

[MAX_CONS_PIPES] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

164

[MAX_PROD_PIPES] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

166

[PROD_LOWEST] = GENMASK(27, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

173

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

181

[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

184

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

186

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

193

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

201

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

202

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v4.9.c

203

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v4.9.c

209

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

211

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

213

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

215

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

223

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

225

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

227

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

229

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

237

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

239

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

241

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

243

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

251

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

253

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

255

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

257

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v4.9.c

266

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v4.9.c

267

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v4.9.c

276

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

283

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

285

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v4.9.c

286

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v4.9.c

288

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v4.9.c

290

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v4.9.c

291

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v4.9.c

301

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v4.9.c

302

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v4.9.c

304

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

305

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v4.9.c

306

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v4.9.c

316

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

318

[DEST_PIPE_INDEX] = GENMASK(8, 4),

drivers/net/ipa/reg/ipa_reg-v4.9.c

320

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v4.9.c

330

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

331

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v4.9.c

332

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v4.9.c

334

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v4.9.c

335

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v4.9.c

34

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22),

drivers/net/ipa/reg/ipa_reg-v4.9.c

355

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

365

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

368

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v4.9.c

371

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

377

[ENDP_RSRC_GRP] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

384

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

392

[STATUS_ENDP] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.9.c

408

[FILTER_HASH_MSK_ALL] = GENMASK(6, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

417

[ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),

drivers/net/ipa/reg/ipa_reg-v4.9.c

81

[ROUTE_DEF_PIPE] = GENMASK(5, 1),

drivers/net/ipa/reg/ipa_reg-v4.9.c

83

[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),

drivers/net/ipa/reg/ipa_reg-v4.9.c

84

[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),

drivers/net/ipa/reg/ipa_reg-v4.9.c

93

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v4.9.c

94

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

102

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

103

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

109

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

110

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v5.0.c

117

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

118

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v5.0.c

120

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

121

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

13

[MAX_PIPES] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

14

[MAX_CONS_PIPES] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

140

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

149

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v5.0.c

15

[MAX_PROD_PIPES] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

150

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v5.0.c

154

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v5.0.c

16

[PROD_LOWEST] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

165

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

173

[DPL_TIMESTAMP_LSB] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

176

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

178

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

185

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

193

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

194

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v5.0.c

195

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v5.0.c

196

[PULSE_GRAN_3] = GENMASK(11, 9),

drivers/net/ipa/reg/ipa_reg-v5.0.c

203

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

205

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

207

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

209

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

217

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

219

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

221

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

223

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

231

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

233

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

235

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

237

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

245

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

247

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

249

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

251

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

259

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

261

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

263

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

265

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

273

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

275

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

277

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

279

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

287

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

289

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

291

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

293

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

301

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

303

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

305

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

307

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

320

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v5.0.c

321

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v5.0.c

330

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

337

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

339

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v5.0.c

340

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v5.0.c

342

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v5.0.c

345

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v5.0.c

346

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v5.0.c

356

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v5.0.c

357

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v5.0.c

359

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

360

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v5.0.c

361

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v5.0.c

364

[HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.0.c

373

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

375

[DEST_PIPE_INDEX] = GENMASK(11, 4),

drivers/net/ipa/reg/ipa_reg-v5.0.c

376

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v5.0.c

386

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

387

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v5.0.c

388

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v5.0.c

390

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v5.0.c

391

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v5.0.c

411

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

413

[TIMER_GRAN_SEL] = GENMASK(9, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

421

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

424

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

427

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v5.0.c

433

[ENDP_RSRC_GRP] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

44

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),

drivers/net/ipa/reg/ipa_reg-v5.0.c

440

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

448

[STATUS_ENDP] = GENMASK(8, 1),

drivers/net/ipa/reg/ipa_reg-v5.0.c

90

[ROUTE_DEF_PIPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.0.c

91

[ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v5.0.c

92

[ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

101

[MEM_SIZE] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

102

[MEM_BADDR] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

108

[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

109

[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v5.5.c

116

[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

117

[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),

drivers/net/ipa/reg/ipa_reg-v5.5.c

119

[GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

120

[GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

13

[MAX_PIPES] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

139

[IPA_BASE_ADDR] = GENMASK(17, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

14

[MAX_CONS_PIPES] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

148

[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),

drivers/net/ipa/reg/ipa_reg-v5.5.c

149

[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),

drivers/net/ipa/reg/ipa_reg-v5.5.c

15

[MAX_PROD_PIPES] = GENMASK(23, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

153

[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),

drivers/net/ipa/reg/ipa_reg-v5.5.c

16

[PROD_LOWEST] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

164

[ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

173

[TAG_TIMESTAMP_LSB] = GENMASK(12, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

175

[NAT_TIMESTAMP_LSB] = GENMASK(20, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

182

[DIV_VALUE] = GENMASK(8, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

190

[PULSE_GRAN_0] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

191

[PULSE_GRAN_1] = GENMASK(5, 3),

drivers/net/ipa/reg/ipa_reg-v5.5.c

192

[PULSE_GRAN_2] = GENMASK(8, 6),

drivers/net/ipa/reg/ipa_reg-v5.5.c

193

[PULSE_GRAN_3] = GENMASK(11, 9),

drivers/net/ipa/reg/ipa_reg-v5.5.c

200

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

202

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

204

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

206

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

214

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

216

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

218

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

220

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

228

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

230

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

232

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

234

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

242

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

244

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

246

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

248

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

256

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

258

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

260

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

262

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

270

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

272

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

274

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

276

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

284

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

286

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

288

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

290

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

298

[X_MIN_LIM] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

300

[X_MAX_LIM] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

302

[Y_MIN_LIM] = GENMASK(21, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

304

[Y_MAX_LIM] = GENMASK(29, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

317

[CS_OFFLOAD_EN] = GENMASK(2, 1),

drivers/net/ipa/reg/ipa_reg-v5.5.c

318

[CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),

drivers/net/ipa/reg/ipa_reg-v5.5.c

328

[NAT_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

335

[HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

337

[HDR_OFST_METADATA] = GENMASK(12, 7),

drivers/net/ipa/reg/ipa_reg-v5.5.c

338

[HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),

drivers/net/ipa/reg/ipa_reg-v5.5.c

340

[HDR_OFST_PKT_SIZE] = GENMASK(25, 20),

drivers/net/ipa/reg/ipa_reg-v5.5.c

343

[HDR_LEN_MSB] = GENMASK(29, 28),

drivers/net/ipa/reg/ipa_reg-v5.5.c

344

[HDR_OFST_METADATA_MSB] = GENMASK(31, 30),

drivers/net/ipa/reg/ipa_reg-v5.5.c

354

[HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),

drivers/net/ipa/reg/ipa_reg-v5.5.c

355

[HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),

drivers/net/ipa/reg/ipa_reg-v5.5.c

357

[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

358

[HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),

drivers/net/ipa/reg/ipa_reg-v5.5.c

359

[HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),

drivers/net/ipa/reg/ipa_reg-v5.5.c

362

[HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),

drivers/net/ipa/reg/ipa_reg-v5.5.c

371

[ENDP_MODE] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

373

[DEST_PIPE_INDEX] = GENMASK(11, 4),

drivers/net/ipa/reg/ipa_reg-v5.5.c

374

[BYTE_THRESHOLD] = GENMASK(27, 12),

drivers/net/ipa/reg/ipa_reg-v5.5.c

384

[AGGR_EN] = GENMASK(1, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

385

[AGGR_TYPE] = GENMASK(4, 2),

drivers/net/ipa/reg/ipa_reg-v5.5.c

386

[BYTE_LIMIT] = GENMASK(10, 5),

drivers/net/ipa/reg/ipa_reg-v5.5.c

388

[TIME_LIMIT] = GENMASK(16, 12),

drivers/net/ipa/reg/ipa_reg-v5.5.c

389

[PKT_LIMIT] = GENMASK(22, 17),

drivers/net/ipa/reg/ipa_reg-v5.5.c

410

[TIMER_LIMIT] = GENMASK(4, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

412

[TIMER_GRAN_SEL] = GENMASK(9, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

420

[DEAGGR_HDR_LEN] = GENMASK(5, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

423

[PACKET_OFFSET_LOCATION] = GENMASK(13, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

426

[MAX_PACKET_LEN] = GENMASK(31, 16),

drivers/net/ipa/reg/ipa_reg-v5.5.c

43

[ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),

drivers/net/ipa/reg/ipa_reg-v5.5.c

432

[ENDP_RSRC_GRP] = GENMASK(2, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

439

[SEQ_TYPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

447

[STATUS_ENDP] = GENMASK(8, 1),

drivers/net/ipa/reg/ipa_reg-v5.5.c

89

[ROUTE_DEF_PIPE] = GENMASK(7, 0),

drivers/net/ipa/reg/ipa_reg-v5.5.c

90

[ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),

drivers/net/ipa/reg/ipa_reg-v5.5.c

91

[ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),

drivers/net/mdio/acpi_mdio.c

40

mdio->phy_mask = GENMASK(31, 0);

drivers/net/mdio/mdio-airoha.c

21

#define AN7583_MII_CL22_REG_ADDR GENMASK(29, 25)

drivers/net/mdio/mdio-airoha.c

23

#define AN7583_MII_PHY_ADDR GENMASK(24, 20)

drivers/net/mdio/mdio-airoha.c

24

#define AN7583_MII_CMD GENMASK(19, 18)

drivers/net/mdio/mdio-airoha.c

31

#define AN7583_MII_ST GENMASK(17, 16)

drivers/net/mdio/mdio-airoha.c

34

#define AN7583_MII_RWDATA GENMASK(15, 0)

drivers/net/mdio/mdio-aspeed.c

22

#define ASPEED_MDIO_CTRL_OP GENMASK(27, 26)

drivers/net/mdio/mdio-aspeed.c

29

#define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)

drivers/net/mdio/mdio-aspeed.c

30

#define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)

drivers/net/mdio/mdio-aspeed.c

31

#define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)

drivers/net/mdio/mdio-aspeed.c

34

#define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)

drivers/net/mdio/mdio-aspeed.c

36

#define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20)

drivers/net/mdio/mdio-aspeed.c

38

#define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)

drivers/net/mdio/mdio-ipq4019.c

20

#define MDIO_MODE_DIV_MASK GENMASK(7, 0)

drivers/net/mdio/mdio-ipq8064.c

27

#define MII_CLKRANGE_MASK GENMASK(4, 2)

drivers/net/mdio/mdio-ipq8064.c

29

#define MII_REG_MASK GENMASK(10, 6)

drivers/net/mdio/mdio-ipq8064.c

31

#define MII_ADDR_MASK GENMASK(15, 11)

drivers/net/mdio/mdio-mscc-miim.c

37

#define MSCC_MIIM_CFG_PRESCALE_MASK GENMASK(7, 0)

drivers/net/mdio/mdio-mux-meson-g12a.c

24

#define PLL_CTL0_N GENMASK(14, 10)

drivers/net/mdio/mdio-mux-meson-g12a.c

25

#define PLL_CTL0_M GENMASK(8, 0)

drivers/net/mdio/mdio-mux-meson-g12a.c

39

#define PHY_CNTL1_ST_MODE GENMASK(2, 0)

drivers/net/mdio/mdio-mux-meson-g12a.c

40

#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)

drivers/net/mdio/mdio-mux-meson-g12a.c

42

#define PHY_CNTL1_MII_MODE GENMASK(15, 14)

drivers/net/mdio/mdio-mux-meson-gxl.c

15

#define REG2_PHYID GENMASK(21, 0)

drivers/net/mdio/mdio-mux-meson-gxl.c

17

#define REG2_LEDACT GENMASK(23, 22)

drivers/net/mdio/mdio-mux-meson-gxl.c

18

#define REG2_LEDLINK GENMASK(25, 24)

drivers/net/mdio/mdio-mux-meson-gxl.c

25

#define REG3_CFGMODE GENMASK(6, 4)

drivers/net/mdio/mdio-mux-meson-gxl.c

27

#define REG3_PHYADDR GENMASK(12, 8)

drivers/net/mdio/mdio-realtek-rtl9300.c

30

#define PHY_CTRL_REG_ADDR GENMASK(24, 20)

drivers/net/mdio/mdio-realtek-rtl9300.c

31

#define PHY_CTRL_PARK_PAGE GENMASK(19, 15)

drivers/net/mdio/mdio-realtek-rtl9300.c

32

#define PHY_CTRL_MAIN_PAGE GENMASK(14, 3)

drivers/net/mdio/mdio-realtek-rtl9300.c

330

glb_ctrl_mask = GENMASK(19, 16);

drivers/net/mdio/mdio-realtek-rtl9300.c

40

#define PHY_CTRL_INDATA GENMASK(31, 16)

drivers/net/mdio/mdio-realtek-rtl9300.c

41

#define PHY_CTRL_DATA GENMASK(15, 0)

drivers/net/mdio/mdio-realtek-rtl9300.c

43

#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)

drivers/net/mdio/mdio-realtek-rtl9300.c

44

#define PHY_CTRL_MMD_REG GENMASK(15, 0)

drivers/net/pcs/pcs-lynx.c

19

#define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2))

drivers/net/pcs/pcs-lynx.c

20

#define IF_MODE_SPEED_MSK GENMASK(3, 2)

drivers/net/pcs/pcs-mtk-lynxi.c

21

#define SGMII_BMCR GENMASK(15, 0)

drivers/net/pcs/pcs-mtk-lynxi.c

22

#define SGMII_BMSR GENMASK(31, 16)

drivers/net/pcs/pcs-mtk-lynxi.c

28

#define SGMII_ADVERTISE GENMASK(15, 0)

drivers/net/pcs/pcs-mtk-lynxi.c

29

#define SGMII_LPA GENMASK(31, 16)

drivers/net/pcs/pcs-mtk-lynxi.c

32

#define SGMII_DEV_VERSION GENMASK(31, 16)

drivers/net/pcs/pcs-mtk-lynxi.c

36

#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)

drivers/net/pcs/pcs-mtk-lynxi.c

44

#define SGMII_SPEED_MASK GENMASK(3, 2)

drivers/net/pcs/pcs-mtk-lynxi.c

56

#define SGMII_PHY_SPEED_MASK GENMASK(3, 2)

drivers/net/pcs/pcs-rzn1-miic.c

35

#define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0)

drivers/net/pcs/pcs-rzn1-miic.c

40

#define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2)

drivers/net/pcs/pcs-rzn1-miic.c

48

#define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14)

drivers/net/pcs/pcs-rzn1-miic.c

52

#define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0)

drivers/net/pcs/pcs-rzn1-miic.c

825

.sw_mode_mask = GENMASK(4, 0),

drivers/net/pcs/pcs-rzn1-miic.c

841

.sw_mode_mask = GENMASK(2, 0),

drivers/net/pcs/pcs-xpcs-nxp.c

23

#define SJA1110_TXRTRIM(x) (((x) << 8) & GENMASK(10, 8))

drivers/net/pcs/pcs-xpcs-nxp.c

26

#define SJA1110_RXRTRIM(x) (((x) << 3) & GENMASK(5, 3))

drivers/net/pcs/pcs-xpcs-nxp.c

47

#define SJA1110_RXPLL_FBDIV(x) (((x) << 2) & GENMASK(9, 2))

drivers/net/pcs/pcs-xpcs-nxp.c

51

#define SJA1110_RXPLL_REFDIV(x) ((x) & GENMASK(4, 0))

drivers/net/pcs/pcs-xpcs-nxp.c

55

#define SJA1110_TXPLL_FBDIV(x) ((x) & GENMASK(11, 0))

drivers/net/pcs/pcs-xpcs-nxp.c

59

#define SJA1110_TXPLL_REFDIV(x) ((x) & GENMASK(5, 0))

drivers/net/pcs/pcs-xpcs-nxp.c

9

#define SJA1110_TXDRV(x) (((x) << 12) & GENMASK(14, 12))

drivers/net/pcs/pcs-xpcs-wx.c

11

#define TXGBE_TX_GENCTL1_VBOOST_LVL GENMASK(10, 8)

drivers/net/pcs/pcs-xpcs-wx.c

14

#define TXGBE_TX_GEN_CTL2_TX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)

drivers/net/pcs/pcs-xpcs-wx.c

16

#define TXGBE_TX_RATE_CTL_TX0_RATE(v) FIELD_PREP(GENMASK(2, 0), v)

drivers/net/pcs/pcs-xpcs-wx.c

18

#define TXGBE_RX_GEN_CTL2_RX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)

drivers/net/pcs/pcs-xpcs-wx.c

20

#define TXGBE_RX_GEN_CTL3_LOS_TRSHLD0 GENMASK(2, 0)

drivers/net/pcs/pcs-xpcs-wx.c

22

#define TXGBE_RX_RATE_CTL_RX0_RATE(v) FIELD_PREP(GENMASK(1, 0), v)

drivers/net/pcs/pcs-xpcs-wx.c

24

#define TXGBE_RX_EQ_ATTN_LVL0 GENMASK(2, 0)

drivers/net/pcs/pcs-xpcs-wx.c

26

#define TXGBE_RX_EQ_CTL0_VGA1_GAIN(v) FIELD_PREP(GENMASK(15, 12), v)

drivers/net/pcs/pcs-xpcs-wx.c

27

#define TXGBE_RX_EQ_CTL0_VGA2_GAIN(v) FIELD_PREP(GENMASK(11, 8), v)

drivers/net/pcs/pcs-xpcs-wx.c

28

#define TXGBE_RX_EQ_CTL0_CTLE_POLE(v) FIELD_PREP(GENMASK(7, 5), v)

drivers/net/pcs/pcs-xpcs-wx.c

29

#define TXGBE_RX_EQ_CTL0_CTLE_BOOST(v) FIELD_PREP(GENMASK(4, 0), v)

drivers/net/pcs/pcs-xpcs-wx.c

45

#define TXGBE_MISC_CTL0_RX_VREF(v) FIELD_PREP(GENMASK(12, 8), v)

drivers/net/pcs/pcs-xpcs.h

23

#define DW_RXFIFO_ERR GENMASK(6, 5)

drivers/net/pcs/pcs-xpcs.h

24

#define DW_PSEQ_ST GENMASK(4, 2)

drivers/net/pcs/pcs-xpcs.h

25

#define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4)

drivers/net/pcs/pcs-xpcs.h

67

#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)

drivers/net/pcs/pcs-xpcs.h

75

#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)

drivers/net/pcs/pcs-xpcs.h

88

#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)

drivers/net/phy/adin.c

124

#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)

drivers/net/phy/adin.c

133

#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)

drivers/net/phy/adin.c

136

#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)

drivers/net/phy/adin.c

151

#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)

drivers/net/phy/adin.c

45

#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)

drivers/net/phy/air_en8811h.c

168

#define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12)

drivers/net/phy/air_en8811h.c

37

#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)

drivers/net/phy/air_en8811h.c

82

#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)

drivers/net/phy/air_en8811h.c

92

#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))

drivers/net/phy/aquantia/aquantia.h

109

#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)

drivers/net/phy/aquantia/aquantia.h

110

#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)

drivers/net/phy/aquantia/aquantia.h

113

#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)

drivers/net/phy/aquantia/aquantia.h

21

#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)

drivers/net/phy/aquantia/aquantia.h

22

#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)

drivers/net/phy/aquantia/aquantia.h

32

#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)

drivers/net/phy/aquantia/aquantia.h

35

#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2)

drivers/net/phy/aquantia/aquantia.h

39

#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)

drivers/net/phy/aquantia/aquantia.h

42

#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)

drivers/net/phy/aquantia/aquantia.h

53

#define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0)

drivers/net/phy/aquantia/aquantia.h

59

#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)

drivers/net/phy/aquantia/aquantia.h

80

#define VEND1_GLOBAL_LED_PROV_ACT_STRETCH GENMASK(0, 1)

drivers/net/phy/aquantia/aquantia_main.c

107

#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)

drivers/net/phy/aquantia/aquantia_main.c

108

#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)

drivers/net/phy/aquantia/aquantia_main.c

145

ret = val & GENMASK(len_l - 1, 0);

drivers/net/phy/aquantia/aquantia_main.c

151

ret += (val & GENMASK(len_h - 1, 0)) << 16;

drivers/net/phy/aquantia/aquantia_main.c

42

#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)

drivers/net/phy/aquantia/aquantia_main.c

60

#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)

drivers/net/phy/aquantia/aquantia_main.c

67

#define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0)

drivers/net/phy/aquantia/aquantia_main.c

70

#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)

drivers/net/phy/aquantia/aquantia_main.c

95

#define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0)

drivers/net/phy/as21xxx.c

18

#define VEND1_GLB_CPU_CTRL_MASK GENMASK(4, 0)

drivers/net/phy/as21xxx.c

19

#define VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK GENMASK(12, 8)

drivers/net/phy/as21xxx.c

39

#define VEND1_LED_REG_A_EVENT GENMASK(15, 11)

drivers/net/phy/as21xxx.c

41

#define VEND1_LED_CONFG_BLINK GENMASK(7, 0)

drivers/net/phy/as21xxx.c

44

#define VEND1_SPEED_MASK GENMASK(7, 0)

drivers/net/phy/as21xxx.c

54

#define AEON_IPC_CMD_SIZE GENMASK(10, 6)

drivers/net/phy/as21xxx.c

55

#define AEON_IPC_CMD_OPCODE GENMASK(5, 0)

drivers/net/phy/as21xxx.c

69

#define AEON_IPC_STS_SIZE GENMASK(14, 10)

drivers/net/phy/as21xxx.c

70

#define AEON_IPC_STS_OPCODE GENMASK(9, 4)

drivers/net/phy/as21xxx.c

71

#define AEON_IPC_STS_STATUS GENMASK(3, 0)

drivers/net/phy/bcm-phy-ptp.c

112

#define HB_READ_MASK GENMASK(11, 10)

drivers/net/phy/bcm-phy-ptp.c

123

#define TX_TIMECODE_SEL GENMASK(7, 0)

drivers/net/phy/bcm-phy-ptp.c

124

#define RX_TIMECODE_SEL GENMASK(15, 8)

drivers/net/phy/bcm-phy-ptp.c

25

#define MODE_TX_REPLACE_TS GENMASK(1, 0)

drivers/net/phy/bcm-phy-ptp.c

29

#define MODE_RX_INSERT_TS_64 GENMASK(1, 0)

drivers/net/phy/bcm-phy-ptp.c

90

#define NSE_GMODE_EN GENMASK(15, 14)

drivers/net/phy/bcm-phy-ptp.c

95

#define NSE_FRAMESYNC_MASK GENMASK(5, 2)

drivers/net/phy/bcm-phy-ptp.c

98

#define NSE_SYNC_OUT_MASK GENMASK(1, 0)

drivers/net/phy/bcm54140.c

27

#define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */

drivers/net/phy/bcm54140.c

39

#define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)

drivers/net/phy/bcm54140.c

57

#define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)

drivers/net/phy/bcm54140.c

66

#define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)

drivers/net/phy/bcm54140.c

70

#define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)

drivers/net/phy/bcm54140.c

74

#define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)

drivers/net/phy/dp83822.c

115

#define DP83822_MLEDCR_CFG GENMASK(6, 3)

drivers/net/phy/dp83822.c

116

#define DP83822_MLEDCR_ROUTE GENMASK(1, 0)

drivers/net/phy/dp83822.c

120

#define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8)

drivers/net/phy/dp83822.c

121

#define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4)

drivers/net/phy/dp83822.c

124

#define DP83822_IOCTRL_MAC_IMPEDANCE_CTRL GENMASK(4, 1)

drivers/net/phy/dp83822.c

127

#define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8)

drivers/net/phy/dp83822.c

129

#define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0)

drivers/net/phy/dp83822.c

133

#define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4)

drivers/net/phy/dp83822.c

136

#define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)

drivers/net/phy/dp83822.c

137

#define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)

drivers/net/phy/dp83822.c

138

#define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)

drivers/net/phy/dp83822.c

168

#define DP83822_STRAP_MODE4 GENMASK(1, 0)

drivers/net/phy/dp83822.c

170

#define DP83822_COL_STRAP_MASK GENMASK(11, 10)

drivers/net/phy/dp83822.c

172

#define DP83822_RX_ER_STR_MASK GENMASK(9, 8)

drivers/net/phy/dp83822.c

176

#define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)

drivers/net/phy/dp83822.c

177

#define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)

drivers/net/phy/dp83822.c

178

#define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)

drivers/net/phy/dp83822.c

179

#define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)

drivers/net/phy/dp83822.c

180

#define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)

drivers/net/phy/dp83822.c

181

#define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)

drivers/net/phy/dp83822.c

182

#define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)

drivers/net/phy/dp83822.c

411

if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))

drivers/net/phy/dp83822.c

419

if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))

drivers/net/phy/dp83867.c

102

#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)

drivers/net/phy/dp83867.c

103

#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)

drivers/net/phy/dp83869.c

87

#define DP83869_STRAP_OP_MODE_MASK GENMASK(11, 9)

drivers/net/phy/dp83869.c

97

#define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12)

drivers/net/phy/dp83tc811.c

282

if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))

drivers/net/phy/dp83tc811.c

290

if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))

drivers/net/phy/dp83tc811.c

298

if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))

drivers/net/phy/dp83td510.c

156

#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2)

drivers/net/phy/dp83td510.c

165

#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0)

drivers/net/phy/dp83td510.c

172

#define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8)

drivers/net/phy/dp83td510.c

174

#define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0)

drivers/net/phy/dp83td510.c

188

#define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0)

drivers/net/phy/dp83td510.c

192

#define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8)

drivers/net/phy/dp83td510.c

194

#define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0)

drivers/net/phy/dp83td510.c

200

#define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0)

drivers/net/phy/dp83td510.c

251

#define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0)

drivers/net/phy/dp83tg720.c

145

#define DP83TG720S_LINK_LOSS_CNT_MASK GENMASK(15, 10)

drivers/net/phy/dp83tg720.c

183

#define DP83TG720S_SQI_OUT_WORST GENMASK(7, 5)

drivers/net/phy/dp83tg720.c

184

#define DP83TG720S_SQI_OUT GENMASK(3, 1)

drivers/net/phy/icplus.c

53

#define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0)

drivers/net/phy/intel-xway.c

18

#define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12)

drivers/net/phy/intel-xway.c

19

#define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8)

drivers/net/phy/marvell-88q2xxx.c

48

#define MDIO_MMD_PCS_MV_LED_FUNC_CTRL_LED_1_MASK GENMASK(7, 4)

drivers/net/phy/marvell-88q2xxx.c

49

#define MDIO_MMD_PCS_MV_LED_FUNC_CTRL_LED_0_MASK GENMASK(3, 0)

drivers/net/phy/marvell.c

110

#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)

drivers/net/phy/marvell.c

287

#define MII_VCT_TXRXPINS_VCTTST GENMASK(14, 13)

drivers/net/phy/marvell.c

293

#define MII_VCT_TXRXPINS_AMPRFLN GENMASK(12, 8)

drivers/net/phy/marvell.c

295

#define MII_VCT_TXRXPINS_DISTRFLN GENMASK(7, 0)

drivers/net/phy/marvell.c

61

#define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)

drivers/net/phy/marvell.c

74

#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)

drivers/net/phy/mdio-open-alliance.h

58

#define OATC14_ADFCAP_HDD_CAPABILITY GENMASK(10, 8)

drivers/net/phy/mdio-open-alliance.h

59

#define OATC14_ADFCAP_SQIPLUS_CAPABILITY GENMASK(4, 1)

drivers/net/phy/mdio-open-alliance.h

68

#define OATC14_HDD_SHORT_OPEN_STATUS GENMASK(1, 0)

drivers/net/phy/mdio-open-alliance.h

72

#define OATC14_DCQ_SQI_VALUE GENMASK(2, 0)

drivers/net/phy/mdio-open-alliance.h

76

#define OATC14_DCQ_SQIPLUS_VALUE GENMASK(7, 0)

drivers/net/phy/mediatek/mtk-2p5ge.c

28

#define PHY_AUX_DPX_MASK GENMASK(5, 5)

drivers/net/phy/mediatek/mtk-2p5ge.c

29

#define PHY_AUX_SPEED_MASK GENMASK(4, 2)

drivers/net/phy/mediatek/mtk-2p5ge.c

33

#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

100

#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)

drivers/net/phy/mediatek/mtk-ge-soc.c

102

#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)

drivers/net/phy/mediatek/mtk-ge-soc.c

111

#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)

drivers/net/phy/mediatek/mtk-ge-soc.c

115

#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)

drivers/net/phy/mediatek/mtk-ge-soc.c

117

#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)

drivers/net/phy/mediatek/mtk-ge-soc.c

121

#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)

drivers/net/phy/mediatek/mtk-ge-soc.c

125

#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

129

#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

140

#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

144

#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)

drivers/net/phy/mediatek/mtk-ge-soc.c

145

#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

148

#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)

drivers/net/phy/mediatek/mtk-ge-soc.c

149

#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

152

#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

153

#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

156

#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

157

#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

160

#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

161

#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

164

#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

165

#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

168

#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

169

#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

172

#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

173

#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

176

#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

179

#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)

drivers/net/phy/mediatek/mtk-ge-soc.c

180

#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

181

#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)

drivers/net/phy/mediatek/mtk-ge-soc.c

182

#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

198

#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

203

#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

204

#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

207

#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

210

#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)

drivers/net/phy/mediatek/mtk-ge-soc.c

213

#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

214

#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

217

#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

218

#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

221

#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

230

#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

233

#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

236

#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

239

#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

242

#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

245

#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

248

#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

251

#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

268

#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

269

#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)

drivers/net/phy/mediatek/mtk-ge-soc.c

27

#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

275

#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

279

#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

283

#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

285

#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

288

#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

289

#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

292

#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

30

#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

302

#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

324

#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

328

#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

331

#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

332

#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

333

#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

334

#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

335

#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

337

#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

338

#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

339

#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

340

#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

341

#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

343

#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

344

#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

346

#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

347

#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))

drivers/net/phy/mediatek/mtk-ge-soc.c

37

#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

41

#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)

drivers/net/phy/mediatek/mtk-ge-soc.c

45

#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

49

#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)

drivers/net/phy/mediatek/mtk-ge-soc.c

53

#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)

drivers/net/phy/mediatek/mtk-ge-soc.c

55

#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)

drivers/net/phy/mediatek/mtk-ge-soc.c

57

#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)

drivers/net/phy/mediatek/mtk-ge-soc.c

59

#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)

drivers/net/phy/mediatek/mtk-ge-soc.c

63

#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)

drivers/net/phy/mediatek/mtk-ge-soc.c

67

#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)

drivers/net/phy/mediatek/mtk-ge-soc.c

69

#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)

drivers/net/phy/mediatek/mtk-ge-soc.c

77

#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)

drivers/net/phy/mediatek/mtk-ge-soc.c

81

#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)

drivers/net/phy/mediatek/mtk-ge-soc.c

87

#define TR_FREEZE_MASK GENMASK(11, 0)

drivers/net/phy/mediatek/mtk-ge-soc.c

92

#define SS_TR_KP100_MASK GENMASK(21, 19)

drivers/net/phy/mediatek/mtk-ge-soc.c

94

#define SS_TR_KF100_MASK GENMASK(18, 16)

drivers/net/phy/mediatek/mtk-ge-soc.c

96

#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)

drivers/net/phy/mediatek/mtk-ge-soc.c

98

#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)

drivers/net/phy/mediatek/mtk-ge.c

19

#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)

drivers/net/phy/mediatek/mtk-ge.c

24

#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)

drivers/net/phy/mediatek/mtk-ge.c

25

#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)

drivers/net/phy/mediatek/mtk-ge.c

28

#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)

drivers/net/phy/mediatek/mtk-ge.c

31

#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)

drivers/net/phy/mediatek/mtk-ge.c

34

#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)

drivers/net/phy/mediatek/mtk-ge.c

35

#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)

drivers/net/phy/mediatek/mtk.h

22

#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)

drivers/net/phy/mediatek/mtk.h

23

#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)

drivers/net/phy/meson-gxl.c

21

#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)

drivers/net/phy/meson-gxl.c

23

#define TSTCNTL_READ_ADDRESS GENMASK(9, 5)

drivers/net/phy/meson-gxl.c

24

#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)

drivers/net/phy/micrel.c

100

#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)

drivers/net/phy/micrel.c

101

#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)

drivers/net/phy/micrel.c

1033

#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)

drivers/net/phy/micrel.c

1034

#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)

drivers/net/phy/micrel.c

1037

#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)

drivers/net/phy/micrel.c

1038

#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)

drivers/net/phy/micrel.c

1039

#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)

drivers/net/phy/micrel.c

1040

#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)

drivers/net/phy/micrel.c

1043

#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)

drivers/net/phy/micrel.c

1044

#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)

drivers/net/phy/micrel.c

1045

#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)

drivers/net/phy/micrel.c

1046

#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)

drivers/net/phy/micrel.c

1049

#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)

drivers/net/phy/micrel.c

1050

#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)

drivers/net/phy/micrel.c

134

#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)

drivers/net/phy/micrel.c

151

#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)

drivers/net/phy/micrel.c

152

#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))

drivers/net/phy/micrel.c

2233

#define KSZ9477_MMD_SQI_MASK GENMASK(14, 8)

drivers/net/phy/micrel.c

3020

#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)

drivers/net/phy/micrel.c

3024

#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)

drivers/net/phy/micrel.c

357

((event) ? GENMASK(11, 8) : GENMASK(7, 4))

drivers/net/phy/micrel.c

359

(((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))

drivers/net/phy/micrel.c

3912

GENMASK(3, 0),

drivers/net/phy/micrel.c

5202

if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)

drivers/net/phy/micrel.c

5203

ts.tv_sec -= GENMASK(1, 0) + 1;

drivers/net/phy/micrel.c

5204

else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)

drivers/net/phy/micrel.c

5208

ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,

drivers/net/phy/micrel.c

5209

ts_header & GENMASK(29, 0));

drivers/net/phy/micrel.c

5561

#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)

drivers/net/phy/micrel.c

5567

#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)

drivers/net/phy/micrel.c

5568

#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)

drivers/net/phy/micrel.c

6034

#define LAN8842_STRAP_REG_PHYADDR_MASK GENMASK(4, 0)

drivers/net/phy/micrel.c

71

#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)

drivers/net/phy/micrel.c

74

#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)

drivers/net/phy/micrel.c

83

#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)

drivers/net/phy/micrel.c

88

#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)

drivers/net/phy/micrel.c

93

#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)

drivers/net/phy/micrel.c

94

#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)

drivers/net/phy/micrel.c

95

#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)

drivers/net/phy/microchip_rds_ptp.c

1043

*nsec = (rc & GENMASK(13, 0)) << 16;

drivers/net/phy/microchip_rds_ptp.c

709

GENMASK(13, 0))));

drivers/net/phy/microchip_rds_ptp.c

723

nsec & GENMASK(15, 0));

drivers/net/phy/microchip_rds_ptp.c

729

(nsec >> 16) & GENMASK(13, 0));

drivers/net/phy/microchip_rds_ptp.c

776

rate_lo = rate & GENMASK(15, 0);

drivers/net/phy/microchip_rds_ptp.c

777

rate_hi = (rate >> 16) & GENMASK(13, 0);

drivers/net/phy/microchip_rds_ptp.c

842

nsecs = (rc & GENMASK(13, 0));

drivers/net/phy/microchip_rds_ptp.c

884

upper_32_bits(ts->tv_sec) & GENMASK(15, 0));

drivers/net/phy/microchip_rds_ptp.c

896

upper_16_bits(ts->tv_nsec) & GENMASK(13, 0));

drivers/net/phy/microchip_rds_ptp.c

977

nsec = (rc & GENMASK(13, 0)) << 16;

drivers/net/phy/microchip_rds_ptp.h

100

#define MCHP_RDS_PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)

drivers/net/phy/microchip_rds_ptp.h

101

#define MCHP_RDS_PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))

drivers/net/phy/microchip_rds_ptp.h

144

#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8)

drivers/net/phy/microchip_rds_ptp.h

70

#define MCHP_RDS_PTP_TX_TS_CNT(v) (((v) & GENMASK(11, 8)) >> 8)

drivers/net/phy/microchip_rds_ptp.h

71

#define MCHP_RDS_PTP_RX_TS_CNT(v) ((v) & GENMASK(3, 0))

drivers/net/phy/microchip_t1.c

154

#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)

drivers/net/phy/microchip_t1.c

1566

GENMASK(15, 0));

drivers/net/phy/microchip_t1.c

1623

((val & GENMASK(15, 4)) ==

drivers/net/phy/microchip_t1.c

1624

(PHY_ID_LAN887X & GENMASK(15, 4))),

drivers/net/phy/microchip_t1.c

179

#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)

drivers/net/phy/microchip_t1.c

1924

length = ((u32)distance & GENMASK(15, 0));

drivers/net/phy/microchip_t1.c

197

#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)

drivers/net/phy/microchip_t1.c

26

#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)

drivers/net/phy/microchip_t1.c

27

#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)

drivers/net/phy/microchip_t1.c

86

#define T1_DCQ_SQI_MSK GENMASK(3, 1)

drivers/net/phy/microchip_t1s.c

178

ret &= GENMASK(4, 0);

drivers/net/phy/microchip_t1s.c

232

cfg_results[0] = FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |

drivers/net/phy/microchip_t1s.c

233

FIELD_PREP(GENMASK(9, 4), 14 + offsets[0]) |

drivers/net/phy/microchip_t1s.c

235

cfg_results[1] = FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);

drivers/net/phy/microchip_t1s.c

252

cfg_results[0] = FIELD_PREP(GENMASK(13, 8), 5 + offsets[0]) |

drivers/net/phy/microchip_t1s.c

254

cfg_results[1] = FIELD_PREP(GENMASK(13, 8), 9 + offsets[0]) |

drivers/net/phy/microchip_t1s.c

256

cfg_results[2] = FIELD_PREP(GENMASK(13, 8), 17 + offsets[0]) |

drivers/net/phy/microchip_t1s.c

38

#define LINK_STATUS_CONFIGURATION GENMASK(12, 11)

drivers/net/phy/motorcomm.c

1033

ds_field_low = FIELD_GET(GENMASK(1, 0), ds);

drivers/net/phy/motorcomm.c

166

#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4)

drivers/net/phy/motorcomm.c

196

#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10)

drivers/net/phy/motorcomm.c

197

#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)

drivers/net/phy/motorcomm.c

198

#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)

drivers/net/phy/motorcomm.c

258

#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13)

drivers/net/phy/motorcomm.c

260

#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */

drivers/net/phy/motorcomm.c

269

#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1)

drivers/net/phy/motorcomm.c

279

#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)

drivers/net/phy/motorcomm.c

300

#define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8)

drivers/net/phy/motorcomm.c

303

#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8)

drivers/net/phy/motorcomm.c

306

#define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0)

drivers/net/phy/motorcomm.c

311

#define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0)

drivers/net/phy/motorcomm.c

314

#define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0)

drivers/net/phy/motorcomm.c

317

#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8)

drivers/net/phy/motorcomm.c

318

#define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0)

drivers/net/phy/motorcomm.c

321

#define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8)

drivers/net/phy/motorcomm.c

322

#define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0)

drivers/net/phy/motorcomm.c

325

#define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0)

drivers/net/phy/motorcomm.c

328

#define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8)

drivers/net/phy/motorcomm.c

329

#define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0)

drivers/net/phy/motorcomm.c

332

#define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8)

drivers/net/phy/motorcomm.c

333

#define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0)

drivers/net/phy/motorcomm.c

336

#define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8)

drivers/net/phy/motorcomm.c

337

#define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0)

drivers/net/phy/motorcomm.c

340

#define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8)

drivers/net/phy/motorcomm.c

341

#define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0)

drivers/net/phy/motorcomm.c

344

#define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12)

drivers/net/phy/motorcomm.c

345

#define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8)

drivers/net/phy/motorcomm.c

348

#define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12)

drivers/net/phy/motorcomm.c

349

#define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8)

drivers/net/phy/motorcomm.c

352

#define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4)

drivers/net/phy/motorcomm.c

353

#define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0)

drivers/net/phy/motorcomm.c

356

#define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4)

drivers/net/phy/motorcomm.c

357

#define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0)

drivers/net/phy/mscc/mscc.h

154

#define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)

drivers/net/phy/mscc/mscc.h

354

#define MSCC_DEV_REV_MASK GENMASK(3, 0)

drivers/net/phy/mscc/mscc.h

40

#define ERR_CNT_MASK GENMASK(7, 0)

drivers/net/phy/mscc/mscc.h

85

#define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))

drivers/net/phy/mscc/mscc_fc_buffer.h

33

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

35

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16)

drivers/net/phy/mscc/mscc_fc_buffer.h

37

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20)

drivers/net/phy/mscc/mscc_fc_buffer.h

40

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

42

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_fc_buffer.h

45

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

47

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_fc_buffer.h

50

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

52

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_fc_buffer.h

55

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

57

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_fc_buffer.h

60

#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_fc_buffer.h

62

#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_mac.h

102

#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_mac.h

134

#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M GENMASK(30, 28)

drivers/net/phy/mscc/mscc_mac.h

137

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_mac.h

143

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M GENMASK(1, 0)

drivers/net/phy/mscc/mscc_mac.h

157

#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)

drivers/net/phy/mscc/mscc_mac.h

85

#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M GENMASK(29, 20)

drivers/net/phy/mscc/mscc_mac.h

89

#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M GENMASK(12, 10)

drivers/net/phy/mscc/mscc_mac.h

98

#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_macsec.h

151

#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE_M GENMASK(12, 10)

drivers/net/phy/mscc/mscc_macsec.h

157

#define MSCC_MS_FC_CFG_LOW_THRESH_M GENMASK(7, 4)

drivers/net/phy/mscc/mscc_macsec.h

159

#define MSCC_MS_FC_CFG_HIGH_THRESH_M GENMASK(11, 8)

drivers/net/phy/mscc/mscc_macsec.h

161

#define MSCC_MS_FC_CFG_LOW_BYTES_VAL_M GENMASK(14, 12)

drivers/net/phy/mscc/mscc_macsec.h

163

#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL_M GENMASK(18, 16)

drivers/net/phy/mscc/mscc_macsec.h

167

#define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_macsec.h

175

#define MSCC_MS_SAM_MISC_MATCH_VLAN_UP_M GENMASK(6, 4)

drivers/net/phy/mscc/mscc_macsec.h

182

#define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT_M GENMASK(13, 12)

drivers/net/phy/mscc/mscc_macsec.h

184

#define MSCC_MS_SAM_MISC_MATCH_PRIORITY_M GENMASK(19, 16)

drivers/net/phy/mscc/mscc_macsec.h

190

#define MSCC_MS_SAM_MASK_MAC_SA_MASK_M GENMASK(5, 0)

drivers/net/phy/mscc/mscc_macsec.h

192

#define MSCC_MS_SAM_MASK_MAC_DA_MASK_M GENMASK(11, 6)

drivers/net/phy/mscc/mscc_macsec.h

210

#define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE_M GENMASK(1, 0)

drivers/net/phy/mscc/mscc_macsec.h

212

#define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT_M GENMASK(3, 2)

drivers/net/phy/mscc/mscc_macsec.h

216

#define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION_M GENMASK(7, 6)

drivers/net/phy/mscc/mscc_macsec.h

218

#define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8_M GENMASK(15, 8)

drivers/net/phy/mscc/mscc_macsec.h

227

#define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE_M GENMASK(22, 21)

drivers/net/phy/mscc/mscc_macsec.h

230

#define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET_M GENMASK(30, 24)

drivers/net/phy/mscc/mscc_macsec.h

235

#define MSCC_MS_SAM_CP_TAG_MAP_TBL_M GENMASK(23, 0)

drivers/net/phy/mscc/mscc_macsec.h

237

#define MSCC_MS_SAM_CP_TAG_DEF_UP_M GENMASK(26, 24)

drivers/net/phy/mscc/mscc_macsec.h

274

#define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX_M GENMASK(5, 0)

drivers/net/phy/mscc/mscc_macsec.h

278

#define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES_M GENMASK(11, 10)

drivers/net/phy/mscc/mscc_macsec.h

280

#define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE_M GENMASK(25, 24)

drivers/net/phy/mscc/mscc_macsec.h

294

#define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL_M GENMASK(23, 0)

drivers/net/phy/mscc/mscc_macsec.h

296

#define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP_M GENMASK(26, 24)

drivers/net/phy/mscc/mscc_macsec.h

305

#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE_M GENMASK(14, 0)

drivers/net/phy/mscc/mscc_macsec.h

310

#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE_M GENMASK(14, 0)

drivers/net/phy/mscc/mscc_macsec.h

318

#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M GENMASK(15, 0)

drivers/net/phy/mscc/mscc_macsec.h

320

#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16)

drivers/net/phy/mscc/mscc_main.c

637

__phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));

drivers/net/phy/mscc/mscc_main.c

859

phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));

drivers/net/phy/mscc/mscc_ptp.c

416

sig[1] = (__force u16)ptphdr->seq_id & GENMASK(7, 0);

drivers/net/phy/mscc/mscc_ptp.c

418

sig[3] = ptphdr->tsmt & GENMASK(3, 0);

drivers/net/phy/mscc/mscc_ptp.c

424

sig[i] = ptphdr->tsmt & GENMASK(3, 0);

drivers/net/phy/mscc/mscc_ptp.h

103

#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST_MASK GENMASK(17, 16)

drivers/net/phy/mscc/mscc_ptp.h

113

#define PTP_LTC_CTRL_CLK_SEL_MASK GENMASK(14, 12)

drivers/net/phy/mscc/mscc_ptp.h

126

#define PTP_LTC_LOAD_SEC_LSB(x) ((x) & GENMASK(31, 0))

drivers/net/phy/mscc/mscc_ptp.h

129

#define PTP_LTC_LOAD_NS(x) ((x) & GENMASK(31, 0))

drivers/net/phy/mscc/mscc_ptp.h

136

#define PTP_LTC_SEQUENCE_A_MASK GENMASK(3, 0)

drivers/net/phy/mscc/mscc_ptp.h

141

#define PTP_LTC_SEQ_ERR_MASK GENMASK(18, 0)

drivers/net/phy/mscc/mscc_ptp.h

145

#define PTP_AUTO_ADJ_NS_ROLLOVER(x) ((x) & GENMASK(29, 0))

drivers/net/phy/mscc/mscc_ptp.h

146

#define PTP_AUTO_ADJ_ADD_SUB_1NS_MASK GENMASK(31, 30)

drivers/net/phy/mscc/mscc_ptp.h

151

#define PTP_LTC_1PPS_WIDTH_ADJ_MASK GENMASK(29, 0)

drivers/net/phy/mscc/mscc_ptp.h

167

#define PTP_INGR_LOCAL_LATENCY_MASK GENMASK(22, 0)

drivers/net/phy/mscc/mscc_ptp.h

180

#define PTP_INGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

190

#define PTP_EGR_LOCAL_LATENCY_MASK GENMASK(22, 0)

drivers/net/phy/mscc/mscc_ptp.h

199

#define PTP_EGR_FIFO_LEVEL_LAST_READ_MASK GENMASK(15, 12)

drivers/net/phy/mscc/mscc_ptp.h

201

#define PTP_EGR_TS_FIFO_THRESH_MASK GENMASK(11, 8)

drivers/net/phy/mscc/mscc_ptp.h

203

#define PTP_EGR_TS_FIFO_SIG_BYTES_MASK GENMASK(4, 0)

drivers/net/phy/mscc/mscc_ptp.h

208

#define PTP_EGR_TS_FIFO_0_MASK GENMASK(15, 0)

drivers/net/phy/mscc/mscc_ptp.h

213

#define PTP_EGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

243

#define ANA_ETH2_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

252

#define ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)

drivers/net/phy/mscc/mscc_ptp.h

256

#define ETH2_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(9, 8)

drivers/net/phy/mscc/mscc_ptp.h

262

#define ANA_MPLS_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

270

#define MPLS_FLOW_CTRL_CHANNEL_MASK_MASK GENMASK(25, 24)

drivers/net/phy/mscc/mscc_ptp.h

276

#define ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

288

#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF_MASK GENMASK(20, 16)

drivers/net/phy/mscc/mscc_ptp.h

290

#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

292

#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK GENMASK(7, 0)

drivers/net/phy/mscc/mscc_ptp.h

301

#define ANA_IP1_NXT_PROT_OFFSET2_MASK GENMASK(6, 0)

drivers/net/phy/mscc/mscc_ptp.h

305

#define IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

307

#define IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK GENMASK(5, 4)

drivers/net/phy/mscc/mscc_ptp.h

313

#define IP1_FLOW_MATCH_ADDR_MASK GENMASK(9, 8)

drivers/net/phy/mscc/mscc_ptp.h

317

#define IP1_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)

drivers/net/phy/mscc/mscc_ptp.h

339

#define ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

345

#define IP2_NXT_PROT_UDP_CHKSUM_OFF_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

347

#define IP2_NXT_PROT_UDP_CHKSUM_WIDTH_MASK GENMASK(5, 4)

drivers/net/phy/mscc/mscc_ptp.h

35

#define ANA_ETH1_NTX_PROT_SIG_OFF_MASK GENMASK(20, 16)

drivers/net/phy/mscc/mscc_ptp.h

351

#define IP2_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)

drivers/net/phy/mscc/mscc_ptp.h

357

#define PTP_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)

drivers/net/phy/mscc/mscc_ptp.h

37

#define ANA_ETH1_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

379

#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET_MASK GENMASK(26, 24)

drivers/net/phy/mscc/mscc_ptp.h

381

#define PTP_FLOW_PTP_ACTION_PTP_CMD_MASK GENMASK(3, 0)

drivers/net/phy/mscc/mscc_ptp.h

385

#define PTP_FLOW_PTP_ACTION_TIME_OFFSET_MASK GENMASK(15, 10)

drivers/net/phy/mscc/mscc_ptp.h

387

#define PTP_FLOW_PTP_ACTION_CORR_OFFSET_MASK GENMASK(9, 5)

drivers/net/phy/mscc/mscc_ptp.h

392

#define PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET_MASK GENMASK(15, 8)

drivers/net/phy/mscc/mscc_ptp.h

394

#define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK GENMASK(3, 0)

drivers/net/phy/mscc/mscc_ptp.h

400

#define PTP_FLOW_PTP_0_FIELD_OFFSET_MASK GENMASK(13, 8)

drivers/net/phy/mscc/mscc_ptp.h

402

#define PTP_FLOW_PTP_0_FIELD_BYTES_MASK GENMASK(3, 0)

drivers/net/phy/mscc/mscc_ptp.h

410

#define ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK GENMASK(1, 0)

drivers/net/phy/mscc/mscc_ptp.h

53

#define ANA_ETH1_NTX_PROT_VLAN_TPID_MASK GENMASK(31, 16)

drivers/net/phy/mscc/mscc_ptp.h

58

#define PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK GENMASK(22, 20)

drivers/net/phy/mscc/mscc_ptp.h

60

#define PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK GENMASK(18, 16)

drivers/net/phy/mscc/mscc_ptp.h

62

#define PTP_ANALYZER_MODE_EGR_ENA_MASK GENMASK(6, 4)

drivers/net/phy/mscc/mscc_ptp.h

64

#define PTP_ANALYZER_MODE_INGR_ENA_MASK GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

71

#define PTP_MODE_CTRL_MODE_MASK GENMASK(2, 0)

drivers/net/phy/mscc/mscc_ptp.h

76

#define ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)

drivers/net/phy/mscc/mscc_ptp.h

80

#define PTP_IP_VERSION_MASK GENMASK(7, 0)

drivers/net/phy/mscc/mscc_ptp.h

84

#define ETH1_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(9, 8)

drivers/net/phy/mscc/mscc_ptp.h

91

#define ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK GENMASK(7, 6)

drivers/net/phy/mscc/mscc_ptp.h

99

#define ANA_ETH1_FLOW_ADDR_MATCH2_MASK_MASK GENMASK(22, 20)

drivers/net/phy/mscc/mscc_serdes.h

11

#define PHY_S6G_PLL5G_CFG2_GAIN_MASK GENMASK(9, 5)

drivers/net/phy/mxl-86110.c

127

#define MXL86111_EXT_CHIP_CFG_MODE_SEL_MASK GENMASK(2, 0)

drivers/net/phy/mxl-86110.c

137

#define MXL86111_EXT_CHIP_CFG_CLDO_MASK GENMASK(5, 4)

drivers/net/phy/mxl-86110.c

149

#define MXL86111_PHY_STAT_SPEED_MASK GENMASK(15, 14)

drivers/net/phy/mxl-86110.c

39

#define MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK GENMASK(3, 1)

drivers/net/phy/mxl-86110.c

57

#define MXL86110_EXT_RGMII_CFG1_RX_DELAY_MASK GENMASK(13, 10)

drivers/net/phy/mxl-86110.c

60

#define MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_MASK GENMASK(3, 0)

drivers/net/phy/mxl-86110.c

63

#define MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_MASK GENMASK(7, 4)

drivers/net/phy/mxl-86110.c

77

#define MXL86110_RGMII_MDIO_CFG_EPA0_MASK GENMASK(6, 6)

drivers/net/phy/mxl-86110.c

78

#define MXL86110_EXT_RGMII_MDIO_CFG_EBA_MASK GENMASK(5, 5)

drivers/net/phy/mxl-86110.c

79

#define MXL86110_EXT_RGMII_MDIO_CFG_BA_MASK GENMASK(4, 0)

drivers/net/phy/mxl-gpy.c

110

#define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)

drivers/net/phy/mxl-gpy.c

116

#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)

drivers/net/phy/mxl-gpy.c

47

#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)

drivers/net/phy/mxl-gpy.c

74

#define PHY_FWV_MAJOR_MASK GENMASK(11, 8)

drivers/net/phy/mxl-gpy.c

75

#define PHY_FWV_MINOR_MASK GENMASK(7, 0)

drivers/net/phy/mxl-gpy.c

78

#define PHY_MDI_MDI_X_MASK GENMASK(1, 0)

drivers/net/phy/mxl-gpy.c

86

#define VSPEC1_LED_BLINKS GENMASK(15, 12)

drivers/net/phy/mxl-gpy.c

87

#define VSPEC1_LED_PULSE GENMASK(11, 8)

drivers/net/phy/mxl-gpy.c

88

#define VSPEC1_LED_CON GENMASK(7, 4)

drivers/net/phy/mxl-gpy.c

89

#define VSPEC1_LED_BLINKF GENMASK(3, 0)

drivers/net/phy/nxp-c45-tja11xx-macsec.c

46

#define MACSEC_RXSC_CFG_VF_MASK GENMASK(9, 8)

drivers/net/phy/nxp-c45-tja11xx-macsec.c

70

#define MACSEC_TXSC_CFG_AN_MASK GENMASK(19, 18)

drivers/net/phy/nxp-c45-tja11xx.c

163

#define TS_SEC_MASK GENMASK(1, 0)

drivers/net/phy/nxp-c45-tja11xx.c

1687

if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4)))

drivers/net/phy/nxp-c45-tja11xx.c

28

#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12)

drivers/net/phy/nxp-c45-tja11xx.c

29

#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8)

drivers/net/phy/nxp-c45-tja11xx.c

329

GENMASK(reg_field->offset + reg_field->size - 1,

drivers/net/phy/nxp-c45-tja11xx.c

350

GENMASK(reg_field->offset + reg_field->size - 1,

drivers/net/phy/nxp-c45-tja11xx.c

726

hwts.nsec = ts_raw & GENMASK(29, 0);

drivers/net/phy/nxp-c45-tja11xx.c

73

#define SQI_MASK GENMASK(2, 0)

drivers/net/phy/nxp-tja11xx.c

103

{ "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },

drivers/net/phy/nxp-tja11xx.c

107

{ "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },

drivers/net/phy/nxp-tja11xx.c

108

{ "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },

drivers/net/phy/nxp-tja11xx.c

28

#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)

drivers/net/phy/nxp-tja11xx.c

40

#define MII_CFG1_INTERFACE_MODE_MASK GENMASK(9, 8)

drivers/net/phy/nxp-tja11xx.c

44

#define MII_CFG1_REVMII_MODE GENMASK(9, 8)

drivers/net/phy/nxp-tja11xx.c

46

#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)

drivers/net/phy/nxp-tja11xx.c

51

#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)

drivers/net/phy/nxp-tja11xx.c

69

#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)

drivers/net/phy/open_alliance_helpers.h

14

#define OA_1000BT1_HDD_TDR_ACTIVATION_MASK GENMASK(1, 0)

drivers/net/phy/open_alliance_helpers.h

18

#define OA_1000BT1_HDD_TDR_STATUS_MASK GENMASK(7, 4)

drivers/net/phy/open_alliance_helpers.h

39

#define OA_1000BT1_HDD_TDR_DISTANCE_MASK GENMASK(13, 8)

drivers/net/phy/phy-caps.h

38

#define LINK_CAPA_ALL GENMASK((__LINK_CAPA_MAX - 1), 0)

drivers/net/phy/phy_device.c

1047

*phy_id = ((upper & GENMASK(15, 0)) << 16) | (lower & GENMASK(15, 0));

drivers/net/phy/phylink.c

471

matched_caps = GENMASK(__fls(caps), __fls(MAC_10HD));

drivers/net/phy/phylink.c

480

matched_caps = GENMASK(__fls(caps), __fls(MAC_10HD));

drivers/net/phy/qcom/at803x.c

112

#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0)

drivers/net/phy/qcom/at803x.c

116

#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8)

drivers/net/phy/qcom/at803x.c

149

#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)

drivers/net/phy/qcom/at803x.c

65

#define AT803X_CLK_OUT_MASK GENMASK(4, 2)

drivers/net/phy/qcom/at803x.c

78

#define AT8035_CLK_OUT_MASK GENMASK(4, 3)

drivers/net/phy/qcom/at803x.c

80

#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)

drivers/net/phy/qcom/qca807x.c

25

#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK GENMASK(3, 0)

drivers/net/phy/qcom/qca807x.c

39

#define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0)

drivers/net/phy/qcom/qca807x.c

62

#define QCA807X_LED_FIBER_PATTERN_MASK GENMASK(11, 1)

drivers/net/phy/qcom/qca807x.c

75

#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5)

drivers/net/phy/qcom/qca807x.c

84

#define PQSGMII_TX_DRIVER_MASK GENMASK(7, 4)

drivers/net/phy/qcom/qca808x.c

10

#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)

drivers/net/phy/qcom/qca808x.c

18

#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)

drivers/net/phy/qcom/qca808x.c

56

#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)

drivers/net/phy/qcom/qca83xx.c

19

#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)

drivers/net/phy/qcom/qca83xx.c

22

{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},

drivers/net/phy/qcom/qca83xx.c

23

{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},

drivers/net/phy/qcom/qca83xx.c

24

{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},

drivers/net/phy/qcom/qcom.h

107

#define QCA808X_LED_BLINK_1 GENMASK(11, 6)

drivers/net/phy/qcom/qcom.h

108

#define QCA808X_LED_BLINK_2 GENMASK(5, 0)

drivers/net/phy/qcom/qcom.h

110

#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3)

drivers/net/phy/qcom/qcom.h

119

#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0)

drivers/net/phy/qcom/qcom.h

130

#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0)

drivers/net/phy/qcom/qcom.h

15

#define AT803X_SS_SPEED_MASK GENMASK(15, 14)

drivers/net/phy/qcom/qcom.h

165

#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13)

drivers/net/phy/qcom/qcom.h

183

#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)

drivers/net/phy/qcom/qcom.h

23

#define QCA808X_SS_SPEED_MASK GENMASK(9, 7)

drivers/net/phy/qcom/qcom.h

43

#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)

drivers/net/phy/qcom/qcom.h

47

#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)

drivers/net/phy/qcom/qcom.h

54

#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)

drivers/net/phy/qcom/qcom.h

55

#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)

drivers/net/phy/qcom/qcom.h

6

#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)

drivers/net/phy/qcom/qcom.h

67

#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)

drivers/net/phy/qcom/qcom.h

68

#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)

drivers/net/phy/qcom/qcom.h

70

#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)

drivers/net/phy/qcom/qcom.h

71

#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)

drivers/net/phy/qcom/qcom.h

72

#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)

drivers/net/phy/qcom/qcom.h

73

#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)

drivers/net/phy/qcom/qcom.h

75

#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)

drivers/net/phy/qcom/qcom.h

81

#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)

drivers/net/phy/realtek/realtek_main.c

125

#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)

drivers/net/phy/realtek/realtek_main.c

130

#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)

drivers/net/phy/realtek/realtek_main.c

144

#define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1))

drivers/net/phy/realtek/realtek_main.c

182

#define RTL_PHYSR_SPEEDL GENMASK(5, 4)

drivers/net/phy/realtek/realtek_main.c

183

#define RTL_PHYSR_SPEEDH GENMASK(10, 9)

drivers/net/phy/realtek/realtek_main.c

59

#define RTL8211E_LEDCR2_MASK GENMASK(2, 0)

drivers/net/phy/realtek/realtek_main.c

68

#define RTL8211E_DELAY_MASK GENMASK(13, 11)

drivers/net/phy/realtek/realtek_main.c

90

#define RTL8211F_LEDCR_MASK GENMASK(4, 0)

drivers/net/phy/vitesse.c

69

#define MII_VSC73XX_PHY_CTRL_EXT3_DOWNSHIFT_CNT GENMASK(3, 2)

drivers/net/thunderbolt/main.c

50

#define TBNET_L0_PORT_NUM(route) ((route) & GENMASK(5, 0))

drivers/net/thunderbolt/main.c

93

#define TBIP_HDR_LENGTH_MASK GENMASK(5, 0)

drivers/net/thunderbolt/main.c

94

#define TBIP_HDR_SN_MASK GENMASK(28, 27)

drivers/net/wan/framer/pef2256/pef2256-regs.h

101

#define PEF2256_12_LIM1_RIL_MASK GENMASK(6, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

110

#define PEF2256_2X_LIM1_RIL_MASK GENMASK(6, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

128

#define PEF2256_LIM2_SLT_MASK GENMASK(5, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

143

#define PEF2256_SIC1_SSD_MASK GENMASK(6, 6)

drivers/net/wan/framer/pef2256/pef2256-regs.h

148

#define PEF2256_SIC1_RBS_MASK GENMASK(5, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

153

#define PEF2256_SIC1_XBS_MASK GENMASK(1, 0)

drivers/net/wan/framer/pef2256/pef2256-regs.h

161

#define PEF2256_SIC2_SICS_MASK GENMASK(3, 1)

drivers/net/wan/framer/pef2256/pef2256-regs.h

172

#define PEF2256_CMR1_RS_MASK GENMASK(5, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

194

#define PEF2256_GPC1_CSFP_MASK GENMASK(7, 5)

drivers/net/wan/framer/pef2256/pef2256-regs.h

240

#define PEF2256_12_WID_MASK GENMASK(1, 0)

drivers/net/wan/framer/pef2256/pef2256-regs.h

242

#define PEF2256_2X_WID_MASK GENMASK(7, 6)

drivers/net/wan/framer/pef2256/pef2256-regs.h

30

#define PEF2256_FMR0_XC_MASK GENMASK(7, 6)

drivers/net/wan/framer/pef2256/pef2256-regs.h

35

#define PEF2256_FMR0_RC_MASK GENMASK(5, 4)

drivers/net/wan/framer/pef2256/pef2256-regs.h

46

#define PEF2256_FMR1_SSD_MASK GENMASK(1, 1)

drivers/net/wan/framer/pef2256/pef2256-regs.h

54

#define PEF2256_FMR2_RFS_MASK GENMASK(7, 6)

drivers/net/wan/framer/pef2256/pef2256-regs.h

64

#define PEF2256_XSW_XY_MASK GENMASK(5, 0)

drivers/net/wireless/ath/ath10k/ce.h

32

#define CE_DESC_ADDR_HI_MASK GENMASK(4, 0)

drivers/net/wireless/ath/ath10k/ce.h

41

#define CE_DDR_RRI_MASK GENMASK(15, 0)

drivers/net/wireless/ath/ath10k/htc.h

55

#define ATH10K_HTC_FLAG_BUNDLE_MASK GENMASK(7, 4)

drivers/net/wireless/ath/ath10k/htc.h

58

#define ATH10K_HTC_BUNDLE_EXTRA_MASK GENMASK(3, 2)

drivers/net/wireless/ath/ath10k/htt.h

1001

#define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0)

drivers/net/wireless/ath/ath10k/htt.h

323

#define HTT_STATS_BIT_MASK GENMASK(16, 0)

drivers/net/wireless/ath/ath10k/htt.h

553

#define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0)

drivers/net/wireless/ath/ath10k/htt.h

993

#define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0)

drivers/net/wireless/ath/ath10k/htt.h

994

#define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16)

drivers/net/wireless/ath/ath10k/hw.c

218

.mask = GENMASK(17, 17),

drivers/net/wireless/ath/ath10k/hw.c

224

.mask = GENMASK(18, 18),

drivers/net/wireless/ath/ath10k/hw.c

230

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.c

241

.mask = GENMASK(0, 0),

drivers/net/wireless/ath/ath10k/hw.c

272

.mask = GENMASK(31, 16),

drivers/net/wireless/ath/ath10k/hw.c

278

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.c

291

.mask = GENMASK(31, 16),

drivers/net/wireless/ath/ath10k/hw.c

297

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.c

350

.mask = GENMASK(16, 16),

drivers/net/wireless/ath/ath10k/hw.c

356

.mask = GENMASK(17, 17),

drivers/net/wireless/ath/ath10k/hw.c

362

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.c

381

.mask = GENMASK(3, 3),

drivers/net/wireless/ath/ath10k/hw.c

386

.mask = GENMASK(0, 0),

drivers/net/wireless/ath/ath10k/hw.c

394

.mask = GENMASK(0, 0),

drivers/net/wireless/ath/ath10k/hw.c

426

.mask = GENMASK(31, 16),

drivers/net/wireless/ath/ath10k/hw.c

432

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.c

445

.mask = GENMASK(31, 16),

drivers/net/wireless/ath/ath10k/hw.c

451

.mask = GENMASK(15, 0),

drivers/net/wireless/ath/ath10k/hw.h

1200

#define CPU_ADDR_MSB_REGION_MASK GENMASK(23, 20)

drivers/net/wireless/ath/ath10k/sdio.c

95

FIELD_PREP(GENMASK(25, 9), address) |

drivers/net/wireless/ath/ath10k/sdio.c

97

FIELD_PREP(GENMASK(7, 0), val);

drivers/net/wireless/ath/ath10k/testmode.c

22

#define ATH10K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0)

drivers/net/wireless/ath/ath10k/testmode.c

23

#define ATH10K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

1987

#define WMI_TLV_PEER_RX_DURATION_HIGH_MASK GENMASK(30, 0)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

2180

#define HW_RATECODE_PREAM_V1_MASK GENMASK(10, 8)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

2183

#define HW_RATECODE_NSS_V1_MASK GENMASK(7, 5)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

2186

#define HW_RATECODE_RATE_V1_MASK GENMASK(4, 0)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

2399

#define WMI_TLV_RFKILL_CFG_GPIO_PIN_NUM GENMASK(5, 0)

drivers/net/wireless/ath/ath10k/wmi-tlv.h

2401

#define WMI_TLV_RFKILL_CFG_PIN_AS_GPIO GENMASK(10, 7)

drivers/net/wireless/ath/ath10k/wmi.h

6545

#define WMI_PEER_NSS_160MHZ_MASK GENMASK(2, 0)

drivers/net/wireless/ath/ath10k/wmi.h

6546

#define WMI_PEER_NSS_80_80MHZ_MASK GENMASK(5, 3)

drivers/net/wireless/ath/ath10k/wmi.h

7434

#define WMI_TLV_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath10k/wmi.h

7435

#define WMI_TLV_TAG GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/ahb.h

13

#define ATH11K_AHB_SMP2P_SMEM_MSG GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/ahb.h

14

#define ATH11K_AHB_SMP2P_SMEM_SEQ_NO GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/cfr.h

134

#define CFIR_DMA_HDR_INFO0_TAG GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/cfr.h

135

#define CFIR_DMA_HDR_INFO0_LEN GENMASK(13, 8)

drivers/net/wireless/ath/ath11k/cfr.h

137

#define CFIR_DMA_HDR_INFO1_UPLOAD_DONE GENMASK(0, 0)

drivers/net/wireless/ath/ath11k/cfr.h

138

#define CFIR_DMA_HDR_INFO1_CAPTURE_TYPE GENMASK(3, 1)

drivers/net/wireless/ath/ath11k/cfr.h

139

#define CFIR_DMA_HDR_INFO1_PREAMBLE_TYPE GENMASK(5, 4)

drivers/net/wireless/ath/ath11k/cfr.h

140

#define CFIR_DMA_HDR_INFO1_NSS GENMASK(8, 6)

drivers/net/wireless/ath/ath11k/cfr.h

141

#define CFIR_DMA_HDR_INFO1_NUM_CHAINS GENMASK(11, 9)

drivers/net/wireless/ath/ath11k/cfr.h

142

#define CFIR_DMA_HDR_INFO1_UPLOAD_PKT_BW GENMASK(14, 12)

drivers/net/wireless/ath/ath11k/cfr.h

143

#define CFIR_DMA_HDR_INFO1_SW_PEER_ID_VALID GENMASK(15, 15)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4671

cfg_params->cfg0 |= FIELD_PREP(GENMASK(15, 1),

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4674

cfg_params->cfg2 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4675

cfg_params->cfg2 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4676

cfg_params->cfg2 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4677

cfg_params->cfg2 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4678

cfg_params->cfg3 |= FIELD_PREP(GENMASK(7, 0), mac_addr[4]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4679

cfg_params->cfg3 |= FIELD_PREP(GENMASK(15, 8), mac_addr[5]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4696

cfg_params->cfg1 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4697

cfg_params->cfg1 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4698

cfg_params->cfg1 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4699

cfg_params->cfg1 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4700

cfg_params->cfg2 |= FIELD_PREP(GENMASK(7, 0), mac_addr[4]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c

4701

cfg_params->cfg2 |= FIELD_PREP(GENMASK(15, 8), mac_addr[5]);

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1133

#define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1134

#define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1135

#define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1136

#define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1137

#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1138

#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1139

#define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1140

#define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1204

#define HTT_SRING_STATS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1205

#define HTT_SRING_STATS_RING_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1206

#define HTT_SRING_STATS_ARENA GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1208

#define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1209

#define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1210

#define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1211

#define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1212

#define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1213

#define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1214

#define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

1215

#define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

152

#define HTT_STATS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

312

#define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

313

#define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

332

#define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

333

#define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

334

#define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

335

#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

357

#define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

358

#define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

359

#define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

360

#define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

384

#define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

385

#define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

425

#define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

426

#define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

427

#define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

553

#define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

554

#define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

859

#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

860

#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

985

#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

986

#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/debugfs_sta.c

850

cfg_params.cfg0 |= FIELD_PREP(GENMASK(15, 1),

drivers/net/wireless/ath/ath11k/debugfs_sta.c

855

cfg_params.cfg2 |= FIELD_PREP(GENMASK(7, 0), sta->addr[0]);

drivers/net/wireless/ath/ath11k/debugfs_sta.c

856

cfg_params.cfg2 |= FIELD_PREP(GENMASK(15, 8), sta->addr[1]);

drivers/net/wireless/ath/ath11k/debugfs_sta.c

857

cfg_params.cfg2 |= FIELD_PREP(GENMASK(23, 16), sta->addr[2]);

drivers/net/wireless/ath/ath11k/debugfs_sta.c

858

cfg_params.cfg2 |= FIELD_PREP(GENMASK(31, 24), sta->addr[3]);

drivers/net/wireless/ath/ath11k/debugfs_sta.c

860

cfg_params.cfg3 |= FIELD_PREP(GENMASK(7, 0), sta->addr[4]);

drivers/net/wireless/ath/ath11k/debugfs_sta.c

861

cfg_params.cfg3 |= FIELD_PREP(GENMASK(15, 8), sta->addr[5]);

drivers/net/wireless/ath/ath11k/dp.h

1002

#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)

drivers/net/wireless/ath/ath11k/dp.h

1040

#define HTT_T2H_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

1041

#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

1042

#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

1048

#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

1049

#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1050

#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

1051

#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1052

#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

1084

#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

1085

#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

1086

#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/dp.h

1088

#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

1089

#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1175

#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/dp.h

1176

#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1191

#define HTT_TLV_TAG GENMASK(11, 0)

drivers/net/wireless/ath/ath11k/dp.h

1192

#define HTT_TLV_LEN GENMASK(23, 12)

drivers/net/wireless/ath/ath11k/dp.h

1204

#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

1205

#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

1207

#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)

drivers/net/wireless/ath/ath11k/dp.h

1234

#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/dp.h

1235

#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)

drivers/net/wireless/ath/ath11k/dp.h

1238

#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)

drivers/net/wireless/ath/ath11k/dp.h

1240

#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/dp.h

1243

#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/dp.h

1244

#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)

drivers/net/wireless/ath/ath11k/dp.h

1245

#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/dp.h

1246

#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)

drivers/net/wireless/ath/ath11k/dp.h

1247

#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)

drivers/net/wireless/ath/ath11k/dp.h

1248

#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)

drivers/net/wireless/ath/ath11k/dp.h

1265

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/dp.h

1268

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/dp.h

1269

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)

drivers/net/wireless/ath/ath11k/dp.h

1270

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/dp.h

1271

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)

drivers/net/wireless/ath/ath11k/dp.h

1272

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)

drivers/net/wireless/ath/ath11k/dp.h

1273

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)

drivers/net/wireless/ath/ath11k/dp.h

1292

#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

1294

#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)

drivers/net/wireless/ath/ath11k/dp.h

1295

#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)

drivers/net/wireless/ath/ath11k/dp.h

1297

#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1316

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/dp.h

1317

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/dp.h

1319

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)

drivers/net/wireless/ath/ath11k/dp.h

1339

#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)

drivers/net/wireless/ath/ath11k/dp.h

1340

#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)

drivers/net/wireless/ath/ath11k/dp.h

1341

#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)

drivers/net/wireless/ath/ath11k/dp.h

1626

#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

1635

#define HTT_MAC_ADDR_L32_0 GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

1636

#define HTT_MAC_ADDR_L32_1 GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

1637

#define HTT_MAC_ADDR_L32_2 GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

1638

#define HTT_MAC_ADDR_L32_3 GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/dp.h

1639

#define HTT_MAC_ADDR_H16_0 GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

1640

#define HTT_MAC_ADDR_H16_1 GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

233

#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)

drivers/net/wireless/ath/ath11k/dp.h

234

#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)

drivers/net/wireless/ath/ath11k/dp.h

239

#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/dp.h

240

#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)

drivers/net/wireless/ath/ath11k/dp.h

241

#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)

drivers/net/wireless/ath/ath11k/dp.h

297

#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)

drivers/net/wireless/ath/ath11k/dp.h

298

#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/dp.h

302

#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)

drivers/net/wireless/ath/ath11k/dp.h

309

#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)

drivers/net/wireless/ath/ath11k/dp.h

310

#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)

drivers/net/wireless/ath/ath11k/dp.h

311

#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)

drivers/net/wireless/ath/ath11k/dp.h

313

#define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/dp.h

314

#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

333

#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

483

#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

484

#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

485

#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

486

#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/dp.h

488

#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

489

#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

495

#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)

drivers/net/wireless/ath/ath11k/dp.h

497

#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

499

#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

556

#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

558

#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)

drivers/net/wireless/ath/ath11k/dp.h

559

#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/dp.h

668

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

669

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp.h

670

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/dp.h

674

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/dp.h

996

#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/dp.h

997

#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/dp_rx.c

3174

rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {

drivers/net/wireless/ath/ath11k/dp_rx.c

3706

rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {

drivers/net/wireless/ath/ath11k/hal.h

247

#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)

drivers/net/wireless/ath/ath11k/hal.h

248

#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

249

#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

255

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal.h

256

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)

drivers/net/wireless/ath/ath11k/hal.h

257

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal.h

259

#define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

261

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)

drivers/net/wireless/ath/ath11k/hal.h

262

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)

drivers/net/wireless/ath/ath11k/hal.h

263

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)

drivers/net/wireless/ath/ath11k/hal.h

264

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)

drivers/net/wireless/ath/ath11k/hal.h

265

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)

drivers/net/wireless/ath/ath11k/hal.h

266

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)

drivers/net/wireless/ath/ath11k/hal.h

267

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)

drivers/net/wireless/ath/ath11k/hal.h

268

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)

drivers/net/wireless/ath/ath11k/hal.h

269

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)

drivers/net/wireless/ath/ath11k/hal.h

272

#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)

drivers/net/wireless/ath/ath11k/hal.h

273

#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

274

#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/hal.h

275

#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

280

#define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal.h

281

#define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)

drivers/net/wireless/ath/ath11k/hal.h

283

#define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

284

#define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23)

drivers/net/wireless/ath/ath11k/hal.h

287

#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17)

drivers/net/wireless/ath/ath11k/hal.h

290

#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal.h

298

#define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)

drivers/net/wireless/ath/ath11k/hal.h

299

#define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal.h

300

#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal.h

301

#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)

drivers/net/wireless/ath/ath11k/hal.h

303

#define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)

drivers/net/wireless/ath/ath11k/hal.h

304

#define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)

drivers/net/wireless/ath/ath11k/hal.h

528

#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)

drivers/net/wireless/ath/ath11k/hal.h

529

#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)

drivers/net/wireless/ath/ath11k/hal.h

730

#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)

drivers/net/wireless/ath/ath11k/hal.h

733

#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)

drivers/net/wireless/ath/ath11k/hal.h

746

#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)

drivers/net/wireless/ath/ath11k/hal.h

750

#define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

11

#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1209

#define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1210

#define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

1215

#define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

1216

#define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

1257

#define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1259

#define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5)

drivers/net/wireless/ath/ath11k/hal_desc.h

1260

#define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

1262

#define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1264

#define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

1265

#define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

13

#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1300

#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1305

#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

1307

#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1309

#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

1397

#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1398

#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

14

#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

1450

#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

1452

#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1453

#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

15

#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)

drivers/net/wireless/ath/ath11k/hal_desc.h

1529

#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

1530

#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3)

drivers/net/wireless/ath/ath11k/hal_desc.h

1533

#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

1534

#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11)

drivers/net/wireless/ath/ath11k/hal_desc.h

1536

#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

1637

#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1638

#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)

drivers/net/wireless/ath/ath11k/hal_desc.h

1639

#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath11k/hal_desc.h

1640

#define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

1641

#define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)

drivers/net/wireless/ath/ath11k/hal_desc.h

1642

#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)

drivers/net/wireless/ath/ath11k/hal_desc.h

1643

#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)

drivers/net/wireless/ath/ath11k/hal_desc.h

1644

#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)

drivers/net/wireless/ath/ath11k/hal_desc.h

1645

#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)

drivers/net/wireless/ath/ath11k/hal_desc.h

1648

#define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1649

#define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24)

drivers/net/wireless/ath/ath11k/hal_desc.h

1651

#define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1657

#define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)

drivers/net/wireless/ath/ath11k/hal_desc.h

1659

#define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1660

#define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

1661

#define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

1662

#define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

1664

#define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

1665

#define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13)

drivers/net/wireless/ath/ath11k/hal_desc.h

1891

#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1892

#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/hal_desc.h

1893

#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

1908

#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1942

#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1945

#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

1948

#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)

drivers/net/wireless/ath/ath11k/hal_desc.h

1953

#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11)

drivers/net/wireless/ath/ath11k/hal_desc.h

1958

#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23)

drivers/net/wireless/ath/ath11k/hal_desc.h

1962

#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

1963

#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13)

drivers/net/wireless/ath/ath11k/hal_desc.h

1968

#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1971

#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)

drivers/net/wireless/ath/ath11k/hal_desc.h

1972

#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)

drivers/net/wireless/ath/ath11k/hal_desc.h

1973

#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

1975

#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1976

#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/hal_desc.h

1978

#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

1979

#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

1980

#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2070

#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2095

#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2097

#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)

drivers/net/wireless/ath/ath11k/hal_desc.h

2100

#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)

drivers/net/wireless/ath/ath11k/hal_desc.h

2111

#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2112

#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

2114

#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11)

drivers/net/wireless/ath/ath11k/hal_desc.h

2129

#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

2144

#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2145

#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2146

#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)

drivers/net/wireless/ath/ath11k/hal_desc.h

2171

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2172

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

2174

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2175

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)

drivers/net/wireless/ath/ath11k/hal_desc.h

2177

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)

drivers/net/wireless/ath/ath11k/hal_desc.h

2178

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)

drivers/net/wireless/ath/ath11k/hal_desc.h

2179

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2181

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2182

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/hal_desc.h

2184

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2185

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

2186

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2188

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

2279

#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

2282

#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

2283

#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2313

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

2315

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

2316

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

2317

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2318

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)

drivers/net/wireless/ath/ath11k/hal_desc.h

2415

#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2416

#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

2455

#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2456

#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2457

#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2458

#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

2459

#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

476

#define HAL_TLV_HDR_TAG GENMASK(9, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

477

#define HAL_TLV_HDR_LEN GENMASK(25, 10)

drivers/net/wireless/ath/ath11k/hal_desc.h

478

#define HAL_TLV_USR_ID GENMASK(31, 26)

drivers/net/wireless/ath/ath11k/hal_desc.h

487

#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

488

#define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

501

#define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

577

#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)

drivers/net/wireless/ath/ath11k/hal_desc.h

578

#define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17)

drivers/net/wireless/ath/ath11k/hal_desc.h

679

#define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

681

#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

682

#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11)

drivers/net/wireless/ath/ath11k/hal_desc.h

683

#define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

686

#define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1)

drivers/net/wireless/ath/ath11k/hal_desc.h

687

#define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5)

drivers/net/wireless/ath/ath11k/hal_desc.h

689

#define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

690

#define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

787

#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

788

#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)

drivers/net/wireless/ath/ath11k/hal_desc.h

789

#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)

drivers/net/wireless/ath/ath11k/hal_desc.h

792

#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

793

#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)

drivers/net/wireless/ath/ath11k/hal_desc.h

863

#define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

864

#define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)

drivers/net/wireless/ath/ath11k/hal_desc.h

865

#define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7)

drivers/net/wireless/ath/ath11k/hal_desc.h

867

#define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

870

#define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

871

#define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

872

#define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_desc.h

882

#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

889

#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

930

#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

932

#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)

drivers/net/wireless/ath/ath11k/hal_desc.h

941

#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

944

#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/hal_desc.h

958

#define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2)

drivers/net/wireless/ath/ath11k/hal_desc.h

959

#define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/hal_desc.h

962

#define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12)

drivers/net/wireless/ath/ath11k/hal_desc.h

963

#define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14)

drivers/net/wireless/ath/ath11k/hal_desc.h

964

#define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_desc.h

966

#define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

973

#define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23)

drivers/net/wireless/ath/ath11k/hal_desc.h

975

#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

979

#define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22)

drivers/net/wireless/ath/ath11k/hal_desc.h

980

#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26)

drivers/net/wireless/ath/ath11k/hal_desc.h

982

#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0)

drivers/net/wireless/ath/ath11k/hal_desc.h

983

#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6)

drivers/net/wireless/ath/ath11k/hal_desc.h

984

#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26)

drivers/net/wireless/ath/ath11k/hal_desc.h

985

#define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30)

drivers/net/wireless/ath/ath11k/hal_desc.h

987

#define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/hal_desc.h

988

#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/hal_rx.h

196

#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

204

#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

206

#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

210

#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)

drivers/net/wireless/ath/ath11k/hal_rx.h

212

#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

213

#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

215

#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

217

#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

218

#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

220

#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

221

#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

223

#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

224

#define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_EOSP_BITMAP GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

226

#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT GENMASK(24, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

227

#define HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

259

#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

262

#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)

drivers/net/wireless/ath/ath11k/hal_rx.h

271

#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

272

#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)

drivers/net/wireless/ath/ath11k/hal_rx.h

278

#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

279

#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)

drivers/net/wireless/ath/ath11k/hal_rx.h

280

#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)

drivers/net/wireless/ath/ath11k/hal_rx.h

286

#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

288

#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)

drivers/net/wireless/ath/ath11k/hal_rx.h

289

#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)

drivers/net/wireless/ath/ath11k/hal_rx.h

291

#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

293

#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/hal_rx.h

319

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)

drivers/net/wireless/ath/ath11k/hal_rx.h

321

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)

drivers/net/wireless/ath/ath11k/hal_rx.h

322

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)

drivers/net/wireless/ath/ath11k/hal_rx.h

323

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)

drivers/net/wireless/ath/ath11k/hal_rx.h

324

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)

drivers/net/wireless/ath/ath11k/hal_rx.h

325

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/hal_rx.h

330

#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

335

#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)

drivers/net/wireless/ath/ath11k/hal_rx.h

345

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB GENMASK(3, 1)

drivers/net/wireless/ath/ath11k/hal_rx.h

347

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR GENMASK(10, 5)

drivers/net/wireless/ath/ath11k/hal_rx.h

348

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE GENMASK(14, 11)

drivers/net/wireless/ath/ath11k/hal_rx.h

349

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW GENMASK(17, 15)

drivers/net/wireless/ath/ath11k/hal_rx.h

350

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)

drivers/net/wireless/ath/ath11k/hal_rx.h

352

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE GENMASK(24, 23)

drivers/net/wireless/ath/ath11k/hal_rx.h

355

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

357

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB GENMASK(10, 8)

drivers/net/wireless/ath/ath11k/hal_rx.h

361

#define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)

drivers/net/wireless/ath/ath11k/hal_rx.h

369

#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

375

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

376

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/hal_rx.h

378

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)

drivers/net/wireless/ath/ath11k/hal_rx.h

384

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

385

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)

drivers/net/wireless/ath/ath11k/hal_rx.h

387

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/hal_rx.h

395

#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/hal_rx.h

397

#define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

411

#define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/hal_rx.h

412

#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

413

#define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/hal_rx.h

445

#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/htc.h

18

#define HTC_HDR_ENDPOINTID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

19

#define HTC_HDR_FLAGS GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/htc.h

20

#define HTC_HDR_PAYLOADLEN GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

21

#define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

22

#define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/htc.h

23

#define HTC_HDR_RESERVED GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

25

#define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

26

#define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/htc.h

27

#define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/htc.h

28

#define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

29

#define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/htc.h

30

#define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/htc.h

32

#define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

33

#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/htc.h

35

#define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

36

#define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

37

#define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/htc.h

38

#define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/htc.h

39

#define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

41

#define HTC_MSG_MESSAGEID GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/htc.h

42

#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0)

drivers/net/wireless/ath/ath11k/htc.h

43

#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/htc.h

44

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/htc.h

45

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/htc.h

46

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/htc.h

79

#define ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/htc.h

80

#define ATH11K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/mac.c

3390

param_val |= FIELD_PREP(GENMASK(15, 8), srg_th);

drivers/net/wireless/ath/ath11k/mac.c

3398

param_val |= (non_srg_th & GENMASK(7, 0));

drivers/net/wireless/ath/ath11k/mac.c

5471

p->cwmin = u8_get_bits(params->mu_edca_param_rec.ecw_min_max, GENMASK(3, 0));

drivers/net/wireless/ath/ath11k/mac.c

5472

p->cwmax = u8_get_bits(params->mu_edca_param_rec.ecw_min_max, GENMASK(7, 4));

drivers/net/wireless/ath/ath11k/mac.c

5473

p->aifs = u8_get_bits(params->mu_edca_param_rec.aifsn, GENMASK(3, 0));

drivers/net/wireless/ath/ath11k/mac.h

114

#define IEEE80211_VHT_MCS_SUPPORT_0_11_MASK GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/mac.h

121

#define ATH11K_PEER_RX_NSS_160MHZ GENMASK(2, 0)

drivers/net/wireless/ath/ath11k/mac.h

122

#define ATH11K_PEER_RX_NSS_80_80MHZ GENMASK(5, 3)

drivers/net/wireless/ath/ath11k/pci.c

27

#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)

drivers/net/wireless/ath/ath11k/pci.c

28

#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/pcic.h

19

#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)

drivers/net/wireless/ath/ath11k/pcic.h

21

#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1021

#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1022

#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)

drivers/net/wireless/ath/ath11k/rx_desc.h

1024

#define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1025

#define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

1028

#define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

1030

#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1045

#define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26)

drivers/net/wireless/ath/ath11k/rx_desc.h

1047

#define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1050

#define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1051

#define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6)

drivers/net/wireless/ath/ath11k/rx_desc.h

1054

#define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

1057

#define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1)

drivers/net/wireless/ath/ath11k/rx_desc.h

1058

#define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6)

drivers/net/wireless/ath/ath11k/rx_desc.h

1108

#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1110

#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

1111

#define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6)

drivers/net/wireless/ath/ath11k/rx_desc.h

1114

#define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

1126

#define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

1130

#define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

132

#define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

1339

#define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21)

drivers/net/wireless/ath/ath11k/rx_desc.h

1340

#define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23)

drivers/net/wireless/ath/ath11k/rx_desc.h

1341

#define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25)

drivers/net/wireless/ath/ath11k/rx_desc.h

29

#define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

30

#define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)

drivers/net/wireless/ath/ath11k/rx_desc.h

356

#define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

362

#define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20)

drivers/net/wireless/ath/ath11k/rx_desc.h

366

#define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)

drivers/net/wireless/ath/ath11k/rx_desc.h

367

#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)

drivers/net/wireless/ath/ath11k/rx_desc.h

370

#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

371

#define RX_MPDU_START_INFO2_TID GENMASK(17, 14)

drivers/net/wireless/ath/ath11k/rx_desc.h

372

#define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/rx_desc.h

374

#define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

379

#define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11)

drivers/net/wireless/ath/ath11k/rx_desc.h

380

#define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13)

drivers/net/wireless/ath/ath11k/rx_desc.h

382

#define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

383

#define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

387

#define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

390

#define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

395

#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

399

#define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

445

#define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

446

#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5)

drivers/net/wireless/ath/ath11k/rx_desc.h

451

#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11)

drivers/net/wireless/ath/ath11k/rx_desc.h

452

#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13)

drivers/net/wireless/ath/ath11k/rx_desc.h

454

#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

455

#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

461

#define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2)

drivers/net/wireless/ath/ath11k/rx_desc.h

462

#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6)

drivers/net/wireless/ath/ath11k/rx_desc.h

463

#define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

465

#define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11)

drivers/net/wireless/ath/ath11k/rx_desc.h

466

#define RX_MPDU_START_INFO9_TID GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/rx_desc.h

468

#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

469

#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2)

drivers/net/wireless/ath/ath11k/rx_desc.h

486

#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

492

#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20)

drivers/net/wireless/ath/ath11k/rx_desc.h

494

#define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

497

#define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10)

drivers/net/wireless/ath/ath11k/rx_desc.h

502

#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

507

#define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

774

#define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

777

#define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16)

drivers/net/wireless/ath/ath11k/rx_desc.h

779

#define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/rx_desc.h

781

#define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

782

#define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

790

#define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17)

drivers/net/wireless/ath/ath11k/rx_desc.h

796

#define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/rx_desc.h

797

#define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

799

#define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/rx_desc.h

800

#define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8)

drivers/net/wireless/ath/ath11k/rx_desc.h

802

#define RX_MSDU_START_INFO3_SGI GENMASK(14, 13)

drivers/net/wireless/ath/ath11k/rx_desc.h

803

#define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15)

drivers/net/wireless/ath/ath11k/rx_desc.h

804

#define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19)

drivers/net/wireless/ath/ath11k/rx_desc.h

805

#define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21)

drivers/net/wireless/ath/ath11k/rx_desc.h

806

#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/spectral.c

101

#define SPECTRAL_FFT_REPORT_INFO2_NUM_STRONG_BINS GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/spectral.c

102

#define SPECTRAL_FFT_REPORT_INFO2_PEAK_MAGNITUDE GENMASK(17, 8)

drivers/net/wireless/ath/ath11k/spectral.c

103

#define SPECTRAL_FFT_REPORT_INFO2_AVG_PWR_DB GENMASK(24, 18)

drivers/net/wireless/ath/ath11k/spectral.c

104

#define SPECTRAL_FFT_REPORT_INFO2_REL_PWR_DB GENMASK(31, 25)

drivers/net/wireless/ath/ath11k/spectral.c

44

#define SPECTRAL_TLV_HDR_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/spectral.c

45

#define SPECTRAL_TLV_HDR_TAG GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/spectral.c

46

#define SPECTRAL_TLV_HDR_SIGN GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/spectral.c

48

#define SPECTRAL_SUMMARY_INFO0_AGC_TOTAL_GAIN GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/spectral.c

50

#define SPECTRAL_SUMMARY_INFO0_GRP_IDX GENMASK(16, 9)

drivers/net/wireless/ath/ath11k/spectral.c

52

#define SPECTRAL_SUMMARY_INFO0_INBAND_PWR_DB GENMASK(27, 18)

drivers/net/wireless/ath/ath11k/spectral.c

54

#define SPECTRAL_SUMMARY_INFO0_DETECTOR_ID GENMASK(30, 29)

drivers/net/wireless/ath/ath11k/spectral.c

57

#define SPECTRAL_SUMMARY_INFO2_PEAK_SIGNED_IDX GENMASK(11, 0)

drivers/net/wireless/ath/ath11k/spectral.c

58

#define SPECTRAL_SUMMARY_INFO2_PEAK_MAGNITUDE GENMASK(21, 12)

drivers/net/wireless/ath/ath11k/spectral.c

59

#define SPECTRAL_SUMMARY_INFO2_NARROWBAND_MASK GENMASK(29, 22)

drivers/net/wireless/ath/ath11k/spectral.c

92

#define SPECTRAL_FFT_REPORT_INFO0_DETECTOR_ID GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/spectral.c

93

#define SPECTRAL_FFT_REPORT_INFO0_FFT_NUM GENMASK(4, 2)

drivers/net/wireless/ath/ath11k/spectral.c

94

#define SPECTRAL_FFT_REPORT_INFO0_RADAR_CHECK GENMASK(16, 5)

drivers/net/wireless/ath/ath11k/spectral.c

95

#define SPECTRAL_FFT_REPORT_INFO0_PEAK_SIGNED_IDX GENMASK(27, 17)

drivers/net/wireless/ath/ath11k/spectral.c

96

#define SPECTRAL_FFT_REPORT_INFO0_CHAIN_IDX GENMASK(30, 28)

drivers/net/wireless/ath/ath11k/spectral.c

98

#define SPECTRAL_FFT_REPORT_INFO1_BASE_PWR_DB GENMASK(8, 0)

drivers/net/wireless/ath/ath11k/spectral.c

99

#define SPECTRAL_FFT_REPORT_INFO1_TOTAL_GAIN_DB GENMASK(16, 9)

drivers/net/wireless/ath/ath11k/testmode.c

15

#define ATH11K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/testmode.c

16

#define ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4)

drivers/net/wireless/ath/ath11k/wmi.h

2502

#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)

drivers/net/wireless/ath/ath11k/wmi.h

3338

#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3473

#define WMI_CHAN_INFO_MODE GENMASK(5, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3488

#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3489

#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/wmi.h

3490

#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)

drivers/net/wireless/ath/ath11k/wmi.h

3491

#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/wmi.h

3493

#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3494

#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/wmi.h

3608

#define WMI_P2P_NOA_INFO_INDEX GENMASK(15, 8)

drivers/net/wireless/ath/ath11k/wmi.h

3610

#define WMI_P2P_NOA_INFO_CTWIN_TU GENMASK(23, 17)

drivers/net/wireless/ath/ath11k/wmi.h

3611

#define WMI_P2P_NOA_INFO_DESC_NUM GENMASK(31, 24)

drivers/net/wireless/ath/ath11k/wmi.h

3833

#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3834

#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)

drivers/net/wireless/ath/ath11k/wmi.h

3835

#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)

drivers/net/wireless/ath/ath11k/wmi.h

3836

#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)

drivers/net/wireless/ath/ath11k/wmi.h

3838

#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)

drivers/net/wireless/ath/ath11k/wmi.h

3839

#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)

drivers/net/wireless/ath/ath11k/wmi.h

3840

#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)

drivers/net/wireless/ath/ath11k/wmi.h

3843

#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 22)

drivers/net/wireless/ath/ath11k/wmi.h

4242

#define WMI_CFR_FRAME_TX_STATUS GENMASK(1, 0)

drivers/net/wireless/ath/ath11k/wmi.h

4246

#define WMI_CFR_CORRELATION_INFO2_BUF_ADDR_HIGH GENMASK(3, 0)

drivers/net/wireless/ath/ath11k/wmi.h

4247

#define WMI_CFR_CORRELATION_INFO2_PPDU_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/wmi.h

4250

#define WMI_CFR_CFO_MEASUREMENT_RAW_DATA GENMASK(14, 1)

drivers/net/wireless/ath/ath11k/wmi.h

51

#define WMI_TLV_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/wmi.h

52

#define WMI_TLV_TAG GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/wmi.h

55

#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)

drivers/net/wireless/ath/ath11k/wmi.h

5707

#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)

drivers/net/wireless/ath/ath11k/wmi.h

5708

#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)

drivers/net/wireless/ath/ath11k/wmi.h

5710

#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/ahb.h

16

#define ATH12K_AHB_SMP2P_SMEM_MSG GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/ahb.h

17

#define ATH12K_AHB_SMP2P_SMEM_SEQ_NO GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/ahb.h

30

#define ATH12K_USERPD_ID_MASK GENMASK(9, 8)

drivers/net/wireless/ath/ath12k/debugfs.h

36

#define HE_EXTRA_MCS_SUPPORT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

117

#define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1174

#define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1175

#define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1176

#define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1178

#define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1179

#define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1180

#define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1181

#define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1182

#define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1183

#define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1184

#define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1185

#define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1609

#define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1610

#define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1611

#define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1612

#define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1613

#define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1614

#define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1727

#define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

1728

#define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

274

#define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

620

#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

621

#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp.h

109

#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/dp.h

236

#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)

drivers/net/wireless/ath/ath12k/dp.h

237

#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)

drivers/net/wireless/ath/ath12k/dp.h

242

#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/dp.h

243

#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)

drivers/net/wireless/ath/ath12k/dp.h

244

#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)

drivers/net/wireless/ath/ath12k/dp.h

298

#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)

drivers/net/wireless/ath/ath12k/dp.h

299

#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)

drivers/net/wireless/ath/ath12k/dp.h

301

#define DP_REO_QREF_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1065

#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/dp_htt.h

1066

#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1081

#define HTT_TLV_TAG GENMASK(11, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1082

#define HTT_TLV_LEN GENMASK(23, 12)

drivers/net/wireless/ath/ath12k/dp_htt.h

1094

#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1095

#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

1097

#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1124

#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1125

#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)

drivers/net/wireless/ath/ath12k/dp_htt.h

1141

#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)

drivers/net/wireless/ath/ath12k/dp_htt.h

1143

#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1146

#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/dp_htt.h

1147

#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

1148

#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/dp_htt.h

1149

#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1150

#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)

drivers/net/wireless/ath/ath12k/dp_htt.h

1151

#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/dp_htt.h

1170

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1173

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/dp_htt.h

1174

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

1175

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/dp_htt.h

1176

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1177

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)

drivers/net/wireless/ath/ath12k/dp_htt.h

1178

#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/dp_htt.h

1197

#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1199

#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)

drivers/net/wireless/ath/ath12k/dp_htt.h

1200

#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)

drivers/net/wireless/ath/ath12k/dp_htt.h

1202

#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1221

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1222

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/dp_htt.h

1224

#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/dp_htt.h

1244

#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1245

#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)

drivers/net/wireless/ath/ath12k/dp_htt.h

1246

#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)

drivers/net/wireless/ath/ath12k/dp_htt.h

1352

#define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1353

#define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

15

#define HTT_TCL_META_DATA_TYPE GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1507

#define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1508

#define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

1509

#define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

1510

#define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/dp_htt.h

1511

#define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

1512

#define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

19

#define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3)

drivers/net/wireless/ath/ath12k/dp_htt.h

20

#define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11)

drivers/net/wireless/ath/ath12k/dp_htt.h

224

#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

225

#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

226

#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

227

#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/dp_htt.h

229

#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

230

#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

236

#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

238

#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

24

#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3)

drivers/net/wireless/ath/ath12k/dp_htt.h

240

#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

241

#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

29

#define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3)

drivers/net/wireless/ath/ath12k/dp_htt.h

297

#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

299

#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)

drivers/net/wireless/ath/ath12k/dp_htt.h

300

#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

33

#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)

drivers/net/wireless/ath/ath12k/dp_htt.h

34

#define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

37

#define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/dp_htt.h

422

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

423

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

424

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

431

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

432

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

433

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19)

drivers/net/wireless/ath/ath12k/dp_htt.h

434

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22)

drivers/net/wireless/ath/ath12k/dp_htt.h

436

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

442

#define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1)

drivers/net/wireless/ath/ath12k/dp_htt.h

444

#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

445

#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

446

#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

447

#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

448

#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

449

#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

450

#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

453

#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

454

#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

455

#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

62

#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

65

#define HTT_OPTION_TAG GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

66

#define HTT_OPTION_LEN GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

67

#define HTT_OPTION_VALUE GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

781

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

782

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

842

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

843

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

844

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

848

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

849

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

850

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)

drivers/net/wireless/ath/ath12k/dp_htt.h

851

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)

drivers/net/wireless/ath/ath12k/dp_htt.h

852

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)

drivers/net/wireless/ath/ath12k/dp_htt.h

854

#define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

867

#define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

868

#define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/dp_htt.h

869

#define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

939

#define HTT_T2H_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

940

#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

941

#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

947

#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

948

#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

949

#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

950

#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

951

#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

952

#define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

953

#define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

987

#define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/dp_htt.h

988

#define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/dp_htt.h

989

#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/dp_htt.h

990

#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/dp_rx.c

1427

rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {

drivers/net/wireless/ath/ath12k/hal.h

1437

#define HAL_TLV_HDR_TAG GENMASK(9, 1)

drivers/net/wireless/ath/ath12k/hal.h

1438

#define HAL_TLV_HDR_LEN GENMASK(25, 10)

drivers/net/wireless/ath/ath12k/hal.h

1439

#define HAL_TLV_USR_ID GENMASK(31, 26)

drivers/net/wireless/ath/ath12k/hal.h

1448

#define HAL_TLV_64_HDR_TAG GENMASK(9, 1)

drivers/net/wireless/ath/ath12k/hal.h

1449

#define HAL_TLV_64_HDR_LEN GENMASK(21, 10)

drivers/net/wireless/ath/ath12k/hal.h

1450

#define HAL_TLV_64_USR_ID GENMASK(31, 26)

drivers/net/wireless/ath/ath12k/hal.h

1458

#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)

drivers/net/wireless/ath/ath12k/hal.h

1459

#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)

drivers/net/wireless/ath/ath12k/hal.h

749

#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/hal.h

751

#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/hal.h

752

#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/hal.h

753

#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)

drivers/net/wireless/ath/ath12k/hal.h

78

#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/hal.h

79

#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)

drivers/net/wireless/ath/ath12k/hal.h

82

#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)

drivers/net/wireless/ath/ath12k/hal.h

83

#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/htc.h

18

#define HTC_HDR_ENDPOINTID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

19

#define HTC_HDR_FLAGS GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/htc.h

20

#define HTC_HDR_PAYLOADLEN GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

21

#define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

22

#define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/htc.h

23

#define HTC_HDR_RESERVED GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

25

#define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

26

#define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/htc.h

27

#define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/htc.h

28

#define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

29

#define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/htc.h

30

#define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/htc.h

32

#define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

33

#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/htc.h

35

#define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

36

#define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

37

#define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/htc.h

38

#define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/htc.h

39

#define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

41

#define HTC_MSG_MESSAGEID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/htc.h

42

#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/htc.h

43

#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/htc.h

44

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/htc.h

45

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/htc.h

46

#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/htc.h

86

#define ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/htc.h

89

#define ATH12K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/mac.c

8734

GENMASK(ppet_bit_len_per_ru - 1, 0));

drivers/net/wireless/ath/ath12k/mac.h

40

#define IEEE80211_VHT_MCS_SUPPORT_0_11_MASK GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/mac.h

45

#define ATH12K_PEER_RX_NSS_160MHZ GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/mac.h

57

#define ATH12K_SCAN_LINKS_MASK GENMASK(ATH12K_NUM_MAX_LINKS, IEEE80211_MLD_MAX_NUM_LINKS)

drivers/net/wireless/ath/ath12k/pci.c

26

#define WINDOW_VALUE_MASK GENMASK(24, 19)

drivers/net/wireless/ath/ath12k/pci.c

28

#define WINDOW_RANGE_MASK GENMASK(18, 0)

drivers/net/wireless/ath/ath12k/pci.c

29

#define WINDOW_STATIC_MASK GENMASK(31, 6)

drivers/net/wireless/ath/ath12k/pci.h

60

#define OTP_BOARD_ID_MASK GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/pci.h

64

#define DOMAIN_NUMBER_MASK GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/pci.h

65

#define BUS_NUMBER_MASK GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/pci.h

76

#define QRTR_PCI_DOMAIN_NR_MASK GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/pci.h

77

#define QRTR_PCI_BUS_NUMBER_MASK GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/testmode.c

16

#define ATH12K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/testmode.c

17

#define ATH12K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wifi7/dp_rx.c

1224

rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {

drivers/net/wireless/ath/ath12k/wifi7/hal.h

252

#define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

253

#define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

254

#define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

268

#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

269

#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

270

#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

277

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

278

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

279

#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

281

#define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

283

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

284

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

285

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

286

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

287

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

288

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

289

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

290

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

291

#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

294

#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

295

#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

296

#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

297

#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

302

#define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

303

#define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

305

#define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

306

#define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

307

#define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

310

#define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

311

#define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

312

#define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

320

#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

328

#define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

329

#define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

330

#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

331

#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

333

#define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

334

#define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

412

#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

415

#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal.h

428

#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1003

#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1010

#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1059

#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1061

#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1070

#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1073

#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1088

#define HAL_TCL_DATA_CMD_INFO0_BANK_ID GENMASK(7, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1089

#define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME GENMASK(10, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1091

#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP GENMASK(30, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1094

#define HAL_TCL_DATA_CMD_INFO1_CMD_NUM GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1096

#define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1103

#define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET GENMASK(31, 23)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1107

#define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL GENMASK(3, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1108

#define HAL_TCL_DATA_CMD_INFO3_TID GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1110

#define HAL_TCL_DATA_CMD_INFO3_PMAC_ID GENMASK(10, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1111

#define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR GENMASK(12, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1112

#define HAL_TCL_DATA_CMD_INFO3_VDEV_ID GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1114

#define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1115

#define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM GENMASK(23, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1118

#define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1119

#define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1283

#define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1285

#define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1287

#define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE GENMASK(10, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1288

#define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE GENMASK(14, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1289

#define HAL_TX_MSDU_EXT_INFO1_BUF_LEN GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1340

#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1345

#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1347

#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1349

#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1436

#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1437

#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1489

#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1491

#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1492

#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1568

#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(3, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1569

#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1572

#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1573

#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1575

#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(28, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1582

#define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1583

#define HAL_WBM_COMPL_RX_INFO0_BM_ACTION GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1584

#define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1585

#define HAL_WBM_COMPL_RX_INFO0_RBM GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1586

#define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1587

#define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1588

#define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1589

#define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1592

#define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1593

#define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE GENMASK(27, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1594

#define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1606

#define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1607

#define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1608

#define HAL_WBM_COMPL_TX_INFO0_RBM GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1609

#define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1611

#define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1615

#define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1616

#define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1619

#define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1622

#define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1623

#define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1625

#define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1626

#define HAL_WBM_COMPL_TX_INFO3_TID GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1627

#define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1628

#define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1640

#define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1641

#define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1642

#define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1643

#define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1644

#define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON GENMASK(18, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1646

#define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 GENMASK(29, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1649

#define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1650

#define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1653

#define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1656

#define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1657

#define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1659

#define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1660

#define HAL_WBM_RELEASE_TX_INFO3_TID GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1661

#define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1662

#define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1673

#define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1674

#define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1675

#define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1676

#define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1678

#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1679

#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1680

#define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1681

#define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1684

#define HAL_WBM_RELEASE_RX_INFO2_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1685

#define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1696

#define HAL_WBM_RELEASE_RX_CC_INFO0_RBM GENMASK(12, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1697

#define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE GENMASK(27, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1709

#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1710

#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1711

#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1712

#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1713

#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1714

#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1715

#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1722

#define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1840

#define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1841

#define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1842

#define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER GENMASK(10, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1844

#define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1847

#define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1848

#define HAL_SW_MONITOR_RING_INFO1_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

1849

#define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2047

#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2048

#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2049

#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2065

#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2099

#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2102

#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2105

#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2110

#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(20, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2115

#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(26, 25)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2119

#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2120

#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(22, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2125

#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2128

#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2129

#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2130

#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2132

#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2133

#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2135

#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2136

#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2137

#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2227

#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2252

#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2254

#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2257

#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2268

#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(9, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2269

#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2271

#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(24, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2292

#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2307

#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2308

#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2309

#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2334

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2335

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(21, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2337

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2338

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2340

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2341

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2342

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2343

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2345

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2346

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2348

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2349

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(27, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2351

#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2447

#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2450

#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2451

#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2481

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2483

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2484

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2485

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2486

#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2583

#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2584

#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2623

#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2624

#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2625

#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2626

#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2627

#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2662

#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2665

#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2676

#define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2678

#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(11, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2679

#define HAL_MON_DEST_INFO0_END_REASON GENMASK(17, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2682

#define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2683

#define HAL_MON_DEST_INFO0_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

2718

#define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE GENMASK(16, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

490

#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

498

#define RX_MPDU_DESC_INFO0_SRC_INFO GENMASK(26, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

500

#define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

505

#define RX_MPDU_DESC_META_DATA_V0_PEER_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

506

#define RX_MPDU_DESC_META_DATA_V0_VDEV_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

509

#define RX_MPDU_DESC_META_DATA_V1_PEER_ID GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

510

#define RX_MPDU_DESC_META_DATA_V1_LOGICAL_LINK_ID GENMASK(15, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

511

#define RX_MPDU_DESC_META_DATA_V1_VDEV_ID GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

512

#define RX_MPDU_DESC_META_DATA_V1_LMAC_ID GENMASK(25, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

513

#define RX_MPDU_DESC_META_DATA_V1_DEVICE_ID GENMASK(28, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

516

#define RX_MPDU_DESC_META_DATA_V1A_PEER_ID GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

517

#define RX_MPDU_DESC_META_DATA_V1A_VDEV_ID GENMASK(21, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

518

#define RX_MPDU_DESC_META_DATA_V1A_LOGICAL_LINK_ID GENMASK(25, 22)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

519

#define RX_MPDU_DESC_META_DATA_V1A_DEVICE_ID GENMASK(28, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

522

#define RX_MPDU_DESC_META_DATA_V1B_PEER_ID GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

523

#define RX_MPDU_DESC_META_DATA_V1B_VDEV_ID GENMASK(21, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

524

#define RX_MPDU_DESC_META_DATA_V1B_HW_LINK_ID GENMASK(25, 22)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

525

#define RX_MPDU_DESC_META_DATA_V1B_DEVICE_ID GENMASK(28, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

595

#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

606

#define RX_MSDU_DESC_INFO0_DST_CHIP_ID GENMASK(28, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

607

#define RX_MSDU_DESC_INFO0_DECAP_FORMAT GENMASK(30, 29)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

693

#define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

694

#define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE GENMASK(13, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

696

#define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET GENMASK(26, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

697

#define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID GENMASK(29, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

724

#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(2, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

725

#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(7, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

726

#define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

728

#define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID GENMASK(15, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

729

#define HAL_REO_DEST_RING_INFO0_SIGNATURE GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

730

#define HAL_REO_DEST_RING_INFO0_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

731

#define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

813

#define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

814

#define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

815

#define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

874

#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

875

#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

876

#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

879

#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

880

#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

881

#define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM GENMASK(10, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

885

#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING GENMASK(18, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

886

#define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM GENMASK(30, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

888

#define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

889

#define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

890

#define HAL_REO_ENTR_RING_INFO2_RING_ID GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_desc.h

891

#define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

130

#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

133

#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

142

#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

143

#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

149

#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

150

#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

151

#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

157

#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

159

#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

160

#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

162

#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

164

#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

187

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

189

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

190

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

191

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

192

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

193

#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

198

#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

203

#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

213

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

215

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

216

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

217

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

218

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

220

#define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

223

#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

224

#define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

227

#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

235

#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

241

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

242

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

244

#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

250

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

251

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

253

#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

268

#define HAL_RX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

269

#define HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

270

#define HAL_RX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

271

#define HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

28

le32_get_bits((__val), GENMASK(7, 0))

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

280

#define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

281

#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

282

#define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

283

#define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

305

#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

31

le32_get_bits((__val), GENMASK(15, 8))

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

324

#define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

325

#define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

326

#define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

327

#define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

337

#define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

339

#define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

34

le32_get_bits((__val), GENMASK(23, 16))

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

340

#define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

341

#define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

345

#define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

346

#define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

347

#define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

348

#define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

349

#define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

37

le32_get_bits((__val), GENMASK(31, 24))

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

467

#define HAL_RX_CMN_USR_INFO0_CP_SETTING GENMASK(17, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

468

#define HAL_RX_CMN_USR_INFO0_LTF_SIZE GENMASK(19, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

476

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

477

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

478

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

479

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS GENMASK(10, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

481

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD GENMASK(13, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

482

#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC GENMASK(17, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

488

#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

489

#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

490

#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

492

#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

494

#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD GENMASK(16, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

500

#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

501

#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

503

#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

506

#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC GENMASK(25, 22)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

512

#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

513

#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

515

#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING GENMASK(22, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

516

#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC GENMASK(26, 23)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

527

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

528

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

529

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM GENMASK(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

531

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

533

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD GENMASK(16, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

534

#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS GENMASK(19, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

583

#define HAL_RX_USIG_CMN_INFO0_PHY_VERSION GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

584

#define HAL_RX_USIG_CMN_INFO0_BW GENMASK(5, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

586

#define HAL_RX_USIG_CMN_INFO0_BSS_COLOR GENMASK(12, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

587

#define HAL_RX_USIG_CMN_INFO0_TXOP GENMASK(19, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

588

#define HAL_RX_USIG_CMN_INFO0_DISREGARD GENMASK(25, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

59

#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

595

#define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

597

#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1 GENMASK(6, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

598

#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2 GENMASK(10, 7)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

599

#define HAL_RX_USIG_TB_INFO0_DISREGARD_1 GENMASK(15, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

60

#define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

600

#define HAL_RX_USIG_TB_INFO0_CRC GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

601

#define HAL_RX_USIG_TB_INFO0_TAIL GENMASK(25, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

608

#define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

61

#define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

610

#define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO GENMASK(7, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

612

#define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS GENMASK(10, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

613

#define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM GENMASK(15, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

614

#define HAL_RX_USIG_MU_INFO0_CRC GENMASK(20, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

615

#define HAL_RX_USIG_MU_INFO0_TAIL GENMASK(26, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

632

#define HAL_RX_USR_INFO0_PHY_PPDU_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

633

#define HAL_RX_USR_INFO0_USR_RSSI GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

634

#define HAL_RX_USR_INFO0_PKT_TYPE GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

636

#define HAL_RX_USR_INFO0_RECEPTION_TYPE GENMASK(31, 29)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

638

#define HAL_RX_USR_INFO1_MCS GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

639

#define HAL_RX_USR_INFO1_SGI GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

641

#define HAL_RX_USR_INFO1_MIMO_SS_BITMAP GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

642

#define HAL_RX_USR_INFO1_RX_BW GENMASK(18, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

643

#define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

646

#define HAL_RX_USR_INFO2_NSS GENMASK(10, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

647

#define HAL_RX_USR_INFO2_STREAM_OFFSET GENMASK(13, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

650

#define HAL_RX_USR_INFO2_RU_TYPE_80_0 GENMASK(19, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

651

#define HAL_RX_USR_INFO2_RU_TYPE_80_1 GENMASK(23, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

652

#define HAL_RX_USR_INFO2_RU_TYPE_80_2 GENMASK(27, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

653

#define HAL_RX_USR_INFO2_RU_TYPE_80_3 GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

655

#define HAL_RX_USR_INFO3_RU_START_IDX_80_0 GENMASK(5, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

656

#define HAL_RX_USR_INFO3_RU_START_IDX_80_1 GENMASK(13, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

657

#define HAL_RX_USR_INFO3_RU_START_IDX_80_2 GENMASK(21, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

658

#define HAL_RX_USR_INFO3_RU_START_IDX_80_3 GENMASK(29, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

71

#define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

72

#define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

73

#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

75

#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

79

#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

81

#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

82

#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

84

#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

86

#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

87

#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

89

#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

90

#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

92

#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

93

#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

95

#define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

96

#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

105

#define RX_MPDU_START_INFO7_VDEV_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

106

#define RX_MPDU_START_INFO7_SERVICE_CODE GENMASK(16, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

108

#define RX_MPDU_START_INFO7_SRC_INFO GENMASK(29, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

18

#define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

19

#define RX_MPDU_START_INFO0_LMAC_PEER_ID_MSB GENMASK(6, 5)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

24

#define RX_MPDU_START_INFO0_RXDMA0_SRC_RING_SEL GENMASK(13, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

25

#define RX_MPDU_START_INFO0_RXDMA0_DST_RING_SEL GENMASK(16, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

32

#define RX_MPDU_START_INFO1_REO_QUEUE_DESC_HI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

33

#define RX_MPDU_START_INFO1_RECV_QUEUE_NUM GENMASK(23, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

39

#define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

40

#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

41

#define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

43

#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(14, 11)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

44

#define RX_MPDU_START_INFO2_TID GENMASK(18, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

46

#define RX_MPDU_START_INFO3_RXPCU_MPDU_FLTR GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

47

#define RX_MPDU_START_INFO3_SW_FRAME_GRP_ID GENMASK(8, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

627

#define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

629

#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

630

#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

632

#define RX_MSDU_END_INFO1_REPORTED_MPDU_LENGTH GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

634

#define RX_MSDU_END_INFO2_CCE_SUPER_RULE GENMASK(13, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

638

#define RX_MSDU_END_INFO3_DA_OFFSET GENMASK(5, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

639

#define RX_MSDU_END_INFO3_SA_OFFSET GENMASK(11, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

643

#define RX_MSDU_END_INFO4_TCP_FLAG GENMASK(8, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

649

#define RX_MSDU_END_INFO5_TID GENMASK(6, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

65

#define RX_MPDU_START_INFO4_MPDU_FRAG_NUMBER GENMASK(13, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

653

#define RX_MSDU_END_INFO5_L3_HDR_PADDING GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

660

#define RX_MSDU_END_INFO6_REO_DEST_IND GENMASK(5, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

661

#define RX_MSDU_END_INFO6_FLOW_IDX GENMASK(25, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

663

#define RX_MSDU_END_INFO6_MESH_STA GENMASK(28, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

668

#define RX_MSDU_END_INFO7_AGGR_COUNT GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

679

#define RX_MSDU_END_INFO8_KEY_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

681

#define RX_MSDU_END_INFO9_SERVICE_CODE GENMASK(14, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

684

#define RX_MSDU_END_INFO9_DEST_CHIP_ID GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

690

#define RX_MSDU_END_INFO10_MSDU_LENGTH GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

693

#define RX_MSDU_END_INFO10_L3_OFFSET GENMASK(22, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

695

#define RX_MSDU_END_INFO10_L4_OFFSET GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

697

#define RX_MSDU_END_INFO11_MSDU_NUMBER GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

698

#define RX_MSDU_END_INFO11_DECAP_FORMAT GENMASK(9, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

706

#define RX_MSDU_END_INFO11_SEL_TOEPLITZ_HASH GENMASK(18, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

71

#define RX_MPDU_START_INFO4_MPDU_SEQ_NUM GENMASK(31, 20)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

712

#define RX_MSDU_END_INFO11_IP4_IP6_NXT_HDR GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

714

#define RX_MSDU_END_INFO12_USER_RSSI GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

715

#define RX_MSDU_END_INFO12_PKT_TYPE GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

716

#define RX_MSDU_END_INFO12_SGI GENMASK(13, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

717

#define RX_MSDU_END_INFO12_RATE_MCS GENMASK(17, 14)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

718

#define RX_MSDU_END_INFO12_RECV_BW GENMASK(20, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

719

#define RX_MSDU_END_INFO12_RECEPTION_TYPE GENMASK(23, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

721

#define RX_MSDU_END_INFO12_MIMO_SS_BITMAP GENMASK(30, 24)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

73

#define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

756

#define RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE GENMASK(12, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

76

#define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

81

#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx_desc.h

86

#define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

106

#define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

107

#define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

115

#define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE GENMASK(29, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

123

#define HAL_TX_Q_EXT_INFO0_FRAME_CTRL GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

124

#define HAL_TX_Q_EXT_INFO0_QOS_CTRL GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

132

#define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS GENMASK(28, 23)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

140

#define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE GENMASK(2, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

141

#define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

142

#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

143

#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

144

#define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

145

#define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

146

#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

147

#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

148

#define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16 GENMASK(31, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

161

#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

162

#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

171

#define HAL_TX_BANK_CONFIG_ENCAP_TYPE GENMASK(2, 1)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

172

#define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE GENMASK(6, 3)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

178

#define HAL_TX_BANK_CONFIG_MESH_EN GENMASK(13, 12)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

180

#define HAL_TX_BANK_CONFIG_PMAC_ID GENMASK(16, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

182

#define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

68

#define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

70

#define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

71

#define HAL_TX_PHY_DESC_INFO0_BANDWIDTH GENMASK(30, 28)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

72

#define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

74

#define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

75

#define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

76

#define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

77

#define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL GENMASK(17, 15)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

86

#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

87

#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

88

#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

89

#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wifi7/hal_tx.h

98

#define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wifi7/pci.c

28

#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/wifi7/pci.c

29

#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wmi.c

3575

param_val |= u32_encode_bits((u8)arg->srg_th, GENMASK(15, 8));

drivers/net/wireless/ath/ath12k/wmi.c

3576

param_val |= u32_encode_bits((u8)arg->non_srg_th, GENMASK(7, 0));

drivers/net/wireless/ath/ath12k/wmi.h

2317

#define WMI_PEER_PUNCTURE_BITMAP GENMASK(23, 8)

drivers/net/wireless/ath/ath12k/wmi.h

2546

#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wmi.h

2681

#define WMI_HW_MODE_CAP_CFG_TYPE GENMASK(27, 0)

drivers/net/wireless/ath/ath12k/wmi.h

2694

#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)

drivers/net/wireless/ath/ath12k/wmi.h

2703

#define WMI_CAPS_PARAMS_PDEV_ID GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wmi.h

2704

#define WMI_CAPS_PARAMS_HW_LINK_ID GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wmi.h

2797

#define WMI_EHT_MCS_NSS_0_7 GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wmi.h

2798

#define WMI_EHT_MCS_NSS_8_9 GENMASK(7, 4)

drivers/net/wireless/ath/ath12k/wmi.h

2799

#define WMI_EHT_MCS_NSS_10_11 GENMASK(11, 8)

drivers/net/wireless/ath/ath12k/wmi.h

2800

#define WMI_EHT_MCS_NSS_12_13 GENMASK(15, 12)

drivers/net/wireless/ath/ath12k/wmi.h

2802

#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION GENMASK(1, 0)

drivers/net/wireless/ath/ath12k/wmi.h

3507

#define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21)

drivers/net/wireless/ath/ath12k/wmi.h

3632

#define WMI_CHAN_INFO_MODE GENMASK(5, 0)

drivers/net/wireless/ath/ath12k/wmi.h

3647

#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

3648

#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

3649

#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wmi.h

3650

#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wmi.h

3652

#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

3653

#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

3723

#define WMI_P2P_NOA_INFO_INDEX GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

3725

#define WMI_P2P_NOA_INFO_CTWIN_TU GENMASK(23, 17)

drivers/net/wireless/ath/ath12k/wmi.h

3726

#define WMI_P2P_NOA_INFO_DESC_NUM GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wmi.h

3762

#define WMI_EMA_BEACON_CNT GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

3763

#define WMI_EMA_BEACON_IDX GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

3764

#define WMI_EMA_BEACON_FIRST GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wmi.h

3765

#define WMI_EMA_BEACON_LAST GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wmi.h

4030

#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

4031

#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)

drivers/net/wireless/ath/ath12k/wmi.h

4032

#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)

drivers/net/wireless/ath/ath12k/wmi.h

4033

#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)

drivers/net/wireless/ath/ath12k/wmi.h

4035

#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

4036

#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)

drivers/net/wireless/ath/ath12k/wmi.h

4037

#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)

drivers/net/wireless/ath/ath12k/wmi.h

4039

#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)

drivers/net/wireless/ath/ath12k/wmi.h

4582

#define WMI_ROAM_REASON_MASK GENMASK(3, 0)

drivers/net/wireless/ath/ath12k/wmi.h

4583

#define WMI_ROAM_SUBNET_STATUS_MASK GENMASK(5, 4)

drivers/net/wireless/ath/ath12k/wmi.h

5141

#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wmi.h

5142

#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wmi.h

5144

#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

5299

#define WMI_RFKILL_CFG_GPIO_PIN_NUM GENMASK(5, 0)

drivers/net/wireless/ath/ath12k/wmi.h

5301

#define WMI_RFKILL_CFG_PIN_AS_GPIO GENMASK(10, 7)

drivers/net/wireless/ath/ath12k/wmi.h

6057

#define ATH12K_TPC_RATE_ARRAY_MU GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

6058

#define ATH12K_TPC_RATE_ARRAY_SU GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

6202

#define CRTL_F_DYNC_FORCE_LINK_NUM GENMASK(3, 2)

drivers/net/wireless/ath/ath12k/wmi.h

6221

#define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_1 GENMASK(7, 0)

drivers/net/wireless/ath/ath12k/wmi.h

6222

#define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_2 GENMASK(15, 8)

drivers/net/wireless/ath/ath12k/wmi.h

6223

#define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_3 GENMASK(23, 16)

drivers/net/wireless/ath/ath12k/wmi.h

6224

#define WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_4 GENMASK(31, 24)

drivers/net/wireless/ath/ath12k/wmi.h

79

#define WMI_TLV_LEN GENMASK(15, 0)

drivers/net/wireless/ath/ath12k/wmi.h

80

#define WMI_TLV_TAG GENMASK(31, 16)

drivers/net/wireless/ath/ath12k/wmi.h

83

#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)

drivers/net/wireless/ath/wcn36xx/dxe.h

180

#define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

185

#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

190

#define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

195

#define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

200

#define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

61

#define WCN36xx_DXE_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CTRL_XTYPE_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

66

#define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

71

#define WCN36xx_DXE_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CTRL_PRIO_SHIFT)

drivers/net/wireless/ath/wcn36xx/dxe.h

76

#define WCN36xx_DXE_CTRL_BDT_IDX_MASK GENMASK(19, WCN36xx_DXE_CTRL_BDT_IDX_SHIFT)

drivers/net/wireless/intel/iwlwifi/fw/api/dbg-tlv.h

14

#define IWL_FW_INI_REGION_ID_MASK GENMASK(15, 0)

drivers/net/wireless/intel/iwlwifi/fw/api/dbg-tlv.h

15

#define IWL_FW_INI_REGION_DUMP_POLICY_MASK GENMASK(31, 16)

drivers/net/wireless/intel/iwlwifi/fw/dbg.c

3449

GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1));

drivers/net/wireless/intel/iwlwifi/iwl-trans.h

1254

return u32_get_bits(trans->info.hw_id, GENMASK(31, 16));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

359

GENMASK(7, 0));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

362

GENMASK(9, 8));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

365

GENMASK(11, 10));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

368

GENMASK(13, 12));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

387

GENMASK(9, 0));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

390

GENMASK(11, 10));

drivers/net/wireless/intel/iwlwifi/mld/tlc.c

393

GENMASK(13, 12));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

328

MAX_NSS_MCS(7, &mcs_rx_20, &mcs_tx_20), GENMASK(7, 0));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

330

MAX_NSS_MCS(9, &mcs_rx_20, &mcs_tx_20), GENMASK(9, 8));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

332

MAX_NSS_MCS(11, &mcs_rx_20, &mcs_tx_20), GENMASK(11, 10));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

334

MAX_NSS_MCS(13, &mcs_rx_20, &mcs_tx_20), GENMASK(13, 12));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

352

MAX_NSS_MCS(9, mcs_rx, mcs_tx), GENMASK(9, 0));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

354

MAX_NSS_MCS(11, mcs_rx, mcs_tx), GENMASK(11, 10));

drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c

356

MAX_NSS_MCS(13, mcs_rx, mcs_tx), GENMASK(13, 12));

drivers/net/wireless/intel/iwlwifi/pcie/drv.c

1113

subdevice_mask = GENMASK(dev_info->subdevice_m_h,

drivers/net/wireless/intel/iwlwifi/tests/devinfo.c

16

u16 subdevice_mask = GENMASK(di->subdevice_m_h, di->subdevice_m_l);

drivers/net/wireless/intel/iwlwifi/tests/devinfo.c

164

u16 subdevice_mask = GENMASK(di->subdevice_m_h,

drivers/net/wireless/mediatek/mt76/dma.h

12

#define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/dma.h

130

#define RRO_RXDMAD_DATA1_SDL0_MASK GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/dma.h

132

#define RRO_RXDMAD_DATA2_RX_TOKEN_ID_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/dma.h

133

#define RRO_RXDMAD_DATA2_IND_REASON_MASK GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/dma.h

135

#define RRO_RXDMAD_DATA3_MAGIC_CNT_MASK GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/dma.h

15

#define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/dma.h

21

#define MT_DMA_CTL_TOKEN GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/dma.h

22

#define MT_DMA_CTL_SDP1_H GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/dma.h

23

#define MT_DMA_CTL_SDP0_H GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/dma.h

26

#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/dma.h

27

#define MT_DMA_PPE_ENTRY GENMASK(30, 16)

drivers/net/wireless/mediatek/mt76/dma.h

34

#define MT_DMA_SDP0 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/dma.h

35

#define MT_DMA_TOKEN_ID GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/dma.h

36

#define MT_DMA_MAGIC_MASK GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/dma.h

42

#define MT_DMA_WED_IND_REASON GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mac80211.c

1920

if ((sband->bitrates[i].hw_value & GENMASK(7, 0)) == idx)

drivers/net/wireless/mediatek/mt76/mt76.h

32

#define MT_QFLAG_WED_RING GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76.h

33

#define MT_QFLAG_WED_TYPE GENMASK(4, 2)

drivers/net/wireless/mediatek/mt76/mt76.h

367

#define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt76.h

371

#define MT_WCID_TX_INFO_RATE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76.h

372

#define MT_WCID_TX_INFO_NSS GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76.h

373

#define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)

drivers/net/wireless/mediatek/mt76/mt76.h

430

#define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt76.h

431

#define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt76.h

432

#define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76.h

434

#define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt76.h

435

#define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0)

drivers/net/wireless/mediatek/mt76/mt76.h

477

#define MT_PACKET_ID_MASK GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7603/beacon.c

117

mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));

drivers/net/wireless/mediatek/mt76/mt7603/eeprom.h

88

#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/eeprom.h

89

#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7603/init.c

192

mt76_set(dev, MT_AGG_TMP, GENMASK(4, 2));

drivers/net/wireless/mediatek/mt76/mt7603/init.c

202

mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));

drivers/net/wireless/mediatek/mt76/mt7603/init.c

444

val &= GENMASK(5, 0);

drivers/net/wireless/mediatek/mt76/mt7603/init.c

469

target_power = -(target_power & GENMASK(5, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

1035

txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

1198

final_rate &= GENMASK(5, 0);

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

1206

final_rate &= GENMASK(5, 0);

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

151

mt76_stop_tx_ac(dev, GENMASK(3, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

156

mt76_start_tx_ac(dev, GENMASK(3, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

16

ret |= GENMASK(3, 0) * !!(mask & BIT(0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

17

ret |= GENMASK(8, 5) * !!(mask & BIT(1));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

18

ret |= GENMASK(13, 10) * !!(mask & BIT(2));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

19

ret |= GENMASK(19, 16) * !!(mask & BIT(3));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

319

mt76_stop_tx_ac(dev, GENMASK(3, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.c

323

mt76_start_tx_ac(dev, GENMASK(3, 0));

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

100

#define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

102

#define MT_RXV4_IB_RSSI1 GENMASK(27, 20)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

103

#define MT_RXV4_F_AGC_LPF_GAIN_X GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

104

#define MT_RXV4_WB_RSSI_X GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

105

#define MT_RXV4_IB_RSSI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

107

#define MT_RXV5_LTF_SNR0 GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

108

#define MT_RXV5_LTF_PROC_TIME GENMASK(25, 19)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

109

#define MT_RXV5_FOE GENMASK(18, 7)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

110

#define MT_RXV5_C_AGC_SATE GENMASK(6, 4)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

111

#define MT_RXV5_F_AGC_LNA_GAIN_0 GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

112

#define MT_RXV5_F_AGC_LNA_GAIN_1 GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

114

#define MT_RXV6_C_AGC_STATE GENMASK(30, 28)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

115

#define MT_RXV6_NS_TS_FIELD GENMASK(27, 25)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

117

#define MT_RXV6_NF2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

118

#define MT_RXV6_NF1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

119

#define MT_RXV6_NF0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

131

#define MT_TXD0_Q_IDX GENMASK(30, 27)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

136

#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

137

#define MT_TXD0_TX_BYTES GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

139

#define MT_TXD1_OWN_MAC GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

141

#define MT_TXD1_TID GENMASK(22, 20)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

143

#define MT_TXD1_HDR_PAD GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

145

#define MT_TXD1_HDR_FORMAT GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

146

#define MT_TXD1_HDR_INFO GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

147

#define MT_TXD1_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

152

#define MT_TXD2_POWER_OFFSET GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

153

#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

154

#define MT_TXD2_FRAG GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

163

#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

164

#define MT_TXD2_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

168

#define MT_TXD3_SEQ GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

169

#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

170

#define MT_TXD3_TX_COUNT GENMASK(10, 6)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

172

#define MT_TXD4_PN_LOW GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

174

#define MT_TXD5_PN_HIGH GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

181

#define MT_TXD5_PID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

185

#define MT_TXD6_TX_RATE GENMASK(29, 18)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

189

#define MT_TXD6_ANT_PRI GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

192

#define MT_TXD6_BW GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

193

#define MT_TXD6_ANT_ID GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

197

#define MT_TX_RATE_NSS GENMASK(10, 9)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

198

#define MT_TX_RATE_MODE GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

199

#define MT_TX_RATE_IDX GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

201

#define MT_TXS0_ANTENNA GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

202

#define MT_TXS0_TID GENMASK(25, 22)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

211

#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

217

#define MT_TXS0_TX_RATE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

219

#define MT_TXS1_F0_TIMESTAMP GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

220

#define MT_TXS1_F1_NOISE_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

221

#define MT_TXS1_F1_NOISE_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

222

#define MT_TXS1_F1_NOISE_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

224

#define MT_TXS2_F0_FRONT_TIME GENMASK(24, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

225

#define MT_TXS2_F1_RCPI_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

226

#define MT_TXS2_F1_RCPI_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

227

#define MT_TXS2_F1_RCPI_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

229

#define MT_TXS3_WCID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

230

#define MT_TXS3_RXV_SEQNO GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

231

#define MT_TXS3_TX_DELAY GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

233

#define MT_TXS4_LAST_TX_RATE GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

234

#define MT_TXS4_TX_COUNT GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

237

#define MT_TXS4_PID GENMASK(21, 14)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

238

#define MT_TXS4_BW GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

239

#define MT_TXS4_F0_SEQNO GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

240

#define MT_TXS4_F1_TSSI GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

27

#define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

28

#define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

31

#define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

32

#define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

33

#define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

57

#define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

58

#define MT_RXD2_NORMAL_TID GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

59

#define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

6

#define MT_RXD0_LENGTH GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

61

#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

63

#define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

64

#define MT_RXD3_NORMAL_WOL GENMASK(18, 14)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

66

#define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

7

#define MT_RXD0_PKT_TYPE GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

70

#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

72

#define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

73

#define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

79

#define MT_RXV1_FRAME_MODE GENMASK(16, 15)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

80

#define MT_RXV1_TX_MODE GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

81

#define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

83

#define MT_RXV1_HT_STBC GENMASK(8, 7)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

84

#define MT_RXV1_TX_RATE GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

86

#define MT_RXV2_VHTA1_B16_B6 GENMASK(31, 21)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

87

#define MT_RXV2_LENGTH GENMASK(20, 0)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

89

#define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

9

#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

91

#define MT_RXV3_RCPI1 GENMASK(27, 20)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

92

#define MT_RXV3_F_AGC0_CAL_GAIN GENMASK(19, 17)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

94

#define MT_RXV3_RCPI0 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/mac.h

98

#define MT_RXV3_VHTA1_B21_B17 GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

101

#define MT_MCU_DEBUG_RESET_QUEUES GENMASK(6, 2)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

104

#define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

105

#define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

108

#define MT_PSE_FRP_P0 GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

109

#define MT_PSE_FRP_P1 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

110

#define MT_PSE_FRP_P2_RQ0 GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

111

#define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

112

#define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

115

#define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

116

#define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

119

#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

120

#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

125

#define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

126

#define MT_PSE_RTA_PORT_ID GENMASK(6, 5)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

128

#define MT_PSE_RTA_TAG_ID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

14

#define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

142

#define MT_AGC_41_RSSI_0 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

143

#define MT_AGC_41_RSSI_1 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

148

#define MT_RXTD_6_ACI_TH GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

149

#define MT_RXTD_6_CCAED_TH GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

15

#define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

151

#define MT_RXTD_8_LOWER_SIGNAL GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

167

#define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

168

#define MT_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

171

#define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

172

#define MT_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

18

#define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

181

#define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

182

#define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

184

#define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

185

#define MT_AGG_ARCR_SPE_DIS_TH GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

19

#define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

190

#define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

196

#define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

212

#define MT_AGG_PCR_RTS_THR GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

213

#define MT_AGG_PCR_RTS_PKT_THR GENMASK(31, 25)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

216

#define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

222

#define MT_AGG_CONTROL_CFEND_RATE GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

224

#define MT_AGG_CONTROL_BAR_RATE GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

229

#define MT_AGG_BWCR_BW GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

232

#define MT_AGG_RETRY_CONTROL_RTS_LIMIT GENMASK(11, 7)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

233

#define MT_AGG_RETRY_CONTROL_BAR_LIMIT GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

239

#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

246

#define MT_DMA_FQCR0_TARGET_WCID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

247

#define MT_DMA_FQCR0_TARGET_BSS GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

248

#define MT_DMA_FQCR0_TARGET_QID GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

249

#define MT_DMA_FQCR0_DEST_PORT_ID GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

250

#define MT_DMA_FQCR0_DEST_QUEUE_ID GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

260

#define MT_DMA_TCFR_TXS_AGGR_TIMEOUT GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

262

#define MT_DMA_TCFR_TXS_AGGR_COUNT GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

263

#define MT_DMA_TCFR_TXS_BIT_MAP GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

271

#define MT_WMM_AIFSN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

277

#define MT_WMM_CWMAX_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

280

#define MT_WMM_CWMIN_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

29

#define MT_INT_RX_DONE_ALL GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

290

#define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

30

#define MT_INT_TX_DONE_ALL GENMASK(19, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

343

#define MT_WF_ARB_CAB_COUNT_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

352

#define MT_TX_ABORT_WCID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

358

#define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

359

#define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

360

#define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

363

#define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

364

#define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

381

#define MT_WMM_TXOP_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

385

#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

386

#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

389

#define MT_TXREQ_CCA_SRC_SEL GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

392

#define MT_RXREQ_DELAY GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

395

#define MT_IFS_EIFS GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

396

#define MT_IFS_RIFS GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

397

#define MT_IFS_SIFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

398

#define MT_IFS_SLOT GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

401

#define MT_TMAC_PCR_RATE GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

403

#define MT_TMAC_PCR_ANT_ID GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

406

#define MT_TMAC_PCR_ANT_PRI GENMASK(26, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

407

#define MT_TMAC_PCR_ANT_PRI_SEL GENMASK(27)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

44

#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

441

#define MT_MAC_ADDR1_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

446

#define MT_BA_CONTROL_1_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

447

#define MT_BA_CONTROL_1_TID GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

455

#define MT_WF_RMACDR_MBSSID_MASK GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

460

#define MT_WF_RMAC_RMCR_SMPS_MODE GENMASK(21, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

461

#define MT_WF_RMAC_RMCR_RX_STREAMS GENMASK(24, 22)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

47

#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

478

#define MT_SEC_SCR_MASK_ORDER GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

484

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

499

#define MT_LPON_T0CR_MODE GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

505

#define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

508

#define MT_PRE_TBTT_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

512

#define MT_TBTT_PERIOD GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

513

#define MT_TBTT_DTIM_PERIOD GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

514

#define MT_TBTT_TBTT_WAKE_PERIOD GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

515

#define MT_TBTT_DTIM_WAKE_PERIOD GENMASK(30, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

522

#define MT_LPON_SBTOR_TIME_OFFSET GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

541

#define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

542

#define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

543

#define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

546

#define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

547

#define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

548

#define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

549

#define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

552

#define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

553

#define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

554

#define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

56

#define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

560

#define MT_MIB_CTL_PSCCA_TIME GENMASK(13, 11)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

561

#define MT_MIB_CTL_CCA_NAV_TX GENMASK(16, 14)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

562

#define MT_MIB_CTL_ED_TIME GENMASK(30, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

568

#define MT_MIB_STAT_CCA_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

571

#define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

576

#define MT_MIB_STAT_ED_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

58

#define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

600

#define MT_LED_STATUS_OFF GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

601

#define MT_LED_STATUS_ON GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

602

#define MT_LED_STATUS_DURATION GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

622

#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

623

#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

624

#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

625

#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

626

#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

635

#define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

649

#define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

650

#define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

652

#define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

661

#define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

663

#define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

664

#define MT_WTBL1_W2_KEY_TYPE GENMASK(6, 3)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

669

#define MT_WTBL1_W2_AMPDU_FACTOR GENMASK(13, 11)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

689

#define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

690

#define MT_WTBL1_W3_WTBL2_ENTRY_ID GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

691

#define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

698

#define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

699

#define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

700

#define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

701

#define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

703

#define MT_WTBL2_W0_PN_LO GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

705

#define MT_WTBL2_W1_PN_HI GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

706

#define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

708

#define MT_WTBL2_W2_TID0_SN GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

709

#define MT_WTBL2_W2_TID1_SN GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

710

#define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

712

#define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

713

#define MT_WTBL2_W3_TID3_SN GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

714

#define MT_WTBL2_W3_TID4_SN GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

715

#define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

717

#define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

718

#define MT_WTBL2_W4_TID6_SN GENMASK(19, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

719

#define MT_WTBL2_W4_TID7_SN GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

721

#define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

724

#define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

725

#define MT_WTBL2_W6_TX_COUNT_RATE3 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

726

#define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

727

#define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

729

#define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

730

#define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

732

#define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

733

#define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

735

#define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

737

#define MT_WTBL2_W9_ANT_PRIORITY GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

738

#define MT_WTBL2_W9_CC_BW_SEL GENMASK(10, 9)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

739

#define MT_WTBL2_W9_CHANGE_BW_RATE GENMASK(13, 11)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

74

#define MT_SCH_4_FORCE_QID GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

740

#define MT_WTBL2_W9_BW_CAP GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

745

#define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

746

#define MT_WTBL2_W9_MPDU_OK_COUNT GENMASK(28, 26)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

747

#define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

749

#define MT_WTBL2_W10_RATE1 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

750

#define MT_WTBL2_W10_RATE2 GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

751

#define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

753

#define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

754

#define MT_WTBL2_W11_RATE4 GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

755

#define MT_WTBL2_W11_RATE5 GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

756

#define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

758

#define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

759

#define MT_WTBL2_W12_RATE7 GENMASK(19, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

760

#define MT_WTBL2_W12_RATE8 GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

762

#define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

763

#define MT_WTBL2_W13_AVG_RCPI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

766

#define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

767

#define MT_WTBL2_W14_CC_NOISE_2S GENMASK(13, 7)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

768

#define MT_WTBL2_W14_CC_NOISE_3S GENMASK(20, 14)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

769

#define MT_WTBL2_W14_CHAN_EST_RMS GENMASK(24, 21)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

771

#define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

773

#define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7603/regs.h

775

#define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/debugfs.c

380

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h

52

#define MT_EE_RATE_POWER_MASK GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h

59

#define MT_EE_NIC_CONF_TX_MASK GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h

60

#define MT_EE_NIC_CONF_RX_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h

62

#define MT_EE_HW_CONF1_TX_MASK GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h

67

#define MT_EE_NIC_WIFI_CONF_BAND_SEL GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

1091

return val & GENMASK(11, 0);

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

1779

mt76_clear(dev, reg, GENMASK(22, 20));

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

10

#define MT_RXD0_LENGTH GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

101

#define MT_RXV3_WB_RSSI GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

102

#define MT_RXV3_IB_RSSI GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

104

#define MT_RXV4_RCPI3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

105

#define MT_RXV4_RCPI2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

106

#define MT_RXV4_RCPI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

107

#define MT_RXV4_RCPI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

109

#define MT_RXV5_FOE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

11

#define MT_RXD0_PKT_FLAG GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

111

#define MT_RXV6_NF3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

112

#define MT_RXV6_NF2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

113

#define MT_RXV6_NF1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

114

#define MT_RXV6_NF0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

12

#define MT_RXD0_PKT_TYPE GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

14

#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

157

#define MT_TXD0_Q_IDX GENMASK(30, 26)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

160

#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

161

#define MT_TXD0_TX_BYTES GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

163

#define MT_TXD1_OWN_MAC GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

164

#define MT_TXD1_PKT_FMT GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

165

#define MT_TXD1_TID GENMASK(23, 21)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

168

#define MT_TXD1_HDR_PAD GENMASK(18, 17)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

171

#define MT_TXD1_HDR_FORMAT GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

172

#define MT_TXD1_HDR_INFO GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

173

#define MT_TXD1_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

178

#define MT_TXD2_POWER_OFFSET GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

179

#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

180

#define MT_TXD2_FRAG GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

189

#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

190

#define MT_TXD2_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

194

#define MT_TXD3_SEQ GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

195

#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

196

#define MT_TXD3_TX_COUNT GENMASK(10, 6)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

200

#define MT_TXD4_PN_LOW GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

202

#define MT_TXD5_PN_HIGH GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

208

#define MT_TXD5_PID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

214

#define MT_TXD6_TX_RATE GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

215

#define MT_TXD6_ANT_ID GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

218

#define MT_TXD6_BW GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

22

#define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

222

#define MT_TXD7_TYPE GENMASK(21, 20)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

223

#define MT_TXD7_SUB_TYPE GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

224

#define MT_TXD7_SPE_IDX GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

227

#define MT_TXD8_L_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

228

#define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

23

#define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

231

#define MT_TX_RATE_NSS GENMASK(10, 9)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

232

#define MT_TX_RATE_MODE GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

233

#define MT_TX_RATE_IDX GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

235

#define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

237

#define MT_TXS0_PID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

24

#define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

246

#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

252

#define MT_TXS0_TX_RATE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

254

#define MT_TXS1_ANT_ID GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

255

#define MT_TXS1_RESP_RATE GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

256

#define MT_TXS1_BW GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

259

#define MT_TXS1_TID GENMASK(11, 9)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

262

#define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

264

#define MT_TXS2_WCID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

265

#define MT_TXS2_RXV_SEQNO GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

266

#define MT_TXS2_TX_DELAY GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

268

#define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

269

#define MT_TXS3_TX_COUNT GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

270

#define MT_TXS3_F1_TSSI1 GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

271

#define MT_TXS3_F1_TSSI0 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

272

#define MT_TXS3_F0_SEQNO GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

274

#define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

275

#define MT_TXS4_F1_TSSI3 GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

276

#define MT_TXS4_F1_TSSI2 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

278

#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

279

#define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

280

#define MT_TXS5_F1_NOISE_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

281

#define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

283

#define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

284

#define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

285

#define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

286

#define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

29

#define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

30

#define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

31

#define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

35

#define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

36

#define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

57

#define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

58

#define MT_RXD2_NORMAL_TID GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

59

#define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

61

#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

63

#define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

64

#define MT_RXD3_NORMAL_WOL GENMASK(18, 14)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

66

#define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

70

#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

72

#define MT_RXD4_FRAME_CONTROL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

74

#define MT_RXD6_SEQ_CTRL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

75

#define MT_RXD6_QOS_CTL GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

77

#define MT_RXD7_HT_CONTROL GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

81

#define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

82

#define MT_RXV1_NUM_RX GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

88

#define MT_RXV1_FRAME_MODE GENMASK(16, 15)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

89

#define MT_RXV1_TX_MODE GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

90

#define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

92

#define MT_RXV1_HT_STBC GENMASK(8, 7)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

93

#define MT_RXV1_TX_RATE GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

97

#define MT_RXV2_NSTS GENMASK(29, 27)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

98

#define MT_RXV2_GROUP_ID GENMASK(26, 21)

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

99

#define MT_RXV2_LENGTH GENMASK(20, 0)

drivers/net/wireless/mediatek/mt76/mt7615/main.c

130

return ffs(~mask & GENMASK(end, start));

drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h

63

#define MT_CHFREQ_SEQ GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

111

#define MT_INT_RX_DONE_ALL GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

112

#define MT_INT_TX_DONE_ALL GENMASK(19, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

122

#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

127

#define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

129

#define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

150

#define MT_MCU_CMD_ERROR_MASK (GENMASK(5, 1) | GENMASK(28, 24))

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

151

#define MT7663_MCU_CMD_ERROR_MASK GENMASK(5, 2)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

168

#define MT_HIF0_MIN_QUOTA GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

179

#define MT_HIF0_MIN_QUOTA GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

181

#define MT_HIF1_MIN_QUOTA GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

185

#define MT_HIF_ALL_EMPTY_MASK GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

187

#define MT_PSE_SRC_CNT GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

191

#define MT_PP_TXDWCNT_TX0_ADD_DW_CNT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

192

#define MT_PP_TXDWCNT_TX1_ADD_DW_CNT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

204

#define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

205

#define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

210

#define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

211

#define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

225

#define MT_WF_PHY_PD_OFDM_MASK(_phy) ((_phy) ? GENMASK(24, 16) : \

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

226

GENMASK(28, 20))

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

238

#define MT_WF_PHY_PD_CCK_MASK(_phy) (_phy) ? GENMASK(31, 24) : \

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

239

GENMASK(8, 1)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

248

#define MT_WF_PHY_RFINTF3_0_ANT GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

264

#define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

265

#define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

267

#define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

272

#define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

278

#define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

284

#define MT_AGG_ACR_CFEND_RATE GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

285

#define MT_AGG_ACR_BAR_RATE GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

311

#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

312

#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

315

#define MT_TMAC_TRCR_CCA_SEL GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

316

#define MT_TMAC_TRCR_SEC_CCA_SEL GENMASK(29, 28)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

319

#define MT_IFS_EIFS GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

320

#define MT_IFS_RIFS GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

321

#define MT_IFS_SIFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

322

#define MT_IFS_SLOT GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

325

#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

326

#define MT_TMAC_CTCR0_INS_DDLMT_DENSITY GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

357

#define MT_WF_RMAC_MORE_MUAR_MODE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

370

#define MT_WF_RMAC_MAR1_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

373

#define MT_WF_RMAC_MAR1_IDX GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

374

#define MT_WF_RMAC_MAR1_GROUP GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

384

#define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

390

#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

401

#define MT_DMA_RCFR0_RX_DROPPED_UCAST GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

402

#define MT_DMA_RCFR0_RX_DROPPED_MCAST GENMASK(27, 26)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

416

#define MT_WTBL_W0_KEY_IDX GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

420

#define MT_WTBL_W2_KEY_TYPE GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

423

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

43

#define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

443

#define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

444

#define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

445

#define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

448

#define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

449

#define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

450

#define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

451

#define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

454

#define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

455

#define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

456

#define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

46

#define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

460

#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

465

#define MT_WTBL_W5_BW_CAP GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

466

#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

467

#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

468

#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

470

#define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

476

#define MT_LPON_TCR_MODE GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

477

#define MT_LPON_TCR_READ GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

48

#define MT7663_TOP_MISC2_FW_STATE GENMASK(3, 1)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

493

#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

496

#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

499

#define MT_MIB_AMPDU_MPDU_COUNT GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

502

#define MT_MIB_AMPDU_ACK_COUNT GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

505

#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

508

#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

510

#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

513

#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

514

#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

517

#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

518

#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

533

#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

534

#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

537

#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

538

#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

544

#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

55

#define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

56

#define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

562

#define MT_LED_STATUS_OFF GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

563

#define MT_LED_STATUS_ON GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

564

#define MT_LED_STATUS_DURATION GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

575

#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

576

#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

577

#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

578

#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

579

#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

597

#define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

598

#define MT_WL_TX_TMOUT_LMT GENMASK(27, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

60

#define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

601

#define MT_WL_RX_AGG_TO GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

602

#define MT_WL_RX_AGG_LMT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

61

#define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

618

#define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8))

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

619

#define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8))

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

84

#define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7615/regs.h

85

#define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac.h

47

#define MT_TXD_LEN_MASK GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

105

#define MT_TXD5_PID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

109

#define MT_TXD6_TX_RATE GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

110

#define MT_TXD6_SGI GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

111

#define MT_TXD6_HELTF GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

114

#define MT_TXD6_ANT_ID GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

117

#define MT_TXD6_BW GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

119

#define MT_TXD7_TXD_LEN GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

122

#define MT_TXD7_TYPE GENMASK(21, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

123

#define MT_TXD7_SUB_TYPE GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

125

#define MT_TXD7_PSE_FID GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

126

#define MT_TXD7_SPE_IDX GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

128

#define MT_TXD7_TX_TIME GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

130

#define MT_TXD8_L_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

131

#define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

134

#define MT_TX_RATE_NSS GENMASK(12, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

135

#define MT_TX_RATE_MODE GENMASK(9, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

139

#define MT_TX_RATE_IDX GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

142

#define MT_TXS0_BW GENMASK(30, 29)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

143

#define MT_TXS0_TID GENMASK(28, 26)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

145

#define MT_TXS0_TXS_FORMAT GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

154

#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

158

#define MT_TXS0_TX_RATE GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

160

#define MT_TXS1_SEQNO GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

161

#define MT_TXS1_RESP_RATE GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

162

#define MT_TXS1_RXV_SEQNO GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

163

#define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

165

#define MT_TXS2_BF_STATUS GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

166

#define MT_TXS2_LAST_TX_RATE GENMASK(29, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

168

#define MT_TXS2_WCID GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

169

#define MT_TXS2_TX_DELAY GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

171

#define MT_TXS3_PID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

172

#define MT_TXS3_ANT_ID GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

174

#define MT_TXS4_TIMESTAMP GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

177

#define MT_TXS5_MPDU_TX_BYTE GENMASK(22, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

178

#define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

180

#define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

181

#define MT_TXS7_MPDU_RETRY_BYTE GENMASK(22, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

182

#define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

185

#define MT_RXD0_LENGTH GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

186

#define MT_RXD0_PKT_FLAG GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

187

#define MT_RXD0_PKT_TYPE GENMASK(31, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

189

#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

194

#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

200

#define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

201

#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

213

#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

216

#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

218

#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

219

#define MT_RXD2_NORMAL_TID GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

233

#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

234

#define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

239

#define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

241

#define MT_RXD4_NORMAL_WOL GENMASK(18, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

242

#define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

244

#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

249

#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

250

#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

251

#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

269

#define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

270

#define MT_RXD6_TA_LO GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

272

#define MT_RXD7_TA_HI GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

274

#define MT_RXD8_SEQ_CTRL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

275

#define MT_RXD8_QOS_CTL GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

277

#define MT_RXD9_HT_CONTROL GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

280

#define MT_PRXV_TX_RATE GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

283

#define MT_PRXV_NSTS GENMASK(9, 7)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

286

#define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

288

#define MT_PRXV_FRAME_MODE GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

289

#define MT_PRXV_HT_SGI GENMASK(16, 15)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

290

#define MT_PRXV_HT_STBC GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

291

#define MT_PRXV_TX_MODE GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

296

#define MT_PRXV_RCPI3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

297

#define MT_PRXV_RCPI2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

298

#define MT_PRXV_RCPI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

299

#define MT_PRXV_RCPI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

300

#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

303

#define MT_CRXV_HT_STBC GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

304

#define MT_CRXV_TX_MODE GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

305

#define MT_CRXV_FRAME_MODE GENMASK(10, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

306

#define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

307

#define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

310

#define MT_CRXV_HE_NUM_USER GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

313

#define MT_CRXV_HE_RU0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

314

#define MT_CRXV_HE_RU1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

315

#define MT_CRXV_HE_RU2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

316

#define MT_CRXV_HE_RU3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

318

#define MT_CRXV_HE_MU_AID GENMASK(30, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

320

#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

321

#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

322

#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

323

#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

325

#define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

326

#define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

330

#define MT_CRXV_SNR GENMASK(18, 13)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

331

#define MT_CRXV_FOE_LO GENMASK(31, 19)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

332

#define MT_CRXV_FOE_HI GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

40

#define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

41

#define MT_TX_FREE_WLAN_ID GENMASK(23, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

42

#define MT_TX_FREE_COUNT GENMASK(12, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

44

#define MT_TX_FREE_STATUS GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

45

#define MT_TX_FREE_MSDU_ID GENMASK(30, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

48

#define MT_TX_FREE_RATE GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

50

#define MT_TXD0_Q_IDX GENMASK(31, 25)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

51

#define MT_TXD0_PKT_FMT GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

52

#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

53

#define MT_TXD0_TX_BYTES GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

57

#define MT_TXD1_OWN_MAC GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

59

#define MT_TXD1_TID GENMASK(22, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

60

#define MT_TXD1_HDR_PAD GENMASK(19, 18)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

61

#define MT_TXD1_HDR_FORMAT GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

62

#define MT_TXD1_HDR_INFO GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

65

#define MT_TXD1_WLAN_IDX GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

69

#define MT_TXD2_POWER_OFFSET GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

70

#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

71

#define MT_TXD2_FRAG GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

80

#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

81

#define MT_TXD2_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

87

#define MT_TXD3_SEQ GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

88

#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

89

#define MT_TXD3_TX_COUNT GENMASK(10, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

97

#define MT_TXD4_PN_LOW GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac2_mac.h

99

#define MT_TXD5_PN_HIGH GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

102

#define MT_PRXV_TX_RATE GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

105

#define MT_PRXV_NSTS GENMASK(10, 7)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

108

#define MT_PRXV_HE_RU_ALLOC GENMASK(30, 22)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

109

#define MT_PRXV_RCPI3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

110

#define MT_PRXV_RCPI2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

111

#define MT_PRXV_RCPI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

112

#define MT_PRXV_RCPI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

113

#define MT_PRXV_HT_SHORT_GI GENMASK(4, 3)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

114

#define MT_PRXV_HT_STBC GENMASK(10, 9)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

115

#define MT_PRXV_TX_MODE GENMASK(14, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

116

#define MT_PRXV_FRAME_MODE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

120

#define MT_CRXV_HE_NUM_USER GENMASK(26, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

121

#define MT_CRXV_HE_LTF_SIZE GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

127

#define MT_CRXV_HE_MU_AID GENMASK(27, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

131

#define MT_CRXV_HE_BSS_COLOR GENMASK(15, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

132

#define MT_CRXV_HE_TXOP_DUR GENMASK(19, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

134

#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

135

#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

136

#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

137

#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

139

#define MT_CRXV_HE_RU0 GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

140

#define MT_CRXV_HE_RU1 GENMASK(17, 9)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

141

#define MT_CRXV_HE_RU2 GENMASK(26, 18)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

142

#define MT_CRXV_HE_RU3_L GENMASK(31, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

143

#define MT_CRXV_HE_RU3_H GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

145

#define MT_CRXV_EHT_NUM_USER GENMASK(26, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

146

#define MT_CRXV_EHT_LTF_SIZE GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

150

#define MT_CRXV_EHT_MU_AID GENMASK(27, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

153

#define MT_CRXV_EHT_BSS_COLOR GENMASK(15, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

154

#define MT_CRXV_EHT_TXOP_DUR GENMASK(23, 17)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

155

#define MT_CRXV_EHT_SR_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

156

#define MT_CRXV_EHT_SR1_MASK GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

157

#define MT_CRXV_EHT_SR2_MASK GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

158

#define MT_CRXV_EHT_SR3_MASK GENMASK(23, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

159

#define MT_CRXV_EHT_RU0 GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

160

#define MT_CRXV_EHT_RU1 GENMASK(17, 9)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

161

#define MT_CRXV_EHT_RU2 GENMASK(26, 18)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

162

#define MT_CRXV_EHT_RU3_L GENMASK(31, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

163

#define MT_CRXV_EHT_RU3_H GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

164

#define MT_CRXV_EHT_SIG_MCS GENMASK(19, 18)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

165

#define MT_CRXV_EHT_LTF_SYM GENMASK(22, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

216

#define MT_TXD0_Q_IDX GENMASK(31, 25)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

217

#define MT_TXD0_PKT_FMT GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

218

#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

219

#define MT_TXD0_TX_BYTES GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

222

#define MT_TXD1_OWN_MAC GENMASK(30, 25)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

223

#define MT_TXD1_TID GENMASK(24, 21)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

226

#define MT_TXD1_HDR_INFO GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

227

#define MT_TXD1_HDR_FORMAT GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

228

#define MT_TXD1_TGID GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

229

#define MT_TXD1_WLAN_IDX GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

231

#define MT_TXD2_POWER_OFFSET GENMASK(31, 26)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

232

#define MT_TXD2_MAX_TX_TIME GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

233

#define MT_TXD2_FRAG GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

236

#define MT_TXD2_HDR_PAD GENMASK(11, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

239

#define MT_TXD2_BF_TYPE GENMASK(6, 7)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

24

#define MT_RXD0_LENGTH GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

240

#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

241

#define MT_TXD2_SUB_TYPE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

247

#define MT_TXD3_SEQ GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

248

#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

249

#define MT_TXD3_TX_COUNT GENMASK(10, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

25

#define MT_RXD0_PKT_FLAG GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

257

#define MT_TXD4_PN_LOW GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

259

#define MT_TXD5_PN_HIGH GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

26

#define MT_RXD0_PKT_TYPE GENMASK(31, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

267

#define MT_TXD5_PID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

269

#define MT_TXD6_TX_SRC GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

272

#define MT_TXD6_BW GENMASK(24, 22)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

273

#define MT_TXD6_TX_RATE GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

275

#define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

276

#define MT_TXD6_TID_ADDBA GENMASK(10, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

277

#define MT_TXD6_MSDU_CNT GENMASK(9, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

278

#define MT_TXD6_MSDU_CNT_V2 GENMASK(15, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

283

#define MT_TXD7_TXD_LEN GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

288

#define MT_TXD7_CTXD_CNT GENMASK(25, 22)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

290

#define MT_TXD7_TX_TIME GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

292

#define MT_TXD9_WLAN_IDX GENMASK(23, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

294

#define MT_TXP_BUF_LEN GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

295

#define MT_TXP_DMA_ADDR_H GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

297

#define MT_TXP0_TOKEN_ID0 GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

30

#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

300

#define MT_TXP1_TID_ADDBA GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

302

#define MT_TXP3_DMA_ADDR_H GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

305

#define MT_TX_RATE_NSS GENMASK(13, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

306

#define MT_TX_RATE_MODE GENMASK(9, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

310

#define MT_TX_RATE_IDX GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

312

#define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

313

#define MT_TXFREE0_MSDU_CNT GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

314

#define MT_TXFREE0_RX_BYTE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

316

#define MT_TXFREE1_VER GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

32

#define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

320

#define MT_TXFREE_INFO_WLAN_ID GENMASK(23, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

321

#define MT_TXFREE_INFO_MSDU_ID GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

322

#define MT_TXFREE_INFO_COUNT GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

323

#define MT_TXFREE_INFO_STAT GENMASK(29, 28)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

328

#define MT_TXS0_BW GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

329

#define MT_TXS0_TID GENMASK(28, 26)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

331

#define MT_TXS0_TXS_FORMAT GENMASK(24, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

340

#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

344

#define MT_TXS0_TX_RATE GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

346

#define MT_TXS1_SEQNO GENMASK(31, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

347

#define MT_TXS1_RESP_RATE GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

348

#define MT_TXS1_RXV_SEQNO GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

349

#define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

351

#define MT_TXS2_BF_STATUS GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

352

#define MT_TXS2_BAND GENMASK(29, 28)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

353

#define MT_TXS2_WCID GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

354

#define MT_TXS2_TX_DELAY GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

356

#define MT_TXS3_PID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

359

#define MT_TXS3_SRC GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

361

#define MT_TXS3_LAST_TX_RATE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

363

#define MT_TXS4_TIMESTAMP GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

368

#define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

369

#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

37

#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

370

#define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

371

#define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

373

#define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

374

#define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

375

#define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

376

#define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

377

#define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

378

#define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

380

#define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

381

#define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

382

#define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

383

#define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

384

#define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

385

#define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

388

#define MT_TXS5_MPDU_TX_CNT GENMASK(30, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

390

#define MT_TXS5_MPDU_TX_BYTE GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

392

#define MT_TXS6_MPDU_FAIL_CNT GENMASK(30, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

394

#define MT_TXS6_MPDU_FAIL_BYTE GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

396

#define MT_TXS7_MPDU_RETRY_CNT GENMASK(30, 20)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

398

#define MT_TXS7_MPDU_RETRY_BYTE GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

43

#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

48

#define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

54

#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

55

#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

57

#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 13)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

58

#define MT_RXD2_NORMAL_SEC_MODE GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

72

#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

73

#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

74

#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

86

#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

87

#define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

94

#define MT_RXD8_FRAME_CONTROL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

96

#define MT_RXD10_SEQ_CTRL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

97

#define MT_RXD10_QOS_CTL GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

99

#define MT_RXD11_HT_CONTROL GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1059

dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

1092

i &= GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c

352

rateidx &= GENMASK(7, 0);

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

10

#define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

1171

#define __MCU_CMD_FIELD_ID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

1172

#define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

16

#define DL_MODE_KEY_IDX GENMASK(2, 1)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

1879

#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

1880

#define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

27

#define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

28

#define PATCH_SEC_TYPE_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

31

#define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

35

#define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

36

#define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

395

#define RA_LEGACY_OFDM GENMASK(13, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

396

#define RA_LEGACY_CCK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

962

#define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

973

#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

974

#define MT_WTBL_RATE_MCS GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

975

#define MT_WTBL_RATE_NSS GENMASK(12, 10)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

976

#define MT_WTBL_RATE_HE_GI GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

977

#define MT_WTBL_RATE_GI GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

979

#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

984

#define MT_WTBL_W5_BW_CAP GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

985

#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

986

#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h

987

#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)

drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h

28

s8 ret = val & GENMASK(5, 0);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

439

coex3 &= ~GENMASK(5, 2);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

466

mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.c

467

mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1);

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

26

#define MT_RF_VCO_BP_CLOSE_LOOP_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

27

#define MT_RF_VCO_CAL_MASK GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

29

#define MT_RF_START_TIME_MASK GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

30

#define MT_RF_SETTLE_TIME_MASK GENMASK(6, 4)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

32

#define MT_RF_PLL_DEN_MASK GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

33

#define MT_RF_PLL_K_MASK GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

35

#define MT_RF_SDM_MASH_PRBS_MASK GENMASK(6, 2)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

37

#define MT_RF_ISI_ISO_MASK GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

38

#define MT_RF_PFD_DLY_MASK GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

39

#define MT_RF_CLK_SEL_MASK GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt76x0/phy.h

40

#define MT_RF_XO_DIV_MASK GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h

58

#define MT_DFS_CHECK_EVENT(x) ((x) != GENMASK(31, 0))

drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h

60

#define MT_DFS_EVENT_TIMESTAMP(x) ((x) & GENMASK(21, 0))

drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h

61

#define MT_DFS_EVENT_WIDTH(x) ((x) & GENMASK(11, 0))

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

12

#define MT_TXD_INFO_LEN GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

19

#define MT_TXD_INFO_QSEL GENMASK(26, 25)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

20

#define MT_TXD_INFO_DPORT GENMASK(29, 27)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

21

#define MT_TXD_INFO_TYPE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

23

#define MT_RX_FCE_INFO_LEN GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

25

#define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

26

#define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

28

#define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

29

#define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

30

#define MT_RX_FCE_INFO_TYPE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

33

#define MT_MCU_MSG_LEN GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

34

#define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

35

#define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

36

#define MT_MCU_MSG_PORT GENMASK(29, 27)

drivers/net/wireless/mediatek/mt76/mt76x02_dma.h

37

#define MT_MCU_MSG_TYPE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h

100

#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h

101

#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h

102

#define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h

106

#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h

116

#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.c

1111

mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0),

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

110

#define MT_TX_PWR_ADJ GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

123

#define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

124

#define MT_TXWI_FLAGS_TXOP GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

127

#define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

133

#define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

26

#define MT_PKTID_RATE GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

27

#define MT_PKTID_AC GENMASK(6, 5)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

65

#define MT_RXINFO_PN_LEN GENMASK(21, 19)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

76

#define MT_RXWI_CTL_WCID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

77

#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

78

#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

79

#define MT_RXWI_CTL_UDF GENMASK(15, 13)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

80

#define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

83

#define MT_RXWI_TID GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

84

#define MT_RXWI_SN GENMASK(15, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

86

#define MT_RXWI_RATE_INDEX GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

88

#define MT_RXWI_RATE_BW GENMASK(8, 7)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

92

#define MT_RXWI_RATE_PHY GENMASK(15, 13)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

94

#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_mac.h

95

#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

110

#define MT_INT_RX_DONE_ALL GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

111

#define MT_INT_TX_DONE_ALL GENMASK(13, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

130

#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

133

#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

142

#define MT_WMM_AIFSN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

146

#define MT_WMM_CWMIN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

150

#define MT_WMM_CWMAX_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

156

#define MT_WMM_TXOP_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

167

#define MT_US_CYC_CNT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

19

#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

199

#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

20

#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

200

#define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

201

#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

21

#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

213

#define MT_RF_CTRL_ADDR GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

22

#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

23

#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

238

#define MT_LED_STATUS_OFF GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

239

#define MT_LED_STATUS_ON GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

240

#define MT_LED_STATUS_DURATION GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

253

#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

254

#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

255

#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

277

#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

281

#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

282

#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

283

#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

287

#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

290

#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

309

#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

313

#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

314

#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

315

#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

316

#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

320

#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

321

#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

331

#define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

332

#define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

337

#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

339

#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

342

#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

348

#define MT_TBTT_TIMER_VAL GENMASK(16, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

351

#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

352

#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

382

#define MT_EDCA_CFG_TXOP GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

383

#define MT_EDCA_CFG_AIFSN GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

384

#define MT_EDCA_CFG_CWMIN GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

385

#define MT_EDCA_CFG_CWMAX GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

393

#define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

394

#define MT_TX_PIN_CFG_RXANT GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

415

#define MT_TXOP_TRUN_EN GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

416

#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

420

#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

421

#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

425

#define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

435

#define MT_PROT_CFG_RATE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

436

#define MT_PROT_CFG_CTRL GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

437

#define MT_PROT_CFG_NAV GENMASK(19, 18)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

438

#define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

448

#define MT_PROT_RATE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

465

#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

476

#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

477

#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

488

#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

489

#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

490

#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

491

#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

494

#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

497

#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

54

#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

543

#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

544

#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

545

#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

546

#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

547

#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

548

#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

55

#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

558

#define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

559

#define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

56

#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

562

#define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

563

#define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

566

#define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

567

#define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

570

#define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

571

#define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

574

#define MT_TX_STA_0_BEACONS GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

584

#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

585

#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

598

#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

599

#define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

621

#define MT_BBP_CORE_R1_BW GENMASK(4, 3)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

623

#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

624

#define MT_BBP_AGC_R0_BW GENMASK(14, 12)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

627

#define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

628

#define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

629

#define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

632

#define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

635

#define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

636

#define MT_BBP_AGC_GAIN GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

638

#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

639

#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

641

#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

658

#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

659

#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

660

#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

664

#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

677

#define MT_SKEY_MODE_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

68

#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

683

#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

71

#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

78

#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

79

#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

88

#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)

drivers/net/wireless/mediatek/mt76/mt76x02_regs.h

96

#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt76x02_util.c

305

(((vif->addr[0] ^ dev->mphy.macaddr[0]) & ~GENMASK(4, 1)) ||

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

107

mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20));

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

108

mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9));

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

83

mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

85

mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

94

mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

96

mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

149

type = (u32)mt76_get_field(dev, MT_FW_EXCEPT_TYPE, GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

150

state = (u32)mt76_get_field(dev, MT_FW_ASSERT_STAT, GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

152

(u32)mt76_get_field(dev, MT_FW_EXCEPT_COUNT, GENMASK(15, 8)) :

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

153

(u32)mt76_get_field(dev, MT_FW_EXCEPT_COUNT, GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

176

(u32)mt76_get_field(dev, base, GENMASK(7, 0)) :

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

177

(u32)mt76_get_field(dev, base, GENMASK(15, 8));

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

182

FIELD_GET(GENMASK(7, 0), irq) : FIELD_GET(GENMASK(23, 16), irq);

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

187

FIELD_GET(GENMASK(7, 0), sch) : FIELD_GET(GENMASK(15, 8), sch);

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

195

FIELD_GET(GENMASK(15, 8), sch) : FIELD_GET(GENMASK(7, 0), sch);

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

209

FIELD_GET(GENMASK(15, 8), irq) : FIELD_GET(GENMASK(7, 0), irq);

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

233

oldest = (u32)mt76_get_field(dev, 0x89050200, GENMASK(20, 16)) + 2;

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

281

(u32)mt76_get_field(dev, MT_FW_CIRQ_IDX, GENMASK(31, 16)) :

drivers/net/wireless/mediatek/mt76/mt7915/coredump.c

282

(u32)mt76_get_field(dev, MT_FW_CIRQ_IDX, GENMASK(15, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

1445

phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0);

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

832

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

834

GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

836

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

855

u8 offs = msta->wcid.idx & GENMASK(4, 0);

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

865

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

912

head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

913

tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

920

head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c

921

tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

46

#define MT_EE_WIFI_CAL_DPD GENMASK(3, 1)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

57

#define MT_EE_WIFI_CONF0_TX_PATH GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

58

#define MT_EE_WIFI_CONF0_RX_PATH GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

59

#define MT_EE_WIFI_CONF0_BAND_SEL GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

60

#define MT_EE_WIFI_CONF1_BAND_SEL GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

61

#define MT_EE_WIFI_CONF_STREAM_NUM GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

62

#define MT_EE_WIFI_CONF3_TX_PATH_B0 GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

63

#define MT_EE_WIFI_CONF3_TX_PATH_B1 GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

68

#define MT_EE_RATE_DELTA_MASK GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7915/init.c

564

GENMASK(11, 8), 4);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

566

GENMASK(11, 8), 4);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

570

GENMASK(7, 4), 1);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

572

GENMASK(11, 8), 1);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

576

GENMASK(27, 24), 3);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

578

GENMASK(31, 28), 3);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

587

GENMASK(11, 8), 4);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

591

GENMASK(11, 8), 1);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

595

GENMASK(31, 28), 3);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

604

GENMASK(11, 8), 4);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

608

GENMASK(7, 4), 1);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

612

GENMASK(27, 24), 3);

drivers/net/wireless/mediatek/mt76/mt7915/init.c

749

#define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/init.c

750

#define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1889

mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1890

mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1894

mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1895

mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1899

mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1900

mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1904

mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1905

mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1910

phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

1911

phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

221

rssi[0] = to_rssi(GENMASK(7, 0), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

222

rssi[1] = to_rssi(GENMASK(15, 8), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

223

rssi[2] = to_rssi(GENMASK(23, 16), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

224

rssi[3] = to_rssi(GENMASK(31, 14), val);

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

10

#define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

12

#define MT_TX_FREE_COUNT GENMASK(12, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

13

#define MT_TX_FREE_COUNT_V3 GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

14

#define MT_TX_FREE_STAT GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

15

#define MT_TX_FREE_STAT_V3 GENMASK(29, 28)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

18

#define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

22

#define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

23

#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

24

#define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

25

#define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

27

#define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

28

#define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

29

#define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

30

#define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

31

#define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

32

#define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

34

#define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

35

#define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

36

#define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

37

#define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

38

#define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

39

#define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mac.h

9

#define MT_TX_FREE_VER GENMASK(18, 16)

drivers/net/wireless/mediatek/mt76/mt7915/main.c

139

return ffs(~mask & GENMASK(end, start));

drivers/net/wireless/mediatek/mt76/mt7915/main.c

194

mvif->bitrate_mask.control[i].legacy = GENMASK(31, 0);

drivers/net/wireless/mediatek/mt76/mt7915/main.c

837

mt76_rmw_field(dev, addr, GENMASK(7, 0), 0xa0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

125

mcs = GENMASK(9, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

128

mcs = GENMASK(8, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

131

mcs = GENMASK(7, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1493

mask->control[band].he_gi == GENMASK(7, 0) &&

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1494

mask->control[band].he_ltf == GENMASK(7, 0) &&

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1508

mask->control[band].he_gi != GENMASK(7, 0)) {

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1518

mt76_rmw_field(dev, addr, GENMASK(31, 24), phy.sgi);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1520

mt76_rmw_field(dev, addr, GENMASK(15, 12), phy.sgi);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1529

if (mask->control[band].he_ltf != GENMASK(7, 0)) {

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1570

ra->supp_cck_rate = supp_rate & GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

2838

#define MAX_PAGE_IDX_MASK GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

2839

#define PAGE_IDX_MASK GENMASK(4, 2)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

3655

req.mod.bf_bitmap = GENMASK(1, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

4106

.idx = cpu_to_le32(u32_get_bits(regidx, GENMASK(31, 24))),

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

4107

.ofs = cpu_to_le32(u32_get_bits(regidx, GENMASK(23, 0))),

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

618

#define TXD_CMP_MAP1 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

619

#define TXD_CMP_MAP2 (GENMASK(31, 0) & ~BIT(23))

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

72

mcs = GENMASK(11, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

75

mcs = GENMASK(9, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

78

mcs = GENMASK(7, 0);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

254

#define WMM_PARAM_SET GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

421

#define RATE_CFG_MCS GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

422

#define RATE_CFG_NSS GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

423

#define RATE_CFG_GI GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

424

#define RATE_CFG_BW GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

425

#define RATE_CFG_STBC GENMASK(19, 16)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

426

#define RATE_CFG_LDPC GENMASK(23, 20)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

427

#define RATE_CFG_PHY_TYPE GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt7915/mcu.h

428

#define RATE_CFG_HE_LTF GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1006

#define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1007

#define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1015

#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1078

#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1079

#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1083

#define MT_LED_STATUS_OFF GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1084

#define MT_LED_STATUS_ON GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1085

#define MT_LED_STATUS_DURATION GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1107

#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1113

#define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1116

#define MT_TOP_WF_AP_PERI_BASE_MASK GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1119

#define MT_TOP_EFUSE_BASE_MASK GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1140

#define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1172

#define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1210

#define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1211

#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

1220

#define MT_WF_PHY_TPC_POWER GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

179

#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

186

#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

187

#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

188

#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

192

#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

193

#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

194

#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

203

#define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

204

#define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

211

#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

216

#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

217

#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

220

#define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

223

#define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

224

#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

227

#define MT_IFS_EIFS_OFDM GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

228

#define MT_IFS_RIFS GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

229

#define MT_IFS_SIFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

230

#define MT_IFS_SLOT GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

233

#define MT_IFS_EIFS_CCK GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

236

#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

247

#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

255

#define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

256

#define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

266

#define MT_ETBF_TX_FB_CPL GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

267

#define MT_ETBF_TX_FB_TRI GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

270

#define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

271

#define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

272

#define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

275

#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

276

#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

279

#define MT_ETBF_RX_FB_ALL GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

280

#define MT_ETBF_RX_FB_HE GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

281

#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

282

#define MT_ETBF_RX_FB_HT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

296

#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

299

#define MT_LPON_TCR_SW_READ GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

312

#define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

315

#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

316

#define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

319

#define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

325

#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

328

#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

331

#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

335

#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

338

#define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

339

#define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

342

#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

348

#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

352

#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

353

#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

357

#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

358

#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

362

#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

365

#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

368

#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

372

#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

375

#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

378

#define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

388

#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

389

#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

396

#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

399

#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

402

#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

403

#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

406

#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

407

#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

413

#define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

414

#define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

417

#define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

420

#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

429

#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

430

#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

433

#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

434

#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

445

#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

448

#define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

449

#define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

452

#define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

455

#define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

458

#define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

464

#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

467

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

473

#define MT_WTBL_LMAC_ID GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

474

#define MT_WTBL_LMAC_DW GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

492

#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

496

#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

497

#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

500

#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

501

#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

507

#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

509

#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

510

#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

568

#define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

569

#define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

572

#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

575

#define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

578

#define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

646

#define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

647

#define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

648

#define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

654

#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

767

#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

771

#define MT_MCU_CMD_WDT_MASK GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

778

#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

787

#define MT_TOP_PWR_KEY_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

795

#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

796

#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

797

#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

801

#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

802

#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

803

#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

805

#define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

806

#define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

807

#define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

835

#define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

861

#define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

862

#define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

863

FIELD_PREP(GENMASK(14, 0), 0x7e4))

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

864

#define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

865

#define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

866

#define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

867

#define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

877

#define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

899

#define MT_ADIE_VERSION_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

900

#define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

901

#define MT_ADIE_IDX0 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

902

#define MT_ADIE_IDX1 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

905

#define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

906

#define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

909

#define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

910

#define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

911

#define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

912

#define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

921

#define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

922

#define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

932

#define MT_ADIE_TRIM_MASK GENMASK(6, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

933

#define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

964

#define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

965

#define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12)

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

998

#define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

33

#define MT_TOP_POS_SKU_MASK GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

472

mode = FIELD_PREP(GENMASK(6, 4), val);

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

475

GENMASK(31, 24),

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

476

FIELD_PREP(GENMASK(31, 24), trim_80m));

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

481

GENMASK(31, 24),

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

482

FIELD_PREP(GENMASK(31, 24), trim_80m));

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

485

GENMASK(23, 16),

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

486

FIELD_PREP(GENMASK(23, 16), trim_40m));

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

491

GENMASK(23, 16),

drivers/net/wireless/mediatek/mt76/mt7915/soc.c

492

FIELD_PREP(GENMASK(23, 16), trim_40m));

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

155

rssi[0] = to_rssi(GENMASK(7, 0), val);

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

156

rssi[1] = to_rssi(GENMASK(15, 8), val);

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

157

rssi[2] = to_rssi(GENMASK(23, 16), val);

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

158

rssi[3] = to_rssi(GENMASK(31, 14), val);

drivers/net/wireless/mediatek/mt76/mt7921/mcu.h

47

#define MT_RA_RATE_NSS GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7921/mcu.h

48

#define MT_RA_RATE_MCS GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7921/mcu.h

49

#define MT_RA_RATE_TX_MODE GENMASK(12, 9)

drivers/net/wireless/mediatek/mt76/mt7921/mcu.h

51

#define MT_RA_RATE_BW GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

17

#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

20

#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

21

#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

22

#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

25

#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

26

#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

27

#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

59

GENMASK(18, 4))

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

67

#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

68

#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

69

#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

75

#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

78

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)

drivers/net/wireless/mediatek/mt76/mt7925/init.c

73

FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

128

rate->eht_gi = FIELD_GET(GENMASK(25, 24), val);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

145

rssi[0] = to_rssi(GENMASK(7, 0), val);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

146

rssi[1] = to_rssi(GENMASK(15, 8), val);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

147

rssi[2] = to_rssi(GENMASK(23, 16), val);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

148

rssi[3] = to_rssi(GENMASK(31, 14), val);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

301

i &= GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

313

i &= GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7925/main.c

191

u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),

drivers/net/wireless/mediatek/mt76/mt7925/main.c

217

u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)),

drivers/net/wireless/mediatek/mt76/mt7925/main.c

223

u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)),

drivers/net/wireless/mediatek/mt76/mt7925/main.c

837

if ((mt76_rates[i].hw_value & GENMASK(7, 0)) == idx)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

1905

eht_mld->eml_cap[0] = u16_get_bits(eml_cap, GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

1906

eht_mld->eml_cap[1] = u16_get_bits(eml_cap, GENMASK(15, 8));

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

59

#define MT_RF_REG_HDR GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

60

#define MT_RF_REG_ANT GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.h

20

#define MT_RA_RATE_NSS GENMASK(8, 6)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.h

21

#define MT_RA_RATE_MCS GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.h

22

#define MT_RA_RATE_TX_MODE GENMASK(12, 9)

drivers/net/wireless/mediatek/mt76/mt7925/mcu.h

24

#define MT_RA_RATE_BW GENMASK(14, 13)

drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h

199

#define MT_EE_HW_TYPE_ENCAP GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

17

#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

20

#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

21

#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

22

#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

25

#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

26

#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

27

#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

63

GENMASK(18, 4))

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

71

#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

72

#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

73

#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

86

#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7925/regs.h

89

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt792x.h

54

#define MT792x_SDIO_HDR_TX_BYTES GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x.h

55

#define MT792x_SDIO_HDR_PKT_TYPE GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt792x_debugfs.c

87

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

103

#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

108

#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

115

#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

122

#define MT_MIB_SDR9_IBF_CNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

123

#define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

126

#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

129

#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

131

#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

138

#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

141

#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

143

#define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

145

#define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

147

#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

150

#define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

155

#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

170

#define MT_WTBL_LMAC_ID GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

171

#define MT_WTBL_LMAC_DW GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

187

#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

191

#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

192

#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

195

#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

196

#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

199

#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

201

#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

202

#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

256

#define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

279

#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

295

#define MT_WFDMA0_GLO_CFG_DMA_SIZE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

345

#define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

346

#define MT_WPDMA0_BASE_PTR_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

37

#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

38

#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

381

#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

41

#define MT_IFS_EIFS GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

413

#define MT_DMASHDL_REFILL_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

415

#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

416

#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

419

#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

42

#define MT_IFS_RIFS GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

420

#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

423

#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

43

#define MT_IFS_SIFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

436

#define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

437

#define MT_WL_TX_TMOUT_LMT GENMASK(27, 8)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

44

#define MT_IFS_SLOT GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

440

#define MT_WL_RX_AGG_TO GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

441

#define MT_WL_RX_AGG_LMT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

47

#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

477

#define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

58

#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

66

#define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

67

#define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

77

#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

85

#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

86

#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

89

#define MT_ETBF_RX_FB_ALL GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

90

#define MT_ETBF_RX_FB_HE GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

91

#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt792x_regs.h

92

#define MT_ETBF_RX_FB_HT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt792x_usb.c

203

val |= GENMASK(9, 4) | GENMASK(22, 20);

drivers/net/wireless/mediatek/mt76/mt792x_usb.c

205

val &= ~(GENMASK(9, 4) | GENMASK(22, 20));

drivers/net/wireless/mediatek/mt76/mt7996/coredump.c

140

GENMASK(20, 16)) + 2;

drivers/net/wireless/mediatek/mt76/mt7996/coredump.c

148

GENMASK(20, 16)) + 2;

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

612

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

614

GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

616

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

654

u8 offs = msta_link->wcid.idx & GENMASK(4, 0);

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

665

GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

715

head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

716

tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

723

head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));

drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c

724

tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c

225

#define WTBL_SIZE_GROUP GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

28

#define MT_EE_WIFI_CONF0_TX_PATH GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

29

#define MT_EE_WIFI_CONF0_BAND_SEL GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

30

#define MT_EE_WIFI_CONF1_BAND_SEL GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

31

#define MT_EE_WIFI_CONF2_BAND_SEL GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

33

#define MT_EE_WIFI_CONF1_TX_PATH_BAND0 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

34

#define MT_EE_WIFI_CONF2_TX_PATH_BAND1 GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

35

#define MT_EE_WIFI_CONF2_TX_PATH_BAND2 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

36

#define MT_EE_WIFI_CONF3_RX_PATH_BAND0 GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

37

#define MT_EE_WIFI_CONF3_RX_PATH_BAND1 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

38

#define MT_EE_WIFI_CONF4_RX_PATH_BAND2 GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

39

#define MT_EE_WIFI_CONF4_STREAM_NUM_BAND0 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

40

#define MT_EE_WIFI_CONF5_STREAM_NUM_BAND1 GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

41

#define MT_EE_WIFI_CONF5_STREAM_NUM_BAND2 GENMASK(5, 3)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

43

#define MT_EE_WIFI_PA_LNA_CONFIG GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h

45

#define MT_EE_RATE_DELTA_MASK GENMASK(5, 0)

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1525

u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),

drivers/net/wireless/mediatek/mt76/mt7996/init.c

1568

u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),

drivers/net/wireless/mediatek/mt76/mt7996/init.c

587

FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

1892

#define MT996_RRO_SN_MASK GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

205

rssi[0] = to_rssi(GENMASK(7, 0), val);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

206

rssi[1] = to_rssi(GENMASK(15, 8), val);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

207

rssi[2] = to_rssi(GENMASK(23, 16), val);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

208

rssi[3] = to_rssi(GENMASK(31, 14), val);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

365

i &= GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

377

i &= GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7996/main.c

174

mlink->bitrate_mask.control[i].legacy = GENMASK(31, 0);

drivers/net/wireless/mediatek/mt76/mt7996/main.c

775

if ((mt76_rates[i].hw_value & GENMASK(7, 0)) == idx)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

137

mcs = GENMASK(11, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

140

mcs = GENMASK(9, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

143

mcs = GENMASK(7, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

182

mcs = GENMASK(9, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

185

mcs = GENMASK(8, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

188

mcs = GENMASK(7, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2118

mask.control[band].he_gi == GENMASK(7, 0) &&

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2119

mask.control[band].he_ltf == GENMASK(7, 0) &&

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2133

mask.control[band].he_gi != GENMASK(7, 0)) {

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2142

mt76_rmw_field(dev, addr, GENMASK(31, 24), phy.sgi);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2144

mt76_rmw_field(dev, addr, GENMASK(15, 12), phy.sgi);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2153

if (mask.control[band].he_ltf != GENMASK(7, 0)) {

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2203

ra->supp_cck_rate = supp_rate & GENMASK(3, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

2934

if (key_info == GENMASK(31, 0) || sec == MT7996_SEC_MODE_PLAIN)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

3767

#define MAX_PAGE_IDX_MASK GENMASK(7, 5)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

3768

#define PAGE_IDX_MASK GENMASK(4, 2)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

4227

GENMASK(2, 0) : GENMASK(1, 0);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

4648

.idx = cpu_to_le16(u32_get_bits(regidx, GENMASK(31, 24))),

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

4649

.ofs = cpu_to_le32(u32_get_bits(regidx, GENMASK(23, 0))),

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

946

#define MT7996_PATCH_SEC GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

947

#define MT7996_PATCH_SCRAMBLE_KEY GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

948

#define MT7996_PATCH_AES_KEY GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

951

#define MT7996_SEC_KEY_IDX GENMASK(2, 1)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

296

#define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

297

#define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

298

#define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

319

#define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

321

#define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

332

#define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

104

#define MT_RRO_PARTICULAR_SID GENMASK(30, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

127

#define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

128

#define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

131

#define MT_RRO_DBG_RD_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

170

#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

174

#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

175

#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

178

#define MT_IFS_EIFS_OFDM GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

179

#define MT_IFS_RIFS GENMASK(14, 10)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

180

#define MT_IFS_SIFS GENMASK(22, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

181

#define MT_IFS_SLOT GENMASK(30, 24)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

184

#define MT_IFS_EIFS_CCK GENMASK(8, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

194

#define MT_DMA_TCRF1_QIDX GENMASK(15, 13)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

201

#define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

202

#define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

212

#define MT_ETBF_RX_FB_BW GENMASK(10, 8)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

213

#define MT_ETBF_RX_FB_NC GENMASK(7, 4)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

214

#define MT_ETBF_RX_FB_NR GENMASK(3, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

225

#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

228

#define MT_LPON_TCR_SW_READ GENMASK(1, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

260

#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

291

#define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

294

#define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

309

#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

321

#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

324

#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

337

#define MT_WTBL_LMAC_ID GENMASK(14, 8)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

338

#define MT_WTBL_LMAC_DW GENMASK(7, 2)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

393

#define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

394

#define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

397

#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

400

#define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

403

#define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

413

#define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

450

#define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

480

#define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

483

#define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

486

#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

615

#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

619

#define MT_MCU_CMD_WDT_MASK GENMASK(31, 30)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

624

#define MT_HIF_REMAP_L1_MASK_7996 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

625

#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

626

#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

627

#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

631

#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

632

#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

633

#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

634

#define MT_HIF_REMAP_L2_MASK_7990 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

635

#define MT_HIF_REMAP_L2_OFFSET_7990 GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

636

#define MT_HIF_REMAP_L2_BASE_7990 GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

641

#define MT_HIF_REMAP_CBTOP_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

642

#define MT_HIF_REMAP_CBTOP_OFFSET GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

643

#define MT_HIF_REMAP_CBTOP_BASE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

690

#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

691

#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

704

#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

719

#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

723

#define MT_ADIE_VERSION_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

724

#define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

727

#define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

730

#define MT_PAD_GPIO_ADIE_COMB_7992 GENMASK(17, 16)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

768

#define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

769

#define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9)

drivers/net/wireless/mediatek/mt76/sdio.h

105

#define TXQ_CNT_L GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/sdio.h

106

#define TXQ_CNT_H GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/sdio.h

27

#define MAX_HIF_RX_LEN_NUM GENMASK(13, 8)

drivers/net/wireless/mediatek/mt76/sdio.h

28

#define MAX_HIF_RX_LEN_NUM_CONNAC2 GENMASK(14, 8) /* supported in CONNAC2 */

drivers/net/wireless/mediatek/mt76/sdio.h

34

#define WHIER_D2H_SW_INT GENMASK(31, 8)

drivers/net/wireless/mediatek/mt76/sdio.h

50

#define TQ0_CNT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/sdio.h

51

#define TQ1_CNT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/sdio.h

52

#define TQ2_CNT GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/sdio.h

53

#define TQ3_CNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/sdio.h

56

#define TQ4_CNT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt76/sdio.h

57

#define TQ5_CNT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt76/sdio.h

58

#define TQ6_CNT GENMASK(23, 16)

drivers/net/wireless/mediatek/mt76/sdio.h

59

#define TQ7_CNT GENMASK(31, 24)

drivers/net/wireless/mediatek/mt76/sdio.h

75

#define RX0_PACKET_LENGTH GENMASK(15, 0)

drivers/net/wireless/mediatek/mt76/sdio.h

76

#define RX1_PACKET_LENGTH GENMASK(31, 16)

drivers/net/wireless/mediatek/mt76/sdio_txrx.c

129

len = le32_get_bits(rxd[0], GENMASK(15, 0));

drivers/net/wireless/mediatek/mt7601u/dma.h

100

#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)

drivers/net/wireless/mediatek/mt7601u/dma.h

104

#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)

drivers/net/wireless/mediatek/mt7601u/dma.h

105

#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)

drivers/net/wireless/mediatek/mt7601u/dma.h

19

#define MT_TXD_INFO_LEN GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/dma.h

20

#define MT_TXD_INFO_D_PORT GENMASK(29, 27)

drivers/net/wireless/mediatek/mt7601u/dma.h

21

#define MT_TXD_INFO_TYPE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt7601u/dma.h

45

#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)

drivers/net/wireless/mediatek/mt7601u/dma.h

55

#define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)

drivers/net/wireless/mediatek/mt7601u/dma.h

56

#define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)

drivers/net/wireless/mediatek/mt7601u/dma.h

88

#define MT_RXD_INFO_LEN GENMASK(13, 0)

drivers/net/wireless/mediatek/mt7601u/dma.h

90

#define MT_RXD_INFO_QSEL GENMASK(26, 25)

drivers/net/wireless/mediatek/mt7601u/dma.h

91

#define MT_RXD_INFO_PORT GENMASK(29, 27)

drivers/net/wireless/mediatek/mt7601u/dma.h

92

#define MT_RXD_INFO_TYPE GENMASK(31, 30)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

118

WARN_ON(reg & ~GENMASK(5, 0));

drivers/net/wireless/mediatek/mt7601u/eeprom.h

119

return reg & GENMASK(5, 0);

drivers/net/wireless/mediatek/mt7601u/eeprom.h

47

#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

48

#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

49

#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

57

#define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

58

#define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

60

#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)

drivers/net/wireless/mediatek/mt7601u/eeprom.h

62

#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)

drivers/net/wireless/mediatek/mt7601u/mac.h

131

#define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5)

drivers/net/wireless/mediatek/mt7601u/mac.h

132

#define MT_TXWI_FLAGS_TXOP GENMASK(9, 8)

drivers/net/wireless/mediatek/mt7601u/mac.h

133

#define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10)

drivers/net/wireless/mediatek/mt7601u/mac.h

138

#define MT_TXWI_RATE_MCS GENMASK(6, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

141

#define MT_TXWI_RATE_STBC GENMASK(10, 9)

drivers/net/wireless/mediatek/mt7601u/mac.h

142

#define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14)

drivers/net/wireless/mediatek/mt7601u/mac.h

146

#define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2)

drivers/net/wireless/mediatek/mt7601u/mac.h

148

#define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

149

#define MT_TXWI_LEN_PKTID GENMASK(15, 12)

drivers/net/wireless/mediatek/mt7601u/mac.h

151

#define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

65

#define MT_RXINFO_PN_LEN GENMASK(21, 19)

drivers/net/wireless/mediatek/mt7601u/mac.h

72

#define MT_RXWI_CTL_WCID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

73

#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)

drivers/net/wireless/mediatek/mt7601u/mac.h

74

#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)

drivers/net/wireless/mediatek/mt7601u/mac.h

75

#define MT_RXWI_CTL_UDF GENMASK(15, 13)

drivers/net/wireless/mediatek/mt7601u/mac.h

76

#define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16)

drivers/net/wireless/mediatek/mt7601u/mac.h

77

#define MT_RXWI_CTL_TID GENMASK(31, 28)

drivers/net/wireless/mediatek/mt7601u/mac.h

79

#define MT_RXWI_FRAG GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

80

#define MT_RXWI_SN GENMASK(15, 4)

drivers/net/wireless/mediatek/mt7601u/mac.h

82

#define MT_RXWI_RATE_MCS GENMASK(6, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

85

#define MT_RXWI_RATE_STBC GENMASK(10, 9)

drivers/net/wireless/mediatek/mt7601u/mac.h

89

#define MT_RXWI_RATE_PHY GENMASK(15, 14)

drivers/net/wireless/mediatek/mt7601u/mac.h

91

#define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/mac.h

92

#define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6)

drivers/net/wireless/mediatek/mt7601u/mac.h

95

#define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/phy.c

467

#define BBP_R47_FLAG GENMASK(2, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

108

#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)

drivers/net/wireless/mediatek/mt7601u/regs.h

111

#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

120

#define MT_WMM_AIFSN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

124

#define MT_WMM_CWMIN_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

128

#define MT_WMM_CWMAX_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

134

#define MT_WMM_TXOP_MASK GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

140

#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

141

#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

149

#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27)

drivers/net/wireless/mediatek/mt7601u/regs.h

157

#define MT_US_CYC_CNT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

191

#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

192

#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

193

#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)

drivers/net/wireless/mediatek/mt7601u/regs.h

204

#define MT_RF_CTRL_ADDR GENMASK(11, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

22

#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

222

#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

223

#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

224

#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)

drivers/net/wireless/mediatek/mt7601u/regs.h

23

#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)

drivers/net/wireless/mediatek/mt7601u/regs.h

24

#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

248

#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

25

#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)

drivers/net/wireless/mediatek/mt7601u/regs.h

252

#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

253

#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

254

#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)

drivers/net/wireless/mediatek/mt7601u/regs.h

258

#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)

drivers/net/wireless/mediatek/mt7601u/regs.h

26

#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

261

#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)

drivers/net/wireless/mediatek/mt7601u/regs.h

264

#define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

265

#define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

286

#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

290

#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

291

#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

292

#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

293

#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)

drivers/net/wireless/mediatek/mt7601u/regs.h

297

#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

298

#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

301

#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

303

#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)

drivers/net/wireless/mediatek/mt7601u/regs.h

306

#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)

drivers/net/wireless/mediatek/mt7601u/regs.h

312

#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

313

#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

338

#define MT_EDCA_CFG_TXOP GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

339

#define MT_EDCA_CFG_AIFSN GENMASK(11, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

340

#define MT_EDCA_CFG_CWMIN GENMASK(15, 12)

drivers/net/wireless/mediatek/mt7601u/regs.h

341

#define MT_EDCA_CFG_CWMAX GENMASK(19, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

366

#define MT_TXOP_TRUN_EN GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

367

#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

371

#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

372

#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

390

#define MT_PROT_RATE GENMASK(15, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

406

#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)

drivers/net/wireless/mediatek/mt7601u/regs.h

417

#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

418

#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

428

#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

429

#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

430

#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

431

#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)

drivers/net/wireless/mediatek/mt7601u/regs.h

434

#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

437

#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

480

#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

481

#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)

drivers/net/wireless/mediatek/mt7601u/regs.h

482

#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)

drivers/net/wireless/mediatek/mt7601u/regs.h

483

#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)

drivers/net/wireless/mediatek/mt7601u/regs.h

484

#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

485

#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)

drivers/net/wireless/mediatek/mt7601u/regs.h

512

#define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1)

drivers/net/wireless/mediatek/mt7601u/regs.h

516

#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

517

#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

52

#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */

drivers/net/wireless/mediatek/mt7601u/regs.h

53

#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */

drivers/net/wireless/mediatek/mt7601u/regs.h

532

#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

54

#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */

drivers/net/wireless/mediatek/mt7601u/regs.h

551

#define MT_BBP_CORE_R1_BW GENMASK(4, 3)

drivers/net/wireless/mediatek/mt7601u/regs.h

553

#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

554

#define MT_BBP_AGC_R0_BW GENMASK(14, 12)

drivers/net/wireless/mediatek/mt7601u/regs.h

557

#define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

560

#define MT_BBP_AGC_GAIN GENMASK(14, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

562

#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

563

#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

565

#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

582

#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)

drivers/net/wireless/mediatek/mt7601u/regs.h

583

#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)

drivers/net/wireless/mediatek/mt7601u/regs.h

584

#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)

drivers/net/wireless/mediatek/mt7601u/regs.h

588

#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)

drivers/net/wireless/mediatek/mt7601u/regs.h

607

#define MT_SKEY_MODE_MASK GENMASK(3, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

613

#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

63

#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

66

#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)

drivers/net/wireless/mediatek/mt7601u/regs.h

74

#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)

drivers/net/wireless/mediatek/mt7601u/regs.h

88

#define MT_INT_RX_DONE_ALL GENMASK(1, 0)

drivers/net/wireless/mediatek/mt7601u/regs.h

89

#define MT_INT_TX_DONE_ALL GENMASK(13, 4)

drivers/net/wireless/microchip/wilc1000/spi.c

83

#define RSP_START_FIELD GENMASK(7, 4)

drivers/net/wireless/microchip/wilc1000/spi.c

84

#define RSP_TYPE_FIELD GENMASK(3, 0)

drivers/net/wireless/microchip/wilc1000/spi.c

93

#define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4)

drivers/net/wireless/microchip/wilc1000/spi.c

94

#define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3)

drivers/net/wireless/microchip/wilc1000/spi.c

95

#define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2)

drivers/net/wireless/microchip/wilc1000/wlan.c

1721

wl->nv_mac_address[0] = FIELD_GET(GENMASK(23, 16), reg1);

drivers/net/wireless/microchip/wilc1000/wlan.c

1722

wl->nv_mac_address[1] = FIELD_GET(GENMASK(15, 8), reg1);

drivers/net/wireless/microchip/wilc1000/wlan.c

1723

wl->nv_mac_address[2] = FIELD_GET(GENMASK(7, 0), reg1);

drivers/net/wireless/microchip/wilc1000/wlan.c

1724

wl->nv_mac_address[3] = FIELD_GET(GENMASK(31, 24), reg2);

drivers/net/wireless/microchip/wilc1000/wlan.c

1725

wl->nv_mac_address[4] = FIELD_GET(GENMASK(23, 16), reg2);

drivers/net/wireless/microchip/wilc1000/wlan.c

1726

wl->nv_mac_address[5] = FIELD_GET(GENMASK(15, 8), reg2);

drivers/net/wireless/microchip/wilc1000/wlan.h

222

#define WILC_CHIP_REV_FIELD GENMASK(11, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

248

#define VO_AC_COUNT_FIELD GENMASK(31, 25)

drivers/net/wireless/microchip/wilc1000/wlan.h

250

#define VI_AC_COUNT_FIELD GENMASK(23, 17)

drivers/net/wireless/microchip/wilc1000/wlan.h

252

#define BE_AC_COUNT_FIELD GENMASK(15, 9)

drivers/net/wireless/microchip/wilc1000/wlan.h

254

#define BK_AC_COUNT_FIELD GENMASK(7, 3)

drivers/net/wireless/microchip/wilc1000/wlan.h

258

#define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22)

drivers/net/wireless/microchip/wilc1000/wlan.h

259

#define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11)

drivers/net/wireless/microchip/wilc1000/wlan.h

260

#define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

262

#define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

264

#define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

268

#define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15)

drivers/net/wireless/microchip/wilc1000/wlan.h

269

#define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

271

#define WILC_VMM_ENTRY_COUNT GENMASK(8, 3)

drivers/net/wireless/microchip/wilc1000/wlan.h

288

#define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)

drivers/net/wireless/microchip/wilc1000/wlan.h

296

#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \

drivers/net/wireless/microchip/wilc1000/wlan.h

325

#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)

drivers/net/wireless/microchip/wilc1000/wlan.h

339

#define WILC_WID_TYPE GENMASK(15, 12)

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

1647

#define XTAL1 GENMASK(22, 17)

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

1648

#define XTAL0 GENMASK(16, 11)

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

433

val32 |= GENMASK(28, 24);

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

448

val32 &= GENMASK(5, 3);

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

545

val32 |= GENMASK(10, 8);

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

556

val32 &= ~GENMASK(31, 30);

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

576

val32 &= ~GENMASK(23, 20);

drivers/net/wireless/realtek/rtl8xxxu/8188f.c

603

val32 &= ~GENMASK(3, 0);

drivers/net/wireless/realtek/rtl8xxxu/8192f.c

1937

#define XTAL1 GENMASK(6, 1)

drivers/net/wireless/realtek/rtl8xxxu/8192f.c

1938

#define XTAL0 GENMASK(30, 25)

drivers/net/wireless/realtek/rtl8xxxu/8192f.c

620

rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30));

drivers/net/wireless/realtek/rtl8xxxu/8192f.c

626

rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

1523

val32 &= ~GENMASK(26, 24);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

1528

val32 &= ~GENMASK(17, 16);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

1758

#define XTAL1 GENMASK(29, 24)

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

1759

#define XTAL0 GENMASK(23, 18)

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

732

val32 |= GENMASK(10, 8);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

743

val32 &= ~GENMASK(31, 30);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

769

val32 &= ~GENMASK(23, 20);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

773

val32 &= ~GENMASK(27, 24);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

787

val32 &= ~GENMASK(23, 20);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

792

val32 &= ~GENMASK(27, 24);

drivers/net/wireless/realtek/rtl8xxxu/8710b.c

966

val32 |= GENMASK(17, 16) | GENMASK(26, 24);

drivers/net/wireless/realtek/rtl8xxxu/8723a.c

527

#define XTAL1 GENMASK(23, 18)

drivers/net/wireless/realtek/rtl8xxxu/8723a.c

528

#define XTAL0 GENMASK(17, 12)

drivers/net/wireless/realtek/rtl8xxxu/regs.h

150

#define LEDCFG0_LED0CM GENMASK(2, 0)

drivers/net/wireless/realtek/rtl8xxxu/regs.h

151

#define LEDCFG0_LED1CM GENMASK(10, 8)

drivers/net/wireless/realtek/rtl8xxxu/regs.h

518

#define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */

drivers/net/wireless/realtek/rtl8xxxu/regs.h

519

#define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

555

#define TXDESC32_PT_STAGE_MASK GENMASK(17, 15)

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

601

#define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5)

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

602

#define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtlwifi/base.h

66

le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(11, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h

179

u8p_replace_bits(__cmd + 1, __value, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h

184

u8p_replace_bits(__cmd + 1, __value, GENMASK(7, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

109

le32p_replace_bits(__pdesc + 2, __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

124

le32p_replace_bits(__pdesc + 3, __val, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

134

le32p_replace_bits(__pdesc + 4, __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

169

le32p_replace_bits(__pdesc + 4, __val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

174

le32p_replace_bits(__pdesc + 4, __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

19

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

194

le32p_replace_bits(__pdesc + 4, __val, GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

199

le32p_replace_bits(__pdesc + 4, __val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

204

le32p_replace_bits(__pdesc + 5, __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

214

le32p_replace_bits(__pdesc + 5, __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

219

le32p_replace_bits(__pdesc + 5, __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

224

le32p_replace_bits(__pdesc + 6, __val, GENMASK(15, 11));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

234

le32p_replace_bits(__pdesc + 7, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

239

return le32_get_bits(*(__pdesc + 7), GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

24

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

259

return le32_get_bits(*(__pdesc), GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

274

return le32_get_bits(*(__pdesc), GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

279

return le32_get_bits(*(__pdesc), GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

289

return le32_get_bits(*(__pdesc), GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

324

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

339

return le32_get_bits(*(__pdesc + 1), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

354

return le32_get_bits(*(__pdesc + 1), GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

359

return le32_get_bits(*(__pdesc + 1), GENMASK(23, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

384

return le32_get_bits(*(__pdesc + 1), GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

399

return le32_get_bits(*(__pdesc + 2), GENMASK(11, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

404

return le32_get_bits(*(__pdesc + 2), GENMASK(15, 12));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

409

return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

444

return le32_get_bits(*(__pdesc + 3), GENMASK(13, 12));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

449

return le32_get_bits(*(__pdesc + 3), GENMASK(15, 14));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

501

return le32_get_bits(*(__status), GENMASK(8, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

516

le32p_replace_bits(__paddr, __value, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

521

le32p_replace_bits(__paddr, __value, GENMASK(15, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

526

le32p_replace_bits(__paddr, __value, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

531

le32p_replace_bits(__paddr, __value, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

536

le32p_replace_bits(__paddr + 1, __value, GENMASK(7, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

541

le32p_replace_bits(__paddr + 1, __value, GENMASK(19, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

546

le32p_replace_bits(__paddr + 1, __value, GENMASK(31, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

64

le32p_replace_bits(__pdesc + 1, __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

69

le32p_replace_bits(__pdesc + 1, __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

74

le32p_replace_bits(__pdesc + 1, __val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

84

le32p_replace_bits(__pdesc + 1, __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h

89

le32p_replace_bits(__pdesc + 1, __val, GENMASK(30, 26));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

101

le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

106

le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

111

le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

116

le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

156

le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

176

le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

181

le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

186

le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

196

le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

201

le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

206

le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

21

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

211

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

231

return le32_get_bits(*(__pdesc), GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

246

return le32_get_bits(*(__pdesc), GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

251

return le32_get_bits(*(__pdesc), GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

26

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

271

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

296

return le32_get_bits(*((__pdesc + 3)), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

66

le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

81

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

86

le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h

91

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

124

return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

157

le32p_replace_bits(__txdesc, __value, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

162

le32p_replace_bits(__txdesc, __value, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

199

le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

219

le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

224

le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

234

le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

239

le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

251

le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

258

le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

263

le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

270

le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

310

le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

330

le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

335

le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

342

le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

352

le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

357

le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

364

le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

371

le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

75

return le32_get_bits(*__rxdesc, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

90

return le32_get_bits(*__rxdesc, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h

95

return le32_get_bits(*__rxdesc, GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

22

le32_get_bits(*(__le32 *)__fwhdr, GENMASK(15, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

24

le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(15, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

26

le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16))

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

28

#define RAID_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

29

#define RATE_MASK_MASK GENMASK(27, 0)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h

31

#define MACID_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

950

#define TXDMA_HIQ_MAP GENMASK(15, 14)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

951

#define TXDMA_MGQ_MAP GENMASK(13, 12)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

952

#define TXDMA_BKQ_MAP GENMASK(11, 10)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

953

#define TXDMA_BEQ_MAP GENMASK(9, 8)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

954

#define TXDMA_VIQ_MAP GENMASK(7, 6)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

955

#define TXDMA_VOQ_MAP GENMASK(5, 4)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

961

#define HPQ_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

962

#define LPQ_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h

963

#define PUBQ_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

102

le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

107

le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

112

le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

117

le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

157

le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

177

le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

182

le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

187

le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

197

le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

202

le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

207

le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

212

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

22

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

232

return le32_get_bits(*__pdesc, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

247

return le32_get_bits(*__pdesc, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

252

return le32_get_bits(*__pdesc, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

257

return le32_get_bits(*__pdesc, GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

27

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

277

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

302

return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

338

le32p_replace_bits(__paddr, __value, GENMASK(2, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

343

le32p_replace_bits(__paddr, __value, GENMASK(15, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

348

le32p_replace_bits(__paddr, __value, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

353

le32p_replace_bits(__paddr, __value, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

358

le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

363

le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

368

le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

62

le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

77

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

82

le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

87

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h

92

le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26));

drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h

43

le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h

116

u8p_replace_bits(__cmd + 1, __val, GENMASK(3, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h

118

u8p_replace_bits(__cmd + 1, __val, GENMASK(7, 4))

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

104

le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

139

le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

145

le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

150

le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

155

le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

160

le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

166

le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

171

le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 5));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

181

le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

187

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

19

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

193

le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

210

le32p_replace_bits(__paddr, __val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

215

le32p_replace_bits(__paddr, __val, GENMASK(18, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

220

le32p_replace_bits(__paddr, __val, GENMASK(17, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

225

le32p_replace_bits(__paddr, __val, GENMASK(5, 2));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

230

le32p_replace_bits((__paddr + 1), __val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

235

le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 17));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

24

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

240

le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

250

GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

290

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

295

le32p_replace_bits(__pdesc, __val, GENMASK(30, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

324

le32p_replace_bits(__status, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

339

le32p_replace_bits(__status, __val, GENMASK(30, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

354

return le32_get_bits(*(__status), GENMASK(30, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

375

return le32_get_bits(*__pdesc, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

390

return le32_get_bits(*__pdesc, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

395

return le32_get_bits(*__pdesc, GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

420

return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

435

return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

64

le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

69

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

74

le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

79

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h

84

le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

100

le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

106

le32p_replace_bits((__pdesc + 4), __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

121

le32p_replace_bits((__pdesc + 4), __val, GENMASK(15, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

141

le32p_replace_bits((__pdesc + 4), __val, GENMASK(20, 19));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

156

le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 27));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

161

le32p_replace_bits((__pdesc + 4), __val, GENMASK(30, 29));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

172

le32p_replace_bits((__pdesc + 5), __val, GENMASK(8, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

177

le32p_replace_bits((__pdesc + 5), __val, GENMASK(14, 9));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

182

le32p_replace_bits((__pdesc + 5), __val, GENMASK(20, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

188

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

225

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

240

return le32_get_bits(*(__pdesc), GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

255

return le32_get_bits(*(__pdesc), GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

260

return le32_get_bits(*(__pdesc), GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

292

return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

32

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

37

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

68

le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

73

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

83

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

89

le32p_replace_bits((__pdesc + 2), __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

447

GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

452

GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

458

GENMASK(30, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

567

mac->vif->bss_conf.beacon_int, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

610

mac->vif->bss_conf.beacon_int, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c

612

mac->assoc_id, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c

543

GENMASK(30, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

104

le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

109

le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

120

le32p_replace_bits((__txdesc + 4), __value, GENMASK(7, 6));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

125

le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

155

le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

175

le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

180

le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

185

le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

19

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

195

le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

200

le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

205

le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

210

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

230

return le32_get_bits(*__pdesc, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

24

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

245

return le32_get_bits(*__pdesc, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

250

return le32_get_bits(*__pdesc, GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

270

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

295

return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

64

le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

79

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

84

le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

89

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h

99

le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h

88

u8p_replace_bits(__ph2ccmd + 1, __val, GENMASK(3, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h

90

u8p_replace_bits(__ph2ccmd + 1, __val, GENMASK(7, 4))

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

104

le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

109

le32p_replace_bits((__pdesc + 3), __val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

144

le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

149

le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

154

le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

159

le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

164

le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

169

le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

179

le32p_replace_bits((__pdesc + 5), __val, GENMASK(6, 5));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

189

le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

19

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

194

le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

204

le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

224

return le32_get_bits(*__pdesc, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

239

return le32_get_bits(*__pdesc, GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

24

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

244

return le32_get_bits(*__pdesc, GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

264

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

279

return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

294

return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

324

return le32_get_bits(*(__pdesc + 4), GENMASK(5, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

356

le32p_replace_bits(__paddr, __value, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

361

le32p_replace_bits(__paddr, __value, GENMASK(15, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

366

le32p_replace_bits(__paddr, __value, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

371

le32p_replace_bits(__paddr, __value, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

376

le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

381

le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

386

le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

64

le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

69

le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

74

le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

79

le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h

84

le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h

177

u8p_replace_bits(__cmd + 1, __value, GENMASK(3, 0))

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h

179

u8p_replace_bits(__cmd + 1, __value, GENMASK(7, 4))

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

104

le32p_replace_bits(__pdesc + 2, __val, GENMASK(22, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

109

le32p_replace_bits(__pdesc + 3, __val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

144

le32p_replace_bits(__pdesc + 3, __val, GENMASK(21, 17));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

149

le32p_replace_bits(__pdesc + 5, __val, GENMASK(27, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

154

le32p_replace_bits(__pdesc + 4, __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

159

le32p_replace_bits(__pdesc + 4, __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

164

le32p_replace_bits(__pdesc + 4, __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

169

le32p_replace_bits(__pdesc + 4, __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

174

le32p_replace_bits(__pdesc + 5, __val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

184

le32p_replace_bits(__pdesc + 5, __val, GENMASK(6, 5));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

19

le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

194

le32p_replace_bits(__pdesc + 5, __val, GENMASK(16, 13));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

199

le32p_replace_bits(__pdesc + 7, __val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

209

le32p_replace_bits(__pdesc + 9, __val, GENMASK(23, 12));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

229

return le32_get_bits(*(__pdesc), GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

24

le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

244

return le32_get_bits(*(__pdesc), GENMASK(19, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

249

return le32_get_bits(*(__pdesc), GENMASK(25, 24));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

269

le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

284

return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

299

return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

324

return le32_get_bits(*(__pdesc + 4), GENMASK(5, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

356

le32p_replace_bits(__paddr, __value, GENMASK(3, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

361

le32p_replace_bits(__paddr, __value, GENMASK(15, 4));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

366

le32p_replace_bits(__paddr, __value, GENMASK(27, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

371

le32p_replace_bits(__paddr, __value, GENMASK(31, 28));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

376

le32p_replace_bits(__paddr, __value, GENMASK(7, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

381

le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

386

le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

64

le32p_replace_bits(__pdesc + 1, __val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

69

le32p_replace_bits(__pdesc + 1, __val, GENMASK(12, 8));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

74

le32p_replace_bits(__pdesc + 1, __val, GENMASK(20, 16));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

79

le32p_replace_bits(__pdesc + 1, __val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h

84

le32p_replace_bits(__pdesc + 1, __val, GENMASK(28, 24));

drivers/net/wireless/realtek/rtw88/bf.h

18

#define BIT_MASK_BEAMFORM (GENMASK(4, 0) | BIT(7))

drivers/net/wireless/realtek/rtw88/coex.c

1025

h2c_para[2] = (u8)u32_get_bits(table_wl, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/coex.c

1026

h2c_para[3] = (u8)u32_get_bits(table_wl, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw88/coex.c

1027

h2c_para[4] = (u8)u32_get_bits(table_wl, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw88/coex.c

1028

h2c_para[5] = (u8)u32_get_bits(table_wl, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw88/coex.c

1049

cur_h2c_para[2] = (u8)u32_get_bits(table, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/coex.c

1050

cur_h2c_para[3] = (u8)u32_get_bits(table, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw88/coex.c

1051

cur_h2c_para[4] = (u8)u32_get_bits(table, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw88/coex.c

1052

cur_h2c_para[5] = (u8)u32_get_bits(table, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw88/coex.c

2703

coex_stat->kt_ver = u8_get_bits(rtw_read8(rtwdev, 0xf1), GENMASK(7, 4));

drivers/net/wireless/realtek/rtw88/coex.c

3783

req.para2 = le16_get_bits(le_addr, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/coex.c

3784

req.para3 = le16_get_bits(le_addr, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw88/coex.h

191

COEX_SCBD_ALL = GENMASK(15, 0),

drivers/net/wireless/realtek/rtw88/coex.h

26

#define PARA1_H2C69_TBTT_TIMES GENMASK(5, 0)

drivers/net/wireless/realtek/rtw88/coex.h

63

le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/efuse.h

16

le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(3, 0))

drivers/net/wireless/realtek/rtw88/efuse.h

18

le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(18, 16))

drivers/net/wireless/realtek/rtw88/efuse.h

20

le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(20, 19))

drivers/net/wireless/realtek/rtw88/efuse.h

22

le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(23, 21))

drivers/net/wireless/realtek/rtw88/efuse.h

24

le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(27, 26))

drivers/net/wireless/realtek/rtw88/fw.h

106

#define RTW_H2C_W0_CMDID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/fw.h

109

#define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw88/fw.h

110

#define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw88/fw.h

401

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))

drivers/net/wireless/realtek/rtw88/fw.h

403

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

405

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))

drivers/net/wireless/realtek/rtw88/fw.h

407

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

417

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))

drivers/net/wireless/realtek/rtw88/fw.h

419

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

422

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

424

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

426

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

428

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))

drivers/net/wireless/realtek/rtw88/fw.h

430

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))

drivers/net/wireless/realtek/rtw88/fw.h

437

le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

439

le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/fw.h

441

le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/fw.h

443

le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

445

le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))

drivers/net/wireless/realtek/rtw88/fw.h

450

u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

452

u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))

drivers/net/wireless/realtek/rtw88/fw.h

454

u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))

drivers/net/wireless/realtek/rtw88/fw.h

456

u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

458

u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))

drivers/net/wireless/realtek/rtw88/fw.h

463

u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))

drivers/net/wireless/realtek/rtw88/fw.h

467

u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

469

u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

472

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

474

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

476

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

485

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))

drivers/net/wireless/realtek/rtw88/fw.h

491

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

493

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

495

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))

drivers/net/wireless/realtek/rtw88/fw.h

497

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))

drivers/net/wireless/realtek/rtw88/fw.h

499

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

501

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))

drivers/net/wireless/realtek/rtw88/fw.h

503

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))

drivers/net/wireless/realtek/rtw88/fw.h

505

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))

drivers/net/wireless/realtek/rtw88/fw.h

507

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))

drivers/net/wireless/realtek/rtw88/fw.h

509

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

511

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))

drivers/net/wireless/realtek/rtw88/fw.h

513

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))

drivers/net/wireless/realtek/rtw88/fw.h

515

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

528

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

530

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))

drivers/net/wireless/realtek/rtw88/fw.h

532

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

534

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

536

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))

drivers/net/wireless/realtek/rtw88/fw.h

538

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))

drivers/net/wireless/realtek/rtw88/fw.h

540

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))

drivers/net/wireless/realtek/rtw88/fw.h

542

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

544

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))

drivers/net/wireless/realtek/rtw88/fw.h

546

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))

drivers/net/wireless/realtek/rtw88/fw.h

548

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))

drivers/net/wireless/realtek/rtw88/fw.h

550

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

587

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

592

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

595

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))

drivers/net/wireless/realtek/rtw88/fw.h

597

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))

drivers/net/wireless/realtek/rtw88/fw.h

599

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

601

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

603

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

605

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

609

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))

drivers/net/wireless/realtek/rtw88/fw.h

611

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))

drivers/net/wireless/realtek/rtw88/fw.h

613

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

615

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))

drivers/net/wireless/realtek/rtw88/fw.h

617

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))

drivers/net/wireless/realtek/rtw88/fw.h

623

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/fw.h

625

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/fw.h

627

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

629

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

631

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

634

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))

drivers/net/wireless/realtek/rtw88/fw.h

636

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))

drivers/net/wireless/realtek/rtw88/fw.h

638

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))

drivers/net/wireless/realtek/rtw88/fw.h

640

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

642

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))

drivers/net/wireless/realtek/rtw88/fw.h

644

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

646

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

648

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

654

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

656

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

660

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

662

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))

drivers/net/wireless/realtek/rtw88/fw.h

664

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))

drivers/net/wireless/realtek/rtw88/fw.h

668

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))

drivers/net/wireless/realtek/rtw88/fw.h

674

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))

drivers/net/wireless/realtek/rtw88/fw.h

678

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

680

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

682

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

684

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

688

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

690

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

692

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

694

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/fw.h

696

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

698

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

700

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

702

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

704

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

708

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

710

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

712

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

714

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

716

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

718

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

720

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

722

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

724

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/fw.h

726

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

728

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

731

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

733

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

742

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

749

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

751

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

772

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/fw.h

774

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

783

le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/fw.h

789

le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

791

le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))

drivers/net/wireless/realtek/rtw88/fw.h

795

le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))

drivers/net/wireless/realtek/rtw88/fw.h

797

le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))

drivers/net/wireless/realtek/rtw88/fw.h

799

le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))

drivers/net/wireless/realtek/rtw88/fw.h

801

le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw88/fw.h

98

#define RTW_C2H_RA_RPT_RATE GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/pci.h

25

#define BITS_DBI_WREN GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/pci.h

26

#define BITS_DBI_ADDR_MASK GENMASK(11, 2)

drivers/net/wireless/realtek/rtw88/pci.h

30

#define BITS_MDIO_ADDR_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw88/pci.h

54

#define TRX_BD_IDX_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw88/pci.h

55

#define TRX_BD_HW_IDX_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw88/phy.c

643

return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);

drivers/net/wireless/realtek/rtw88/reg.h

136

#define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */

drivers/net/wireless/realtek/rtw88/reg.h

164

#define BITS_PMC_BT_IQK_STS GENMASK(22, 21)

drivers/net/wireless/realtek/rtw88/reg.h

174

#define BIT_MASK_USB23_SW_MODE_V1 GENMASK(19, 18)

drivers/net/wireless/realtek/rtw88/reg.h

327

#define BIT_MASK_BLK_DESC_NUM GENMASK(7, 4)

drivers/net/wireless/realtek/rtw88/reg.h

360

#define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/reg.h

361

#define BIT_DMA_AGG_TO_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw88/reg.h

371

#define BIT_DMA_BURST_CNT GENMASK(3, 2)

drivers/net/wireless/realtek/rtw88/reg.h

372

#define BIT_DMA_BURST_SIZE GENMASK(5, 4)

drivers/net/wireless/realtek/rtw88/reg.h

403

#define BITS_RRSR_RSC GENMASK(22, 21)

drivers/net/wireless/realtek/rtw88/reg.h

423

#define BIT_EXC_CODE GENMASK(6, 2)

drivers/net/wireless/realtek/rtw88/reg.h

451

#define BIT_MASK_TXOP_LMT GENMASK(26, 16)

drivers/net/wireless/realtek/rtw88/reg.h

452

#define BIT_MASK_CWMAX GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/reg.h

453

#define BIT_MASK_CWMIN GENMASK(11, 8)

drivers/net/wireless/realtek/rtw88/reg.h

454

#define BIT_MASK_AIFS GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/reg.h

467

#define BIT_AC_QUEUE GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/reg.h

583

#define BIT_PTA_SW_CTL GENMASK(4, 3)

drivers/net/wireless/realtek/rtw88/reg.h

591

#define BIT_MASK_SAMPLE_RATE GENMASK(5, 0)

drivers/net/wireless/realtek/rtw88/reg.h

629

#define BIT_PSD_INI GENMASK(23, 22)

drivers/net/wireless/realtek/rtw88/reg.h

646

#define BIT_IQ_WGT GENMASK(9, 8)

drivers/net/wireless/realtek/rtw88/reg.h

648

#define BIT_MBC_WIN GENMASK(5, 4)

drivers/net/wireless/realtek/rtw88/reg.h

658

#define DIS_DPD_MASK GENMASK(9, 0)

drivers/net/wireless/realtek/rtw88/reg.h

66

#define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4)

drivers/net/wireless/realtek/rtw88/reg.h

669

#define DIS_DPD_RATEALL GENMASK(9, 0)

drivers/net/wireless/realtek/rtw88/reg.h

684

#define BB_SWING_MASK GENMASK(31, 21)

drivers/net/wireless/realtek/rtw88/reg.h

714

#define BIT_MASK_RFE_SEL89 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/reg.h

721

#define BIT_MASK_RFE_INV89 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw88/reg.h

789

#define BIT_CF_L_V2 GENMASK(29, 28)

drivers/net/wireless/realtek/rtw88/reg.h

792

#define BIT_XCAP_0 GENMASK(23, 10)

drivers/net/wireless/realtek/rtw88/reg.h

89

#define BIT_LED2_CM GENMASK(18, 16)

drivers/net/wireless/realtek/rtw88/reg.h

91

#define BIT_LED1_CM GENMASK(10, 8)

drivers/net/wireless/realtek/rtw88/reg.h

925

#define BIT_RFE_SELSW0_D GENMASK(27, 20)

drivers/net/wireless/realtek/rtw88/reg.h

93

#define BIT_LED0_CM GENMASK(2, 0)

drivers/net/wireless/realtek/rtw88/reg.h

954

#define BIT_USB3_PHY_ADR_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw88/reg.h

962

#define BIT_BAND GENMASK(18, 16)

drivers/net/wireless/realtek/rtw88/reg.h

975

#define BIT_DATA_L GENMASK(11, 0)

drivers/net/wireless/realtek/rtw88/rtw8703b.c

1277

u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16);

drivers/net/wireless/realtek/rtw88/rtw8703b.c

1650

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8703b.c

846

GENMASK(31, 30), 0x0);

drivers/net/wireless/realtek/rtw88/rtw8703b.c

860

rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26),

drivers/net/wireless/realtek/rtw88/rtw8703b.h

100

#define BIT_MASK_AGG_BURST_SIZE (GENMASK(5, 4))

drivers/net/wireless/realtek/rtw88/rtw8703b.h

12

#define VGA_BITS GENMASK(4, 0)

drivers/net/wireless/realtek/rtw88/rtw8703b.h

13

#define LNA_L_BITS GENMASK(7, 5)

drivers/net/wireless/realtek/rtw88/rtw8703b.h

17

#define BIT_LNA_L_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw88/rtw8703b.h

99

#define BIT_MASK_AGG_BURST_NUM (GENMASK(3, 2))

drivers/net/wireless/realtek/rtw88/rtw8723d.c

1383

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8723d.h

14

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

18

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

20

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

22

le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

24

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

26

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

28

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

30

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8723d.h

32

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8723x.c

329

efuse->rf_board_option &= GENMASK(5, 0);

drivers/net/wireless/realtek/rtw88/rtw8723x.c

616

if (bitmap & GENMASK(j + 1, j))

drivers/net/wireless/realtek/rtw88/rtw8723x.h

189

#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

211

#define BIT_MASK_RXBB_DFIR GENMASK(27, 24)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

227

#define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

228

#define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

242

#define BIT_MASK_RXDSP GENMASK(28, 24)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

259

#define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

261

#define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

274

#define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

280

#define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

281

#define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

286

#define BIT_MASK_CTX_TYPE GENMASK(6, 4)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

294

#define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

295

#define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

297

#define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

298

#define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

300

#define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

319

#define BIT_MASK_RES_TX GENMASK(25, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

321

#define BIT_MASK_RES_TY GENMASK(25, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

323

#define BIT_MASK_RES_RX GENMASK(25, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

328

#define BIT_MASK_RES_RY GENMASK(25, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

334

#define BIT_MASK_HT_CRC_OK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

335

#define BIT_MASK_HT_CRC_ERR GENMASK(31, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

337

#define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

338

#define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

341

#define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

342

#define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

343

#define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing)

drivers/net/wireless/realtek/rtw88/rtw8723x.h

344

#define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing)

drivers/net/wireless/realtek/rtw88/rtw8812a.c

316

rtw_write32_mask(rtwdev, REG_CK_MONHA, GENMASK(26, 24), 0x7);

drivers/net/wireless/realtek/rtw88/rtw8812a.c

317

rtw_write32_mask(rtwdev, REG_CK_MONHB, GENMASK(26, 24), 0x7);

drivers/net/wireless/realtek/rtw88/rtw8812a.c

862

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8814a.c

1893

rtw_write32_mask(rtwdev, txagc_reg[path], GENMASK(29, 25),

drivers/net/wireless/realtek/rtw88/rtw8814a.c

1976

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8821a.c

430

rtw_write32_mask(rtwdev, REG_CK_MONHA, GENMASK(26, 24), 0x7);

drivers/net/wireless/realtek/rtw88/rtw8821a.c

700

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

1065

rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

1066

rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),

drivers/net/wireless/realtek/rtw88/rtw8821c.c

1143

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

571

rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),

drivers/net/wireless/realtek/rtw88/rtw8821c.c

742

dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

743

dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

746

dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

747

dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

750

dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

751

dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

754

dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

755

dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

758

dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

762

dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

796

iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/rtw8821c.h

180

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

182

le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

184

le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

188

#define BIT_LNA_L_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw88/rtw8821c.h

192

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

194

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

196

le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

198

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

200

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

202

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

204

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

206

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

208

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

210

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

212

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8821c.h

261

#define BIT_MASK_R_RFE_SEL_15 GENMASK(31, 28)

drivers/net/wireless/realtek/rtw88/rtw8821c.h

272

#define CTRL_TYPE_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1090

iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1413

rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx);

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1414

rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21),

drivers/net/wireless/realtek/rtw88/rtw8822b.c

1500

GENMASK(17, 16), 0x03);

drivers/net/wireless/realtek/rtw88/rtw8822b.h

126

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

130

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

132

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

134

le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

136

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

138

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

140

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

142

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

144

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

146

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

148

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

150

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822b.h

160

#define BIT_MA_LEVEL GENMASK(1, 0)

drivers/net/wireless/realtek/rtw88/rtw8822b.h

167

#define BIT_SOURCE_OPTION GENMASK(29, 28)

drivers/net/wireless/realtek/rtw88/rtw8822c.c

1105

thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2834

parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2835

rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2836

crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2837

crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2838

mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2839

mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2840

fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

2841

sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3266

dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3267

dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3275

corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3276

rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3445

dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3967

GENMASK(31, 28), 0x9);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3969

GENMASK(31, 28), 0x1);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3971

GENMASK(31, 28), 0x0);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

4213

rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),

drivers/net/wireless/realtek/rtw88/rtw8822c.h

146

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

148

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

150

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

152

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

154

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

158

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

160

le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

162

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

164

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

166

le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

168

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

170

le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

172

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

174

le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

176

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

178

le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw88/rtw8822c.h

183

#define XCAP_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

191

#define BIT_ANT_PATH GENMASK(1, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

194

#define BIT_EDCCA_OPTION GENMASK(30, 29)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

199

#define BITS_SUBTUNE GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

218

#define BIT_3WIRE_EN GENMASK(1, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

227

#define BITS_RXAGC_CCK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

228

#define BITS_RXAGC_OFDM GENMASK(8, 4)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

235

#define BIT_BBMODE GENMASK(2, 1)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

257

#define BIT_SEL_PATH GENMASK(2, 1)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

258

#define BIT_SUBPAGE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

260

#define BIT_GS_PWSF GENMASK(27, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

266

#define BIT_TX_CFIR GENMASK(31, 30)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

267

#define BIT_CFIR_EN GENMASK(26, 24)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

272

#define BIT_GLOSS_DB GENMASK(14, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

277

#define BIT_I_GAIN GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

279

#define BIT_Q_GAIN_SEL GENMASK(14, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

280

#define BIT_Q_GAIN GENMASK(11, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

282

#define BIT_GAPK_RPT_IDX GENMASK(11, 8)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

288

#define BIT_IQ_SWITCH GENMASK(5, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

293

#define BIT_RPT_SEL GENMASK(20, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

294

#define BIT_DPD_CLK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

300

#define BIT_RPT_DGAIN GENMASK(27, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

301

#define BIT_GAPK_RPT0 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

302

#define BIT_GAPK_RPT1 GENMASK(7, 4)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

303

#define BIT_GAPK_RPT2 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

304

#define BIT_GAPK_RPT3 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

305

#define BIT_GAPK_RPT4 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

306

#define BIT_GAPK_RPT5 GENMASK(23, 20)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

307

#define BIT_GAPK_RPT6 GENMASK(27, 24)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

308

#define BIT_GAPK_RPT7 GENMASK(31, 28)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

328

#define BIT_CCA_ON_BY_PW GENMASK(11, 3)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

334

#define BIT_ANTSEG GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

338

#define BIT_STOP_TX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

349

#define BIT_RPT_CIP_STATUS GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

365

#define BIT_RF_MODE GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

366

#define BIT_RXAGC GENMASK(9, 5)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

367

#define BIT_TXAGC GENMASK(4, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

371

#define BIT_BW_TXBB GENMASK(14, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

372

#define BIT_BW_RXBB GENMASK(11, 10)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

375

#define BIT_BB_GAIN GENMASK(18, 14)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

376

#define BIT_RF_GAIN GENMASK(4, 2)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

378

#define BIT_GAIN_TXBB GENMASK(4, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

380

#define BIT_TX_MODE GENMASK(19, 8)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

382

#define BIT_GAIN_TX_PAD_H GENMASK(11, 8)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

383

#define BIT_GAIN_TX_PAD_L GENMASK(7, 4)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

385

#define RF_PABIAS_2G_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

386

#define RF_PABIAS_5G_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

388

#define BIT_TXA_LB_ATT GENMASK(15, 14)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

389

#define BIT_LB_SW GENMASK(13, 12)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

390

#define BIT_LB_ATT GENMASK(4, 2)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

394

#define BIT_RXA_MIX_GAIN GENMASK(4, 3)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

406

#define RF_THEMAL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

408

#define PPG_2G_A_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

409

#define PPG_2G_B_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

413

#define PPG_PABIAS_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c.h

416

#define PPG_5G_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43625

0x1d58, GENMASK(11, 3), 0x1ff,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43632

0x180c, GENMASK(1, 0), 0x0,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43633

0x410c, GENMASK(1, 0), 0x0,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43634

0x1a14, GENMASK(9, 8), 0x3,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43635

0x80c, GENMASK(3, 0), 0x8,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43636

0x824, GENMASK(19, 16), 0x3,

drivers/net/wireless/realtek/rtw88/rtw8822c_table.c

43637

0x824, GENMASK(27, 24), 0x3,

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

148

antenna = u8_get_bits(val8, GENMASK(7, 5));

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

151

antenna = u8_get_bits(val8, GENMASK(3, 1));

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

159

wmode = u8_get_bits(val8, GENMASK(3, 2));

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

1880

rtw_write32_mask(rtwdev, reg_txscale[path], GENMASK(31, 21),

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

794

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x2);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

795

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x2);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

800

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

801

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

817

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

818

rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

948

rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x17);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

953

rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x02);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

955

rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

987

rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x15);

drivers/net/wireless/realtek/rtw88/rtw88xxa.c

988

rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

103

#define RTW_JGRPHY_W2_BT_RF_CH_LSB GENMASK(7, 2)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

104

#define RTW_JGRPHY_W2_CFO_TAIL_A GENMASK(15, 8) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

105

#define RTW_JGRPHY_W2_CFO_TAIL_B GENMASK(23, 16) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

106

#define RTW_JGRPHY_W2_PCTS_MSK_RPT_0 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

108

#define RTW_JGRPHY_W3_PCTS_MSK_RPT_1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

110

#define RTW_JGRPHY_W3_RXEVM_1 GENMASK(15, 8) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

111

#define RTW_JGRPHY_W3_RXEVM_2 GENMASK(23, 16) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

112

#define RTW_JGRPHY_W3_RXSNR_A GENMASK(31, 24) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

114

#define RTW_JGRPHY_W4_RXSNR_B GENMASK(7, 0) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

115

#define RTW_JGRPHY_W4_PCTS_MSK_RPT_2 GENMASK(21, 8)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

117

#define RTW_JGRPHY_W4_RXEVM_3 GENMASK(31, 24) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

119

#define RTW_JGRPHY_W5_RXEVM_4 GENMASK(7, 0) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

121

#define RTW_JGRPHY_W5_CSI_CURRENT_1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

122

#define RTW_JGRPHY_W5_CSI_CURRENT_2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

124

#define RTW_JGRPHY_W5_RXSNR_C GENMASK(15, 8) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

125

#define RTW_JGRPHY_W5_RXSNR_D GENMASK(23, 16) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

126

#define RTW_JGRPHY_W5_GAIN_C GENMASK(30, 24)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

129

#define RTW_JGRPHY_W6_GAIN_D GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

131

#define RTW_JGRPHY_W6_SIGEVM GENMASK(15, 8) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

132

#define RTW_JGRPHY_W6_ANTIDX_ANTC GENMASK(18, 16)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

133

#define RTW_JGRPHY_W6_ANTIDX_ANTD GENMASK(21, 19)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

136

#define RTW_JGRPHY_W6_ANTIDX_ANTA GENMASK(26, 24)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

137

#define RTW_JGRPHY_W6_ANTIDX_ANTB GENMASK(29, 27)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

138

#define RTW_JGRPHY_W6_HW_ANTSW_OCCUR GENMASK(31, 30)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

82

#define RTW_JGRPHY_W0_GAIN_A GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

84

#define RTW_JGRPHY_W0_GAIN_B GENMASK(14, 8)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

86

#define RTW_JGRPHY_W0_CHL_NUM GENMASK(25, 16)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

87

#define RTW_JGRPHY_W0_SUB_CHNL GENMASK(29, 26)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

88

#define RTW_JGRPHY_W0_R_RFMOD GENMASK(31, 30)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

91

#define RTW_JGRPHY_W1_SIG_QUAL GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

92

#define RTW_JGRPHY_W1_AGC_RPT_VGA_IDX GENMASK(12, 8)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

93

#define RTW_JGRPHY_W1_AGC_RPT_LNA_IDX GENMASK(15, 13)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

94

#define RTW_JGRPHY_W1_BB_POWER GENMASK(23, 16)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

96

#define RTW_JGRPHY_W1_PWDB_ALL GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

97

#define RTW_JGRPHY_W1_CFO_SHORT_A GENMASK(15, 8) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

98

#define RTW_JGRPHY_W1_CFO_SHORT_B GENMASK(23, 16) /* s8 */

drivers/net/wireless/realtek/rtw88/rtw88xxa.h

99

#define RTW_JGRPHY_W1_BT_RF_CH_MSB GENMASK(31, 30)

drivers/net/wireless/realtek/rtw88/rx.h

26

#define RTW_RX_DESC_W0_PKT_LEN GENMASK(13, 0)

drivers/net/wireless/realtek/rtw88/rx.h

29

#define RTW_RX_DESC_W0_DRV_INFO_SIZE GENMASK(19, 16)

drivers/net/wireless/realtek/rtw88/rx.h

30

#define RTW_RX_DESC_W0_ENC_TYPE GENMASK(22, 20)

drivers/net/wireless/realtek/rtw88/rx.h

31

#define RTW_RX_DESC_W0_SHIFT GENMASK(25, 24)

drivers/net/wireless/realtek/rtw88/rx.h

35

#define RTW_RX_DESC_W1_MACID GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/rx.h

38

#define RTW_RX_DESC_W2_PPDU_CNT GENMASK(30, 29)

drivers/net/wireless/realtek/rtw88/rx.h

40

#define RTW_RX_DESC_W3_RX_RATE GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/rx.h

42

#define RTW_RX_DESC_W4_BW GENMASK(5, 4)

drivers/net/wireless/realtek/rtw88/rx.h

44

#define RTW_RX_DESC_W5_TSFL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw88/sdio.h

124

#define REG_SDIO_CMD_ADDR_MSK GENMASK(16, 13)

drivers/net/wireless/realtek/rtw88/tx.h

25

#define RTW_TX_DESC_W0_TXPKTSIZE GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/tx.h

26

#define RTW_TX_DESC_W0_OFFSET GENMASK(23, 16)

drivers/net/wireless/realtek/rtw88/tx.h

30

#define RTW_TX_DESC_W1_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw88/tx.h

31

#define RTW_TX_DESC_W1_QSEL GENMASK(12, 8)

drivers/net/wireless/realtek/rtw88/tx.h

32

#define RTW_TX_DESC_W1_RATE_ID GENMASK(20, 16)

drivers/net/wireless/realtek/rtw88/tx.h

33

#define RTW_TX_DESC_W1_SEC_TYPE GENMASK(23, 22)

drivers/net/wireless/realtek/rtw88/tx.h

34

#define RTW_TX_DESC_W1_PKT_OFFSET GENMASK(28, 24)

drivers/net/wireless/realtek/rtw88/tx.h

38

#define RTW_TX_DESC_W2_AMPDU_DEN GENMASK(22, 20)

drivers/net/wireless/realtek/rtw88/tx.h

40

#define RTW_TX_DESC_W3_HW_SSN_SEL GENMASK(7, 6)

drivers/net/wireless/realtek/rtw88/tx.h

45

#define RTW_TX_DESC_W3_MAX_AGG_NUM GENMASK(21, 17)

drivers/net/wireless/realtek/rtw88/tx.h

46

#define RTW_TX_DESC_W4_DATARATE GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/tx.h

47

#define RTW_TX_DESC_W4_DATARATE_FB_LIMIT GENMASK(12, 8)

drivers/net/wireless/realtek/rtw88/tx.h

48

#define RTW_TX_DESC_W4_RTSRATE GENMASK(28, 24)

drivers/net/wireless/realtek/rtw88/tx.h

50

#define RTW_TX_DESC_W5_DATA_BW GENMASK(6, 5)

drivers/net/wireless/realtek/rtw88/tx.h

52

#define RTW_TX_DESC_W5_DATA_STBC GENMASK(9, 8)

drivers/net/wireless/realtek/rtw88/tx.h

54

#define RTW_TX_DESC_W6_SW_DEFINE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw88/tx.h

55

#define RTW_TX_DESC_W7_TXDESC_CHECKSUM GENMASK(15, 0)

drivers/net/wireless/realtek/rtw88/tx.h

56

#define RTW_TX_DESC_W7_DMA_TXAGG_NUM GENMASK(31, 24)

drivers/net/wireless/realtek/rtw88/tx.h

58

#define RTW_TX_DESC_W9_SW_SEQ GENMASK(23, 12)

drivers/net/wireless/realtek/rtw88/tx.h

60

#define RTW_TX_DESC_W9_TIM_OFFSET GENMASK(6, 0)

drivers/net/wireless/realtek/rtw88/wow.c

216

mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6));

drivers/net/wireless/realtek/rtw88/wow.c

217

mask_hw[i] |= u8_get_bits(mask[i + 1], GENMASK(5, 0)) << 2;

drivers/net/wireless/realtek/rtw88/wow.c

219

mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6));

drivers/net/wireless/realtek/rtw88/wow.c

222

mask_hw[0] &= (~GENMASK(5, 0));

drivers/net/wireless/realtek/rtw89/cam.c

31

key32[i] = FIELD_PREP(GENMASK(7, 0), sec_cam->key[j + 0]) |

drivers/net/wireless/realtek/rtw89/cam.c

32

FIELD_PREP(GENMASK(15, 8), sec_cam->key[j + 1]) |

drivers/net/wireless/realtek/rtw89/cam.c

33

FIELD_PREP(GENMASK(23, 16), sec_cam->key[j + 2]) |

drivers/net/wireless/realtek/rtw89/cam.c

34

FIELD_PREP(GENMASK(31, 24), sec_cam->key[j + 3]);

drivers/net/wireless/realtek/rtw89/cam.h

100

#define ADDR_CAM_W11_SEC_ENT3 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

101

#define ADDR_CAM_W11_SEC_ENT4 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

102

#define ADDR_CAM_W11_SEC_ENT5 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

103

#define ADDR_CAM_W11_SEC_ENT6 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

104

#define ADDR_CAM_W12_BSSID_IDX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

105

#define ADDR_CAM_W12_BSSID_OFFSET GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

106

#define ADDR_CAM_W12_BSSID_LEN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

109

#define ADDR_CAM_W13_BSSID_MASK GENMASK(7, 2)

drivers/net/wireless/realtek/rtw89/cam.h

110

#define ADDR_CAM_W13_BSSID_BSS_COLOR GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/cam.h

111

#define ADDR_CAM_W13_BSSID_BSSID0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

112

#define ADDR_CAM_W13_BSSID_BSSID1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

113

#define ADDR_CAM_W14_BSSID_BSSID2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

114

#define ADDR_CAM_W14_BSSID_BSSID3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

115

#define ADDR_CAM_W14_BSSID_BSSID4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

116

#define ADDR_CAM_W14_BSSID_BSSID5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

117

#define ADDR_CAM_W15_UPD_MODE GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/cam.h

12

#define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/cam.h

13

#define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/cam.h

139

#define DCTLINFO_V1_C0_MACID GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/cam.h

142

#define DCTLINFO_V1_W0_QOS_FIELD_H GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

143

#define DCTLINFO_V1_W0_HW_EXSEQ_MACID GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/cam.h

145

#define DCTLINFO_V1_W0_AES_IV_L GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/cam.h

146

#define DCTLINFO_V1_W0_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

147

#define DCTLINFO_V1_W1_AES_IV_H GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

148

#define DCTLINFO_V1_W1_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

149

#define DCTLINFO_V1_W2_SEQ0 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

150

#define DCTLINFO_V1_W2_SEQ1 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

151

#define DCTLINFO_V1_W2_AMSDU_MAX_LEN GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/cam.h

155

#define DCTLINFO_V1_W2_ALL GENMASK(29, 0)

drivers/net/wireless/realtek/rtw89/cam.h

156

#define DCTLINFO_V1_W3_SEQ2 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

157

#define DCTLINFO_V1_W3_SEQ3 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

158

#define DCTLINFO_V1_W3_TGT_IND GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/cam.h

160

#define DCTLINFO_V1_W3_HTC_LB GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/cam.h

161

#define DCTLINFO_V1_W3_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

162

#define DCTLINFO_V1_W4_MHDR_LEN GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/cam.h

164

#define DCTLINFO_V1_W4_VLAN_TAG_SEL GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/cam.h

166

#define DCTLINFO_V1_W4_SEC_KEY_ID GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/cam.h

168

#define DCTLINFO_V1_W4_SEC_ENT_MODE GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/cam.h

169

#define DCTLINFO_V1_W4_SEC_ENT0_KEYID GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/cam.h

170

#define DCTLINFO_V1_W4_SEC_ENT1_KEYID GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/cam.h

171

#define DCTLINFO_V1_W4_SEC_ENT2_KEYID GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/cam.h

172

#define DCTLINFO_V1_W4_SEC_ENT3_KEYID GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/cam.h

173

#define DCTLINFO_V1_W4_SEC_ENT4_KEYID GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/cam.h

174

#define DCTLINFO_V1_W4_SEC_ENT5_KEYID GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/cam.h

175

#define DCTLINFO_V1_W4_SEC_ENT6_KEYID GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/cam.h

176

#define DCTLINFO_V1_W4_ALL (GENMASK(31, 15) | GENMASK(10, 0))

drivers/net/wireless/realtek/rtw89/cam.h

177

#define DCTLINFO_V1_W5_SEC_ENT_VALID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

178

#define DCTLINFO_V1_W5_SEC_ENT0 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

179

#define DCTLINFO_V1_W5_SEC_ENT1 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

180

#define DCTLINFO_V1_W5_SEC_ENT2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

181

#define DCTLINFO_V1_W5_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

182

#define DCTLINFO_V1_W6_SEC_ENT3 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

183

#define DCTLINFO_V1_W6_SEC_ENT4 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

184

#define DCTLINFO_V1_W6_SEC_ENT5 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

185

#define DCTLINFO_V1_W6_SEC_ENT6 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

186

#define DCTLINFO_V1_W6_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

224

#define DCTLINFO_V2_C0_MACID GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/cam.h

227

#define DCTLINFO_V2_W0_QOS_FIELD_H GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

228

#define DCTLINFO_V2_W0_HW_EXSEQ_MACID GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/cam.h

230

#define DCTLINFO_V2_W0_AES_IV_L GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/cam.h

231

#define DCTLINFO_V2_W0_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

232

#define DCTLINFO_V2_W1_AES_IV_H GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

233

#define DCTLINFO_V2_W1_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

234

#define DCTLINFO_V2_W2_SEQ0 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

235

#define DCTLINFO_V2_W2_SEQ1 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

236

#define DCTLINFO_V2_W2_AMSDU_MAX_LEN GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/cam.h

242

#define DCTLINFO_V2_W2_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

243

#define DCTLINFO_V2_W3_SEQ2 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

244

#define DCTLINFO_V2_W3_SEQ3 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

245

#define DCTLINFO_V2_W3_TGT_IND GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/cam.h

247

#define DCTLINFO_V2_W3_HTC_LB GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/cam.h

248

#define DCTLINFO_V2_W3_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

249

#define DCTLINFO_V2_W4_VLAN_TAG_SEL GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/cam.h

251

#define DCTLINFO_V2_W4_SEC_KEY_ID GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/cam.h

257

#define DCTLINFO_V2_W4_SEC_ENT_MODE GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/cam.h

258

#define DCTLINFO_V2_W4_SEC_ENT0_KEYID GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/cam.h

259

#define DCTLINFO_V2_W4_SEC_ENT1_KEYID GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/cam.h

260

#define DCTLINFO_V2_W4_SEC_ENT2_KEYID GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/cam.h

261

#define DCTLINFO_V2_W4_SEC_ENT3_KEYID GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/cam.h

262

#define DCTLINFO_V2_W4_SEC_ENT4_KEYID GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/cam.h

263

#define DCTLINFO_V2_W4_SEC_ENT5_KEYID GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/cam.h

264

#define DCTLINFO_V2_W4_SEC_ENT6_KEYID GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/cam.h

265

#define DCTLINFO_V2_W4_ALL GENMASK(31, 5)

drivers/net/wireless/realtek/rtw89/cam.h

266

#define DCTLINFO_V2_W5_SEC_ENT7_KEYID GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/cam.h

267

#define DCTLINFO_V2_W5_SEC_ENT8_KEYID GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/cam.h

268

#define DCTLINFO_V2_W5_SEC_ENT_VALID_V1 GENMASK(23, 8)

drivers/net/wireless/realtek/rtw89/cam.h

269

#define DCTLINFO_V2_W5_SEC_ENT0_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

270

#define DCTLINFO_V2_W5_ALL (GENMASK(31, 8) | GENMASK(3, 0))

drivers/net/wireless/realtek/rtw89/cam.h

271

#define DCTLINFO_V2_W6_SEC_ENT1_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

272

#define DCTLINFO_V2_W6_SEC_ENT2_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

273

#define DCTLINFO_V2_W6_SEC_ENT3_V1 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

274

#define DCTLINFO_V2_W6_SEC_ENT4_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

275

#define DCTLINFO_V2_W6_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

276

#define DCTLINFO_V2_W7_SEC_ENT5_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

277

#define DCTLINFO_V2_W7_SEC_ENT6_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

278

#define DCTLINFO_V2_W7_SEC_ENT7 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

279

#define DCTLINFO_V2_W7_SEC_ENT8 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

280

#define DCTLINFO_V2_W7_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

281

#define DCTLINFO_V2_W8_MLD_SMA_0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

282

#define DCTLINFO_V2_W8_MLD_SMA_1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

283

#define DCTLINFO_V2_W8_MLD_SMA_2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

284

#define DCTLINFO_V2_W8_MLD_SMA_3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

285

#define DCTLINFO_V2_W8_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

286

#define DCTLINFO_V2_W9_MLD_SMA_4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

287

#define DCTLINFO_V2_W9_MLD_SMA_5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

288

#define DCTLINFO_V2_W9_MLD_TMA_0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

289

#define DCTLINFO_V2_W9_MLD_TMA_1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

290

#define DCTLINFO_V2_W9_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

291

#define DCTLINFO_V2_W10_MLD_TMA_2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

292

#define DCTLINFO_V2_W10_MLD_TMA_3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

293

#define DCTLINFO_V2_W10_MLD_TMA_4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

294

#define DCTLINFO_V2_W10_MLD_TMA_5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

295

#define DCTLINFO_V2_W10_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

296

#define DCTLINFO_V2_W11_MLD_BSSID_0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

297

#define DCTLINFO_V2_W11_MLD_BSSID_1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

298

#define DCTLINFO_V2_W11_MLD_BSSID_2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

299

#define DCTLINFO_V2_W11_MLD_BSSID_3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

300

#define DCTLINFO_V2_W11_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

301

#define DCTLINFO_V2_W12_MLD_BSSID_4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

302

#define DCTLINFO_V2_W12_MLD_BSSID_5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

303

#define DCTLINFO_V2_W12_ALL GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/cam.h

341

#define DCTLINFO_V3_C0_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/cam.h

344

#define DCTLINFO_V3_W0_QOS_FIELD_H GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

345

#define DCTLINFO_V3_W0_HW_EXSEQ_MACID GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/cam.h

347

#define DCTLINFO_V3_W0_AES_IV_L GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/cam.h

348

#define DCTLINFO_V3_W0_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

349

#define DCTLINFO_V3_W1_AES_IV_H GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

350

#define DCTLINFO_V3_W1_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

351

#define DCTLINFO_V3_W2_SEQ0 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

352

#define DCTLINFO_V3_W2_SEQ1 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

353

#define DCTLINFO_V3_W2_AMSDU_MAX_LEN GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/cam.h

359

#define DCTLINFO_V3_W2_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

360

#define DCTLINFO_V3_W3_SEQ2 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

361

#define DCTLINFO_V3_W3_SEQ3 GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/cam.h

362

#define DCTLINFO_V3_W3_TGT_IND GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/cam.h

364

#define DCTLINFO_V3_W3_HTC_LB GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/cam.h

365

#define DCTLINFO_V3_W3_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

366

#define DCTLINFO_V3_W4_VLAN_TAG_SEL GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/cam.h

368

#define DCTLINFO_V3_W4_SEC_KEY_ID GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/cam.h

374

#define DCTLINFO_V3_W4_SEC_ENT_MODE GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/cam.h

375

#define DCTLINFO_V3_W4_SEC_ENT0_KEYID GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/cam.h

376

#define DCTLINFO_V3_W4_SEC_ENT1_KEYID GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/cam.h

377

#define DCTLINFO_V3_W4_SEC_ENT2_KEYID GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/cam.h

378

#define DCTLINFO_V3_W4_SEC_ENT3_KEYID GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/cam.h

379

#define DCTLINFO_V3_W4_SEC_ENT4_KEYID GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/cam.h

38

#define ADDR_CAM_W1_IDX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

380

#define DCTLINFO_V3_W4_SEC_ENT5_KEYID GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/cam.h

381

#define DCTLINFO_V3_W4_SEC_ENT6_KEYID GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/cam.h

382

#define DCTLINFO_V3_W4_ALL GENMASK(31, 5)

drivers/net/wireless/realtek/rtw89/cam.h

383

#define DCTLINFO_V3_W5_SEC_ENT7_KEYID GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/cam.h

384

#define DCTLINFO_V3_W5_SEC_ENT8_KEYID GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/cam.h

385

#define DCTLINFO_V3_W5_SEC_ENT_VALID_V1 GENMASK(23, 8)

drivers/net/wireless/realtek/rtw89/cam.h

386

#define DCTLINFO_V3_W5_ALL (GENMASK(23, 8) | GENMASK(3, 0))

drivers/net/wireless/realtek/rtw89/cam.h

387

#define DCTLINFO_V3_W6_SEC_ENT0_V2 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/cam.h

388

#define DCTLINFO_V3_W6_SEC_ENT1_V2 GENMASK(18, 10)

drivers/net/wireless/realtek/rtw89/cam.h

389

#define DCTLINFO_V3_W6_SEC_ENT2_V2 GENMASK(28, 20)

drivers/net/wireless/realtek/rtw89/cam.h

39

#define ADDR_CAM_W1_OFFSET GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

390

#define DCTLINFO_V3_W6_ALL GENMASK(28, 0)

drivers/net/wireless/realtek/rtw89/cam.h

391

#define DCTLINFO_V3_W7_SEC_ENT3_V2 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/cam.h

392

#define DCTLINFO_V3_W7_SEC_ENT4_V2 GENMASK(18, 10)

drivers/net/wireless/realtek/rtw89/cam.h

393

#define DCTLINFO_V3_W7_SEC_ENT5_V2 GENMASK(28, 20)

drivers/net/wireless/realtek/rtw89/cam.h

394

#define DCTLINFO_V3_W7_ALL GENMASK(28, 0)

drivers/net/wireless/realtek/rtw89/cam.h

395

#define DCTLINFO_V3_W8_SEC_ENT6_V2 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/cam.h

396

#define DCTLINFO_V3_W8_SEC_ENT7_V1 GENMASK(18, 10)

drivers/net/wireless/realtek/rtw89/cam.h

397

#define DCTLINFO_V3_W8_SEC_ENT8_V1 GENMASK(28, 20)

drivers/net/wireless/realtek/rtw89/cam.h

398

#define DCTLINFO_V3_W8_ALL GENMASK(28, 0)

drivers/net/wireless/realtek/rtw89/cam.h

399

#define DCTLINFO_V3_W9_MLD_SMA_0_V2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

40

#define ADDR_CAM_W1_LEN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

400

#define DCTLINFO_V3_W9_MLD_SMA_1_V2 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

401

#define DCTLINFO_V3_W9_MLD_SMA_2_V2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

402

#define DCTLINFO_V3_W9_MLD_SMA_3_V2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

403

#define DCTLINFO_V3_W9_MLD_SMA_L_V2 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

404

#define DCTLINFO_V3_W9_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

405

#define DCTLINFO_V3_W10_MLD_SMA_4_V2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

406

#define DCTLINFO_V3_W10_MLD_SMA_5_V2 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

407

#define DCTLINFO_V3_W10_MLD_SMA_H_V2 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/cam.h

408

#define DCTLINFO_V3_W10_MLD_TMA_0_V2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

409

#define DCTLINFO_V3_W10_MLD_TMA_1_V2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

41

#define ADDR_CAM_W1_V1_IDX GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/cam.h

410

#define DCTLINFO_V3_W10_MLD_TMA_L_V2 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/cam.h

411

#define DCTLINFO_V3_W10_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

412

#define DCTLINFO_V3_W11_MLD_TMA_2_V2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

413

#define DCTLINFO_V3_W11_MLD_TMA_3_V2 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

414

#define DCTLINFO_V3_W11_MLD_TMA_4_V2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

415

#define DCTLINFO_V3_W11_MLD_TMA_5_V2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

416

#define DCTLINFO_V3_W11_MLD_TMA_H_V2 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

417

#define DCTLINFO_V3_W11_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

418

#define DCTLINFO_V3_W12_MLD_TA_BSSID_0_V2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

419

#define DCTLINFO_V3_W12_MLD_TA_BSSID_1_V2 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

42

#define ADDR_CAM_W1_V1_OFFSET GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

420

#define DCTLINFO_V3_W12_MLD_TA_BSSID_2_V2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

421

#define DCTLINFO_V3_W12_MLD_TA_BSSID_3_V2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

422

#define DCTLINFO_V3_W12_MLD_TA_BSSID_L_V2 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

423

#define DCTLINFO_V3_W12_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/cam.h

424

#define DCTLINFO_V3_W13_MLD_TA_BSSID_4_V2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

425

#define DCTLINFO_V3_W13_MLD_TA_BSSID_5_V2 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

426

#define DCTLINFO_V3_W13_MLD_TA_BSSID_H_V2 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/cam.h

427

#define DCTLINFO_V3_W13_HW_EXSEQ_MACID_V1 GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/cam.h

428

#define DCTLINFO_V3_W13_ALL GENMASK(24, 0)

drivers/net/wireless/realtek/rtw89/cam.h

43

#define ADDR_CAM_W1_V1_LEN GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

45

#define ADDR_CAM_W2_NET_TYPE GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/cam.h

46

#define ADDR_CAM_W2_BCN_HIT_COND GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/cam.h

47

#define ADDR_CAM_W2_HIT_RULE GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/cam.h

49

#define ADDR_CAM_W2_ADDR_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/cam.h

50

#define ADDR_CAM_W2_MASK_SEL GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/cam.h

51

#define ADDR_CAM_W2_SMA_HASH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

52

#define ADDR_CAM_W2_TMA_HASH GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

53

#define ADDR_CAM_W3_BSSID_CAM_IDX GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/cam.h

54

#define ADDR_CAM_W4_SMA0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

55

#define ADDR_CAM_W4_SMA1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

56

#define ADDR_CAM_W4_SMA2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

57

#define ADDR_CAM_W4_SMA3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

58

#define ADDR_CAM_W5_SMA4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

59

#define ADDR_CAM_W5_SMA5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

60

#define ADDR_CAM_W5_TMA0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

61

#define ADDR_CAM_W5_TMA1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

62

#define ADDR_CAM_W6_TMA2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

63

#define ADDR_CAM_W6_TMA3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

64

#define ADDR_CAM_W6_TMA4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

65

#define ADDR_CAM_W6_TMA5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/cam.h

66

#define ADDR_CAM_W8_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

67

#define ADDR_CAM_W8_PORT_INT GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/cam.h

68

#define ADDR_CAM_W8_TSF_SYNC GENMASK(13, 11)

drivers/net/wireless/realtek/rtw89/cam.h

71

#define ADDR_CAM_W8_TGT_IND GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/cam.h

72

#define ADDR_CAM_W8_FRM_TGT_IND GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/cam.h

73

#define ADDR_CAM_W8_V1_MACID GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/cam.h

74

#define ADDR_CAM_W8_V1_PORT_INT GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/cam.h

75

#define ADDR_CAM_W8_V1_TSF_SYNC GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/cam.h

81

#define ADDR_CAM_W9_AID12 GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/cam.h

82

#define ADDR_CAM_W9_AID12_0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

83

#define ADDR_CAM_W9_AID12_1 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/cam.h

88

#define ADDR_CAM_W9_SEC_ENT_MODE GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/cam.h

89

#define ADDR_CAM_W9_SEC_ENT0_KEYID GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/cam.h

90

#define ADDR_CAM_W9_SEC_ENT1_KEYID GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/cam.h

91

#define ADDR_CAM_W9_SEC_ENT2_KEYID GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/cam.h

92

#define ADDR_CAM_W9_SEC_ENT3_KEYID GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/cam.h

93

#define ADDR_CAM_W9_SEC_ENT4_KEYID GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/cam.h

94

#define ADDR_CAM_W9_SEC_ENT5_KEYID GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/cam.h

95

#define ADDR_CAM_W9_SEC_ENT6_KEYID GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/cam.h

96

#define ADDR_CAM_W10_SEC_ENT_VALID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/cam.h

97

#define ADDR_CAM_W10_SEC_ENT0 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/cam.h

98

#define ADDR_CAM_W10_SEC_ENT1 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/cam.h

99

#define ADDR_CAM_W10_SEC_ENT2 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/coex.c

1301

GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/coex.c

1307

GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/coex.c

2480

bit_map = GENMASK(2, 0);

drivers/net/wireless/realtek/rtw89/coex.c

2483

bit_map = GENMASK(2, 0) | BIT(8);

drivers/net/wireless/realtek/rtw89/coex.c

2486

bit_map = GENMASK(2, 0) | BIT(9);

drivers/net/wireless/realtek/rtw89/coex.c

2496

bit_map = GENMASK(6, 3);

drivers/net/wireless/realtek/rtw89/coex.c

2499

bit_map = GENMASK(6, 3) | BIT(8);

drivers/net/wireless/realtek/rtw89/coex.c

2502

bit_map = GENMASK(7, 3);

drivers/net/wireless/realtek/rtw89/coex.c

2505

bit_map = GENMASK(8, 3);

drivers/net/wireless/realtek/rtw89/coex.c

2514

bit_map = GENMASK(6, 0);

drivers/net/wireless/realtek/rtw89/coex.c

2517

bit_map = GENMASK(7, 0);

drivers/net/wireless/realtek/rtw89/coex.c

2521

bit_map = GENMASK(8, 0);

drivers/net/wireless/realtek/rtw89/coex.c

2524

bit_map = GENMASK(9, 0);

drivers/net/wireless/realtek/rtw89/coex.c

2534

bit_map = GENMASK(6, 2);

drivers/net/wireless/realtek/rtw89/coex.c

2537

bit_map = GENMASK(6, 2) | BIT(8);

drivers/net/wireless/realtek/rtw89/coex.c

2540

bit_map = GENMASK(8, 2);

drivers/net/wireless/realtek/rtw89/coex.c

2543

bit_map = GENMASK(9, 2);

drivers/net/wireless/realtek/rtw89/coex.c

3016

#define WL_TX_POWER_NO_BTC_CTRL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/coex.c

3017

#define WL_TX_POWER_ALL_TIME GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/coex.c

3018

#define WL_TX_POWER_WITH_BT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/coex.c

3019

#define WL_TX_POWER_INT_PART GENMASK(8, 2)

drivers/net/wireless/realtek/rtw89/coex.c

3020

#define WL_TX_POWER_FRA_PART GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/coex.c

438

BTC_BSCB_ALL = GENMASK(30, 0),

drivers/net/wireless/realtek/rtw89/coex.c

6568

#define BTC_SCB_INV_VALUE GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/coex.c

692

BTC_COEX_INFO_ALL = GENMASK(7, 0),

drivers/net/wireless/realtek/rtw89/coex.c

695

#define BTC_CXP_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/coex.c

711

BTC_WSCB_ALL = GENMASK(23, 0),

drivers/net/wireless/realtek/rtw89/coex.c

777

BTC_RESET_ALL = GENMASK(7, 0),

drivers/net/wireless/realtek/rtw89/coex.c

8028

#define BT_PROFILE_PROTOCOL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/coex.c

8824

ver_main = FIELD_GET(GENMASK(31, 24), RTW89_COEX_VERSION);

drivers/net/wireless/realtek/rtw89/coex.c

8825

ver_sub = FIELD_GET(GENMASK(23, 16), RTW89_COEX_VERSION);

drivers/net/wireless/realtek/rtw89/coex.c

8826

ver_hotfix = FIELD_GET(GENMASK(15, 8), RTW89_COEX_VERSION);

drivers/net/wireless/realtek/rtw89/coex.c

8827

id_branch = FIELD_GET(GENMASK(7, 0), RTW89_COEX_VERSION);

drivers/net/wireless/realtek/rtw89/coex.c

8832

ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw_coex);

drivers/net/wireless/realtek/rtw89/coex.c

8833

ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw_coex);

drivers/net/wireless/realtek/rtw89/coex.c

8834

ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw_coex);

drivers/net/wireless/realtek/rtw89/coex.c

8835

id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw_coex);

drivers/net/wireless/realtek/rtw89/coex.c

8839

ver_main = FIELD_GET(GENMASK(31, 24), chip->wlcx_desired);

drivers/net/wireless/realtek/rtw89/coex.c

8840

ver_sub = FIELD_GET(GENMASK(23, 16), chip->wlcx_desired);

drivers/net/wireless/realtek/rtw89/coex.c

8841

ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->wlcx_desired);

drivers/net/wireless/realtek/rtw89/coex.c

8856

ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw);

drivers/net/wireless/realtek/rtw89/coex.c

8857

ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw);

drivers/net/wireless/realtek/rtw89/coex.c

8858

ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw);

drivers/net/wireless/realtek/rtw89/coex.c

8859

id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw);

drivers/net/wireless/realtek/rtw89/coex.c

9070

u32 ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw_coex);

drivers/net/wireless/realtek/rtw89/coex.c

9608

id_to_ant(FIELD_GET(GENMASK(7, 0), dm->set_ant_path)),

drivers/net/wireless/realtek/rtw89/coex.h

154

#define B_BTC_BB_GNT_MUX GENMASK(20, 17)

drivers/net/wireless/realtek/rtw89/coex.h

155

#define B_BTC_BB_PRE_AGC_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/coex.h

39

#define BTC_RFK_PATH_MAP GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/coex.h

40

#define BTC_RFK_PHY_MAP GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/coex.h

41

#define BTC_RFK_BAND_MAP GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/core.c

5430

u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),

drivers/net/wireless/realtek/rtw89/core.h

2739

#define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/core.h

2740

#define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/core.h

2757

#define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/core.h

2758

#define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/core.h

2984

#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/core.h

658

RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),

drivers/net/wireless/realtek/rtw89/core.h

659

RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),

drivers/net/wireless/realtek/rtw89/core.h

660

RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),

drivers/net/wireless/realtek/rtw89/core.h

661

RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),

drivers/net/wireless/realtek/rtw89/core.h

67

#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/core.h

69

#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)

drivers/net/wireless/realtek/rtw89/core.h

72

#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)

drivers/net/wireless/realtek/rtw89/core.h

74

#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/core.h

81

#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/core.h

83

#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/core.h

88

#define RTW89_TF_PAD GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/core.h

92

le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))

drivers/net/wireless/realtek/rtw89/core.h

94

le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))

drivers/net/wireless/realtek/rtw89/core.h

96

le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))

drivers/net/wireless/realtek/rtw89/debug.c

4520

#define __DIAG_MAC_IO GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/efuse.c

10

#define EFUSE_B1_MSSDEVTYPE_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/efuse.c

11

#define EFUSE_B1_MSSCUSTIDX0_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/efuse.c

12

#define EFUSE_B2_MSSKEYNUM_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/efuse.c

19

#define EFUSE_B1_EXTERNALPN_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/efuse.c

20

#define EFUSE_B2_CUSTOMER_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/efuse.c

21

#define EFUSE_B2_SERIALNUM_MASK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/efuse.h

10

#define RTW89_EFUSE_BLOCK_ID_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/efuse.h

11

#define RTW89_EFUSE_BLOCK_SIZE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/efuse.h

16

#define EF_CV_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/efuse_be.c

195

#define EFUSE_HDR_CONST_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/efuse_be.c

196

#define EFUSE_HDR_PAGE_MASK GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/efuse_be.c

197

#define EFUSE_HDR_OFFSET_MASK GENMASK(16, 4)

drivers/net/wireless/realtek/rtw89/efuse_be.c

198

#define EFUSE_HDR_OFFSET_DAV_MASK GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/efuse_be.c

199

#define EFUSE_HDR_WORD_EN_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1001

#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1004

le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1006

GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/fw.h

101

#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1015

#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1018

le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));

drivers/net/wireless/realtek/rtw89/fw.h

102

#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1020

GENMASK(7, 4));

drivers/net/wireless/realtek/rtw89/fw.h

1029

#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1032

le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));

drivers/net/wireless/realtek/rtw89/fw.h

1034

GENMASK(11, 9));

drivers/net/wireless/realtek/rtw89/fw.h

109

#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

110

#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1113

#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1116

le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

1118

GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

1120

#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1123

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1125

GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

113

#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1141

#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1144

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1146

GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1148

#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

115

#define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1151

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtw89/fw.h

1153

GENMASK(21, 20));

drivers/net/wireless/realtek/rtw89/fw.h

1155

#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1158

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtw89/fw.h

1160

GENMASK(23, 22));

drivers/net/wireless/realtek/rtw89/fw.h

1162

#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1165

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1167

GENMASK(25, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1169

#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1172

le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));

drivers/net/wireless/realtek/rtw89/fw.h

1174

GENMASK(27, 26));

drivers/net/wireless/realtek/rtw89/fw.h

1205

#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1208

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1210

GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1215

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));

drivers/net/wireless/realtek/rtw89/fw.h

1217

GENMASK(3, 2));

drivers/net/wireless/realtek/rtw89/fw.h

1222

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));

drivers/net/wireless/realtek/rtw89/fw.h

1224

GENMASK(5, 4));

drivers/net/wireless/realtek/rtw89/fw.h

1229

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

1231

GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

1234

#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1237

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1239

GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1241

#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1244

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1246

GENMASK(16, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1255

#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1258

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));

drivers/net/wireless/realtek/rtw89/fw.h

1260

GENMASK(19, 18));

drivers/net/wireless/realtek/rtw89/fw.h

1264

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));

drivers/net/wireless/realtek/rtw89/fw.h

1266

GENMASK(21, 20));

drivers/net/wireless/realtek/rtw89/fw.h

1271

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));

drivers/net/wireless/realtek/rtw89/fw.h

1273

GENMASK(23, 22));

drivers/net/wireless/realtek/rtw89/fw.h

1275

#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1278

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1280

GENMASK(27, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1285

le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtw89/fw.h

1287

GENMASK(31, 30));

drivers/net/wireless/realtek/rtw89/fw.h

1289

#define SET_CMC_TBL_MASK_NC GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1292

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1294

GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1296

#define SET_CMC_TBL_MASK_NR GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1299

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));

drivers/net/wireless/realtek/rtw89/fw.h

1301

GENMASK(5, 3));

drivers/net/wireless/realtek/rtw89/fw.h

1303

#define SET_CMC_TBL_MASK_NG GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1306

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

1308

GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

1310

#define SET_CMC_TBL_MASK_CB GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1313

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1315

GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1317

#define SET_CMC_TBL_MASK_CS GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1320

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

1322

GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

1352

#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1355

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1357

GENMASK(24, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1359

#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1362

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));

drivers/net/wireless/realtek/rtw89/fw.h

1364

GENMASK(27, 25));

drivers/net/wireless/realtek/rtw89/fw.h

1369

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));

drivers/net/wireless/realtek/rtw89/fw.h

1371

GENMASK(29, 28));

drivers/net/wireless/realtek/rtw89/fw.h

1374

#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1377

le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));

drivers/net/wireless/realtek/rtw89/fw.h

1379

GENMASK(31, 30));

drivers/net/wireless/realtek/rtw89/fw.h

1418

#define CCTLINFO_G7_C0_MACID GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1421

#define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1422

#define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1424

#define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1434

#define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1435

#define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1436

#define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1437

#define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1438

#define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1439

#define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1440

#define CCTLINFO_G7_W1_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1441

#define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1446

#define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1448

#define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/fw.h

1450

#define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1452

#define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1453

#define CCTLINFO_G7_W2_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1454

#define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1455

#define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1457

#define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1459

#define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1460

#define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/fw.h

1461

#define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)

drivers/net/wireless/realtek/rtw89/fw.h

1462

#define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/fw.h

1467

#define CCTLINFO_G7_W3_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1468

#define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1470

#define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1478

#define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1479

#define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1480

#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1481

#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/fw.h

1482

#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1483

#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

1484

#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1485

#define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1486

#define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1487

#define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1488

#define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1489

#define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1490

#define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1492

#define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1493

#define CCTLINFO_G7_W7_NC GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1494

#define CCTLINFO_G7_W7_NR GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/fw.h

1495

#define CCTLINFO_G7_W7_NG GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

1496

#define CCTLINFO_G7_W7_CB GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1497

#define CCTLINFO_G7_W7_CS GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1501

#define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1502

#define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/fw.h

1503

#define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1512

#define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1513

#define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1514

#define CCTLINFO_G7_W8_ALL GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1516

#define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1517

#define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1518

#define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1519

#define CCTLINFO_G7_W14_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1520

#define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1521

#define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1522

#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1523

#define CCTLINFO_G7_W15_ALL GENMASK(27, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1561

#define BE_CCTL_INFO_C0_V1_MACID GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1564

#define BE_CCTL_INFO_W0_DATARATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1565

#define BE_CCTL_INFO_W0_DATA_GI_LTF GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1567

#define BE_CCTL_INFO_W0_ARFR_CTRL GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1577

#define BE_CCTL_INFO_W0_AMPDU_DENSITY GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1578

#define BE_CCTL_INFO_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1579

#define BE_CCTL_INFO_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1580

#define BE_CCTL_INFO_W1_RTS_TXCNT_LMT GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1581

#define BE_CCTL_INFO_W1_RTSRATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1582

#define BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1583

#define BE_CCTL_INFO_W1_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1584

#define BE_CCTL_INFO_W2_DATA_TX_CNT_LMT GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1589

#define BE_CCTL_INFO_W2_CCA_RTS GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1591

#define BE_CCTL_INFO_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/fw.h

1593

#define BE_CCTL_INFO_W2_AMPDU_MAX_LEN GENMASK(26, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1595

#define BE_CCTL_INFO_W2_AMPDU_MAX_TIME GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1596

#define BE_CCTL_INFO_W2_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1597

#define BE_CCTL_INFO_W3_MAX_AGG_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1598

#define BE_CCTL_INFO_W3_DATA_BW GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1600

#define BE_CCTL_INFO_W3_BA_BMAP GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1602

#define BE_CCTL_INFO_W3_VO_LFTIME_SEL GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1603

#define BE_CCTL_INFO_W3_VI_LFTIME_SEL GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/fw.h

1604

#define BE_CCTL_INFO_W3_BE_LFTIME_SEL GENMASK(24, 22)

drivers/net/wireless/realtek/rtw89/fw.h

1605

#define BE_CCTL_INFO_W3_BK_LFTIME_SEL GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/fw.h

1610

#define BE_CCTL_INFO_W3_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1611

#define BE_CCTL_INFO_W4_MULTI_PORT_ID GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1613

#define BE_CCTL_INFO_W4_MBSSID GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1614

#define BE_CCTL_INFO_W4_TID_DISABLE_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1615

#define BE_CCTL_INFO_W4_ACT_SUBCH_CBW GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1616

#define BE_CCTL_INFO_W4_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1617

#define BE_CCTL_INFO_W5_ADDR_CAM_INDEX_V1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1618

#define BE_CCTL_INFO_W5_SR_MCS_SU GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1626

#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1 GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/fw.h

1627

#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1 GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1628

#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1 GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/fw.h

1629

#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1 GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1630

#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1 GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/fw.h

1631

#define BE_CCTL_INFO_W5_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1632

#define BE_CCTL_INFO_W6_AID12_PAID GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1633

#define BE_CCTL_INFO_W6_RESP_REF_RATE GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1635

#define BE_CCTL_INFO_W6_ALL (BIT(31) | GENMASK(23, 0))

drivers/net/wireless/realtek/rtw89/fw.h

1636

#define BE_CCTL_INFO_W7_NC GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1637

#define BE_CCTL_INFO_W7_NR GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/fw.h

1638

#define BE_CCTL_INFO_W7_NG GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

1639

#define BE_CCTL_INFO_W7_CB GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1640

#define BE_CCTL_INFO_W7_CS GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1644

#define BE_CCTL_INFO_W7_CSI_FIX_RATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1645

#define BE_CCTL_INFO_W7_CSI_BW GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/fw.h

1646

#define BE_CCTL_INFO_W7_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1655

#define BE_CCTL_INFO_W8_CTRL_CNT_V1 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1656

#define BE_CCTL_INFO_W8_RESP_SEC_TYPE GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1657

#define BE_CCTL_INFO_W8_ALL GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1658

#define BE_CCTL_INFO_W9_EMLSR_TRANS_DLY GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1659

#define BE_CCTL_INFO_W9_ALL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1660

#define BE_CCTL_INFO_W10_SW_EHT_NLTF GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1662

#define BE_CCTL_INFO_W10_ALL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1663

#define BE_CCTL_INFO_W14_VO_CURR_RATE GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1664

#define BE_CCTL_INFO_W14_VI_CURR_RATE GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1665

#define BE_CCTL_INFO_W14_BE_CURR_RATE_L GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1666

#define BE_CCTL_INFO_W14_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1667

#define BE_CCTL_INFO_W15_BE_CURR_RATE_H GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1668

#define BE_CCTL_INFO_W15_BK_CURR_RATE GENMASK(15, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1669

#define BE_CCTL_INFO_W15_MGNT_CURR_RATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1670

#define BE_CCTL_INFO_W15_ALL GENMASK(27, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1678

#define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1679

#define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1680

#define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1681

#define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1682

#define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1683

#define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1684

#define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1685

#define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1686

#define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/fw.h

1688

#define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/fw.h

1689

#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/fw.h

1690

#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)

drivers/net/wireless/realtek/rtw89/fw.h

1691

#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/fw.h

1692

#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)

drivers/net/wireless/realtek/rtw89/fw.h

1697

#define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)

drivers/net/wireless/realtek/rtw89/fw.h

1732

#define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1733

#define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1734

#define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1735

#define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1736

#define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1737

#define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1738

#define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1739

#define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1740

#define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/fw.h

1741

#define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1743

#define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/fw.h

1744

#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/fw.h

1745

#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)

drivers/net/wireless/realtek/rtw89/fw.h

1746

#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/fw.h

1747

#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)

drivers/net/wireless/realtek/rtw89/fw.h

1752

#define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)

drivers/net/wireless/realtek/rtw89/fw.h

1753

#define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1754

#define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1755

#define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1756

#define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1757

#define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1758

#define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1759

#define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1760

#define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1761

#define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1762

#define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1770

#define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1771

#define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1772

#define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1779

#define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1780

#define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1781

#define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1782

#define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/fw.h

1783

#define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1784

#define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1785

#define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1791

#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1792

#define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1793

#define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1794

#define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)

drivers/net/wireless/realtek/rtw89/fw.h

1795

#define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)

drivers/net/wireless/realtek/rtw89/fw.h

1796

#define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/fw.h

1797

#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1815

#define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1818

#define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

1821

#define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/fw.h

1822

#define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1823

#define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/fw.h

1824

#define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/fw.h

1825

#define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1826

#define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)

drivers/net/wireless/realtek/rtw89/fw.h

1827

#define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/fw.h

1828

#define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1830

#define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1837

#define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1838

#define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/fw.h

1839

#define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1840

#define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1850

le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1855

le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1860

le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1865

le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1870

le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1875

le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1880

le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1885

le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1890

le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1895

le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1905

#define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/fw.h

1906

#define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1907

#define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1908

#define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1909

#define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/fw.h

1910

#define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1913

#define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/fw.h

1922

#define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

1923

#define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

1924

#define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

1925

#define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/fw.h

1926

#define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1930

#define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

1936

#define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

1937

#define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/fw.h

1942

le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

1947

le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

1952

le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

1957

le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));

drivers/net/wireless/realtek/rtw89/fw.h

1962

le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

1987

le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2084

#define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2088

le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2093

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2098

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

2103

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

2108

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2113

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2118

le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2123

le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2128

le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2133

le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2138

le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2143

le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2148

le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));

drivers/net/wireless/realtek/rtw89/fw.h

2153

le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

2173

le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2178

le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

2183

le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

2188

le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2200

#define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2201

#define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2202

#define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2220

#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2264

le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

2277

#define RTW89_H2C_WOW_CAM_UPD_W0_IDX GENMASK(7, 1)

drivers/net/wireless/realtek/rtw89/fw.h

2278

#define RTW89_H2C_WOW_CAM_UPD_WKFM0 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2279

#define RTW89_H2C_WOW_CAM_UPD_WKFM1 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2280

#define RTW89_H2C_WOW_CAM_UPD_WKFM2 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2281

#define RTW89_H2C_WOW_CAM_UPD_WKFM3 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2282

#define RTW89_H2C_WOW_CAM_UPD_W5_CRC GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2303

#define RTW89_H2C_WOW_PLD_CAM_UPD_W0_IDX GENMASK(7, 1)

drivers/net/wireless/realtek/rtw89/fw.h

2304

#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM0 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2305

#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM1 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2306

#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM2 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2307

#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM3 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2312

#define RTW89_H2C_WOW_PLD_CAM_UPD_W6_CRC GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2328

#define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2329

#define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2330

#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2331

#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2332

#define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)

drivers/net/wireless/realtek/rtw89/fw.h

2341

#define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2342

#define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2343

#define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2411

u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2416

u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

25

#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2511

#define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/fw.h

2512

#define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

2517

#define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/fw.h

2532

u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2537

u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2607

u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));

drivers/net/wireless/realtek/rtw89/fw.h

2622

u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

2632

u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));

drivers/net/wireless/realtek/rtw89/fw.h

2637

u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2642

u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2647

le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2652

le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2657

le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2662

le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2667

le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2677

u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));

drivers/net/wireless/realtek/rtw89/fw.h

2692

u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

27

#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2702

u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));

drivers/net/wireless/realtek/rtw89/fw.h

2707

u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2712

u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2717

le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2722

le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2727

le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2742

le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));

drivers/net/wireless/realtek/rtw89/fw.h

2767

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));

drivers/net/wireless/realtek/rtw89/fw.h

2772

u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2777

u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2782

u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2787

u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2792

u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2797

u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

28

#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

2802

u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2807

u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2812

u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2817

u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2822

u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2827

u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2832

le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2837

le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2842

le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2847

le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2852

le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2857

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2862

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));

drivers/net/wireless/realtek/rtw89/fw.h

2867

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

2872

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2877

le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));

drivers/net/wireless/realtek/rtw89/fw.h

2882

le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

2887

le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));

drivers/net/wireless/realtek/rtw89/fw.h

2892

le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));

drivers/net/wireless/realtek/rtw89/fw.h

2905

#define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2906

#define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2907

#define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2908

#define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2909

#define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2910

#define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)

drivers/net/wireless/realtek/rtw89/fw.h

2911

#define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2914

#define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/fw.h

2915

#define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2921

#define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2922

#define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2923

#define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2924

#define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2925

#define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2926

#define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2927

#define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2928

#define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2929

#define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2942

#define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2943

#define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2944

#define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2945

#define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2946

#define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2947

#define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/fw.h

2952

#define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)

drivers/net/wireless/realtek/rtw89/fw.h

2954

#define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/fw.h

2955

#define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2956

#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2957

#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2958

#define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2959

#define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2960

#define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2961

#define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2962

#define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2963

#define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2964

#define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

2965

#define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2966

#define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

2967

#define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2968

#define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2969

#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

2970

#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

2971

#define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3002

#define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3003

#define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3004

#define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3006

#define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/fw.h

3007

#define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/fw.h

3011

#define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/fw.h

3012

#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/fw.h

3013

#define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3014

#define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3015

#define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3016

#define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3017

#define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3018

#define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3019

#define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3020

#define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3027

#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3028

#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/fw.h

3029

#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3030

#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3040

#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3041

#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3042

#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/fw.h

3043

#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/fw.h

3045

#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3046

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3047

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3048

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/fw.h

3049

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/fw.h

3050

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3051

#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3052

#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3053

#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3054

#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3056

#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3057

#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3058

#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3059

#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3060

#define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3077

#define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3078

#define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/fw.h

3079

#define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3082

#define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3083

#define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3084

#define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/fw.h

3086

#define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3087

#define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3088

#define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3089

#define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3090

#define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3091

#define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3092

#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3093

#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3094

#define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3095

#define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3096

#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3097

#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3098

#define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3099

#define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3100

#define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3101

#define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3102

#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3103

#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3104

#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3105

#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3106

#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3107

#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3113

#define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3120

#define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3121

#define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3125

le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3130

le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3135

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));

drivers/net/wireless/realtek/rtw89/fw.h

3140

le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3170

le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3180

le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3195

le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));

drivers/net/wireless/realtek/rtw89/fw.h

3200

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3236

le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3241

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3246

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3251

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

3256

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3261

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));

drivers/net/wireless/realtek/rtw89/fw.h

3266

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/fw.h

3286

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));

drivers/net/wireless/realtek/rtw89/fw.h

3291

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));

drivers/net/wireless/realtek/rtw89/fw.h

3311

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));

drivers/net/wireless/realtek/rtw89/fw.h

3316

le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3326

le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3331

le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3356

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3366

le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));

drivers/net/wireless/realtek/rtw89/fw.h

3371

le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));

drivers/net/wireless/realtek/rtw89/fw.h

3376

le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3386

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

3391

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3396

le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3401

le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3406

le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3416

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3426

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3439

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3444

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3449

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3454

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3459

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3464

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3475

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3480

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3485

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3490

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

3508

le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3520

le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

3525

le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

3530

le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/fw.h

3536

le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3542

le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3548

le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3554

le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

3616

#define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3617

#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3622

#define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3623

#define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3624

#define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3625

#define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/fw.h

3628

#define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3629

#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3630

#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3631

#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3639

#define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3641

#define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3642

#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3643

#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3654

#define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3655

#define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3656

#define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3677

#define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3678

#define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3679

#define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3685

#define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3689

#define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3690

#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

37

#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3707

#define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3708

#define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3727

#define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3729

#define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3730

#define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3746

#define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3747

#define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

3748

#define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3749

#define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/fw.h

3750

#define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3770

#define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3771

#define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3773

#define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3774

#define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3793

#define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3794

#define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)

drivers/net/wireless/realtek/rtw89/fw.h

3795

#define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3796

#define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3820

#define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3821

#define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)

drivers/net/wireless/realtek/rtw89/fw.h

3822

#define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3823

#define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3824

#define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3825

#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3828

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))

drivers/net/wireless/realtek/rtw89/fw.h

3830

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))

drivers/net/wireless/realtek/rtw89/fw.h

3832

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw89/fw.h

3834

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))

drivers/net/wireless/realtek/rtw89/fw.h

3861

#define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3862

#define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3)

drivers/net/wireless/realtek/rtw89/fw.h

3871

#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3872

#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3873

#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/fw.h

3874

#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3882

#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3883

#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3885

#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3886

#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3887

#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/fw.h

3888

#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/fw.h

39

#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3931

#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3932

#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3933

#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/fw.h

3934

#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3935

#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3936

#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \

drivers/net/wireless/realtek/rtw89/fw.h

3937

FIELD_PREP(GENMASK(2, 0), mcs))

drivers/net/wireless/realtek/rtw89/fw.h

3940

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw89/fw.h

3942

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))

drivers/net/wireless/realtek/rtw89/fw.h

3944

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))

drivers/net/wireless/realtek/rtw89/fw.h

3958

#define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3959

#define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3960

#define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/fw.h

3961

#define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3962

#define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3963

#define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/fw.h

3964

#define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/fw.h

3966

#define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3967

#define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3968

#define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3969

#define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3970

#define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

3971

#define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

3974

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))

drivers/net/wireless/realtek/rtw89/fw.h

3976

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw89/fw.h

3979

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))

drivers/net/wireless/realtek/rtw89/fw.h

3981

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))

drivers/net/wireless/realtek/rtw89/fw.h

3983

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw89/fw.h

3995

#define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

3996

#define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3997

#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/fw.h

3998

#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/fw.h

40

#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

4022

#define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4023

#define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

4024

#define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/fw.h

4038

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4040

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw89/fw.h

4042

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))

drivers/net/wireless/realtek/rtw89/fw.h

4044

le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4046

le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4048

le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4050

le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4053

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4055

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))

drivers/net/wireless/realtek/rtw89/fw.h

4057

le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))

drivers/net/wireless/realtek/rtw89/fw.h

4059

le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4061

le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))

drivers/net/wireless/realtek/rtw89/fw.h

4068

#define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4069

#define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

41

#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4100

#define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4109

#define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4110

#define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

4118

#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4119

#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4120

#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4127

#define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4158

#define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4166

#define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4167

#define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4177

#define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/fw.h

4178

#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/fw.h

4179

#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4180

#define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

4181

#define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4182

#define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

4189

#define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4190

#define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4191

#define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4197

#define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4198

#define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4199

#define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)

drivers/net/wireless/realtek/rtw89/fw.h

42

#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

428

#define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)

drivers/net/wireless/realtek/rtw89/fw.h

429

#define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/fw.h

43

#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

430

#define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

433

#define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/fw.h

438

#define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/fw.h

439

#define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/fw.h

44

#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

442

#define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

443

#define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)

drivers/net/wireless/realtek/rtw89/fw.h

445

#define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4494

#define H2C_HDR_CAT GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4495

#define H2C_HDR_CLASS GENMASK(7, 2)

drivers/net/wireless/realtek/rtw89/fw.h

4496

#define H2C_HDR_FUNC GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4497

#define H2C_HDR_DEL_TYPE GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4498

#define H2C_HDR_H2C_SEQ GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

4499

#define H2C_HDR_TOTAL_LEN GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/fw.h

450

#define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/fw.h

451

#define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

452

#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/fw.h

453

#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)

drivers/net/wireless/realtek/rtw89/fw.h

454

#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/fw.h

456

#define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

459

#define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/fw.h

460

#define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29)

drivers/net/wireless/realtek/rtw89/fw.h

469

#define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/fw.h

470

#define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/fw.h

471

#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

472

#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4748

#define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4750

#define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/fw.h

4754

#define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4755

#define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

4756

#define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4757

#define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

4758

#define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

4759

#define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

476

le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

4760

#define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

4761

#define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

481

le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));

drivers/net/wireless/realtek/rtw89/fw.h

486

le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/fw.h

49

#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

491

le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));

drivers/net/wireless/realtek/rtw89/fw.h

50

#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

506

le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

51

#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

511

le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

516

le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

52

#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

521

le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

526

le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));

drivers/net/wireless/realtek/rtw89/fw.h

53

#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

54

#define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

541

le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));

drivers/net/wireless/realtek/rtw89/fw.h

546

le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));

drivers/net/wireless/realtek/rtw89/fw.h

548

#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)

drivers/net/wireless/realtek/rtw89/fw.h

549

#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/fw.h

550

#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/fw.h

551

#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

56

#define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

57

#define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

575

#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

576

#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

577

#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/fw.h

578

#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/fw.h

58

#define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

581

#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

59

#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

596

#define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

597

#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

598

#define FW_HDR_W1_SUBVERSION GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

599

#define FW_HDR_W1_SUBINDEX GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

60

#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

600

#define FW_HDR_W2_COMMITID GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

601

#define FW_HDR_W3_LEN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

602

#define FW_HDR_W3_HDR_VER GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

603

#define FW_HDR_W4_MONTH GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

604

#define FW_HDR_W4_DATE GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

605

#define FW_HDR_W4_HOUR GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

606

#define FW_HDR_W4_MIN GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

607

#define FW_HDR_W5_YEAR GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

608

#define FW_HDR_W6_SEC_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

609

#define FW_HDR_W7_PART_SIZE GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

61

#define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

611

#define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)

drivers/net/wireless/realtek/rtw89/fw.h

612

#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

62

#define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

621

#define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

622

#define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

623

#define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/fw.h

624

#define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/fw.h

627

#define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

629

#define FORMATTED_MSSC_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

630

#define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/fw.h

648

#define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

649

#define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

650

#define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

651

#define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

652

#define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/fw.h

653

#define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

654

#define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

655

#define FW_HDR_V1_W4_MONTH GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

656

#define FW_HDR_V1_W4_DATE GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

657

#define FW_HDR_V1_W4_HOUR GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

658

#define FW_HDR_V1_W4_MIN GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

659

#define FW_HDR_V1_W5_YEAR GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

66

#define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

660

#define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

661

#define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

663

#define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/fw.h

665

#define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)

drivers/net/wireless/realtek/rtw89/fw.h

68

#define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

69

#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

70

#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

71

#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

714

le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));

drivers/net/wireless/realtek/rtw89/fw.h

72

#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

721

#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

724

le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

726

GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

73

#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

735

#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

738

le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

74

#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

740

GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

742

#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

745

le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));

drivers/net/wireless/realtek/rtw89/fw.h

747

GENMASK(14, 12));

drivers/net/wireless/realtek/rtw89/fw.h

75

#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

756

#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

759

le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

76

#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

761

GENMASK(19, 16));

drivers/net/wireless/realtek/rtw89/fw.h

77

#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

78

#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

79

#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

80

#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

81

#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

812

#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

815

le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

817

GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

819

#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

82

#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

822

le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

824

GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/fw.h

83

#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

84

#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

847

#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

85

#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

850

le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));

drivers/net/wireless/realtek/rtw89/fw.h

852

GENMASK(15, 12));

drivers/net/wireless/realtek/rtw89/fw.h

854

#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/fw.h

857

le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));

drivers/net/wireless/realtek/rtw89/fw.h

859

GENMASK(24, 16));

drivers/net/wireless/realtek/rtw89/fw.h

86

#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

868

#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

87

#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

871

le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

873

GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

875

#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/fw.h

878

le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));

drivers/net/wireless/realtek/rtw89/fw.h

88

#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

880

GENMASK(5, 0));

drivers/net/wireless/realtek/rtw89/fw.h

89

#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/fw.h

90

#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/fw.h

91

#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

910

#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

913

le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

915

GENMASK(11, 10));

drivers/net/wireless/realtek/rtw89/fw.h

92

#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/fw.h

924

#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

927

le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));

drivers/net/wireless/realtek/rtw89/fw.h

929

GENMASK(14, 13));

drivers/net/wireless/realtek/rtw89/fw.h

931

#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/fw.h

934

le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));

drivers/net/wireless/realtek/rtw89/fw.h

936

GENMASK(26, 16));

drivers/net/wireless/realtek/rtw89/fw.h

94

#define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

945

#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

948

le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

95

#define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/fw.h

950

GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

952

#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/fw.h

955

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

957

GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/fw.h

959

#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/fw.h

962

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

964

GENMASK(9, 8));

drivers/net/wireless/realtek/rtw89/fw.h

966

#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

969

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));

drivers/net/wireless/realtek/rtw89/fw.h

971

GENMASK(18, 16));

drivers/net/wireless/realtek/rtw89/fw.h

973

#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

976

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));

drivers/net/wireless/realtek/rtw89/fw.h

978

GENMASK(21, 19));

drivers/net/wireless/realtek/rtw89/fw.h

980

#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

983

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));

drivers/net/wireless/realtek/rtw89/fw.h

985

GENMASK(24, 22));

drivers/net/wireless/realtek/rtw89/fw.h

987

#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/fw.h

990

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));

drivers/net/wireless/realtek/rtw89/fw.h

992

GENMASK(27, 25));

drivers/net/wireless/realtek/rtw89/fw.h

994

#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/fw.h

997

le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/fw.h

999

GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/mac.c

4327

u8 sh = FIELD_GET(GENMASK(4, 0), macid);

drivers/net/wireless/realtek/rtw89/mac.h

715

#define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)

drivers/net/wireless/realtek/rtw89/mac.h

716

#define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/mac80211.c

450

aifsn = FIELD_GET(GENMASK(3, 0), mu_edca->aifsn);

drivers/net/wireless/realtek/rtw89/pci.c

1478

txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma));

drivers/net/wireless/realtek/rtw89/pci.c

1479

txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma));

drivers/net/wireless/realtek/rtw89/pci.h

1017

#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/pci.h

1033

#define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/pci.h

1034

#define B_BE_APPEND_LEN_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/pci.h

107

#define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1109

#define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1124

#define RTW89_PCIE_SUPPORT_GEN_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1126

#define RTW89_BCFG_LINK_SPEED_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/pci.h

1130

#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1138

#define RTW89_L1DLY_MASK GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/pci.h

1139

#define RTW89_L0DLY_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/pci.h

116

#define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/pci.h

125

#define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/pci.h

137

#define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/pci.h

140

#define FILTER_OUT_EQ_MASK GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/pci.h

142

#define REG_FILTER_OUT_MASK GENMASK(6, 2)

drivers/net/wireless/realtek/rtw89/pci.h

1458

#define RTW89_PCI_TXBD_OPT_DMA_HI GENMASK(13, 6)

drivers/net/wireless/realtek/rtw89/pci.h

1473

#define RTW89_PCI_ADDR_HIGH_MASK GENMASK(13, 6)

drivers/net/wireless/realtek/rtw89/pci.h

1474

#define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))

drivers/net/wireless/realtek/rtw89/pci.h

1486

#define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1487

#define B_PCIADDR_HIGH_SEL_V1_MASK GENMASK(14, 11)

drivers/net/wireless/realtek/rtw89/pci.h

1495

#define RTW89_PCI_RPP_SEQ GENMASK(30, 16)

drivers/net/wireless/realtek/rtw89/pci.h

1496

#define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/pci.h

1497

#define RTW89_PCI_RPP_QSEL GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/pci.h

1498

#define RTW89_PCI_RPP_MACID GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1504

#define RTW89_PCI_RPP_W0_MACID_V1_MASK GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1505

#define RTW89_PCI_RPP_W0_DMA_CH_MASK GENMASK(13, 10)

drivers/net/wireless/realtek/rtw89/pci.h

1506

#define RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK GENMASK(16, 14)

drivers/net/wireless/realtek/rtw89/pci.h

1507

#define RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK GENMASK(31, 17)

drivers/net/wireless/realtek/rtw89/pci.h

1508

#define RTW89_PCI_RPP_W1_QSEL_V1_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1520

#define RTW89_PCI_RXBD_OPT_DMA_HI GENMASK(13, 6)

drivers/net/wireless/realtek/rtw89/pci.h

1526

#define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/pci.h

1527

#define RTW89_PCI_RXBD_TAG GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/pci.h

16

#define OOBS_SEN_MASK GENMASK(5, 1)

drivers/net/wireless/realtek/rtw89/pci.h

174

#define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/pci.h

177

#define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/pci.h

22

#define MANUAL_LVL_MASK GENMASK(8, 5)

drivers/net/wireless/realtek/rtw89/pci.h

29

#define ADDR_SEL_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/pci.h

324

#define B_BE_RTK_ASPM_CTRL_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/pci.h

337

#define B_BE_ELBI_PHY_REMAP_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/pci.h

34

#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/pci.h

341

#define B_BE_RTK_LDO_POWER_LATENCY_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/pci.h

342

#define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/pci.h

343

#define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/pci.h

39

#define BAC_AUTOK_N_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/pci.h

45

#define OOBS_LEVEL_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/pci.h

46

#define OFFSET_CAL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/pci.h

48

#define B_AX_DEGLITCH GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/pci.h

50

#define B_AX_RXEN GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/pci.h

554

#define TXBD_HW_IDX_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/pci.h

555

#define TXBD_HOST_IDX_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/pci.h

56

#define B_AX_DIV GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/pci.h

617

#define B_AX_DESC_NUM_MSK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/pci.h

64

#define B_AX_DBI_WREN_MSK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/pci.h

65

#define B_AX_DBI_ADDR_MSK GENMASK(11, 2)

drivers/net/wireless/realtek/rtw89/pci.h

66

#define B_AX_DBI_2LSB GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

665

#define BDRAM_SIDX_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

666

#define BDRAM_MAX_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/pci.h

667

#define BDRAM_MIN_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/pci.h

676

#define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14)

drivers/net/wireless/realtek/rtw89/pci.h

680

#define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/pci.h

705

#define B_AX_TX_STOP1_ALL GENMASK(18, 8)

drivers/net/wireless/realtek/rtw89/pci.h

720

#define B_AX_TX_STOP2_ALL GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

734

#define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/pci.h

739

#define B_AX_RXBD_CLR_ALL GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

744

#define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

805

#define B_BE_TX_START_OFFSET_MASK GENMASK(12, 4)

drivers/net/wireless/realtek/rtw89/pci.h

806

#define B_BE_TX_NUM_SEL_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/pci.h

813

#define B_BE_RX_START_OFFSET_MASK GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/pci.h

814

#define B_BE_RX_NUM_SEL_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/pci.h

83

#define B_AX_ASPM_CTRL_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/pci.h

867

#define B_BE_TX_ACQ_DESA_L_MASK GENMASK(31, 3)

drivers/net/wireless/realtek/rtw89/pci.h

869

#define B_BE_TX_ACQ_DESA_H_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

871

#define B_BE_TX_NACQ_DESA_L_MASK GENMASK(31, 3)

drivers/net/wireless/realtek/rtw89/pci.h

873

#define B_BE_TX_NACQ_DESA_H_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

881

#define B_BE_RX_HOST0_DESA_L_MASK GENMASK(31, 3)

drivers/net/wireless/realtek/rtw89/pci.h

883

#define B_BE_RX_HOST0_DESA_H_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

892

#define B_AX_WD_ITVL_IDLE GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/pci.h

893

#define B_AX_WD_ITVL_ACT GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/pci.h

894

#define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/pci.h

902

#define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/pci.h

907

#define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/pci.h

908

#define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

915

#define B_AX_MIT_RXTIMER_UNIT_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/pci.h

916

#define B_AX_MIT_RXCOUNTER_MATCH_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/pci.h

917

#define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

922

#define B_AX_CPL_STATUS_MASK GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/pci.h

935

#define B_AX_LBC_TIMER GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/pci.h

944

#define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/pci.h

948

#define B_AX_MAX_TAG_NUM GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/pci.h

972

#define B_BE_END_PL1_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/pci.h

973

#define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/pci.h

976

#define B_BE_PCIE_MIT0_RX_TMR_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/pci.h

981

#define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/pci.h

984

#define B_BE_PCIE_RX_MIT0_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/pci.h

985

#define B_BE_PCIE_TX_MIT0_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/pci.h

986

#define B_BE_PCIE_RX_MIT0_TMR_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/pci.h

987

#define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/phy.c

1056

val = u32_encode_bits(rf_path, GENMASK(10, 8)) |

drivers/net/wireless/realtek/rtw89/phy.c

1057

u32_encode_bits(addr, GENMASK(7, 0));

drivers/net/wireless/realtek/rtw89/phy.c

3070

val = FIELD_PREP(GENMASK(7, 0), v[0]) |

drivers/net/wireless/realtek/rtw89/phy.c

3071

FIELD_PREP(GENMASK(15, 8), v[1]) |

drivers/net/wireless/realtek/rtw89/phy.c

3072

FIELD_PREP(GENMASK(23, 16), v[2]) |

drivers/net/wireless/realtek/rtw89/phy.c

3073

FIELD_PREP(GENMASK(31, 24), v[3]);

drivers/net/wireless/realtek/rtw89/phy.c

3102

val = FIELD_PREP(GENMASK(3, 0), v[0]) |

drivers/net/wireless/realtek/rtw89/phy.c

3103

FIELD_PREP(GENMASK(7, 4), v[1]) |

drivers/net/wireless/realtek/rtw89/phy.c

3104

FIELD_PREP(GENMASK(11, 8), v[2]) |

drivers/net/wireless/realtek/rtw89/phy.c

3105

FIELD_PREP(GENMASK(15, 12), v[3]) |

drivers/net/wireless/realtek/rtw89/phy.c

3106

FIELD_PREP(GENMASK(19, 16), v[4]);

drivers/net/wireless/realtek/rtw89/phy.c

3109

GENMASK(19, 0), val);

drivers/net/wireless/realtek/rtw89/phy.c

3137

val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |

drivers/net/wireless/realtek/rtw89/phy.c

3138

FIELD_PREP(GENMASK(15, 8), ptr[1]) |

drivers/net/wireless/realtek/rtw89/phy.c

3139

FIELD_PREP(GENMASK(23, 16), ptr[2]) |

drivers/net/wireless/realtek/rtw89/phy.c

3140

FIELD_PREP(GENMASK(31, 24), ptr[3]);

drivers/net/wireless/realtek/rtw89/phy.c

3172

val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |

drivers/net/wireless/realtek/rtw89/phy.c

3173

FIELD_PREP(GENMASK(15, 8), ptr[1]) |

drivers/net/wireless/realtek/rtw89/phy.c

3174

FIELD_PREP(GENMASK(23, 16), ptr[2]) |

drivers/net/wireless/realtek/rtw89/phy.c

3175

FIELD_PREP(GENMASK(31, 24), ptr[3]);

drivers/net/wireless/realtek/rtw89/phy.c

5066

s32 min_cfo_ub = GENMASK(30, 0);

drivers/net/wireless/realtek/rtw89/phy.c

6670

val &= ~(GENMASK(RTW89_PHYSTS_IE07_CMN_EXT_PATH_D,

drivers/net/wireless/realtek/rtw89/phy.c

7980

#define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/phy.c

7981

#define RTW89_CH_OFFSET_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/phy.h

13

#define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)

drivers/net/wireless/realtek/rtw89/phy.h

15

#define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)

drivers/net/wireless/realtek/rtw89/phy.h

16

#define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \

drivers/net/wireless/realtek/rtw89/phy.h

17

FIELD_PREP(GENMASK(7, 0), cv))

drivers/net/wireless/realtek/rtw89/phy.h

19

#define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)

drivers/net/wireless/realtek/rtw89/phy.h

20

#define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)

drivers/net/wireless/realtek/rtw89/phy.h

21

#define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)

drivers/net/wireless/realtek/rtw89/phy.h

22

#define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)

drivers/net/wireless/realtek/rtw89/phy_be.c

1018

val = u32_encode_bits(v[0], GENMASK(7, 0)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1019

u32_encode_bits(v[1], GENMASK(15, 8)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1020

u32_encode_bits(v[2], GENMASK(23, 16)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1021

u32_encode_bits(v[3], GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/phy_be.c

1064

val = u32_encode_bits(v[RTW89_RATE_OFFSET_CCK], GENMASK(3, 0)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1065

u32_encode_bits(v[RTW89_RATE_OFFSET_OFDM], GENMASK(7, 4)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1066

u32_encode_bits(v[RTW89_RATE_OFFSET_HT], GENMASK(11, 8)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1067

u32_encode_bits(v[RTW89_RATE_OFFSET_VHT], GENMASK(15, 12)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1068

u32_encode_bits(v[RTW89_RATE_OFFSET_HE], GENMASK(19, 16)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1069

u32_encode_bits(v[RTW89_RATE_OFFSET_EHT], GENMASK(23, 20)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1070

u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_HE], GENMASK(27, 24)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1071

u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_EHT], GENMASK(31, 28));

drivers/net/wireless/realtek/rtw89/phy_be.c

1354

val = u32_encode_bits(ptr[0], GENMASK(7, 0)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1355

u32_encode_bits(ptr[1], GENMASK(15, 8)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1356

u32_encode_bits(ptr[2], GENMASK(23, 16)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1357

u32_encode_bits(ptr[3], GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/phy_be.c

1494

val = u32_encode_bits(ptr[0], GENMASK(7, 0)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1495

u32_encode_bits(ptr[1], GENMASK(15, 8)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1496

u32_encode_bits(ptr[2], GENMASK(23, 16)) |

drivers/net/wireless/realtek/rtw89/phy_be.c

1497

u32_encode_bits(ptr[3], GENMASK(31, 24));

drivers/net/wireless/realtek/rtw89/phy_be.c

215

#define BB_GAIN_TYPE_SUB0_BE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/phy_be.c

216

#define BB_GAIN_TYPE_SUB1_BE GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/phy_be.c

218

#define BB_GAIN_PATH_BE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/phy_be.c

219

#define BB_GAIN_BW_BE GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10000

#define B_DACK_DADCK00 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10004

#define B_DACK_BIAS01 GENMASK(11, 2)

drivers/net/wireless/realtek/rtw89/reg.h

10006

#define B_DACK_S0M1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10009

#define B_DACK_DADCK01 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10013

#define B_DRCK_MUL GENMASK(21, 17)

drivers/net/wireless/realtek/rtw89/reg.h

10016

#define B_DRCK_VAL GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10018

#define B_DRCK_RES GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10023

#define B_DRCK_V1_CV GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10025

#define B_DRCK_RS_LPS GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10028

#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

10030

#define B_P0_CFCH_BW0 GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

10031

#define B_P0_CFCH_EN GENMASK(14, 11)

drivers/net/wireless/realtek/rtw89/reg.h

10032

#define B_P0_CFCH_CTL GENMASK(10, 7)

drivers/net/wireless/realtek/rtw89/reg.h

10035

#define B_P0_CFCH_BW1 GENMASK(8, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10037

#define B_WDADC_SEL GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10039

#define B_ADCMOD_LP GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10042

#define B_DCIM_RC GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10043

#define B_DCIM_FR GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/reg.h

10045

#define B_ADDCK0D_VAL2 GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

10046

#define B_ADDCK0D_VAL GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10051

#define B_ADDCK0 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

10052

#define B_ADDCK0_MAN GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10054

#define B_ADDCK0_VAL GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10057

#define B_ADDCK0_RLS GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

10058

#define B_ADDCK0_RL1 GENMASK(27, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10059

#define B_ADDCK0_RL0 GENMASK(17, 8)

drivers/net/wireless/realtek/rtw89/reg.h

10061

#define B_ADDCKR0_A0 GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10062

#define B_ADDCKR0_DC GENMASK(15, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10063

#define B_ADDCKR0_A1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10066

#define B_DACK10 GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/reg.h

10068

#define B_DACK1_VAL GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10072

#define B_DACK11 GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/reg.h

10074

#define B_DACK2_VAL GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10080

#define B_DACK_BIAS10 GENMASK(11, 2)

drivers/net/wireless/realtek/rtw89/reg.h

10082

#define B_DACK10S GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10086

#define B_DACK_DADCK10 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10090

#define B_DACK_BIAS11 GENMASK(11, 2)

drivers/net/wireless/realtek/rtw89/reg.h

10092

#define B_DACK11S GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10096

#define B_DACK_DADCK11 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10098

#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

101

#define B_AX_GPIOSEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10100

#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10103

#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10105

#define B_ADDCK1D_VAL2 GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

10106

#define B_ADDCK1D_VAL GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10109

#define B_ADDCK1 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

10110

#define B_ADDCK1_MAN GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10114

#define B_ADDCK1_RLS GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

10115

#define B_ADDCK1_RL1 GENMASK(27, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10116

#define B_ADDCK1_RL0 GENMASK(17, 8)

drivers/net/wireless/realtek/rtw89/reg.h

10118

#define B_ADDCKR1_A0 GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10119

#define B_ADDCKR1_A1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10122

#define B_DACKN0_V GENMASK(21, 14)

drivers/net/wireless/realtek/rtw89/reg.h

10124

#define B_DACKN1_V GENMASK(21, 14)

drivers/net/wireless/realtek/rtw89/reg.h

10138

#define B_GOTX_IQKDPK GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

10151

#define B_TXPWRB_MAX_BE GENMASK(20, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10154

#define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10155

#define B_TSSI_MAP_OFST_CCK GENMASK(26, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10157

#define B_TXAGC_OFDM_REF_DBM_P0 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10158

#define B_TXAGC_CCK_REF_DBM_P0 GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10160

#define B_TSSI_K_OFDM_P0 GENMASK(29, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10164

#define B_TXAGC_OFDM_REF_DBM_P1 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10165

#define B_TXAGC_CCK_REF_DBM_P1 GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10167

#define B_TSSI_K_OFDM_P1 GENMASK(29, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10172

#define B_COMP_CIM3K_TH2_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10261

#define B_DPD_DBW160_TH0_0_BE4 GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10262

#define B_DPD_DBW160_TH0_1_BE4 GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/reg.h

10263

#define B_DPD_DBW160_TH0_2_BE4 GENMASK(24, 22)

drivers/net/wireless/realtek/rtw89/reg.h

10264

#define B_DPD_DBW160_TH0_3_BE4 GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/reg.h

10265

#define B_DPD_DBW160_TH0_4_BE4 GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

10267

#define B_DPD_DBW160_TH1_5_BE4 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10268

#define B_DPD_DBW160_TH1_6_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10269

#define B_DPD_DBW160_TH1_7_BE4 GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10271

#define B_DPD_CBW20_TH0_0_BE4 GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10272

#define B_DPD_CBW20_TH0_1_BE4 GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10273

#define B_DPD_CBW20_TH0_2_BE4 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10274

#define B_DPD_CBW20_TH0_3_BE4 GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10275

#define B_DPD_CBW20_TH0_4_BE4 GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

10276

#define B_DPD_CBW20_TH0_5_BE4 GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10277

#define B_DPD_CBW20_TH0_6_BE4 GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/reg.h

10279

#define B_DPD_CBW20_TH1_7_BE4 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10280

#define B_DPD_CBW40_TH1_0_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10281

#define B_DPD_CBW40_TH1_1_BE4 GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10282

#define B_DPD_CBW40_TH1_2_BE4 GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10283

#define B_DPD_CBW40_TH1_3_BE4 GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10284

#define B_DPD_CBW40_TH1_4_BE4 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10285

#define B_DPD_CBW40_TH1_5_BE4 GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10286

#define B_DPD_CBW40_TH1_6_BE4 GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

10287

#define B_DPD_CBW40_TH1_7_BE4 GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10288

#define B_DPD_CBW80_TH1_0_BE4 GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/reg.h

10290

#define B_DPD_CBW80_TH2_1_BE4 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10291

#define B_DPD_CBW80_TH2_2_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10292

#define B_DPD_CBW80_TH2_3_BE4 GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10293

#define B_DPD_CBW80_TH2_4_BE4 GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10294

#define B_DPD_CBW80_TH2_5_BE4 GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10295

#define B_DPD_CBW80_TH2_6_BE4 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10296

#define B_DPD_CBW80_TH2_7_BE4 GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10298

#define B_QAM_TH0_0_BE4 GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10299

#define B_QAM_TH0_1_BE4 GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/reg.h

10300

#define B_QAM_TH0_2_BE4 GENMASK(24, 22)

drivers/net/wireless/realtek/rtw89/reg.h

10301

#define B_QAM_TH0_3_BE4 GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/reg.h

10302

#define B_QAM_TH0_4_BE4 GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

10304

#define B_QAM_TH1_0_BE4 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10305

#define B_QAM_TH1_1_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10306

#define B_QAM_TH1_2_BE4 GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10307

#define B_QAM_TH1_3_BE4 GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10308

#define B_QAM_TH1_4_BE4 GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10309

#define B_QAM_TH1_5_BE4 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10310

#define B_QAM_TH1_6_BE4 GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10311

#define B_QAM_TH1_7_BE4 GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

10312

#define B_QAM_TH1_8_BE4 GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10313

#define B_QAM_TH1_9_BE4 GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/reg.h

10315

#define B_QAM_TH2_0_BE4 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10316

#define B_QAM_TH2_1_BE4 GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

10317

#define B_QAM_TH2_2_BE4 GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10318

#define B_QAM_TH2_3_BE4 GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

10319

#define B_QAM_TH2_4_BE4 GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10320

#define B_QAM_TH2_5_BE4 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10321

#define B_QAM_TH2_6_BE4 GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

10322

#define B_QAM_TH2_7_BE4 GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

10323

#define B_QAM_TH2_8_BE4 GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10325

#define B_RFSI_CT_ER_BE4 GENMASK(18, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10326

#define B_RFSI_CT_SUBF_BE4 GENMASK(22, 19)

drivers/net/wireless/realtek/rtw89/reg.h

10327

#define B_RFSI_CT_FTM_BE4 GENMASK(26, 23)

drivers/net/wireless/realtek/rtw89/reg.h

10328

#define B_RFSI_CT_SENS_BE4 GENMASK(30, 27)

drivers/net/wireless/realtek/rtw89/reg.h

10330

#define B_FBTB_CT_DEF_BE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10331

#define B_FBTB_CT_PB_BE4 GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

10332

#define B_FBTB_CT_DL_WO_BE4 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

10333

#define B_FBTB_CT_DL_BF_BE4 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

10334

#define B_FBTB_CT_MUMIMO_BE4 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10335

#define B_FBTB_CT_FTM_BE4 GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10336

#define B_FBTB_CT_SENS_BE4 GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

10344

#define B_QAM_COMP_TH4_L GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10345

#define B_QAM_COMP_TH4_M GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10346

#define B_QAM_COMP_TH4_H GENMASK(24, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10347

#define B_QAM_COMP_TH4_2L GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10348

#define B_QAM_COMP_TH4_2M GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10349

#define B_QAM_COMP_TH4_2H GENMASK(29, 25)

drivers/net/wireless/realtek/rtw89/reg.h

10351

#define B_QAM_COMP_TH5_L GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10352

#define B_QAM_COMP_TH5_M GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10353

#define B_QAM_COMP_TH5_H GENMASK(24, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10354

#define B_QAM_COMP_TH5_2L GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10355

#define B_QAM_COMP_TH5_2M GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10356

#define B_QAM_COMP_TH5_2H GENMASK(29, 25)

drivers/net/wireless/realtek/rtw89/reg.h

10358

#define B_QAM_COMP_TH6_L GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10359

#define B_QAM_COMP_TH6_M GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10360

#define B_QAM_COMP_TH6_2L GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

10361

#define B_QAM_COMP_TH6_2M GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

10374

#define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/reg.h

10378

#define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

10379

#define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20)

drivers/net/wireless/realtek/rtw89/reg.h

10380

#define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10382

#define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10384

#define B_IFS_T1_AVG_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10385

#define B_IFS_T2_AVG_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10387

#define B_IFS_T3_AVG_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10388

#define B_IFS_T4_AVG_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10390

#define B_IFS_T1_CLM_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10391

#define B_IFS_T2_CLM_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10393

#define B_IFS_T3_CLM_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10394

#define B_IFS_T4_CLM_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10396

#define B_IFS_TOTAL_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10399

#define B_IFS_T1_HIS_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

104

#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

10400

#define B_IFS_T2_HIS_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10402

#define B_IFS_T3_HIS_BE4 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10403

#define B_IFS_T4_HIS_BE4 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

10409

#define B_CHINFO_OPT_BE4 GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/reg.h

10411

#define B_CHINFO_NX_BE4 GENMASK(16, 6)

drivers/net/wireless/realtek/rtw89/reg.h

10413

#define B_CHINFO_ALG_BE4 GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

10416

#define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

10429

#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1058

#define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1059

#define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

106

#define B_AX_DBG_SEL1 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1060

#define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1063

#define B_AX_BULK_SIZE GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

107

#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

1072

#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

1073

#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1074

#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

1075

#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

1077

#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

1081

#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1082

#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1084

#define B_AX_MAX_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1085

#define B_AX_MIN_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

109

#define B_AX_DBG_SEL0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1100

#define B_AX_AVAL_PG_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1101

#define B_AX_USE_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1117

#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1118

#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

112

#define B_AX_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1121

#define B_AX_PUBPG_G1_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1122

#define B_AX_PUBPG_G0_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1125

#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1128

#define B_AX_G1_USE_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1129

#define B_AX_G0_USE_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1132

#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1135

#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1136

#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1139

#define B_AX_WP_THRD_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

114

#define B_AX_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1142

#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1145

#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1146

#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1147

#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1150

#define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1154

#define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1155

#define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

116

#define B_AX_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

117

#define B_AX_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

12

#define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

1358

#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1359

#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1366

#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1367

#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1368

#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1369

#define B_AX_DLE_USE_PGNUM GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1370

#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1371

#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1379

#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

138

#define B_AX_R_AX_BG GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1380

#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1382

#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1385

#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1386

#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1387

#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

141

#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1411

#define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1412

#define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1418

#define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1562

#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1563

#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1571

#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1572

#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1574

#define B_AX_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1575

#define B_AX_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

158

#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1587

#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1588

#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

159

#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1590

#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1593

#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1594

#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1597

#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1598

#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1599

#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1600

#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1603

#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1604

#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

165

#define B_AX_DEBUG_ST_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

171

#define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1727

#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1728

#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1733

#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1734

#define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1739

#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

174

#define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1740

#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1741

#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1745

#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)

drivers/net/wireless/realtek/rtw89/reg.h

1746

#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1747

#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

1748

#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1752

#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1753

#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1758

#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

176

#define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

177

#define MIO_ADDR_PAGE_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

180

#define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1818

#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

183

#define B_AX_CHIP_VER_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

1836

#define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

186

#define B_AX_SEL_0XC0_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1860

#define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

188

#define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

1889

#define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

1890

#define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1891

#define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1893

#define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1897

#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1901

#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1905

#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1909

#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1961

#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1962

#define B_AX_DFI_ADDR_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1964

#define B_AX_DFI_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1968

#define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

1973

#define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1974

#define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

1977

#define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

1979

#define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

202

#define B_AX_IDMEM_SHARE_MODE_RECORD_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

204

#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

2040

#define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2042

#define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2043

#define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2046

#define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2047

#define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2123

#define B_AX_FSM_MON_SEL_MASK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2126

#define B_AX_FSM_PAR_MASK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

213

#define PS_RPWM_SEQ_NUM GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

2146

#define B_AX_CMAC_ALLCKEN GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2157

#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

217

#define PS_CPWM_SEQ_NUM GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

2178

#define B_AX_TXSC_80M_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2179

#define B_AX_TXSC_40M_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

218

#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2180

#define B_AX_TXSC_20M_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2184

#define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2186

#define B_AX_RSC_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

2187

#define B_AX_RRSR_CCK_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

219

#define PS_CPWM_STATE GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2198

#define CMAC0_ERR_IMR_EN GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2199

#define CMAC1_ERR_IMR_EN GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2226

#define B_AX_SYNC_PORT_SRC GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2228

#define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)

drivers/net/wireless/realtek/rtw89/reg.h

223

#define B_AX_BOOT_REASON_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2233

#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2238

#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2243

#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2248

#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2253

#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2257

#define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2258

#define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2259

#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2260

#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2292

#define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2296

#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2297

#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2298

#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

230

#define B_AX_UDM1_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

231

#define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

232

#define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

233

#define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

234

#define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2343

#define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2355

#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2356

#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2360

#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2376

#define B_AX_NET_TYPE_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

239

#define B_AX_VREFPFM_L_MASK GENMASK(25, 22)

drivers/net/wireless/realtek/rtw89/reg.h

2393

#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2394

#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

240

#define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)

drivers/net/wireless/realtek/rtw89/reg.h

2401

#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2402

#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2409

#define B_AX_BCNERLY_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

241

#define B_AX_OCP_L1_MASK GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/reg.h

2416

#define B_AX_TBTTERLY_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

242

#define B_AX_VOL_L1_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2423

#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2430

#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2431

#define B_AX_BCN_SPACE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2438

#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2439

#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2440

#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2447

#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2448

#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2449

#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2450

#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2470

#define B_AX_DTIM_NUM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2471

#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2478

#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2480

#define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2487

#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2494

#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2501

#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2513

#define B_AX_P0MB_ALL_MASK GENMASK(23, 1)

drivers/net/wireless/realtek/rtw89/reg.h

2514

#define B_AX_P0MB_NUM_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2538

#define B_AX_PCIE_MODE_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

2549

#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2550

#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2551

#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2552

#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2556

#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2557

#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2558

#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2562

#define B_AX_AMPDU_MAX_LEN_VHT_MASK GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2567

#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2568

#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

2571

#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2572

#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2577

#define B_AX_DEFT_RATE_MASK GENMASK(15, 7)

drivers/net/wireless/realtek/rtw89/reg.h

2579

#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

2586

#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2587

#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2592

#define B_AX_RATE_SEL_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2593

#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2594

#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2598

#define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

260

#define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2601

#define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

2602

#define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

2604

#define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

2610

#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2624

#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2625

#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2626

#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2627

#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

263

#define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2631

#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

264

#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

265

#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2653

#define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2686

#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2697

GENMASK((_port) * 2 + 1, (_port) * 2); \

drivers/net/wireless/realtek/rtw89/reg.h

2700

#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2704

#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

272

#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)

drivers/net/wireless/realtek/rtw89/reg.h

273

#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)

drivers/net/wireless/realtek/rtw89/reg.h

274

#define B_AX_XTAL_SC_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2758

#define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29)

drivers/net/wireless/realtek/rtw89/reg.h

2759

#define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25)

drivers/net/wireless/realtek/rtw89/reg.h

2760

#define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/reg.h

2761

#define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19)

drivers/net/wireless/realtek/rtw89/reg.h

2762

#define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13)

drivers/net/wireless/realtek/rtw89/reg.h

2763

#define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/reg.h

277

#define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/reg.h

278

#define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2782

#define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2783

#define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

2784

#define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

2789

#define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

279

#define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2790

#define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

2791

#define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/reg.h

2792

#define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2797

#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)

drivers/net/wireless/realtek/rtw89/reg.h

2799

#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

280

#define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2801

#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)

drivers/net/wireless/realtek/rtw89/reg.h

2803

#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

2806

#define B_AX_DBG_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2810

#define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

2811

#define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

2812

#define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

2814

#define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)

drivers/net/wireless/realtek/rtw89/reg.h

2815

#define B_AX_MACRX_CS_MASK GENMASK(18, 14)

drivers/net/wireless/realtek/rtw89/reg.h

2816

#define B_AX_RXSTS_CS_MASK GENMASK(13, 9)

drivers/net/wireless/realtek/rtw89/reg.h

2818

#define B_AX_TXRPT_CS_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

285

#define B_AX_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

288

#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

291

#define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

292

#define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

295

#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2951

#define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2953

#define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2955

#define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/reg.h

2969

#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

2972

#define B_AX_TCR_USTIME GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2977

#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2978

#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

2982

#define B_AX_TSFT_OFS_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2983

#define B_AX_STMP_THSD_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2992

#define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

2993

#define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

2994

#define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

2996

#define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

2998

#define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

2999

#define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3003

#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3004

#define B_AX_MACTX_DMA_CNT GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3009

#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3013

#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3017

#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3021

#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3033

#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3034

#define B_AX_ACKTO_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3051

#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3052

#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3061

#define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

3062

#define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3063

#define B_AX_NESS_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

3066

#define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3067

#define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

3068

#define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

3070

#define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3079

#define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)

drivers/net/wireless/realtek/rtw89/reg.h

3082

#define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3085

#define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3089

#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3092

#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/reg.h

3094

#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3099

#define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3141

#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3145

#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3149

#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

315

#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

316

#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3166

#define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3178

#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3182

#define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

320

#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

321

#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3216

#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

322

#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

323

#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3231

#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3232

#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3233

#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3239

#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3240

#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

3243

#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)

drivers/net/wireless/realtek/rtw89/reg.h

3257

#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

326

#define B_AX_R1_L1_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

3262

#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

3269

#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

327

#define B_AX_C3_L1_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3270

#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3271

#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

3272

#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

3273

#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

328

#define B_AX_C2_L1_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

3281

#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3282

#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3283

#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

329

#define B_AX_C1_L1_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3291

#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3292

#define B_AX_CH_EN_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3296

#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3297

#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3314

#define B_AX_UID_FILTER_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3316

#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

3317

#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

332

#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3324

#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

334

#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/reg.h

3352

#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3353

#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

3362

#define B_AX_BACAM_RST_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3393

#define B_AX_BCAID_P0_MASK GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3397

#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3398

#define B_AX_STATE_CUR_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3399

#define B_AX_STATE_NXT_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

340

#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3401

#define B_AX_STATE_SEL_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

345

#define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

346

#define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

347

#define B_AX_DMA_MODE_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

3470

#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3471

#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

3472

#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3476

#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3480

#define B_AX_PWR_REF GENMASK(27, 10)

drivers/net/wireless/realtek/rtw89/reg.h

3482

#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3487

#define B_AX_TXAGC_BT_MASK GENMASK(11, 3)

drivers/net/wireless/realtek/rtw89/reg.h

3491

#define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3495

#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3501

#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3513

#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)

drivers/net/wireless/realtek/rtw89/reg.h

3517

#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3522

#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3523

#define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3524

#define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3526

#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3527

#define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3528

#define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3556

#define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

356

#define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3562

#define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3595

#define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

360

#define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3608

#define B_AX_BTC_MODE_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

3611

#define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3615

#define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/reg.h

3624

#define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

3625

#define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

3626

#define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

3627

#define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3628

#define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3652

#define B_BTC_PRI_MASK_TX_TIME GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/reg.h

3653

#define B_BTC_PRI_MASK_RX_TIME_V1 GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

3666

#define B_AX_TIMER_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3672

#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

3674

#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3676

#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3686

#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3687

#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3689

#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3690

#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3731

#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

3732

#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

3733

#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

3743

#define B_AX_BT_TIME_MASK GENMASK(31, 6)

drivers/net/wireless/realtek/rtw89/reg.h

3744

#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3782

#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

3784

#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3868

#define B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

3905

#define B_BE_HR_BE_DBG GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/reg.h

392

#define B_AX_EP_IDX GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3984

#define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

3987

#define B_BE_EF_ADDR_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

3990

#define B_BE_EF_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4011

#define B_BE_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4013

#define B_BE_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4015

#define B_BE_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4016

#define B_BE_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

404

#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

405

#define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/reg.h

4091

#define B_BE_SDIO_PAD_E_MASK GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

4169

#define B_BE_LPSOP_DSWR_ADJ_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

4173

#define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4200

#define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4203

#define B_BE_FSM_MON_SEL_MASK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4212

#define B_BE_FSM_PAR_MASK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4224

#define B_BE_EF_PGTS_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

4226

#define B_BE_EF_TEST_SEL_MASK GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4232

#define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4236

#define B_BE_DATA_LINE_MASK GENMASK(30, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4239

#define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

424

#define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

4249

#define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

426

#define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)

drivers/net/wireless/realtek/rtw89/reg.h

4276

#define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4277

#define B_BE_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

428

#define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4281

#define B_BE_PCIE_MIO_WE_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4282

#define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4285

#define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4291

#define B_BE_VERIFY_ENV_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4292

#define B_BE_HW_ID_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

430

#define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/reg.h

4301

#define B_BE_HALT_H2C_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4304

#define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

4305

#define B_BE_ERROR_CODE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

435

#define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4461

#define B_BE_RUN_ENV_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

4462

#define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26)

drivers/net/wireless/realtek/rtw89/reg.h

4472

#define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4473

#define B_BE_FW_BOOT_MODE_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

4478

#define B_BE_BOOT_REASON_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4482

#define B_BE_LDM_MASK GENMASK(30, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4485

#define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

4486

#define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4487

#define B_BE_UDM0_FS_CODE_MASK GENMASK(23, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4497

#define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4498

#define B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

4499

#define B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4500

#define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4501

#define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4504

#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4507

#define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/reg.h

4508

#define B_BE_REG_LPF_R2_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4509

#define B_BE_REG_LPF_C3_MASK GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

4510

#define B_BE_REG_LPF_C2_MASK GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/reg.h

4511

#define B_BE_REG_LPF_C1_MASK GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

4513

#define B_BE_REG_CP_ICP_SEL_FAST_MASK GENMASK(13, 10)

drivers/net/wireless/realtek/rtw89/reg.h

4514

#define B_BE_REG_CP_ICP_SEL_MASK GENMASK(9, 6)

drivers/net/wireless/realtek/rtw89/reg.h

4515

#define B_BE_REG_IB_PI_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4518

#define B_BE_LDO_VSEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4521

#define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/reg.h

4530

#define B_BE_REG_LPF_R3_FAST_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4531

#define B_BE_REG_LPF_R2_FAST_MASK GENMASK(15, 11)

drivers/net/wireless/realtek/rtw89/reg.h

4532

#define B_BE_REG_LPF_C3_FAST_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4533

#define B_BE_REG_LPF_C2_FAST_MASK GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

4534

#define B_BE_REG_LPF_C1_FAST_MASK GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/reg.h

4535

#define B_BE_REG_LPF_R3_4_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4538

#define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

4539

#define B_BE_LDO_VSEL_DA_0_MASK GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

4540

#define B_BE_LDO_VSEL_D2S_1_MASK GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

4541

#define B_BE_LDO_VSEL_D2S_0_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4542

#define B_BE_LDO_VSEL_BUF_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

4543

#define B_BE_REG_R2_L_MASK GENMASK(21, 19)

drivers/net/wireless/realtek/rtw89/reg.h

4544

#define B_BE_REG_R1_L_MASK GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4552

#define B_BE_REG_12LDO_SEL_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

4553

#define B_BE_REG_09LDO_SEL_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4560

#define B_BE_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4564

#define B_BE_WL_XTAL_SI_CHIPID_MASK GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

4565

#define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4566

#define B_BE_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4567

#define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4568

#define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4571

#define B_BE_PCIE_SER_DBG_MASK GENMASK(31, 10)

drivers/net/wireless/realtek/rtw89/reg.h

4581

#define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4583

#define B_BE_WLMAC_PWR_STE_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4584

#define B_BE_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

4585

#define B_BE_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4586

#define B_BE_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

4587

#define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4713

#define B_BE_LAT_LTR_IDX_DRV_V1_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

4715

#define B_BE_LAT_LTR_IDX_FW_V1_MASK GENMASK(20, 19)

drivers/net/wireless/realtek/rtw89/reg.h

4717

#define B_BE_LAT_LTR_IDX_HW_V1_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4718

#define B_BE_LTR_IDX_DRV_V1_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

4720

#define B_BE_LTR_IDX_DISABLE_V1_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4721

#define B_BE_LTR_EN_PORT_V1_MASK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/reg.h

4725

#define B_BE_LTR_SPACE_IDX_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4756

#define B_BE_BOOT_STATUS_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4757

#define B_BE_SECUREBOOT_STATUS_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4760

#define B_BE_DBG_WOW_READY GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4811

#define B_BE_LTR_IDX_FW_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4812

#define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4817

#define B_BE_LTR_IDX_DISABLE_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4818

#define B_BE_LTR_IDX_IDLE_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

4819

#define B_BE_LTR_IDX_ACTIVE_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

4820

#define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4827

#define B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4828

#define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

483

#define B_AX_EP_IDX_V1 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4831

#define B_BE_NO_RX_ERR_TO_MASK GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/reg.h

4835

#define B_BE_MACID_MPDU_PROCESSOR_OFFSET_MASK GENMASK(26, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4838

#define B_BE_DMAC_CTRL_INFO_OFFSET_MASK GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4841

#define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

4842

#define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4843

#define B_BE_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4844

#define B_BE_SER_L0_COUNTER_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4847

#define B_BE_DMAC_BB_PHY1_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4848

#define B_BE_DMAC_BB_PHY0_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4927

#define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4928

#define B_BE_SER_L1_SEC_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4929

#define B_BE_SER_L1_MPDU_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4930

#define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4933

#define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4934

#define B_BE_SER_L1_TXPKTCTRL_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4935

#define B_BE_SER_L1_PLE_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4936

#define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4939

#define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4940

#define B_BE_SER_L1_APB_BRIDGE_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4941

#define B_BE_SER_L1_DLE_W_CPUIO_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4942

#define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4945

#define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4946

#define B_BE_SER_L1_P_AXIDMA_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4947

#define B_BE_SER_L1_H_AXIDMA_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

4948

#define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4951

#define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

4952

#define B_BE_SER_L1_DLE_D_CPUIO_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

4955

#define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4958

#define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

4961

#define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5331

#define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5332

#define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5335

#define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

5336

#define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

5337

#define B_BE_FWD_WLAN_CPU_TYPE_11_MASK GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

5338

#define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

5339

#define B_BE_FWD_WLAN_CPU_TYPE_9_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

5340

#define B_BE_FWD_WLAN_CPU_TYPE_8_MASK GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/reg.h

5341

#define B_BE_FWD_WLAN_CPU_TYPE_7_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

5342

#define B_BE_FWD_WLAN_CPU_TYPE_6_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5343

#define B_BE_FWD_WLAN_CPU_TYPE_5_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

5344

#define B_BE_FWD_WLAN_CPU_TYPE_4_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

5345

#define B_BE_FWD_WLAN_CPU_TYPE_3_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

5346

#define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5347

#define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

5348

#define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5349

#define B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

5350

#define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5353

#define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5354

#define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5355

#define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5359

#define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

5449

#define B_BE_WDE_Q0_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5450

#define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5453

#define B_BE_WDE_Q1_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5454

#define B_BE_WDE_Q1_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5457

#define B_BE_WDE_Q2_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5458

#define B_BE_WDE_Q2_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5461

#define B_BE_WDE_Q3_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5462

#define B_BE_WDE_Q3_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5465

#define B_BE_WDE_Q4_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5466

#define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5474

#define B_BE_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5475

#define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5476

#define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5480

#define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

55

#define B_AX_EF_PGPD_MASK GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

5570

#define B_BE_PLE_Q0_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5571

#define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5574

#define B_BE_PLE_Q1_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5575

#define B_BE_PLE_Q1_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5578

#define B_BE_PLE_Q2_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5579

#define B_BE_PLE_Q2_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5582

#define B_BE_PLE_Q3_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5583

#define B_BE_PLE_Q3_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5586

#define B_BE_PLE_Q4_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5587

#define B_BE_PLE_Q4_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5590

#define B_BE_PLE_Q5_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5591

#define B_BE_PLE_Q5_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5594

#define B_BE_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5595

#define B_BE_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5598

#define B_BE_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5599

#define B_BE_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5602

#define B_BE_PLE_Q8_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5603

#define B_BE_PLE_Q8_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5606

#define B_BE_PLE_Q9_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5607

#define B_BE_PLE_Q9_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5610

#define B_BE_PLE_Q10_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5611

#define B_BE_PLE_Q10_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5614

#define B_BE_PLE_Q11_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5615

#define B_BE_PLE_Q11_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5618

#define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5619

#define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5622

#define B_BE_PLE_Q13_MAX_SIZE_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5623

#define B_BE_PLE_Q13_MIN_SIZE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5638

#define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5639

#define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5642

#define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5646

#define B_BE_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5647

#define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

5648

#define B_BE_WDRLS_MODE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5684

#define B_BE_RLSRPT0_FWD_TRGT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5685

#define B_BE_RLSRPT0_PID_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5686

#define B_BE_RLSRPT0_QID_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5691

#define B_BE_RLSRPT0_FLTR_MAP_V1_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

5697

#define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

57

#define B_AX_EF_VDDQST_MASK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

5702

#define B_BE_RLSRPT0_TO_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5703

#define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5757

#define B_BE_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5758

#define B_BE_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5762

#define B_BE_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5766

#define B_BE_WD_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

5767

#define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5770

#define B_BE_WD_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

5771

#define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5772

#define B_BE_WD_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5775

#define B_BE_WD_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

5776

#define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5777

#define B_BE_WD_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5780

#define B_BE_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5781

#define B_BE_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5785

#define B_BE_WD_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5786

#define B_BE_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5790

#define B_BE_PL_BUF_REQ_QUOTA_ID_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5791

#define B_BE_PL_BUF_REQ_LEN_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5795

#define B_BE_PL_BUF_STAT_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5799

#define B_BE_PL_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

58

#define B_AX_EF_PGTS_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

5800

#define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5803

#define B_BE_PL_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

5804

#define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5805

#define B_BE_PL_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5808

#define B_BE_PL_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

5809

#define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5810

#define B_BE_PL_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5813

#define B_BE_PL_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5814

#define B_BE_PL_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5818

#define B_BE_PL_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5819

#define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5857

#define B_BE_WPKT_WLANCPU_QSEL_MASK GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

5858

#define B_BE_WPKT_DATACPU_QSEL_MASK GENMASK(26, 25)

drivers/net/wireless/realtek/rtw89/reg.h

5860

#define B_BE_FWD_RPKT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5861

#define B_BE_FWD_WPKT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5862

#define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5875

#define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

5876

#define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23)

drivers/net/wireless/realtek/rtw89/reg.h

5878

#define B_BE_FWD_PPDU_QUEID_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5879

#define B_BE_FWD_OTHER_RPKT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5880

#define B_BE_FWD_PPDU_STAT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5887

#define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5888

#define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5898

#define B_BE_HDR_INFO_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

5916

#define B_BE_WMAC_SEC_PN_SEL_MASK GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

5920

#define B_BE_SEC_DBG_SEL_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

593

#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

594

#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5948

#define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5952

#define B_BE_SEC_CAM_OFFSET_MASK GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5955

#define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5958

#define B_BE_DBG_READ_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5987

#define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5988

#define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

5994

#define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

5995

#define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

5998

#define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6004

#define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6005

#define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

603

#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6039

#define B_BE_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

604

#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6040

#define B_BE_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6041

#define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6044

#define B_BE_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6045

#define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

61

#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

611

#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

6119

#define B_BE_DLYTX_SEL_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

612

#define B_AX_SER_L1_COUNTER_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6120

#define B_BE_WMM3_SWITCH_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

6121

#define B_BE_WMM2_SWITCH_MASK GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/reg.h

6122

#define B_BE_WMM1_SWITCH_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

6123

#define B_BE_WMM0_SWITCH_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

613

#define B_AX_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

614

#define B_AX_SER_L0_COUNTER_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6167

#define B_BE_TXL_READ_MACID_MASK GENMASK(29, 20)

drivers/net/wireless/realtek/rtw89/reg.h

6168

#define B_BE_TXL_MACID_1_MASK GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

6169

#define B_BE_TXL_MACID_0_MASK GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6172

#define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

6173

#define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6179

#define B_BE_RXBD_DONE_MODE_MASK GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/reg.h

6180

#define B_BE_RXQ_RXBD_MODE_MASK GENMASK(12, 11)

drivers/net/wireless/realtek/rtw89/reg.h

6181

#define B_BE_DMA_MODE_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6190

#define B_BE_MAX_RXDMA_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

6191

#define B_BE_MAX_TXDMA_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6224

#define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6261

#define B_BE_WD_PAGE_MODE_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6262

#define B_BE_HCI_FC_CH14_FULL_COND_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

6263

#define B_BE_HCI_FC_TWD_FULL_COND_MASK GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

6264

#define B_BE_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

6265

#define B_BE_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6266

#define B_BE_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

6267

#define B_BE_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

6269

#define B_BE_HCI_FC_MODE_MASK GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

6273

#define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6274

#define B_BE_FULL_WD_PG_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6275

#define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6279

#define B_BE_CH0_MAX_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6280

#define B_BE_CH0_MIN_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6283

#define B_BE_CH0_AVAL_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6284

#define B_BE_CH0_USE_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6287

#define B_BE_G1_AVAL_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6288

#define B_BE_G0_AVAL_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6291

#define B_BE_PUBPG_G1_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6292

#define B_BE_PUBPG_G0_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6295

#define B_BE_PUBPG_ALL_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6298

#define B_BE_G1_USE_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6299

#define B_BE_G0_USE_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6302

#define B_BE_PUB_AVAL_PG_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6305

#define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6306

#define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6307

#define B_BE_FULL_PAGE_WP_CH811_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6308

#define B_BE_PREC_PAGE_WP_CH811_V1_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6309

#define B_BE_FULL_PAGE_WP_CH07_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6310

#define B_BE_PREC_PAGE_WP_CH07_V1_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6313

#define B_BE_WP_THRD_MASK GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6316

#define B_BE_WP_AVAL_PG_MASK GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6332

#define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6333

#define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

64

#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

6497

#define B_BE_WMAC_RFMOD_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6519

#define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6521

#define B_BE_TXSB_160M_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

6524

#define B_BE_TXSB_80M_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6528

#define B_BE_TXSB_40M_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

6532

#define B_BE_TXSB_20M_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6539

#define B_BE_RRSR_HE_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6540

#define B_BE_RRSR_VHT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6541

#define B_BE_RRSR_HT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6542

#define B_BE_RRSR_OFDM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6546

#define B_BE_RRSR_EHT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6547

#define B_BE_RRSR_RATE_EN_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6548

#define B_BE_RSC_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

6549

#define B_BE_RRSR_CCK_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6553

#define B_BE_SEQ_EN_GUARD_CYE_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

6601

#define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6602

#define B_BE_SER_L0_DMA_CNT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6603

#define B_BE_SER_L0_PTCL_CNT_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6604

#define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6608

#define B_BE_SER_L0_TMAC_COUNTER_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6609

#define B_BE_SER_L0_RMAC_COUNTER_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6610

#define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

663

#define DMAC_ERR_IMR_EN GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6655

#define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6656

#define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6679

#define B_BE_BCNQ_CW_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6680

#define B_BE_BCNQ_AIFS_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6682

#define B_BE_PIFS_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6683

#define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6687

#define B_BE_100NS_TIME_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6688

#define B_BE_RX_AIR_END_TIME_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6689

#define B_BE_MACTX_LATENCY_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6690

#define B_BE_PREBKF_TIME_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6694

#define B_BE_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6695

#define B_BE_SIFS_PREBKF_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6696

#define B_BE_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6697

#define B_BE_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

67

#define B_AX_EF_ADDR_MASK GENMASK(26, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6701

#define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6725

#define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6726

#define B_BE_CCK_SIFS_COMP_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6727

#define B_BE_PIFS_TIMEUNIT_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

6728

#define B_BE_PREBKF_TIME_NONAC_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6740

#define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6741

#define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6743

#define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

6745

#define B_BE_MUEDCA_EN_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6768

#define B_BE_CTN_TXEN_ALL_MASK GENMASK(17, 0)

drivers/net/wireless/realtek/rtw89/reg.h

68

#define B_AX_EF_DATA_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6847

#define B_BE_NET_TYPE_P0_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

6861

#define B_BE_TBTT_HOLD_P0_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6862

#define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6867

#define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6871

#define B_BE_BCNERLY_P0_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6875

#define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6879

#define B_BE_TBTT_AGG_NUM_P0_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6883

#define B_BE_SUB_BCN_SPACE_P0_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6884

#define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6888

#define B_BE_FORCE_BCN_NUM_P0_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6889

#define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6893

#define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

6894

#define B_BE_BCN_ERR_CNT_NAV_P0_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6895

#define B_BE_BCN_ERR_CNT_EDCCA_P0_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6896

#define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6907

#define B_BE_DTIM_NUM_P0_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

6908

#define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6917

#define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6921

#define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6925

#define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

6932

#define B_BE_P0MB_NUM_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

6956

#define B_BE_PCIE_MODE_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

7003

#define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7007

#define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7010

#define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7011

#define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7012

#define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7017

#define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7018

#define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7019

#define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7026

#define B_BE_BW_SIGTA_MASK GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

7030

#define B_BE_BAR_TXRATE_FOR_NULL_WD_MASK GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/reg.h

7031

#define B_BE_STBC_CFEND_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

7032

#define B_BE_STBC_CFEND_RATE_MASK GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

7033

#define B_BE_BASIC_CFEND_RATE_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7037

#define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7038

#define B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

7040

#define B_BE_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7041

#define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7045

#define B_BE_LATENCY_PADDING_PKT_TH_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7046

#define B_BE_PLCP_FETCH_BUFF_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7050

#define B_BE_MAX_TXNSS_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

7058

#define B_BE_S_TXCNT_LMT_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7059

#define B_BE_L_TXCNT_LMT_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7064

#define B_BE_RATE_SEL_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7065

#define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7066

#define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7108

#define B_BE_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7122

#define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7123

#define B_BE_BSS_COLOB_BE_PORT_2_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7124

#define B_BE_BSS_COLOB_BE_PORT_1_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7125

#define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7129

#define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7214

#define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7216

#define B_BE_PTCL_FSM1_TO_THR_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7218

#define B_BE_PTCL_FSM0_TO_THR_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7220

#define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7227

#define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

73

#define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7351

#define B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK GENMASK(30, 25)

drivers/net/wireless/realtek/rtw89/reg.h

7352

#define B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

7353

#define B_BE_RXDMA_TXRPT_PORT_ID_SW_MASK GENMASK(17, 14)

drivers/net/wireless/realtek/rtw89/reg.h

7354

#define B_BE_RXDMA_F2PCMDRPT_PORT_ID_SW_MASK GENMASK(13, 10)

drivers/net/wireless/realtek/rtw89/reg.h

7355

#define B_BE_DBG_SEL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7508

#define B_BE_TSFT_OFS_MASK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7509

#define B_BE_STMP_THSD_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7520

#define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7521

#define B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7522

#define B_BE_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7523

#define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7536

#define B_BE_ACKTO_CCK_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7537

#define B_BE_ACKTO_MASK GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7553

#define B_BE_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7555

#define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7560

#define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7561

#define B_BE_NESS_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/reg.h

7566

#define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7572

#define B_BE_MACLBK_RDY_PERIOD_MASK GENMASK(28, 17)

drivers/net/wireless/realtek/rtw89/reg.h

7573

#define B_BE_MACLBK_PLCP_DLY_MASK GENMASK(16, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7575

#define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3)

drivers/net/wireless/realtek/rtw89/reg.h

7585

#define B_BE_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)

drivers/net/wireless/realtek/rtw89/reg.h

7588

#define B_BE_WMAC_NAV_UPPER_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7590

#define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7594

#define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7597

#define B_BE_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/reg.h

7599

#define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7604

#define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7606

#define B_BE_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7653

#define B_BE_WMAC_CHNSTS_STATE_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7654

#define B_BE_DBGSEL_TRIGCMD_SEL_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7655

#define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7659

#define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

7660

#define B_BE_PHYINTF_RXTB_EN_PHASE_MASK GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/reg.h

7661

#define B_BE_PHYINTF_MIMO_WIDTH_MASK GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

7662

#define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7663

#define B_BE_PHYINTF_TIMEOUT_THR_V1_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7707

#define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7712

#define B_BE_BFMEE_CSI_RSC_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/reg.h

7719

#define B_BE_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

7720

#define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7721

#define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

7722

#define B_BE_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

7723

#define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7727

#define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7736

#define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

7737

#define B_BE_BFMEE_HE_CSI_RATE_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

7738

#define B_BE_BFMEE_VHT_CSI_RATE_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7739

#define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

7994

#define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

7995

#define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

7996

#define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8001

#define B_BE_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8003

#define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8012

#define B_BE_PLCP_RXFA_RESET_TYPE_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8026

#define B_BE_RXGCK_GCK_RATE_LIMIT_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8029

#define B_BE_RXGCK_ENTRY_DELAY_MASK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8030

#define B_BE_RXGCK_GCK_CYCLE_MASK GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8036

#define B_BE_UID_FILTER_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8038

#define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8043

#define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8055

#define B_BE_CTRL_STYPE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8061

#define B_BE_MGNT_STYPE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8065

#define B_BE_DATA_STYPE_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8069

#define B_BE_ADDR_CAM_RANGE_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8071

#define B_BE_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8083

#define B_BE_BACAM_TEMP_SZ_MASK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8084

#define B_BE_BACAM_RST_IDX_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8090

#define B_BE_BACAM_RST_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8099

#define B_BE_PPDU_STAT_WR_BW_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8110

#define B_BE_SR_OP_MODE_MASK GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8139

#define B_BE_BCAID_P0_MASK GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8191

#define B_BE_PLCP_BW_SRC_MASK GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8209

#define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8210

#define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8214

#define B_BE_RESP_IMR_1_MASK GENMASK(31, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8277

#define B_BE_PWR_LISTEN_PATH_EN GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

8280

#define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1)

drivers/net/wireless/realtek/rtw89/reg.h

8281

#define B_BE_PWR_REF_CTRL_CCK GENMASK(18, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8282

#define B_BE_PWR_OFST_LMT_DB GENMASK(27, 19)

drivers/net/wireless/realtek/rtw89/reg.h

8284

#define B_BE_PWR_OFST_LMTBF_DB GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8289

#define B_BE_PWR_OFST_BYRATE_DB GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8291

#define B_BE_FORCE_PWR_BY_RATE_VAL GENMASK(28, 20)

drivers/net/wireless/realtek/rtw89/reg.h

8302

#define B_BE_PWR_OFST_RULMT_DB GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8307

#define B_BE_PWR_FORCE_MACID_DBM_VAL GENMASK(17, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8320

#define B_BE_PWR_BT_VAL GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8321

#define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)

drivers/net/wireless/realtek/rtw89/reg.h

8327

#define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8331

#define B_BE_PWR_BY_RATE_DBW_ON GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

8361

#define RR_MOD_IQK GENMASK(19, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8362

#define RR_MOD_DPK GENMASK(19, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8363

#define RR_MOD_MASK GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8364

#define RR_MOD_DCK GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8365

#define RR_MOD_RGM GENMASK(13, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8366

#define RR_MOD_RXB GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8376

#define RR_MOD_NBW GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8377

#define RR_MOD_M_RXG GENMASK(13, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8378

#define RR_MOD_M_RXBB GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8381

#define RR_TXG_SEL GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/reg.h

8382

#define RR_MODOPT_M_TXPWR GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8384

#define RR_WLSEL_AG GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8392

#define RR_LOKVB_COI GENMASK(19, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8393

#define RR_LOKVB_COQ GENMASK(9, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8395

#define RR_TXIG_TG GENMASK(16, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8396

#define RR_TXIG_GR1 GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8397

#define RR_TXIG_GR0 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8399

#define RR_CHTR_MOD GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8400

#define RR_CHTR_TXRX GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8403

#define RR_CFGCH_BAND1 GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8411

#define RR_CFGCH_BAND0 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8415

#define RR_CFGCH_BW_V2 GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8421

#define RR_CFGCH_BW GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8422

#define RR_CFGCH_CH GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8428

#define RR_APK_MOD GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8430

#define RR_BTC_TXBB GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8431

#define RR_BTC_RXBB GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8433

#define RR_RCKC_CA GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8436

#define RR_RCKO_OFF GENMASK(13, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8438

#define RR_RXKPLL_OFF GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8441

#define RR_RSV4_AGH GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8442

#define RR_RSV4_PLLCH GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8448

#define RR_LUTWA_MASK GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8449

#define RR_LUTWA_M1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8450

#define RR_LUTWA_M2 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8453

#define RR_LUTWD0_MB GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8454

#define RR_LUTWD0_LB GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8457

#define RR_TM_VAL_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8458

#define RR_TM_VAL GENMASK(6, 1)

drivers/net/wireless/realtek/rtw89/reg.h

8460

#define RR_TM2_OFF GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8469

#define RR_TXGA_LOK_EXT GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8474

#define RR_GAINTX_ALL GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8475

#define RR_GAINTX_PAD GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8476

#define RR_GAINTX_BB GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8478

#define RR_TXMO_COI GENMASK(19, 15)

drivers/net/wireless/realtek/rtw89/reg.h

8479

#define RR_TXMO_COQ GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8480

#define RR_TXMO_FII GENMASK(9, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8481

#define RR_TXMO_FIQ GENMASK(5, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8483

#define RR_TXA_TRK GENMASK(19, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8489

#define RR_TXAC_IQG GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8491

#define RR_BIASA_TXA GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8492

#define RR_BIASA_TXG GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8493

#define RR_BIASD_TXA_V1 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8494

#define RR_BIASA_TXA_V1 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8495

#define RR_BIASD_TXG_V1 GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8496

#define RR_BIASA_TXG_V1 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8497

#define RR_BIASA_A GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8499

#define RR_BIASA2_LB GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8501

#define RR_TXATANK_LBSW2 GENMASK(17, 15)

drivers/net/wireless/realtek/rtw89/reg.h

8502

#define RR_TXATANK_LBSW GENMASK(16, 15)

drivers/net/wireless/realtek/rtw89/reg.h

8504

#define RR_TXA2_LDO GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8514

#define RR_RXPOW_IQK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8516

#define RR_RXBB_VOBUF GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8517

#define RR_RXBB_C2G GENMASK(16, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8518

#define RR_RXBB_C2 GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8519

#define RR_RXBB_C1G GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8520

#define RR_RXBB_FATT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8521

#define RR_RXBB_ATTR GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8522

#define RR_RXBB_ATTC GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8524

#define RR_RXG_IQKMOD GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8526

#define RR_XGLNA2_SW GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8528

#define RR_RXAE_IQKMOD GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8530

#define RR_RXA_DPK GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8533

#define RR_RAA2_SATT GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/reg.h

8534

#define RR_RAA2_SWATT GENMASK(15, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8535

#define RR_RXA2_C1 GENMASK(12, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8536

#define RR_RXA2_C2 GENMASK(9, 3)

drivers/net/wireless/realtek/rtw89/reg.h

8537

#define RR_RXA2_CC2 GENMASK(8, 7)

drivers/net/wireless/realtek/rtw89/reg.h

8538

#define RR_RXA2_IATT GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8539

#define RR_RXA2_HATT GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8540

#define RR_RXA2_ATT GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8542

#define RR_RXIQGEN_ATTL GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8543

#define RR_RXIQGEN_ATTH GENMASK(14, 13)

drivers/net/wireless/realtek/rtw89/reg.h

8547

#define RR_EN_TIA_IDA GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8548

#define RR_RXBB2_IDAC GENMASK(11, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8549

#define RR_RXBB2_EBW GENMASK(6, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8551

#define RR_XALNA2_SW2 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8552

#define RR_XALNA2_SW GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8554

#define RR_DCK_S1 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8555

#define RR_DCK_TIA GENMASK(15, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8556

#define RR_DCK_DONE GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

8560

#define RR_DCK1_S1 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8561

#define RR_DCK1_TIA GENMASK(15, 9)

drivers/net/wireless/realtek/rtw89/reg.h

8563

#define RR_DCK1_CLR GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8566

#define RR_DCK2_CYCLE GENMASK(7, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8570

#define RR_IQGEN_BIAS GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8572

#define RR_TXIQK_ATT2 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8573

#define RR_TXIQK_ATT1 GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8577

#define RR_MIXER_GN GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/reg.h

8579

#define RR_POW_SYN GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8580

#define RR_POW_SYN_V1 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8582

#define RR_LOGEN_RPT GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8585

#define RR_IBD_VAL GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8587

#define RR_LDO_SEL GENMASK(8, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8589

#define RR_VCO_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8610

#define RR_IQKPLL_MOD GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8614

#define RR_RCKD_POW GENMASK(19, 13)

drivers/net/wireless/realtek/rtw89/reg.h

8639

#define B_EMLSR_PARM GENMASK(27, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8646

#define B_CHINFO_SEG_LEN GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8647

#define B_CHINFO_SEG GENMASK(16, 7)

drivers/net/wireless/realtek/rtw89/reg.h

8652

#define B_CHINFO_DATA_BITMAP GENMASK(22, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8654

#define B_ANAPAR_PW15 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8655

#define B_ANAPAR_PW15_H GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8656

#define B_ANAPAR_PW15_H2 GENMASK(27, 26)

drivers/net/wireless/realtek/rtw89/reg.h

8658

#define B_ANAPAR_15 GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8662

#define B_ANAPAR_CRXBB GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8664

#define B_ANAPAR_14 GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8668

#define B_RFE_SEL0_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8671

#define B_CIRST_SYN GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/reg.h

8673

#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8674

#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)

drivers/net/wireless/realtek/rtw89/reg.h

8675

#define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

8678

#define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8680

#define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8681

#define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8682

#define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8684

#define B_VHTMCS_LMT GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/reg.h

8685

#define B_HTMCS_LMT GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8687

#define B_RXEHT_NSS_MAX GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8689

#define B_RXEHT_N_USER_MAX GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8690

#define B_RXEHTTB_NSS_MAX GENMASK(16, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8695

#define B_TB_NSS_MAX GENMASK(25, 23)

drivers/net/wireless/realtek/rtw89/reg.h

8696

#define B_NSS_MAX GENMASK(16, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8697

#define B_N_USR_MAX GENMASK(13, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8702

#define B_UPD_CLK_ADC_VAL GENMASK(26, 25)

drivers/net/wireless/realtek/rtw89/reg.h

8706

#define B_RSTB_ASYNC_BW80 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8710

#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8712

#define B_CH_IDX_SEG0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8715

#define B_STS_PARSING_TIME GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8720

#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8740

#define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20)

drivers/net/wireless/realtek/rtw89/reg.h

8744

#define B_PMAC_GNT_P1 GENMASK(20, 17)

drivers/net/wireless/realtek/rtw89/reg.h

8745

#define B_PMAC_GNT_P2 GENMASK(29, 26)

drivers/net/wireless/realtek/rtw89/reg.h

8747

#define B_PMAC_OPT1_MSK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8749

#define B_PMAC_RXMOD_MSK GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8752

#define B_MAC_SEL GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/reg.h

8755

#define B_MAC_SEL_MOD GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/reg.h

8759

#define B_PMAC_TX_PRD_MSK GENMASK(31, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8763

#define B_PMAC_TX_CNT_MSK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8770

#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8771

#define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8776

#define B_NHM_PERIOD_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8777

#define B_NHM_COUNTER_MSK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8780

#define B_NHM_TH0_MSK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8782

#define B_NHM_TH1_MSK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8783

#define B_NHM_TH2_MSK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8784

#define B_NHM_TH3_MSK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8785

#define B_NHM_TH4_MSK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8787

#define B_NHM_TH5_MSK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8788

#define B_NHM_TH6_MSK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8789

#define B_NHM_TH7_MSK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8790

#define B_NHM_TH8_MSK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8792

#define B_NHM_TH9_MSK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8793

#define B_NHM_TH10_MSK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8794

#define B_NHM_PWDB_METHOD_MSK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8799

#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8800

#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8805

#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8807

#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8810

#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8812

#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8815

#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8817

#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8820

#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8822

#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8827

#define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8837

#define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20)

drivers/net/wireless/realtek/rtw89/reg.h

8838

#define B_TXRX_FORCE_VAL GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8843

#define B_TXRFC_RST GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/reg.h

8847

#define B_SNDCCA_A1_EN GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8849

#define B_SNDCCA_A2_VAL GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8853

#define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8855

#define B_RXHT_MCS_LIMIT GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8857

#define B_RXVHT_MCS_LIMIT GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/reg.h

8861

#define B_RXHETB_MAX_NSS GENMASK(25, 23)

drivers/net/wireless/realtek/rtw89/reg.h

8862

#define B_RXHE_MAX_NSS GENMASK(16, 14)

drivers/net/wireless/realtek/rtw89/reg.h

8863

#define B_RXHE_USER_MAX GENMASK(13, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8876

#define B_CTLTOP_VAL GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8878

#define B_CLK_GCK GENMASK(24, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8881

#define B_ADC_FIFO_EN_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8883

#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

8885

#define B_P0_RXCK_ADJ GENMASK(31, 23)

drivers/net/wireless/realtek/rtw89/reg.h

8887

#define B_P0_TXCK_ALL GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8889

#define B_P0_RXCK_VAL GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8891

#define B_P0_TXCK_VAL GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8893

#define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8894

#define B_P0_RFMODE_MUX GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8896

#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/reg.h

8898

#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8903

#define B_S0_RXDC_I GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8904

#define B_S0_RXDC_Q GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

8906

#define B_S0_RXDC2_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8907

#define B_S0_RXDC2_AVG GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

8908

#define B_S0_RXDC2_MEN GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

8909

#define B_S0_RXDC2_Q2 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8921

#define B_EDCCA_RPT_B_PATH_MASK GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

8930

#define B_NHM_CNT0_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8931

#define B_NHM_CNT1_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8933

#define B_NHM_CNT2_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8934

#define B_NHM_CNT3_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8936

#define B_NHM_CNT4_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8937

#define B_NHM_CNT5_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8939

#define B_NHM_CNT6_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8940

#define B_NHM_CNT7_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8942

#define B_NHM_CNT8_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8943

#define B_NHM_CNT9_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8945

#define B_NHM_CNT10_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8946

#define B_NHM_CNT11_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8952

#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8953

#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8957

#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8958

#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8962

#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8963

#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8966

#define B_IFS_T4_HIS_MSK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8967

#define B_IFS_T3_HIS_MSK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8968

#define B_IFS_T2_HIS_MSK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

8969

#define B_IFS_T1_HIS_MSK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8972

#define B_IFS_T2_AVG_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8973

#define B_IFS_T1_AVG_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8976

#define B_IFS_T4_AVG_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8977

#define B_IFS_T3_AVG_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8980

#define B_IFS_T2_CCA_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8981

#define B_IFS_T1_CCA_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8984

#define B_IFS_T4_CCA_MSK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

8985

#define B_IFS_T3_CCA_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8989

#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8991

#define B_TXAGC_TP GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8993

#define B_TSSI_THER GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

8996

#define B_TSSI_CWRPT GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

8998

#define B_TXAGC_BTP GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9000

#define B_TXAGC_BB_OFT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9001

#define B_TXAGC_BB GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9002

#define B_TXAGC_RF GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9004

#define B_PATH0_TXPWR GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9006

#define B_S0_ADDCK_I GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9007

#define B_S0_ADDCK_Q GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9009

#define B_TXCKEN_FORCE_ALL GENMASK(24, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9011

#define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9012

#define B_EDCCA_RPT_SEL_P1_MSK GENMASK(5, 3)

drivers/net/wireless/realtek/rtw89/reg.h

9014

#define B_ADC_FIFO_RST GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9015

#define B_ADC_FIFO_RXK GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9021

#define B_TXFIR_C01 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9023

#define B_TXFIR_C23 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9025

#define B_TXFIR_C45 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9027

#define B_TXFIR_C67 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9029

#define B_TXFIR_C89 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9031

#define B_TXFIR_CAB GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9033

#define B_TXFIR_CCD GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9035

#define B_TXFIR_CEF GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9039

#define B_RPL_OFST_MASK GENMASK(14, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9047

#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9049

#define B_RXSCOBC_TH GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9051

#define B_RXSCOCCK_TH GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9058

#define B_AFEDAC0 GENMASK(31, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9060

#define B_AFEDAC1 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9065

#define B_HWSI_ADD_MASK GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9066

#define B_HWSI_ADD_CTL_MASK GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9068

#define B_HWSI_ADD_POLL_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9072

#define B_HWSI_DATA_VAL GENMASK(27, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9073

#define B_HWSI_DATA_ADDR GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9085

#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9088

#define B_P1_TXCK_ALL GENMASK(19, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9090

#define B_P1_RXCK_VAL GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9092

#define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9093

#define B_P1_RFMODE_MUX GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9095

#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9097

#define B_P1_RFMODE_FTM_RX GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9101

#define B_S1_RXDC_I GENMASK(25, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9102

#define B_S1_RXDC_Q GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

9104

#define B_S1_RXDC2_EN GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9105

#define B_S1_RXDC2_SEL GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9106

#define B_S1_RXDC2_Q2 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9108

#define B_TXAGC_BB_S1_OFT GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9109

#define B_TXAGC_BB_S1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9111

#define B_PATH1_TXPWR GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9113

#define B_S1_ADDCK_I GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9114

#define B_S1_ADDCK_Q GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9116

#define B_OP1DB_A GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9118

#define B_TIA10_A GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9119

#define B_TIA1_A GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9120

#define B_TIA0_A GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9122

#define B_BKOFF_IBADC_A GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9124

#define B_LNA_IBADC_A GENMASK(29, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9125

#define B_BACKOFF_LNA_A GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9126

#define B_BACKOFF_IBADC_A GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9128

#define B_RXBY_WBADC_A GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9138

#define B_FORCE_FIR_A GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9140

#define B_DCFO GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9143

#define B_SEG0CSI_IDX GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9151

#define B_BSS_CLR_MAP_TGT GENMASK(27, 22)

drivers/net/wireless/realtek/rtw89/reg.h

9152

#define B_BSS_CLR_MAP_STAID GENMASK(21, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9155

#define B_CFO_TRK_MSK GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9166

#define B_DCFO_COMP_S0_MSK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9169

#define B_DCFO_WEIGHT_MSK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9172

#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9176

#define B_DPD_BF_OFDM GENMASK(16, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9177

#define B_DPD_BF_SCA GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9179

#define B_LNA6 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9181

#define B_TIA10_B GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9182

#define B_TIA1_B GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9183

#define B_TIA0_B GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9185

#define B_BKOFF_IBADC_B GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9187

#define B_LNA_IBADC_B GENMASK(29, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9188

#define B_BACKOFF_LNA_B GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9189

#define B_BACKOFF_IBADC_B GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9191

#define B_RXBY_WBADC_B GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9199

#define B_TXPATH_SEL_MSK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9201

#define B_FORCE_FIR_B GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9203

#define B_TXPWR_MSK GENMASK(30, 22)

drivers/net/wireless/realtek/rtw89/reg.h

9205

#define B_TXNSS_MAP_MSK GENMASK(20, 17)

drivers/net/wireless/realtek/rtw89/reg.h

9207

#define B_PCOEFF01_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9209

#define B_PCOEFF23_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9211

#define B_PCOEFF45_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9213

#define B_PCOEFF67_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9215

#define B_PCOEFF89_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9217

#define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9219

#define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9221

#define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9223

#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9225

#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9226

#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9227

#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9229

#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9230

#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9231

#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9233

#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9234

#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9235

#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9236

#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9238

#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9239

#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9240

#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9242

#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9244

#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9245

#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9247

#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9248

#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9249

#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9251

#define B_PATH0_IB_PBK_MSK GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9253

#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

9256

#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9258

#define B_PATH0_BTG_SHEN GENMASK(18, 17)

drivers/net/wireless/realtek/rtw89/reg.h

9272

#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9274

#define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9276

#define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9278

#define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9279

#define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9290

#define B_P0_NBIIDX_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9293

#define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

9296

#define B_P1_MODE_SEL GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

93

#define B_AX_BTMODE_MASK GENMASK(7, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9301

#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9307

#define B_PATH1_BTG_SHEN GENMASK(18, 17)

drivers/net/wireless/realtek/rtw89/reg.h

9309

#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/reg.h

9311

#define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9323

#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9325

#define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9334

#define B_P1_NBIIDX_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9343

#define B_EDCCA_LVL_MSK3 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9344

#define B_EDCCA_LVL_MSK1 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9345

#define B_EDCCA_LVL_MSK0 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9348

#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)

drivers/net/wireless/realtek/rtw89/reg.h

9350

#define B_PWOFST GENMASK(21, 17)

drivers/net/wireless/realtek/rtw89/reg.h

9355

#define B_FC0_BW_SET GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9356

#define B_ANT_RX_BT_SEG0 GENMASK(25, 22)

drivers/net/wireless/realtek/rtw89/reg.h

9357

#define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9358

#define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)

drivers/net/wireless/realtek/rtw89/reg.h

9359

#define B_FC0_BW_INV GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9361

#define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9362

#define B_Q_MATRIX_00_REAL GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9366

#define B_CHBW_MOD_SBW GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9367

#define B_CHBW_MOD_PRICH GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9368

#define B_ANT_RX_SEG0 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9370

#define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9371

#define B_Q_MATRIX_11_REAL GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9375

#define B_P0_RPL1_41_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9376

#define B_P0_RPL1_40_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9377

#define B_P0_RPL1_20_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9380

#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9382

#define B_P0_RTL2_8A_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9383

#define B_P0_RTL2_81_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9384

#define B_P0_RTL2_80_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9385

#define B_P0_RTL2_42_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9387

#define B_P0_RTL3_89_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9388

#define B_P0_RTL3_84_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9389

#define B_P0_RTL3_83_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9390

#define B_P0_RTL3_82_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9394

#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/reg.h

9399

#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9401

#define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9403

#define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9410

#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9413

#define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9415

#define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9417

#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9419

#define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9421

#define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9422

#define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9424

#define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9425

#define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9427

#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9430

#define B_PATH0_NOTCH_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9433

#define B_PATH0_NOTCH2_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9439

#define B_PATH0_5MDET_TH GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9441

#define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9444

#define B_PATH1_NOTCH_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9447

#define B_PATH1_NOTCH2_VAL GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9453

#define B_PATH1_5MDET_TH GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9456

#define B_S0S1_CSI_WGT_TONE_IDX GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9458

#define B_CHINFO_ELM_BITMAP GENMASK(22, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9459

#define B_CHINFO_SRC GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9461

#define B_CHINFO_TYPE GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

9464

#define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9466

#define B_RPL_PATHB_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9467

#define B_RPL_PATHA_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9469

#define B_RSSI_M_PATHB_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9470

#define B_RSSI_M_PATHA_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9472

#define B_FC0_MSK_V1 GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9476

#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9479

#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9489

#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9490

#define B_CFO_COMP_VAL_MSK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9494

#define B_P0_TSSI_ALIM1 GENMASK(29, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9495

#define B_P0_TSSI_ALIM11 GENMASK(29, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9496

#define B_P0_TSSI_ALIM12 GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9497

#define B_P0_TSSI_ALIM13 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9499

#define B_P0_TSSI_ALIM31 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9502

#define B_P0_TSSI_ALIM2 GENMASK(29, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9506

#define B_P0_TSSI_ADC_CLK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9509

#define B_ACK_VAL GENMASK(30, 29)

drivers/net/wireless/realtek/rtw89/reg.h

9516

#define B_TXPWRB_VAL GENMASK(27, 19)

drivers/net/wireless/realtek/rtw89/reg.h

9517

#define B_TXPWRB_MAX GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9520

#define B_DPD_TSSI_CW GENMASK(26, 18)

drivers/net/wireless/realtek/rtw89/reg.h

9521

#define B_DPD_PWR_CW GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/reg.h

9522

#define B_DPD_REF GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9526

#define B_DPD_OFT_ADDR GENMASK(31, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9530

#define B_P0_TMETER GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9539

#define B_P0_TSSI_RFC GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9541

#define B_P0_TSSI_OFT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9546

#define B_P0_TSSI_AVG GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9548

#define B_P0_CLKG_FORCE GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9550

#define B_P0_GOT_TXRX GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9551

#define B_P0_RFCTM_VAL GENMASK(25, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9560

#define B_P0_TRSW_SO_A2 GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/reg.h

9567

#define B_P0_ANTSEL_TX_ORI GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9568

#define B_P0_ANTSEL_RX_ALT GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9569

#define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9571

#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9573

#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9581

#define B_P0_RFM_OUT GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9585

#define B_P0_TXDPD GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9590

#define B_P0_TXPW_RSTB GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9591

#define B_P0_TSSI_MV_MIX GENMASK(19, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9592

#define B_P0_TSSI_MV_AVG GENMASK(13, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9596

#define B_TXGAIN_SCALE_OFT GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9601

#define B_S0_DACKI_AR GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9604

#define B_S0_DACKI2_K GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9606

#define B_S0_DACKI7_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9608

#define B_S0_DACKI8_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9610

#define B_S0_DACKQ_AR GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9613

#define B_S0_DACKQ2_K GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9615

#define B_S0_DACKQ7_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9617

#define B_S0_DACKQ8_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9620

#define B_DCFO_WEIGHT_MSK_BE GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9622

#define B_DAC_CLK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9627

#define B_TXFCTR_THD GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9631

#define B_PCOEFF01 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9633

#define B_PCOEFF23 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9635

#define B_PCOEFF45 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9637

#define B_PCOEFF67 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9639

#define B_PCOEFF89 GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9641

#define B_PCOEFFAB GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9643

#define B_PCOEFFCD GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9645

#define B_PCOEFFEF GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9647

#define B_MGAIN_BIAS_BW20 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9648

#define B_MGAIN_BIAS_BW40 GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9650

#define B_CCK_RPL_OFST GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9652

#define B_BK_FC0INV GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9654

#define B_CCK_FC0INV GENMASK(18, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9663

#define B_FC0 GENMASK(12, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9665

#define B_SMALLBW GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9666

#define B_RX_BT_SG0 GENMASK(25, 22)

drivers/net/wireless/realtek/rtw89/reg.h

9667

#define B_RX_1RCCA GENMASK(17, 14)

drivers/net/wireless/realtek/rtw89/reg.h

9668

#define B_FC0_INV GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9671

#define B_CHBW_BW GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9672

#define B_CHBW_PRICH GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9673

#define B_ANT_RX_SG0 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9675

#define B_EHT_RATE_TH GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9676

#define B_SLOPE_B GENMASK(27, 14)

drivers/net/wireless/realtek/rtw89/reg.h

9677

#define B_SLOPE_A GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9679

#define B_SC_CORNER GENMASK(10, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9681

#define B_MGA_AEND GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9683

#define B_BY_SLOPE GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9684

#define B_MAG_AB GENMASK(23, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9687

#define B_HE_RATE_TH GENMASK(30, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9690

#define B_HT_VHT_TH GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9696

#define B_BEDGE_CFG GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9703

#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9707

#define B_P1_TSSI_ALIM1 GENMASK(29, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9708

#define B_P1_TSSI_ALIM11 GENMASK(29, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9709

#define B_P1_TSSI_ALIM12 GENMASK(19, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9710

#define B_P1_TSSI_ALIM13 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9712

#define B_P1_TSSI_ALIM31 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9714

#define B_P1_TSSI_ALIM2 GENMASK(29, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9716

#define B_P1_TSSI_ADC_CLK GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9718

#define B_P1_TXAGC_MAXMIN GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9724

#define B_P1_TMETER GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/reg.h

9729

#define B_P1_TSSI_RFC GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9731

#define B_P1_TSSI_OFT GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9734

#define B_P1_TSSI_AVG GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9736

#define B_P1_CLKG_FORCE GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/reg.h

9737

#define B_P1_GOT_TXRX GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9739

#define B_P1_RFCTM_VAL GENMASK(25, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9740

#define B_P1_RFCTM_DEL GENMASK(19, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9749

#define B_P1_TXPW_RSTB GENMASK(28, 27)

drivers/net/wireless/realtek/rtw89/reg.h

9750

#define B_P1_TSSI_MV_MIX GENMASK(19, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9751

#define B_P1_TSSI_MV_AVG GENMASK(13, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9757

#define B_S1_DACKI_AR GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9760

#define B_S1_DACKI2_K GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9762

#define B_S1_DACKI_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9764

#define B_S1_DACKI8_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9766

#define B_S1_DACKQ_AR GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9769

#define B_S1_DACKQ2_K GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9771

#define B_S1_DACKQ7_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9773

#define B_S1_DACKQ8_K GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9775

#define B_NCTL_CFG_SPAGE GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

9779

#define B_NCTL_N1_CIP GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9783

#define B_IQK_DIF_TRX GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9785

#define B_IQK_DIF1_TXPI GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9787

#define B_IQK_DIF2_RXPI GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9789

#define B_IQK_DIF4_RXT GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9790

#define B_IQK_DIF4_TXT GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9793

#define B_IQK_CFG_SET GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9795

#define B_IQK_RXAGC GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/reg.h

9798

#define B_TPG_MOD_F GENMASK(2, 1)

drivers/net/wireless/realtek/rtw89/reg.h

9801

#define B_MDPK_SYNC_MAN GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9802

#define B_MDPK_SYNC_DMAN GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9806

#define B_KIP_MOD GENMASK(19, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9811

#define B_DPK_IDL_SEL GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/reg.h

9815

#define B_LDL_NORM_PN GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9816

#define B_LDL_NORM_OP GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9820

#define B_DPK_CFG_IDX GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9825

#define B_KPATH_CFG_ED GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9827

#define B_KIP_RPT1_SEL GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9828

#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9847

#define B_PRT_COM_DCI GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9848

#define B_PRT_COM_CORV GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9849

#define B_RPT_COM_RDY GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9850

#define B_PRT_COM_DCQ GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9852

#define B_PRT_COM_GL GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9853

#define B_PRT_COM_CORI GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9854

#define B_PRT_COM_RXBB GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9855

#define B_PRT_COM_RXBB_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9860

#define B_COEF_SEL_IQC_V1 GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9862

#define B_COEF_SEL_MDPD_V1 GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9868

#define B_IQK_RES_TXCFIR GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9869

#define B_IQK_RES_RXCFIR GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9874

#define B_RXIQC_NEWP GENMASK(19, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9875

#define B_RXIQC_NEWX GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9880

#define B_RFGAIN_PAD GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9881

#define B_RFGAIN_TXBB GENMASK(12, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9883

#define B_RFGAIN_BND GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9892

#define B_CFIR_LUT_GP_V1 GENMASK(2, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9893

#define B_CFIR_LUT_GP GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9895

#define B_DPK_GN_EN GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9896

#define B_DPK_GN_AG GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9901

#define B_DPD_BND_1 GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9902

#define B_DPD_BND_0 GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9904

#define B_DPD_MEN GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9905

#define B_DPD_ORDER GENMASK(26, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9906

#define B_DPD_ORDER_V1 GENMASK(26, 25)

drivers/net/wireless/realtek/rtw89/reg.h

9907

#define B_DPD_CFG GENMASK(22, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9908

#define B_DPD_SEL GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9910

#define B_TXAGC_RFK_CH0 GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9914

#define B_KIP_IQP_SW GENMASK(13, 12)

drivers/net/wireless/realtek/rtw89/reg.h

9915

#define B_KIP_IQP_IQSW GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9917

#define B_KIP_RPT_SEL GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9921

#define B_LOAD_COEF_CFIR GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9925

#define B_DPK_GL_A0 GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/reg.h

9926

#define B_DPK_GL_A1 GENMASK(17, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9928

#define B_RPT_PER_KSET GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/reg.h

9929

#define B_RPT_PER_TSSI GENMASK(28, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9930

#define B_RPT_PER_OF GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9931

#define B_RPT_PER_TH GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9953

#define B_IQKINF_VER GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/reg.h

9954

#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9955

#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9956

#define B_IQKINF_FAIL GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9962

#define B_IQKCH_CH GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9963

#define B_IQKCH_BW GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/reg.h

9964

#define B_IQKCH_BAND GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9966

#define B_IQKINF2_FCNT GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/reg.h

9967

#define B_IQKINF2_KCNT GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/reg.h

9968

#define B_IQKINF2_NCTLV GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9970

#define B_TXAGC_OFDM_REF_DBM_RF1_P0 GENMASK(10, 2)

drivers/net/wireless/realtek/rtw89/reg.h

9971

#define B_TXAGC_CCK_REF_DBM_RF1_P0 GENMASK(19, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9973

#define B_TSSI_K_OFDM_RF1_P0 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9975

#define B_TXAGC_OFDM_REF_DBM_RF1_P1 GENMASK(10, 2)

drivers/net/wireless/realtek/rtw89/reg.h

9976

#define B_TXAGC_CCK_REF_DBM_RF1_P1 GENMASK(19, 11)

drivers/net/wireless/realtek/rtw89/reg.h

9978

#define B_TSSI_K_OFDM_RF1_P1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/reg.h

9982

#define B_DCOF0_V GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/reg.h

9984

#define B_DCOF1_VAL GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9988

#define B_DCOF8_V GENMASK(4, 1)

drivers/net/wireless/realtek/rtw89/reg.h

9990

#define B_DCOF9_VAL GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/reg.h

9995

#define B_DACK_BIAS00 GENMASK(11, 2)

drivers/net/wireless/realtek/rtw89/reg.h

9997

#define B_DACK_S0M0 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/rtw8851b.c

140

{0x46D0, GENMASK(1, 0), 0x3},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

141

{0x4AD4, GENMASK(31, 0), 0xf},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

142

{0x4688, GENMASK(23, 16), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

143

{0x4688, GENMASK(31, 24), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

144

{0x4694, GENMASK(7, 0), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

145

{0x4694, GENMASK(15, 8), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

146

{0x4AE4, GENMASK(11, 6), 0x34},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

147

{0x4AE4, GENMASK(17, 12), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

148

{0x469C, GENMASK(31, 26), 0x34},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

154

{0x46D0, GENMASK(1, 0), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

155

{0x4AD4, GENMASK(31, 0), 0x60},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

156

{0x4688, GENMASK(23, 16), 0x10},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

157

{0x4690, GENMASK(31, 24), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

158

{0x4694, GENMASK(15, 8), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

159

{0x4AE4, GENMASK(11, 6), 0x26},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

160

{0x4AE4, GENMASK(17, 12), 0x1e},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

161

{0x469C, GENMASK(31, 26), 0x26},

drivers/net/wireless/realtek/rtw89/rtw8851b.c

1771

bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/rtw8851b.c

1772

rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));

drivers/net/wireless/realtek/rtw89/rtw8851b.c

577

*high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);

drivers/net/wireless/realtek/rtw89/rtw8851b.c

579

*low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);

drivers/net/wireless/realtek/rtw89/rtw8851b.c

755

pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));

drivers/net/wireless/realtek/rtw89/rtw8851b.c

756

pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));

drivers/net/wireless/realtek/rtw89/rtw8851b.c

797

efuse->adc_td = phycap_map[addr_adc_td - phycap_addr] & GENMASK(4, 0);

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1156

0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(10, 7)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1158

0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(14, 11)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1160

0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(27, 26)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1162

0xc0d8, rtw89_phy_read32_mask(rtwdev, 0xc0d8, GENMASK(8, 5)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1164

0xc0c4, rtw89_phy_read32_mask(rtwdev, 0xc0c4, GENMASK(21, 17)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1166

0xc0e8, rtw89_phy_read32_mask(rtwdev, 0xc0e8, GENMASK(31, 16)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1168

0xc0e4, rtw89_phy_read32_mask(rtwdev, 0xc0e4, GENMASK(5, 4)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1170

0x12a0, rtw89_phy_read32_mask(rtwdev, 0x12a0, GENMASK(31, 23)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1172

0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(14, 13)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

1174

0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(23, 16)));

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

28

#define _TSSI_DE_MASK GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1491

bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1492

rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1501

return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1544

GENMASK(27, 10), 0x0);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1930

return FIELD_GET(GENMASK(15, 0), ctrl);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1948

return FIELD_GET(GENMASK(31, 16), ctrl);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

196

{0x4624, GENMASK(20, 14), 0x40},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

197

{0x46f8, GENMASK(20, 14), 0x40},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

1970

#define __do_clr(_chk) ((_chk) == GENMASK(15, 0))

drivers/net/wireless/realtek/rtw89/rtw8852a.c

198

{0x4674, GENMASK(20, 19), 0x2},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

199

{0x4748, GENMASK(20, 19), 0x2},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

200

{0x4650, GENMASK(14, 10), 0x18},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

201

{0x4724, GENMASK(14, 10), 0x18},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

202

{0x4688, GENMASK(1, 0), 0x3},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

203

{0x475c, GENMASK(1, 0), 0x3},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

209

{0x4624, GENMASK(20, 14), 0x1a},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

210

{0x46f8, GENMASK(20, 14), 0x1a},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

211

{0x4674, GENMASK(20, 19), 0x1},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

212

{0x4748, GENMASK(20, 19), 0x1},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

213

{0x4650, GENMASK(14, 10), 0x12},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

214

{0x4724, GENMASK(14, 10), 0x12},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

215

{0x4688, GENMASK(1, 0), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

216

{0x475c, GENMASK(1, 0), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8852a.c

800

pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852a.c

801

pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

1218

bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

1219

rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

138

{0x46D0, GENMASK(1, 0), 0x3},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

139

{0x4790, GENMASK(1, 0), 0x3},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

140

{0x4AD4, GENMASK(31, 0), 0xf},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

141

{0x4AE0, GENMASK(31, 0), 0xf},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

142

{0x4688, GENMASK(31, 24), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

143

{0x476C, GENMASK(31, 24), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

144

{0x4694, GENMASK(7, 0), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

145

{0x4694, GENMASK(15, 8), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

146

{0x4778, GENMASK(7, 0), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

147

{0x4778, GENMASK(15, 8), 0x80},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

148

{0x4AE4, GENMASK(23, 0), 0x780D1E},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

149

{0x4AEC, GENMASK(23, 0), 0x780D1E},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

150

{0x469C, GENMASK(31, 26), 0x34},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

151

{0x49F0, GENMASK(31, 26), 0x34},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

157

{0x46D0, GENMASK(1, 0), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

158

{0x4790, GENMASK(1, 0), 0x0},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

159

{0x4AD4, GENMASK(31, 0), 0x60},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

160

{0x4AE0, GENMASK(31, 0), 0x60},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

161

{0x4688, GENMASK(31, 24), 0x1a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

162

{0x476C, GENMASK(31, 24), 0x1a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

163

{0x4694, GENMASK(7, 0), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

164

{0x4694, GENMASK(15, 8), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

165

{0x4778, GENMASK(7, 0), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

166

{0x4778, GENMASK(15, 8), 0x2a},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

167

{0x4AE4, GENMASK(23, 0), 0x79E99E},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

168

{0x4AEC, GENMASK(23, 0), 0x79E99E},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

169

{0x469C, GENMASK(31, 26), 0x26},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

170

{0x49F0, GENMASK(31, 26), 0x26},

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

209

*high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

211

*low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

397

pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852b_common.c

398

pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c

27

#define _TSSI_DE_MASK GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/rtw8852bt.c

635

u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/rtw8852bt.c

636

u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

24

#define _TSSI_DE_MASK GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/rtw8852c.c

1996

bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

1997

rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

2007

return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));

drivers/net/wireless/realtek/rtw89/rtw8852c.c

2061

GENMASK(27, 10), 0x0);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

520

*high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

522

*low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

672

#define __THM_MASK_3BITS GENMASK(3, 1)

drivers/net/wireless/realtek/rtw89/rtw8852c.c

737

pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852c.c

738

pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c

25

#define _TSSI_DE_MASK GENMASK(21, 12)

drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c

2558

#define _DPK_PARA_TXAGC GENMASK(15, 10)

drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c

2559

#define _DPK_PARA_THER GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/rtw8922a.c

2604

u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/rtw8922a.c

2605

u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));

drivers/net/wireless/realtek/rtw89/rtw8922a.c

664

#define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/rtw8922a.c

737

pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8922a.c

738

pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);

drivers/net/wireless/realtek/rtw89/rtw8922a.c

779

pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0));

drivers/net/wireless/realtek/rtw89/rtw8922a.c

780

pad_bias_5g = u8_get_bits(info->pad_bias_trim[i], GENMASK(7, 4));

drivers/net/wireless/realtek/rtw89/ser.c

641

return wcpu_addr & GENMASK(28, 0);

drivers/net/wireless/realtek/rtw89/txrx.h

10

#define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)

drivers/net/wireless/realtek/rtw89/txrx.h

100

#define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

101

#define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

104

#define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

105

#define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

106

#define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

107

#define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

11

#define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

113

#define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

114

#define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/txrx.h

115

#define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

119

#define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

12

#define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

120

#define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/txrx.h

121

#define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

127

#define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

131

#define RTW89_TXWD_INFO1_DATA_TXCNT_LMT GENMASK(30, 25)

drivers/net/wireless/realtek/rtw89/txrx.h

132

#define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

134

#define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

137

#define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/txrx.h

138

#define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)

drivers/net/wireless/realtek/rtw89/txrx.h

14

#define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

141

#define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

149

#define RTW89_TXWD_INFO4_SW_DEFINE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

15

#define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

154

#define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

155

#define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2)

drivers/net/wireless/realtek/rtw89/txrx.h

162

#define BE_TXD_BODY0_HDR_LLC_LEN GENMASK(15, 11)

drivers/net/wireless/realtek/rtw89/txrx.h

163

#define BE_TXD_BODY0_CH_DMA GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

168

#define BE_TXD_BODY0_WP_OFFSET_V1 GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

17

#define DATA_RATE_HT_NSS_MASK GENMASK(4, 3)

drivers/net/wireless/realtek/rtw89/txrx.h

170

#define BE_TXD_BODY0_WD_SOURCE GENMASK(30, 29)

drivers/net/wireless/realtek/rtw89/txrx.h

174

#define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

175

#define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7)

drivers/net/wireless/realtek/rtw89/txrx.h

176

#define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/txrx.h

177

#define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

179

#define BE_TXD_BODY1_REUSE_SIZE GENMASK(23, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

18

#define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

180

#define BE_TXD_BODY1_REUSE_START_OFFSET GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

181

#define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/txrx.h

184

#define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

188

#define BE_TXD_BODY2_QSEL GENMASK(22, 17)

drivers/net/wireless/realtek/rtw89/txrx.h

19

#define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

190

#define BE_TXD_BODY2_MACID GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

191

#define BE_TXD_BODY2_QSEL_V1 GENMASK(20, 15)

drivers/net/wireless/realtek/rtw89/txrx.h

193

#define BE_TXD_BODY2_MACID_V1 GENMASK(31, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

196

#define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

20

#define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)

drivers/net/wireless/realtek/rtw89/txrx.h

202

#define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

203

#define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

208

#define BE_TXD_BODY3_DRIVER_QUEUE_TIME GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

21

#define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

211

#define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

212

#define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

213

#define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

216

#define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

217

#define BE_TXD_BODY5_SEC_IV_H3 GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

218

#define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

219

#define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

222

#define BE_TXD_BODY6_MU_TC GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

223

#define BE_TXD_BODY6_RU_TC GENMASK(9, 5)

drivers/net/wireless/realtek/rtw89/txrx.h

230

#define BE_TXD_BODY6_S_IDX GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

231

#define BE_TXD_BODY6_RU_POS GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

232

#define BE_TXD_BODY6_MU_TC_V1 GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

233

#define BE_TXD_BODY6_RU_TC_V1 GENMASK(8, 5)

drivers/net/wireless/realtek/rtw89/txrx.h

238

#define BE_TXD_BODY7_RTS_TC GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

239

#define BE_TXD_BODY7_MSDU_NUM GENMASK(9, 6)

drivers/net/wireless/realtek/rtw89/txrx.h

243

#define BE_TXD_BODY7_GI_LTF GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/txrx.h

244

#define BE_TXD_BODY7_DATARATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

245

#define BE_TXD_BODY7_DATA_BW GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

249

#define BE_TXD_INFO0_MBSSID GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

250

#define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

255

#define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

262

#define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

263

#define BE_TXD_INFO1_BCN_SRCH_SEQ GENMASK(9, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

268

#define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

269

#define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

272

#define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

274

#define BE_TXD_INFO2_SEC_CAM_IDX_V1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

276

#define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13)

drivers/net/wireless/realtek/rtw89/txrx.h

278

#define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18)

drivers/net/wireless/realtek/rtw89/txrx.h

280

#define BE_TXD_INFO2_OBW_CTS2SELF_DUP_TYPE GENMASK(29, 26)

drivers/net/wireless/realtek/rtw89/txrx.h

285

#define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

286

#define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

296

#define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

299

#define BE_TXD_INFO3_SIGNALING_TA_PKT_SC GENMASK(30, 27)

drivers/net/wireless/realtek/rtw89/txrx.h

303

#define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

304

#define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

308

#define BE_TXD_INFO4_SW_EHT_NLTF GENMASK(22, 21)

drivers/net/wireless/realtek/rtw89/txrx.h

309

#define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23)

drivers/net/wireless/realtek/rtw89/txrx.h

312

#define BE_TXD_INFO4_CCA_RTS GENMASK(30, 29)

drivers/net/wireless/realtek/rtw89/txrx.h

316

#define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

318

#define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

321

#define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

322

#define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/txrx.h

326

#define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18)

drivers/net/wireless/realtek/rtw89/txrx.h

327

#define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

331

#define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1)

drivers/net/wireless/realtek/rtw89/txrx.h

333

#define BE_TXD_INFO7_UL_APEP_UNIT GENMASK(10, 9)

drivers/net/wireless/realtek/rtw89/txrx.h

334

#define BE_TXD_INFO7_UL_TRI_PAD GENMASK(13, 11)

drivers/net/wireless/realtek/rtw89/txrx.h

335

#define BE_TXD_INFO7_UL_T_PE GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/txrx.h

337

#define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17)

drivers/net/wireless/realtek/rtw89/txrx.h

338

#define BE_TXD_INFO7_ULBW GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

339

#define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

341

#define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

342

#define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

345

#define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

346

#define AX_RXD_SHIFT_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/txrx.h

347

#define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

350

#define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

351

#define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

355

#define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

356

#define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

358

#define AX_RXD_USER_ID_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

359

#define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

360

#define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

361

#define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)

drivers/net/wireless/realtek/rtw89/txrx.h

366

#define AX_RXD_BW_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/txrx.h

367

#define AX_RXD_BW_v1_MASK GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/txrx.h

370

#define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

387

#define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/txrx.h

388

#define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

389

#define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)

drivers/net/wireless/realtek/rtw89/txrx.h

395

#define AX_RXD_TYPE_MASK GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

402

#define AX_RXD_TID_MASK GENMASK(11, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

406

#define AX_RXD_SEQ_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

407

#define AX_RXD_FRAG_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

410

#define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

411

#define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

412

#define AX_RXD_MAC_ID_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

413

#define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

419

#define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

422

#define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

424

#define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)

drivers/net/wireless/realtek/rtw89/txrx.h

426

#define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

439

#define RTW89_RXINFO_USER_MACID GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

440

#define RTW89_RXINFO_USER_MACID_V1 GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

448

#define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

449

#define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

450

#define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

451

#define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

452

#define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

456

#define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/txrx.h

457

#define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

458

#define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

465

#define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

468

#define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

469

#define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

470

#define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

471

#define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

472

#define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

473

#define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

480

#define RTW89_PHY_STS_HDR_V2_W0_PATH_EN GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

486

#define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

487

#define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)

drivers/net/wireless/realtek/rtw89/txrx.h

490

#define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

491

#define BE_RXD_SHIFT_MASK GENMASK(15, 14)

drivers/net/wireless/realtek/rtw89/txrx.h

492

#define BE_RXD_DRV_INFO_SZ_MASK GENMASK(19, 18)

drivers/net/wireless/realtek/rtw89/txrx.h

493

#define BE_RXD_HDR_CNV_SZ_MASK GENMASK(21, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

494

#define BE_RXD_PHY_RPT_SZ_MASK GENMASK(23, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

495

#define BE_RXD_RPKT_TYPE_MASK GENMASK(29, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

500

#define BE_RXD_PKT_ID_MASK GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

501

#define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

502

#define BE_RXD_BCN_FW_INFO_MASK GENMASK(25, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

506

#define BE_RXD_MAC_ID_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

507

#define BE_RXD_MAC_ID_V1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

508

#define BE_RXD_TYPE_MASK GENMASK(11, 10)

drivers/net/wireless/realtek/rtw89/txrx.h

513

#define BE_RXD_SEQ_MASK GENMASK(27, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

514

#define BE_RXD_TID_MASK GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

517

#define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

538

#define BE_RXD_FRAG_MASK GENMASK(27, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

539

#define BE_RXD_GET_CH_INFO_V2 GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/txrx.h

540

#define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)

drivers/net/wireless/realtek/rtw89/txrx.h

543

#define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

544

#define BE_RXD_PPDU_CNT_MASK GENMASK(10, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

545

#define BE_RXD_BW_MASK GENMASK(14, 12)

drivers/net/wireless/realtek/rtw89/txrx.h

546

#define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

548

#define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

551

#define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

554

#define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

555

#define BE_RXD_ADDR_CAM_V1 GENMASK(9, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

561

#define BE_RXD_USER_ID_MASK GENMASK(21, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

562

#define BE_RXD_SEC_CAM_IDX_V1 GENMASK(31, 22)

drivers/net/wireless/realtek/rtw89/txrx.h

565

#define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

568

#define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

573

#define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12)

drivers/net/wireless/realtek/rtw89/txrx.h

578

#define BE_RXD_RXSC_ENTRY_MASK GENMASK(22, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

584

#define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

587

#define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

588

#define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

589

#define BE_RXD_WL_HD_IV_LEN_MASK GENMASK(26, 21)

drivers/net/wireless/realtek/rtw89/txrx.h

592

#define BE_RXD_PHY_RSSI GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

601

#define RTW89_PHY_STS_IE00_W0_RPL GENMASK(15, 7)

drivers/net/wireless/realtek/rtw89/txrx.h

602

#define RTW89_PHY_STS_IE00_W3_RX_PATH_EN GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

615

#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

616

#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B GENMASK(17, 9)

drivers/net/wireless/realtek/rtw89/txrx.h

617

#define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C GENMASK(26, 18)

drivers/net/wireless/realtek/rtw89/txrx.h

618

#define RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D GENMASK(8, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

629

#define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

630

#define RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

631

#define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)

drivers/net/wireless/realtek/rtw89/txrx.h

632

#define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

633

#define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)

drivers/net/wireless/realtek/rtw89/txrx.h

634

#define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

635

#define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)

drivers/net/wireless/realtek/rtw89/txrx.h

636

#define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

653

#define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)

drivers/net/wireless/realtek/rtw89/txrx.h

654

#define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

655

#define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

656

#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C GENMASK(11, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

657

#define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D GENMASK(23, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

69

#define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

70

#define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

74

#define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

75

#define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)

drivers/net/wireless/realtek/rtw89/txrx.h

79

#define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)

drivers/net/wireless/realtek/rtw89/txrx.h

80

#define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

83

#define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)

drivers/net/wireless/realtek/rtw89/txrx.h

84

#define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)

drivers/net/wireless/realtek/rtw89/txrx.h

85

#define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)

drivers/net/wireless/realtek/rtw89/txrx.h

86

#define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

89

#define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)

drivers/net/wireless/realtek/rtw89/txrx.h

91

#define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)

drivers/net/wireless/realtek/rtw89/txrx.h

92

#define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)

drivers/net/wireless/realtek/rtw89/txrx.h

97

#define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)

drivers/net/wireless/realtek/rtw89/usb.c

26

value = u32_get_bits(addr, GENMASK(15, 0));

drivers/net/wireless/realtek/rtw89/usb.c

27

index = u32_get_bits(addr, GENMASK(23, 16));

drivers/net/wireless/realtek/rtw89/wow.c

1007

mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6)) |

drivers/net/wireless/realtek/rtw89/wow.c

1008

u8_get_bits(mask[i + 1], GENMASK(5, 0)) << 2;

drivers/net/wireless/realtek/rtw89/wow.c

1010

mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6));

drivers/net/wireless/realtek/rtw89/wow.c

1013

mask_hw[0] &= ~GENMASK(5, 0);

drivers/net/wireless/realtek/rtw89/wow.c

951

da_mask == GENMASK(5, 0))

drivers/net/wireless/realtek/rtw89/wow.c

982

mask[0] & GENMASK(5, 0));

drivers/net/wwan/t7xx/t7xx_cldma.h

104

#define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_cldma.h

105

#define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_cldma.h

25

#define CLDMA_ALL_Q GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_cldma.h

28

#define EMPTY_STATUS_BITMASK GENMASK(15, 8)

drivers/net/wwan/t7xx/t7xx_cldma.h

29

#define TXRX_STATUS_BITMASK GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_cldma.h

34

#define TQ_ERR_INT_BITMASK GENMASK(23, 16)

drivers/net/wwan/t7xx/t7xx_cldma.h

35

#define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)

drivers/net/wwan/t7xx/t7xx_cldma.h

37

#define RQ_ERR_INT_BITMASK GENMASK(23, 16)

drivers/net/wwan/t7xx/t7xx_cldma.h

38

#define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)

drivers/net/wwan/t7xx/t7xx_cldma.h

62

#define UL_CFG_BIT_MODE_MASK GENMASK(7, 5)

drivers/net/wwan/t7xx/t7xx_cldma.h

79

#define DL_CFG_BIT_MODE_MASK GENMASK(12, 10)

drivers/net/wwan/t7xx/t7xx_dpmaif.h

127

#define DP_UL_INT_QDONE_MSK GENMASK(4, 0)

drivers/net/wwan/t7xx/t7xx_dpmaif.h

128

#define DP_UL_INT_EMPTY_MSK GENMASK(9, 5)

drivers/net/wwan/t7xx/t7xx_dpmaif.h

129

#define DP_UL_INT_MD_NOTREADY_MSK GENMASK(14, 10)

drivers/net/wwan/t7xx/t7xx_dpmaif.h

130

#define DP_UL_INT_MD_PWR_NOTREADY_MSK GENMASK(19, 15)

drivers/net/wwan/t7xx/t7xx_dpmaif.h

131

#define DP_UL_INT_ERR_MSK GENMASK(24, 20)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.c

58

#define DPMAIF_RX_PUSH_THRESHOLD_MASK GENMASK(2, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

25

#define NETIF_MASK GENMASK(4, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

48

#define PD_PIT_DATA_LEN GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

49

#define PD_PIT_BUFFER_ID GENMASK(15, 3)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

54

#define PD_PIT_DLQ_DONE GENMASK(31, 30)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

55

#define PD_PIT_ULQ_DONE GENMASK(29, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

56

#define PD_PIT_HEADER_OFFSET GENMASK(23, 19)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

57

#define PD_PIT_BI_F GENMASK(18, 17)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

59

#define PD_PIT_RES GENMASK(15, 11)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

60

#define PD_PIT_H_BID GENMASK(10, 8)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

61

#define PD_PIT_PIT_SEQ GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

64

#define MSG_PIT_RES GENMASK(30, 27)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

65

#define MSG_PIT_NETWORK_TYPE GENMASK(26, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

66

#define MSG_PIT_CHANNEL_ID GENMASK(23, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

67

#define MSG_PIT_RES2 GENMASK(15, 12)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

68

#define MSG_PIT_HPC_IDX GENMASK(11, 8)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

69

#define MSG_PIT_SRC_QID GENMASK(7, 5)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

71

#define MSG_PIT_CHECKSUM GENMASK(3, 2)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

75

#define MSG_PIT_HP_IDX GENMASK(31, 27)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

76

#define MSG_PIT_CMD GENMASK(26, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

77

#define MSG_PIT_RES3 GENMASK(23, 21)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

78

#define MSG_PIT_FLOW GENMASK(20, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

79

#define MSG_PIT_COUNT GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

81

#define MSG_PIT_HASH GENMASK(31, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

82

#define MSG_PIT_RES4 GENMASK(23, 18)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

83

#define MSG_PIT_PRO GENMASK(17, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

84

#define MSG_PIT_VBID GENMASK(15, 3)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

85

#define MSG_PIT_RES5 GENMASK(2, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

87

#define MSG_PIT_DLQ_DONE GENMASK(31, 30)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

88

#define MSG_PIT_ULQ_DONE GENMASK(29, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

91

#define MSG_PIT_MR GENMASK(21, 20)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

92

#define MSG_PIT_RES7 GENMASK(19, 17)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

94

#define MSG_PIT_RES8 GENMASK(15, 11)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

95

#define MSG_PIT_H_BID GENMASK(10, 8)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_rx.h

96

#define MSG_PIT_PIT_SEQ GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

45

#define DRB_HDR_DATA_LEN GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

46

#define DRB_HDR_RESERVED GENMASK(15, 3)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

48

#define DRB_HDR_DTYP GENMASK(1, 0)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

50

#define DRB_MSG_DW2_RES GENMASK(31, 30)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

54

#define DRB_MSG_NETWORK_TYPE GENMASK(26, 24)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

55

#define DRB_MSG_CHANNEL_ID GENMASK(23, 16)

drivers/net/wwan/t7xx/t7xx_hif_dpmaif_tx.h

56

#define DRB_MSG_COUNT_L GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_modem_ops.c

51

#define FEATURE_VER GENMASK(7, 4)

drivers/net/wwan/t7xx/t7xx_modem_ops.c

52

#define FEATURE_MSK GENMASK(3, 0)

drivers/net/wwan/t7xx/t7xx_netdev.c

45

#define SBD_PACKET_TYPE_MASK GENMASK(7, 4)

drivers/net/wwan/t7xx/t7xx_port.h

34

#define PORT_CH_ID_MASK GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_port_ctrl_msg.c

30

#define PORT_MSG_VERSION GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_port_ctrl_msg.c

31

#define PORT_MSG_PRT_CNT GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_port_proxy.c

45

#define INVALID_SEQ_NUM GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_port_proxy.h

60

#define CCCI_H_SEQ_FLD GENMASK(30, 16)

drivers/net/wwan/t7xx/t7xx_port_proxy.h

61

#define CCCI_H_CHN_FLD GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_port_proxy.h

84

#define PORT_INFO_RSRVD GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_port_proxy.h

86

#define PORT_INFO_CH_ID GENMASK(14, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

110

#define MISC_STAGE_MASK GENMASK(2, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

114

#define MISC_LK_EVENT_MASK GENMASK(11, 8)

drivers/net/wwan/t7xx/t7xx_reg.h

115

#define HOST_EVENT_MASK GENMASK(31, 28)

drivers/net/wwan/t7xx/t7xx_reg.h

133

#define T7XX_PCIE_RESOURCE_STS_MSK GENMASK(4, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

146

#define MSIX_MSK_SET_ALL GENMASK(31, 24)

drivers/net/wwan/t7xx/t7xx_reg.h

193

#define DPMAIF_AP_ALL_L2TISAR0_MASK GENMASK(31, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

194

#define DPMAIF_AP_APDL_ALL_L2TISAR0_MASK GENMASK(31, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

195

#define DPMAIF_AP_IP_BUSY_MASK GENMASK(31, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

238

#define DPMA_HPC_ALL_INT_MASK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

261

#define DPMAIF_UL_DRB_RIDX_MSK GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_reg.h

274

#define DPMAIF_UL_ADD_COUNT_MASK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

275

#define DPMAIF_UL_ALL_QUE_ARB_EN GENMASK(11, 8)

drivers/net/wwan/t7xx/t7xx_reg.h

280

#define DPMAIF_DL_ADD_COUNT_MASK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

298

#define DPMAIF_PIT_SIZE_MSK GENMASK(17, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

300

#define DPMAIF_PIT_REM_CNT_MSK GENMASK(17, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

304

#define DPMAIF_BAT_SIZE_MSK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

306

#define DPMAIF_BAT_BID_MAXCNT_MSK GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_reg.h

307

#define DPMAIF_BAT_REMAIN_MINSZ_MSK GENMASK(15, 8)

drivers/net/wwan/t7xx/t7xx_reg.h

308

#define DPMAIF_PIT_CHK_NUM_MSK GENMASK(31, 24)

drivers/net/wwan/t7xx/t7xx_reg.h

309

#define DPMAIF_BAT_BUF_SZ_MSK GENMASK(16, 8)

drivers/net/wwan/t7xx/t7xx_reg.h

310

#define DPMAIF_FRG_BUF_SZ_MSK GENMASK(16, 8)

drivers/net/wwan/t7xx/t7xx_reg.h

311

#define DPMAIF_BAT_RSV_LEN_MSK GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

312

#define DPMAIF_PKT_ALIGN_MSK GENMASK(23, 22)

drivers/net/wwan/t7xx/t7xx_reg.h

314

#define DPMAIF_BAT_CHECK_THRES_MSK GENMASK(21, 16)

drivers/net/wwan/t7xx/t7xx_reg.h

315

#define DPMAIF_FRG_CHECK_THRES_MSK GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

319

#define DPMAIF_DRB_SIZE_MSK GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

321

#define DPMAIF_DL_RD_WR_IDX_MSK GENMASK(17, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

342

#define DPMAIF_DL_PIT_SEQ_MSK GENMASK(7, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

356

#define DPMAIF_DLQ_LOW_TIMEOUT_THRES_MKS GENMASK(15, 0)

drivers/net/wwan/t7xx/t7xx_reg.h

357

#define DPMAIF_DLQ_HIGH_TIMEOUT_THRES_MSK GENMASK(31, 16)

drivers/net/wwan/t7xx/t7xx_state_monitor.h

82

#define FSM_CMD_EX_REASON GENMASK(23, 16)

drivers/ntb/test/ntb_msi_test.c

341

ret = ntb_db_clear_mask(ntb, GENMASK(peers - 1, 0));

drivers/nvmem/an8855-efuse.c

15

#define AN8855_EFUSE_R50O GENMASK(30, 24)

drivers/nvmem/core.c

1639

*p &= GENMASK((cell->nbits % BITS_PER_BYTE) - 1, 0);

drivers/nvmem/core.c

1727

*b++ |= GENMASK(bit_offset - 1, 0) & v;

drivers/nvmem/core.c

1747

*p |= GENMASK(7, (nbits + bit_offset) % BITS_PER_BYTE) & v;

drivers/nvmem/imx-ocotp-ele.c

101

*buf++ = readl_relaxed(reg + (i << 2)) & GENMASK(15, 0);

drivers/nvmem/meson-mx-efuse.c

26

#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)

drivers/nvmem/meson-mx-efuse.c

31

#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)

drivers/nvmem/microchip-otpc.c

20

#define MCHP_OTPC_MR_ADDR GENMASK(31, 16)

drivers/nvmem/microchip-otpc.c

25

#define MCHP_OTPC_HR_SIZE GENMASK(15, 8)

drivers/nvmem/qfprom.c

35

#define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)

drivers/nvmem/qfprom.c

37

#define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)

drivers/nvmem/rockchip-otp.c

36

#define OTPC_USER_ADDR_MASK GENMASK(31, 16)

drivers/nvmem/rockchip-otp.c

38

#define OTPC_USE_USER_MASK GENMASK(16, 16)

drivers/nvmem/rockchip-otp.c

40

#define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)

drivers/nvmem/rockchip-otp.c

46

#define SBPI_DAP_ADDR_MASK GENMASK(31, 24)

drivers/nvmem/rockchip-otp.c

47

#define SBPI_CMD_VALID_MASK GENMASK(31, 16)

drivers/nvmem/rockchip-otp.c

53

#define SBPI_ENABLE_MASK GENMASK(16, 16)

drivers/nvmem/sc27xx-efuse.c

28

#define SC27XX_EFUSE_BLOCK_MASK GENMASK(4, 0)

drivers/nvmem/sprd-efuse.c

27

#define SPRD_EFUSE_ERR_CLR_MASK GENMASK(13, 0)

drivers/nvmem/sunplus-ocotp.c

38

#define OTP_RD_PERIOD GENMASK(15, 8)

drivers/nvmem/sunplus-ocotp.c

39

#define OTP_RD_PERIOD_MASK ~GENMASK(15, 8)

drivers/nvmem/vf610-ocotp.c

34

#define OCOTP_CTRL_WR_UNLOCK_MASK GENMASK(31, 16)

drivers/nvmem/vf610-ocotp.c

36

#define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)

drivers/nvmem/vf610-ocotp.c

42

#define OCOTP_TIMING_STROBE_READ_MASK GENMASK(21, 16)

drivers/nvmem/vf610-ocotp.c

44

#define OCOTP_TIMING_RELAX_MASK GENMASK(15, 12)

drivers/nvmem/vf610-ocotp.c

46

#define OCOTP_TIMING_STROBE_PROG_MASK GENMASK(11, 0)

drivers/nvmem/zynqmp_nvmem.c

15

#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)

drivers/nvmem/zynqmp_nvmem.c

16

#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)

drivers/pci/controller/cadence/pci-j721e.c

226

mask = GENMASK(9, 8);

drivers/pci/controller/cadence/pci-j721e.c

41

#define LINK_STATUS GENMASK(1, 0)

drivers/pci/controller/cadence/pci-j721e.c

53

#define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0)

drivers/pci/controller/cadence/pci-j721e.c

54

#define GENERATION_SEL_MASK GENMASK(1, 0)

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

111

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

219

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

49

(regval & ~GENMASK(0, 0)));

drivers/pci/controller/cadence/pcie-cadence-host.c

169

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-host.c

276

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

105

#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

108

#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

111

#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

120

#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

134

#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

137

#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

147

#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

156

#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

170

#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

173

#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

43

(GENMASK(5, 0) << (0x4 + (f) * 10))

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

47

(GENMASK(3, 0) << ((f) * 10))

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

56

#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

59

#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

62

#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14)

drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h

65

#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10)

drivers/pci/controller/cadence/pcie-cadence-hpa.c

113

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-hpa.c

146

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-hpa.c

18

if (pl_reg_val & GENMASK(0, 0))

drivers/pci/controller/cadence/pcie-cadence-hpa.c

58

(lower_32_bits(pci_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

123

#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

132

#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

144

#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

147

#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

150

#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

161

#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

170

#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

177

#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

184

#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

195

#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

206

#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

222

#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

225

#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

23

#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

27

#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

34

#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

41

#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

43

#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

60

(GENMASK(4, 0) << ((b) * 8))

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

64

(GENMASK(7, 5) << ((b) * 8))

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

73

#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

76

#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

79

#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)

drivers/pci/controller/cadence/pcie-cadence-lga-regs.h

82

#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)

drivers/pci/controller/cadence/pcie-cadence.c

124

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence.c

155

(lower_32_bits(cpu_addr) & GENMASK(31, 8));

drivers/pci/controller/cadence/pcie-cadence.c

31

if (pl_reg_val & GENMASK(0, 0))

drivers/pci/controller/cadence/pcie-cadence.c

71

(lower_32_bits(pci_addr) & GENMASK(31, 8));

drivers/pci/controller/dwc/pci-dra7xx.c

580

.b1co_mode_sel_mask = GENMASK(3, 2),

drivers/pci/controller/dwc/pci-dra7xx.c

590

.b1co_mode_sel_mask = GENMASK(3, 2),

drivers/pci/controller/dwc/pci-imx6.c

193

#define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))

drivers/pci/controller/dwc/pci-imx6.c

43

#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)

drivers/pci/controller/dwc/pci-imx6.c

60

#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)

drivers/pci/controller/dwc/pci-imx6.c

67

#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0)

drivers/pci/controller/dwc/pci-imx6.c

71

#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8)

drivers/pci/controller/dwc/pci-imx6.c

72

#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0)

drivers/pci/controller/dwc/pci-imx6.c

75

#define IMX95_PE0_LUT_REQID GENMASK(31, 16)

drivers/pci/controller/dwc/pci-imx6.c

76

#define IMX95_PE0_LUT_MASK GENMASK(15, 0)

drivers/pci/controller/dwc/pci-imx6.c

78

#define IMX95_SID_MASK GENMASK(5, 0)

drivers/pci/controller/dwc/pci-keystone.c

39

#define RTL GENMASK(15, 11)

drivers/pci/controller/dwc/pcie-al.c

103

#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)

drivers/pci/controller/dwc/pcie-al.c

113

#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-al.c

114

#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)

drivers/pci/controller/dwc/pcie-al.c

117

#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)

drivers/pci/controller/dwc/pcie-al.c

118

#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)

drivers/pci/controller/dwc/pcie-amd-mdb.c

29

#define AMD_MDB_TLP_PCIE_INTX_MASK GENMASK(23, 16)

drivers/pci/controller/dwc/pcie-artpec6.c

52

#define PCIECFG_DEVICE_TYPE_MASK GENMASK(19, 16)

drivers/pci/controller/dwc/pcie-bt1.c

116

#define BT1_PCIE_AXI2MGM_LANESEL_MASK GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-bt1.c

119

#define BT1_PCIE_AXI2MGM_PHYREG_ADDR_MASK GENMASK(20, 0)

drivers/pci/controller/dwc/pcie-bt1.c

125

#define BT1_PCIE_AXI2MGM_WDATA GENMASK(15, 0)

drivers/pci/controller/dwc/pcie-bt1.c

128

#define BT1_PCIE_AXI2MGM_RDATA GENMASK(15, 0)

drivers/pci/controller/dwc/pcie-bt1.c

206

mask = GENMASK(size * BITS_PER_BYTE - 1, 0);

drivers/pci/controller/dwc/pcie-bt1.c

43

#define BT1_CCU_PCIE_LTSSM_STATE_MASK GENMASK(5, 0)

drivers/pci/controller/dwc/pcie-bt1.c

88

#define BT1_CCU_PCIE_PM_DSTAT_MASK GENMASK(18, 16)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

18

#define LANE_SELECT GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

21

#define EINJ_VAL_DIFF GENMASK(28, 16)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

22

#define EINJ_VC_NUM GENMASK(14, 12)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

24

#define EINJ0_TYPE GENMASK(11, 8)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

26

#define EINJ2_TYPE GENMASK(9, 8)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

27

#define EINJ3_TYPE GENMASK(10, 8)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

28

#define EINJ4_TYPE GENMASK(10, 8)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

30

#define EINJ_COUNT GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

37

#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

38

#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

39

#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8)

drivers/pci/controller/dwc/pcie-designware-debugfs.c

41

#define EVENT_COUNTER_ENABLE GENMASK(4, 2)

drivers/pci/controller/dwc/pcie-designware-ep.c

438

rebar_ctrl &= ~GENMASK(31, 16);

drivers/pci/controller/dwc/pcie-designware.h

107

#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-designware.h

109

#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)

drivers/pci/controller/dwc/pcie-designware.h

128

#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)

drivers/pci/controller/dwc/pcie-designware.h

131

#define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-designware.h

133

#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8)

drivers/pci/controller/dwc/pcie-designware.h

137

#define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0)

drivers/pci/controller/dwc/pcie-designware.h

138

#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5)

drivers/pci/controller/dwc/pcie-designware.h

139

#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10)

drivers/pci/controller/dwc/pcie-designware.h

140

#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14)

drivers/pci/controller/dwc/pcie-designware.h

143

#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2)

drivers/pci/controller/dwc/pcie-designware.h

188

#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)

drivers/pci/controller/dwc/pcie-designware.h

189

#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)

drivers/pci/controller/dwc/pcie-designware.h

190

#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)

drivers/pci/controller/dwc/pcie-designware.h

209

#define PCIE_DMA_NUM_WR_CHAN GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-designware.h

210

#define PCIE_DMA_NUM_RD_CHAN GENMASK(19, 16)

drivers/pci/controller/dwc/pcie-designware.h

225

#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24)

drivers/pci/controller/dwc/pcie-designware.h

226

#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16)

drivers/pci/controller/dwc/pcie-designware.h

227

#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8)

drivers/pci/controller/dwc/pcie-designware.h

228

#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0)

drivers/pci/controller/dwc/pcie-designware.h

236

#define MARGINING_MAXLANES GENMASK(20, 16)

drivers/pci/controller/dwc/pcie-designware.h

237

#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8)

drivers/pci/controller/dwc/pcie-designware.h

238

#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0)

drivers/pci/controller/dwc/pcie-designware.h

259

#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-designware.h

75

#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)

drivers/pci/controller/dwc/pcie-designware.h

77

#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)

drivers/pci/controller/dwc/pcie-designware.h

81

#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)

drivers/pci/controller/dwc/pcie-designware.h

83

#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)

drivers/pci/controller/dwc/pcie-designware.h

88

#define PORT_LINK_MODE_MASK GENMASK(21, 16)

drivers/pci/controller/dwc/pcie-designware.h

97

#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)

drivers/pci/controller/dwc/pcie-dw-rockchip.c

38

#define PCIE_CLIENT_MODE_MASK GENMASK(7, 4)

drivers/pci/controller/dwc/pcie-dw-rockchip.c

56

#define PCIE_INTR_MASK GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-dw-rockchip.c

69

#define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1)

drivers/pci/controller/dwc/pcie-dw-rockchip.c

85

#define PCIE_LINKUP_MASK GENMASK(17, 16)

drivers/pci/controller/dwc/pcie-dw-rockchip.c

86

#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)

drivers/pci/controller/dwc/pcie-histb.c

44

#define PCIE_DEVICE_TYPE_MASK GENMASK(31, 28)

drivers/pci/controller/dwc/pcie-histb.c

49

#define PCIE_LTSSM_STATE_MASK GENMASK(5, 0)

drivers/pci/controller/dwc/pcie-keembay.c

32

#define EDMA_INT_EN GENMASK(7, 0)

drivers/pci/controller/dwc/pcie-keembay.c

47

#define LJPLL_FOUT_EN GENMASK(24, 21)

drivers/pci/controller/dwc/pcie-keembay.c

49

#define LJPLL_REF_DIV GENMASK(17, 12)

drivers/pci/controller/dwc/pcie-keembay.c

50

#define LJPLL_FB_DIV GENMASK(11, 0)

drivers/pci/controller/dwc/pcie-keembay.c

52

#define LJPLL_POST_DIV3A GENMASK(24, 22)

drivers/pci/controller/dwc/pcie-keembay.c

53

#define LJPLL_POST_DIV2A GENMASK(18, 16)

drivers/pci/controller/dwc/pcie-nxp-s32g.c

26

#define DEVICE_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-qcom-ep.c

147

#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)

drivers/pci/controller/dwc/pcie-qcom.c

101

#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)

drivers/pci/controller/dwc/pcie-qcom.c

102

#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)

drivers/pci/controller/dwc/pcie-qcom.c

103

#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)

drivers/pci/controller/dwc/pcie-qcom.c

106

#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)

drivers/pci/controller/dwc/pcie-qcom.c

107

#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)

drivers/pci/controller/dwc/pcie-qcom.c

110

#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)

drivers/pci/controller/dwc/pcie-qcom.c

119

#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)

drivers/pci/controller/dwc/pcie-rcar-gen4.c

45

#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)

drivers/pci/controller/dwc/pcie-rcar-gen4.c

722

rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22));

drivers/pci/controller/dwc/pcie-rcar-gen4.c

723

rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16));

drivers/pci/controller/dwc/pcie-rcar-gen4.c

724

rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6));

drivers/pci/controller/dwc/pcie-rcar-gen4.c

725

rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(1, 0));

drivers/pci/controller/dwc/pcie-rcar-gen4.c

726

rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15));

drivers/pci/controller/dwc/pcie-sophgo.c

21

#define PCIE_INT_SIGNAL_INTX GENMASK(8, 5)

drivers/pci/controller/dwc/pcie-sophgo.c

23

#define PCIE_INT_EN_INTX GENMASK(4, 1)

drivers/pci/controller/dwc/pcie-stm32.h

14

#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8)

drivers/pci/controller/dwc/pcie-tegra194.c

138

#define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)

drivers/pci/controller/dwc/pcie-tegra194.c

146

#define APPL_DM_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-tegra194.c

151

#define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12)

drivers/pci/controller/dwc/pcie-tegra194.c

154

#define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18)

drivers/pci/controller/dwc/pcie-tegra194.c

158

#define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)

drivers/pci/controller/dwc/pcie-tegra194.c

182

#define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(1, 0)

drivers/pci/controller/dwc/pcie-tegra194.c

189

#define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2)

drivers/pci/controller/dwc/pcie-tegra194.c

192

#define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0)

drivers/pci/controller/dwc/pcie-tegra194.c

197

#define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)

drivers/pci/controller/dwc/pcie-tegra194.c

198

#define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)

drivers/pci/controller/dwc/pcie-tegra194.c

52

#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)

drivers/pci/controller/dwc/pcie-tegra194.c

97

#define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6)

drivers/pci/controller/dwc/pcie-uniphier-ep.c

57

#define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8)

drivers/pci/controller/dwc/pcie-uniphier-ep.c

58

#define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0)

drivers/pci/controller/dwc/pcie-uniphier.c

47

#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)

drivers/pci/controller/dwc/pcie-uniphier.c

54

#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)

drivers/pci/controller/dwc/pcie-uniphier.c

55

#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)

drivers/pci/controller/dwc/pcie-uniphier.c

57

#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)

drivers/pci/controller/pci-aardvark.c

107

#define PCIE_ISR0_ERR_MASK GENMASK(13, 11)

drivers/pci/controller/pci-aardvark.c

110

#define PCIE_ISR0_ALL_MASK GENMASK(31, 0)

drivers/pci/controller/pci-aardvark.c

116

#define PCIE_ISR1_ALL_MASK GENMASK(31, 0)

drivers/pci/controller/pci-aardvark.c

121

#define PCIE_MSI_ALL_MASK GENMASK(31, 0)

drivers/pci/controller/pci-aardvark.c

123

#define PCIE_MSI_DATA_MASK GENMASK(15, 0)

drivers/pci/controller/pci-aardvark.c

1265

data_strobe = GENMASK(size - 1, 0) << offset;

drivers/pci/controller/pci-aardvark.c

141

#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)

drivers/pci/controller/pci-aardvark.c

144

#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)

drivers/pci/controller/pci-aardvark.c

147

#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)

drivers/pci/controller/pci-aardvark.c

151

#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)

drivers/pci/controller/pci-aardvark.c

157

#define OB_WIN_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/pci-aardvark.c

246

#define PCIE_IRQ_ALL_MASK GENMASK(31, 0)

drivers/pci/controller/pci-aardvark.c

47

#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/pci-aardvark.c

51

#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)

drivers/pci/controller/pci-mvebu.c

62

#define PCIE_INT_ALL_MASK GENMASK(31, 0)

drivers/pci/controller/pci-mvebu.c

73

#define PCIE_SSPL_VALUE_MASK GENMASK(7, 0)

drivers/pci/controller/pci-mvebu.c

75

#define PCIE_SSPL_SCALE_MASK GENMASK(9, 8)

drivers/pci/controller/pci-xgene-msi.c

29

#define MSI_GROUP_MASK GENMASK(22, 19)

drivers/pci/controller/pci-xgene-msi.c

30

#define MSI_INDEX_MASK GENMASK(18, 16)

drivers/pci/controller/pci-xgene-msi.c

31

#define MSI_INTR_MASK GENMASK(19, 16)

drivers/pci/controller/pci-xgene-msi.c

33

#define MSInRx_HWIRQ_MASK GENMASK(6, 4)

drivers/pci/controller/pci-xgene-msi.c

34

#define DATA_HWIRQ_MASK GENMASK(3, 0)

drivers/pci/controller/pcie-altera.c

90

#define AGLX_CFG_TARGET GENMASK(13, 12)

drivers/pci/controller/pcie-apple.c

100

#define PORT_OUTS_CPLS_SHRD GENMASK(14, 8)

drivers/pci/controller/pcie-apple.c

101

#define PORT_OUTS_CPLS_WAIT GENMASK(6, 0)

drivers/pci/controller/pcie-apple.c

119

#define PORT_OUTS_PREQS_HDR_MASK GENMASK(9, 0)

drivers/pci/controller/pcie-apple.c

121

#define PORT_OUTS_PREQS_DATA_MASK GENMASK(15, 0)

drivers/pci/controller/pcie-apple.c

138

#define PORT_MSIMAP_TARGET GENMASK(7, 0)

drivers/pci/controller/pcie-apple.c

95

#define PORT_RXWR_FIFO_HDR GENMASK(15, 10)

drivers/pci/controller/pcie-apple.c

96

#define PORT_RXWR_FIFO_DATA GENMASK(9, 0)

drivers/pci/controller/pcie-apple.c

98

#define PORT_RXRD_FIFO_REQ GENMASK(6, 0)

drivers/pci/controller/pcie-aspeed.c

101

#define ASPEED_REMAP_PCI_ADDR_63_32(x) (((x) >> 32) & GENMASK(31, 0))

drivers/pci/controller/pcie-aspeed.c

103

#define ASPEED_REMAP_PCI_ADDR_31_12(x) ((x) & GENMASK(31, 12))

drivers/pci/controller/pcie-aspeed.c

113

#define ASPEED_RC0_DECODE_DMA_BASE(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/pci/controller/pcie-aspeed.c

114

#define ASPEED_RC0_DECODE_DMA_LIMIT(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/pci/controller/pcie-aspeed.c

115

#define ASPEED_RC1_DECODE_DMA_BASE(x) FIELD_PREP(GENMASK(23, 16), x)

drivers/pci/controller/pcie-aspeed.c

116

#define ASPEED_RC1_DECODE_DMA_LIMIT(x) FIELD_PREP(GENMASK(31, 24), x)

drivers/pci/controller/pcie-aspeed.c

122

#define ASPEED_TLP_COMMON_FIELDS GENMASK(31, 24)

drivers/pci/controller/pcie-aspeed.c

125

#define CPL_STS(x) FIELD_GET(GENMASK(15, 13), (x))

drivers/pci/controller/pcie-aspeed.c

144

#define TLP_HEADER_BYTE_EN(x, y) ((GENMASK((x) - 1, 0) << ((y) % 4)))

drivers/pci/controller/pcie-aspeed.c

146

(((x) >> ((((z) % 4)) * 8)) & GENMASK((8 * (y)) - 1, 0))

drivers/pci/controller/pcie-aspeed.c

148

((((x) & GENMASK((8 * (y)) - 1, 0)) << ((((z) % 4)) * 8)))

drivers/pci/controller/pcie-aspeed.c

346

FIELD_PREP(GENMASK(11, 8), pcie->tx_tag) |

drivers/pci/controller/pcie-aspeed.c

42

#define ASPEED_PCIE_INTX_STS GENMASK(3, 0)

drivers/pci/controller/pcie-aspeed.c

508

FIELD_PREP(GENMASK(11, 8), pcie->tx_tag) |

drivers/pci/controller/pcie-aspeed.c

51

#define ASPEED_PCIE_STATUS_OF_TX GENMASK(25, 24)

drivers/pci/controller/pcie-aspeed.c

55

#define ASPEED_AHB_REMAP_LO_ADDR(x) (x & GENMASK(15, 4))

drivers/pci/controller/pcie-aspeed.c

56

#define ASPEED_AHB_MASK_LO_ADDR(x) FIELD_PREP(GENMASK(31, 20), x)

drivers/pci/controller/pcie-aspeed.c

808

u32 pci_addr_lo = pci_addr & GENMASK(31, 0);

drivers/pci/controller/pcie-aspeed.c

809

u32 pci_addr_hi = (pci_addr >> 32) & GENMASK(31, 0);

drivers/pci/controller/pcie-aspeed.c

85

#define ASPEED_CFGI_BYTE_EN_MASK GENMASK(19, 16)

drivers/pci/controller/pcie-brcmstb.c

207

#define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)

drivers/pci/controller/pcie-brcmstb.c

208

#define BRCM_INT_PCI_MSI_LEGACY_MASK GENMASK(31, \

drivers/pci/controller/pcie-mediatek-gen3.c

106

#define PCIE_RSRC_SYS_CLK_RDY_TIME_MASK GENMASK(7, 0)

drivers/pci/controller/pcie-mediatek-gen3.c

124

(((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)

drivers/pci/controller/pcie-mediatek-gen3.c

125

#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))

drivers/pci/controller/pcie-mediatek-gen3.c

128

#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))

drivers/pci/controller/pcie-mediatek-gen3.c

142

#define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0)

drivers/pci/controller/pcie-mediatek-gen3.c

273

bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);

drivers/pci/controller/pcie-mediatek-gen3.c

35

#define PCIE_BASE_CFG_SPEED GENMASK(15, 8)

drivers/pci/controller/pcie-mediatek-gen3.c

38

#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)

drivers/pci/controller/pcie-mediatek-gen3.c

39

#define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)

drivers/pci/controller/pcie-mediatek-gen3.c

423

GENMASK(pcie->max_link_speed - 2, 0));

drivers/pci/controller/pcie-mediatek-gen3.c

431

GENMASK(fls(pcie->num_lanes >> 2), 0));

drivers/pci/controller/pcie-mediatek-gen3.c

45

#define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)

drivers/pci/controller/pcie-mediatek-gen3.c

453

val &= ~GENMASK(31, 8);

drivers/pci/controller/pcie-mediatek-gen3.c

46

#define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8)

drivers/pci/controller/pcie-mediatek-gen3.c

47

#define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16)

drivers/pci/controller/pcie-mediatek-gen3.c

48

#define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24)

drivers/pci/controller/pcie-mediatek-gen3.c

51

#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))

drivers/pci/controller/pcie-mediatek-gen3.c

52

#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))

drivers/pci/controller/pcie-mediatek-gen3.c

53

#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16))

drivers/pci/controller/pcie-mediatek-gen3.c

66

#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)

drivers/pci/controller/pcie-mediatek-gen3.c

79

#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)

drivers/pci/controller/pcie-mediatek-gen3.c

83

GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)

drivers/pci/controller/pcie-mediatek-gen3.c

87

#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)

drivers/pci/controller/pcie-mediatek-gen3.c

90

#define PCIE_K_FINETUNE_MAX GENMASK(5, 0)

drivers/pci/controller/pcie-mediatek-gen3.c

91

#define PCIE_K_FINETUNE_ERR GENMASK(7, 6)

drivers/pci/controller/pcie-mediatek-gen3.c

92

#define PCIE_K_PRESET_TO_USE GENMASK(18, 8)

drivers/pci/controller/pcie-mediatek-gen3.c

95

#define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21)

drivers/pci/controller/pcie-mediatek-gen3.c

970

regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));

drivers/pci/controller/pcie-mediatek.c

112

#define APP_CPL_STATUS GENMASK(7, 5)

drivers/pci/controller/pcie-mediatek.c

118

#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))

drivers/pci/controller/pcie-mediatek.c

119

#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))

drivers/pci/controller/pcie-mediatek.c

120

#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))

drivers/pci/controller/pcie-mediatek.c

121

#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))

drivers/pci/controller/pcie-mediatek.c

122

#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))

drivers/pci/controller/pcie-mediatek.c

123

#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))

drivers/pci/controller/pcie-mediatek.c

124

#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))

drivers/pci/controller/pcie-mediatek.c

128

(GENMASK(((size) - 1), 0) << ((where) & 0x3))

drivers/pci/controller/pcie-mediatek.c

139

#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)

drivers/pci/controller/pcie-mediatek.c

47

#define PCIE_BAR_MAP_MAX GENMASK(31, 16)

drivers/pci/controller/pcie-mediatek.c

52

#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \

drivers/pci/controller/pcie-mediatek.c

53

((((regn) >> 8) & GENMASK(3, 0)) << 24))

drivers/pci/controller/pcie-mediatek.c

54

#define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))

drivers/pci/controller/pcie-mediatek.c

55

#define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))

drivers/pci/controller/pcie-mediatek.c

56

#define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))

drivers/pci/controller/pcie-mediatek.c

63

#define PCIE_FTS_NUM_MASK GENMASK(15, 8)

drivers/pci/controller/pcie-mediatek.c

67

#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))

drivers/pci/controller/pcie-mediatek.c

83

#define INTX_MASK GENMASK(19, 16)

drivers/pci/controller/pcie-mediatek.c

863

regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));

drivers/pci/controller/pcie-mediatek.c

94

#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))

drivers/pci/controller/pcie-mt7621.c

37

#define PCIE_FTS_NUM_MASK GENMASK(15, 8)

drivers/pci/controller/pcie-mt7621.c

57

#define PCIE_BAR_MAP_MAX GENMASK(30, 16)

drivers/pci/controller/pcie-rcar-ep.c

54

val &= ~GENMASK(2, 0);

drivers/pci/controller/pcie-rcar-ep.c

59

val &= ~GENMASK(14, 12);

drivers/pci/controller/pcie-rcar-ep.c

61

val &= ~GENMASK(7, 5);

drivers/pci/controller/pcie-rcar.h

65

#define MSICAP0_MMESE_MASK GENMASK(22, 20)

drivers/pci/controller/pcie-rcar.h

82

#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */

drivers/pci/controller/pcie-rcar.h

90

#define PMSTATE GENMASK(18, 16)

drivers/pci/controller/pcie-rockchip-host.c

80

return GENMASK(MAX_LANE_NUM - 1, 0);

drivers/pci/controller/pcie-rockchip.h

105

#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)

drivers/pci/controller/pcie-rockchip.h

162

#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)

drivers/pci/controller/pcie-rockchip.h

206

#define RC_REGION_0_TYPE_MASK GENMASK(3, 0)

drivers/pci/controller/pcie-rockchip.h

209

#define ROCKCHIP_PCIE_MSG_ROUTING_MASK GENMASK(7, 5)

drivers/pci/controller/pcie-rockchip.h

212

#define ROCKCHIP_PCIE_MSG_CODE_MASK GENMASK(15, 8)

drivers/pci/controller/pcie-rockchip.h

221

#define ROCKCHIP_PCIE_EP_MSI_CP1_MASK GENMASK(15, 8)

drivers/pci/controller/pcie-rockchip.h

224

#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17)

drivers/pci/controller/pcie-rockchip.h

226

#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20)

drivers/pci/controller/pcie-rockchip.h

231

#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8)

drivers/pci/controller/pcie-rockchip.h

240

(PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12)))

drivers/pci/controller/pcie-rockchip.h

242

(PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12)))

drivers/pci/controller/pcie-rockchip.h

252

#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)

drivers/pci/controller/pcie-rockchip.h

256

#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)

drivers/pci/controller/pcie-rockchip.h

265

#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)

drivers/pci/controller/pcie-rockchip.h

280

(GENMASK(4, 0) << ((b) * 8))

drivers/pci/controller/pcie-rockchip.h

285

(GENMASK(7, 5) << ((b) * 8))

drivers/pci/controller/pcie-rockchip.h

54

#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)

drivers/pci/controller/pcie-rockchip.h

58

#define PCIE_CLIENT_NEG_LINK_WIDTH_MASK GENMASK(7, 6)

drivers/pci/controller/pcie-rockchip.h

66

#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)

drivers/pci/controller/pcie-rzg3s-host.c

103

#define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8)

drivers/pci/controller/pcie-rzg3s-host.c

108

#define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1)

drivers/pci/controller/pcie-rzg3s-host.c

45

#define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24)

drivers/pci/controller/pcie-rzg3s-host.c

46

#define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19)

drivers/pci/controller/pcie-rzg3s-host.c

47

#define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16)

drivers/pci/controller/pcie-rzg3s-host.c

48

#define RZG3S_PCI_REQADR1_REG GENMASK(11, 0)

drivers/pci/controller/pcie-rzg3s-host.c

51

#define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0)

drivers/pci/controller/pcie-rzg3s-host.c

54

#define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16)

drivers/pci/controller/pcie-rzg3s-host.c

55

#define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8)

drivers/pci/controller/pcie-rzg3s-host.c

63

#define RZG3S_PCI_MSIRCVWADRL_MASK GENMASK(31, 3)

drivers/pci/controller/pcie-rzg3s-host.c

70

#define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2)

drivers/pci/controller/pcie-rzg3s-host.c

971

max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);

drivers/pci/controller/pcie-rzg3s-host.c

99

#define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10)

drivers/pci/controller/pcie-xilinx-cpm.c

69

#define XILINX_CPM_PCIE_IDRN_MASK GENMASK(19, 16)

drivers/pci/controller/pcie-xilinx-cpm.c

74

#define XILINX_CPM_PCIE_RPEFR_REQ_ID GENMASK(15, 0)

drivers/pci/controller/pcie-xilinx-dma-pl.c

60

#define XILINX_PCIE_DMA_IDRN_MASK GENMASK(19, 16)

drivers/pci/controller/pcie-xilinx-dma-pl.c

64

#define XILINX_PCIE_DMA_RPEFR_REQ_ID GENMASK(15, 0)

drivers/pci/controller/pcie-xilinx-nwl.c

113

#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)

drivers/pci/controller/pcie-xilinx-nwl.c

114

#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)

drivers/pci/controller/pcie-xilinx-nwl.c

129

#define E_ECAM_SIZE_LOC GENMASK(20, 16)

drivers/pci/controller/pcie-xilinx-nwl.c

133

#define CFG_DMA_REG_BAR GENMASK(2, 0)

drivers/pci/controller/pcie-xilinx-nwl.c

134

#define CFG_PCIE_CACHE GENMASK(7, 0)

drivers/pci/controller/pcie-xilinx.c

68

#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)

drivers/pci/controller/pcie-xilinx.c

74

#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)

drivers/pci/controller/pcie-xilinx.c

79

#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)

drivers/pci/controller/pcie-xilinx.c

83

#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

40

#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

41

#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)

drivers/pci/controller/plda/pcie-microchip-host.c

42

#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)

drivers/pci/controller/plda/pcie-microchip-host.c

43

#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)

drivers/pci/controller/plda/pcie-microchip-host.c

44

#define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

48

#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

49

#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)

drivers/pci/controller/plda/pcie-microchip-host.c

50

#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)

drivers/pci/controller/plda/pcie-microchip-host.c

51

#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)

drivers/pci/controller/plda/pcie-microchip-host.c

52

#define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

601

writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL);

drivers/pci/controller/plda/pcie-microchip-host.c

602

writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI);

drivers/pci/controller/plda/pcie-microchip-host.c

615

writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST);

drivers/pci/controller/plda/pcie-microchip-host.c

729

port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0);

drivers/pci/controller/plda/pcie-microchip-host.c

80

#define PCIE_EVENT_INT_MASK GENMASK(2, 0)

drivers/pci/controller/plda/pcie-microchip-host.c

84

#define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)

drivers/pci/controller/plda/pcie-plda-host.c

277

events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0);

drivers/pci/controller/plda/pcie-plda.h

17

#define REVISION_ID_MASK GENMASK(7, 0)

drivers/pci/controller/plda/pcie-plda.h

18

#define CLASS_CODE_ID_MASK GENMASK(31, 8)

drivers/pci/controller/plda/pcie-plda.h

21

#define NUM_MSI_MSGS_MASK GENMASK(6, 4)

drivers/pci/controller/plda/pcie-plda.h

71

#define SYS_AND_MSI_MASK GENMASK(31, 28)

drivers/pci/controller/plda/pcie-plda.h

92

#define ATR_SIZE_MASK GENMASK(6, 1)

drivers/pci/controller/plda/pcie-starfive.c

36

#define STG_SYSCON_AXI4_SLVL_AR_MASK GENMASK(22, 8)

drivers/pci/controller/plda/pcie-starfive.c

37

#define STG_SYSCON_AXI4_SLVL_PHY_AR(x) FIELD_PREP(GENMASK(20, 17), x)

drivers/pci/controller/plda/pcie-starfive.c

39

#define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0)

drivers/pci/controller/plda/pcie-starfive.c

40

#define STG_SYSCON_AXI4_SLVL_PHY_AW(x) FIELD_PREP(GENMASK(12, 9), x)

drivers/pci/controller/plda/pcie-starfive.c

418

plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)

drivers/pci/controller/plda/pcie-starfive.c

42

#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)

drivers/pci/endpoint/functions/pci-epf-ntb.c

62

#define DB_COUNT_MASK GENMASK(15, 0)

drivers/pci/endpoint/functions/pci-epf-vntb.c

67

#define DB_COUNT_MASK GENMASK(15, 0)

drivers/pci/ide.c

529

#define SEL_ADDR1_LOWER GENMASK(31, 20)

drivers/pci/of_property.c

40

#define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24)

drivers/pci/of_property.c

42

#define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16)

drivers/pci/of_property.c

43

#define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11)

drivers/pci/of_property.c

44

#define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8)

drivers/pci/of_property.c

45

#define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0)

drivers/pci/pci-bridge-emul.c

104

GENMASK(11, 8) | GENMASK(3, 0)),

drivers/pci/pci-bridge-emul.c

111

.rw = GENMASK(31, 20) | GENMASK(15, 4),

drivers/pci/pci-bridge-emul.c

114

.ro = GENMASK(19, 16) | GENMASK(3, 0),

drivers/pci/pci-bridge-emul.c

119

.rw = GENMASK(31, 20) | GENMASK(15, 4),

drivers/pci/pci-bridge-emul.c

122

.ro = GENMASK(19, 16) | GENMASK(3, 0),

drivers/pci/pci-bridge-emul.c

138

.ro = GENMASK(7, 0),

drivers/pci/pci-bridge-emul.c

157

.rw = (GENMASK(7, 0) |

drivers/pci/pci-bridge-emul.c

167

.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),

drivers/pci/pci-bridge-emul.c

181

.ro = GENMASK(30, 0),

drivers/pci/pci-bridge-emul.c

191

.ro = BIT(15) | GENMASK(5, 0),

drivers/pci/pci-bridge-emul.c

199

.rw = GENMASK(14, 0),

drivers/pci/pci-bridge-emul.c

206

.w1c = GENMASK(3, 0) << 16,

drivers/pci/pci-bridge-emul.c

207

.ro = GENMASK(5, 4) << 16,

drivers/pci/pci-bridge-emul.c

226

.rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),

drivers/pci/pci-bridge-emul.c

227

.ro = GENMASK(13, 0) << 16,

drivers/pci/pci-bridge-emul.c

228

.w1c = GENMASK(15, 14) << 16,

drivers/pci/pci-bridge-emul.c

243

.rw = GENMASK(14, 0),

drivers/pci/pci-bridge-emul.c

269

.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,

drivers/pci/pci-bridge-emul.c

278

.ro = BIT(31) | GENMASK(23, 0),

drivers/pci/pci-bridge-emul.c

288

.rw = GENMASK(15, 12) | GENMASK(10, 0),

drivers/pci/pci-bridge-emul.c

293

.ro = BIT(31) | GENMASK(24, 1),

drivers/pci/pci-bridge-emul.c

303

.rw = GENMASK(15, 0),

drivers/pci/pci-bridge-emul.c

305

.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,

drivers/pci/pci-bridge-emul.c

402

~GENMASK(15, 8);

drivers/pci/pci-bridge-emul.c

410

~GENMASK(31, 24);

drivers/pci/pci-bridge-emul.c

431

bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);

drivers/pci/pci-bridge-emul.c

432

bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);

drivers/pci/pci-bridge-emul.c

92

.rw = GENMASK(24, 0),

drivers/pci/pci-bridge-emul.c

94

.ro = GENMASK(31, 24),

drivers/pci/pci-bridge-emul.c

99

.rw = (GENMASK(15, 12) | GENMASK(7, 4)),

drivers/pci/pci.c

5999

speeds &= GENMASK(lnkcap & PCI_EXP_LNKCAP_SLS, 0);

drivers/pci/pcie/bwctrl.c

94

desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

34

#define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18)

drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

36

#define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13)

drivers/peci/controller/peci-aspeed.c

26

#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16)

drivers/peci/controller/peci-aspeed.c

27

#define ASPEED_PECI_CTRL_RD_MODE_MASK GENMASK(13, 12)

drivers/peci/controller/peci-aspeed.c

31

#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8)

drivers/peci/controller/peci-aspeed.c

40

#define ASPEED_PECI_T_NEGO_MSG_MASK GENMASK(15, 8)

drivers/peci/controller/peci-aspeed.c

41

#define ASPEED_PECI_T_NEGO_ADDR_MASK GENMASK(7, 0)

drivers/peci/controller/peci-aspeed.c

46

#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24)

drivers/peci/controller/peci-aspeed.c

55

#define ASPEED_PECI_RD_LEN_MASK GENMASK(23, 16)

drivers/peci/controller/peci-aspeed.c

56

#define ASPEED_PECI_WR_LEN_MASK GENMASK(15, 8)

drivers/peci/controller/peci-aspeed.c

57

#define ASPEED_PECI_TARGET_ADDR_MASK GENMASK(7, 0)

drivers/peci/controller/peci-aspeed.c

61

#define ASPEED_PECI_EXPECTED_RD_FCS_MASK GENMASK(23, 16)

drivers/peci/controller/peci-aspeed.c

62

#define ASPEED_PECI_EXPECTED_AW_FCS_AUTO_MASK GENMASK(15, 8)

drivers/peci/controller/peci-aspeed.c

63

#define ASPEED_PECI_EXPECTED_WR_FCS_MASK GENMASK(7, 0)

drivers/peci/controller/peci-aspeed.c

67

#define ASPEED_PECI_CAPTURED_RD_FCS_MASK GENMASK(23, 16)

drivers/peci/controller/peci-aspeed.c

68

#define ASPEED_PECI_CAPTURED_WR_FCS_MASK GENMASK(7, 0)

drivers/peci/controller/peci-aspeed.c

72

#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30)

drivers/peci/controller/peci-aspeed.c

76

#define ASPEED_PECI_INT_MASK GENMASK(4, 0)

drivers/peci/controller/peci-aspeed.c

85

#define ASPEED_PECI_INT_TIMING_RESULT_MASK GENMASK(29, 16)

drivers/peci/controller/peci-npcm.c

39

#define NPCM_PECI_RD_LEN_MASK GENMASK(6, 0)

drivers/peci/controller/peci-npcm.c

42

#define NPCM_PECI_CTL2_MASK GENMASK(7, 6)

drivers/peci/controller/peci-npcm.c

45

#define NPCM_PECI_WR_LEN_MASK GENMASK(6, 0)

drivers/peci/controller/peci-npcm.c

48

#define NPCM_PECI_PDDR_MASK GENMASK(4, 0)

drivers/peci/device.c

18

#define REVISION_NUM_MASK GENMASK(15, 8)

drivers/perf/alibaba_uncore_drw_pmu.c

110

#define DRW_CONFIG_EVENTID GENMASK(7, 0)

drivers/perf/alibaba_uncore_drw_pmu.c

346

val &= ~(GENMASK(7, 0) << shift);

drivers/perf/alibaba_uncore_drw_pmu.c

364

val &= ~(GENMASK(7, 0) << shift);

drivers/perf/alibaba_uncore_drw_pmu.c

50

#define ALI_DRW_PMU_CYCLE_CNT_HIGH_MASK GENMASK(23, 0)

drivers/perf/alibaba_uncore_drw_pmu.c

51

#define ALI_DRW_PMU_CYCLE_CNT_LOW_MASK GENMASK(31, 0)

drivers/perf/alibaba_uncore_drw_pmu.c

61

#define ALI_DRW_PMCOM_CNT_EVENT_MASK GENMASK(5, 0)

drivers/perf/alibaba_uncore_drw_pmu.c

75

#define ALI_DRW_PMCOM_CNT_OV_INTR_MASK GENMASK(23, 8)

drivers/perf/alibaba_uncore_drw_pmu.c

76

#define ALI_DRW_PMBW_CNT_OV_INTR_MASK GENMASK(7, 0)

drivers/perf/apple_m1_cpu_pmu.c

24

#define M1_PMU_CFG_EVENT GENMASK(7, 0)

drivers/perf/apple_m1_cpu_pmu.c

26

#define ANY_BUT_0_1 GENMASK(9, 2)

drivers/perf/apple_m1_cpu_pmu.c

27

#define ONLY_2_TO_7 GENMASK(7, 2)

drivers/perf/arm-cmn.c

31

#define CMN_CHILD_NODE_ADDR GENMASK(29, 0)

drivers/perf/arm-ni.c

19

#define NI_NODE_TYPE_NODE_ID GENMASK(31, 16)

drivers/perf/arm-ni.c

20

#define NI_NODE_TYPE_NODE_TYPE GENMASK(15, 0)

drivers/perf/arm-ni.c

34

#define NI_PIDR0_PART_7_0 GENMASK(7, 0)

drivers/perf/arm-ni.c

36

#define NI_PIDR1_PART_11_8 GENMASK(3, 0)

drivers/perf/arm-ni.c

38

#define NI_PIDR2_VERSION GENMASK(7, 4)

drivers/perf/arm-ni.c

46

#define NI_PMEVTYPER_NODE_TYPE GENMASK(12, 9)

drivers/perf/arm-ni.c

47

#define NI_PMEVTYPER_NODE_ID GENMASK(8, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

107

#define PMCFGR_SIZE GENMASK(13, 8)

drivers/perf/arm_cspmu/arm_cspmu.h

108

#define PMCFGR_N GENMASK(7, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

123

#define PMIIDR_IMPLEMENTER GENMASK(11, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

124

#define PMIIDR_IMPLEMENTER_DES_0 GENMASK(3, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

125

#define PMIIDR_IMPLEMENTER_DES_1 GENMASK(6, 4)

drivers/perf/arm_cspmu/arm_cspmu.h

126

#define PMIIDR_IMPLEMENTER_DES_2 GENMASK(11, 8)

drivers/perf/arm_cspmu/arm_cspmu.h

127

#define PMIIDR_REVISION GENMASK(15, 12)

drivers/perf/arm_cspmu/arm_cspmu.h

128

#define PMIIDR_VARIANT GENMASK(19, 16)

drivers/perf/arm_cspmu/arm_cspmu.h

129

#define PMIIDR_PRODUCTID GENMASK(31, 20)

drivers/perf/arm_cspmu/arm_cspmu.h

130

#define PMIIDR_PRODUCTID_PART_0 GENMASK(27, 20)

drivers/perf/arm_cspmu/arm_cspmu.h

131

#define PMIIDR_PRODUCTID_PART_1 GENMASK(31, 28)

drivers/perf/arm_cspmu/arm_cspmu.h

134

#define PMPIDR0_PART_0 GENMASK(7, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

137

#define PMPIDR1_DES_0 GENMASK(7, 4)

drivers/perf/arm_cspmu/arm_cspmu.h

138

#define PMPIDR1_PART_1 GENMASK(3, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

141

#define PMPIDR2_REVISION GENMASK(7, 4)

drivers/perf/arm_cspmu/arm_cspmu.h

142

#define PMPIDR2_DES_1 GENMASK(2, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

145

#define PMPIDR3_REVAND GENMASK(7, 4)

drivers/perf/arm_cspmu/arm_cspmu.h

146

#define PMPIDR3_CMOD GENMASK(3, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

149

#define PMPIDR4_SIZE GENMASK(7, 4)

drivers/perf/arm_cspmu/arm_cspmu.h

150

#define PMPIDR4_DES_2 GENMASK(3, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

96

#define PMCFGR_NCG GENMASK(31, 28)

drivers/perf/arm_dmc620_pmu.c

62

#define DMC620_PMU_COUNTERn_CONTROL_EVENT_MUX GENMASK(6, 2)

drivers/perf/arm_dmc620_pmu.c

63

#define DMC620_PMU_COUNTERn_CONTROL_INCR_MUX GENMASK(8, 7)

drivers/perf/arm_smmuv3_pmu.c

101

#define SMMU_PMCG_PIDR3_REVAND GENMASK(7, 4)

drivers/perf/arm_smmuv3_pmu.c

103

#define SMMU_PMCG_PIDR4_DES_2 GENMASK(3, 0)

drivers/perf/arm_smmuv3_pmu.c

110

#define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0)

drivers/perf/arm_smmuv3_pmu.c

74

#define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8)

drivers/perf/arm_smmuv3_pmu.c

75

#define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0)

drivers/perf/arm_smmuv3_pmu.c

79

#define SMMU_PMCG_IIDR_PRODUCTID GENMASK(31, 20)

drivers/perf/arm_smmuv3_pmu.c

80

#define SMMU_PMCG_IIDR_VARIANT GENMASK(19, 16)

drivers/perf/arm_smmuv3_pmu.c

81

#define SMMU_PMCG_IIDR_REVISION GENMASK(15, 12)

drivers/perf/arm_smmuv3_pmu.c

82

#define SMMU_PMCG_IIDR_IMPLEMENTER GENMASK(11, 0)

drivers/perf/arm_smmuv3_pmu.c

93

#define SMMU_PMCG_PIDR0_PART_0 GENMASK(7, 0)

drivers/perf/arm_smmuv3_pmu.c

95

#define SMMU_PMCG_PIDR1_DES_0 GENMASK(7, 4)

drivers/perf/arm_smmuv3_pmu.c

96

#define SMMU_PMCG_PIDR1_PART_1 GENMASK(3, 0)

drivers/perf/arm_smmuv3_pmu.c

98

#define SMMU_PMCG_PIDR2_REVISION GENMASK(7, 4)

drivers/perf/arm_smmuv3_pmu.c

99

#define SMMU_PMCG_PIDR2_DES_1 GENMASK(2, 0)

drivers/perf/cxl_pmu.c

249

#define CXL_PMU_ATTR_CONFIG2_HDM_MSK GENMASK(15, 0)

drivers/perf/cxl_pmu.c

62

#define CXL_PMU_FILTER_CFG_VALUE_MSK GENMASK(31, 0)

drivers/perf/cxl_pmu.c

637

cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */

drivers/perf/dwc_pcie_pmu.c

33

#define DWC_PCIE_CNT_EVENT_SEL GENMASK(27, 16)

drivers/perf/dwc_pcie_pmu.c

34

#define DWC_PCIE_CNT_LANE_SEL GENMASK(11, 8)

drivers/perf/dwc_pcie_pmu.c

36

#define DWC_PCIE_CNT_ENABLE GENMASK(4, 2)

drivers/perf/dwc_pcie_pmu.c

39

#define DWC_PCIE_EVENT_CLEAR GENMASK(1, 0)

drivers/perf/dwc_pcie_pmu.c

43

#define DWC_PCIE_CNT_EVENT_SEL_GROUP GENMASK(11, 8)

drivers/perf/dwc_pcie_pmu.c

44

#define DWC_PCIE_CNT_EVENT_SEL_EVID GENMASK(7, 0)

drivers/perf/dwc_pcie_pmu.c

49

#define DWC_PCIE_TIME_BASED_REPORT_SEL GENMASK(31, 24)

drivers/perf/dwc_pcie_pmu.c

50

#define DWC_PCIE_TIME_BASED_DURATION_SEL GENMASK(15, 8)

drivers/perf/dwc_pcie_pmu.c

66

#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0)

drivers/perf/dwc_pcie_pmu.c

67

#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16)

drivers/perf/dwc_pcie_pmu.c

68

#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20)

drivers/perf/fsl_imx9_ddr_perf.c

18

#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)

drivers/perf/fsl_imx9_ddr_perf.c

24

#define MX93_PMCFG2_ID GENMASK(17, 0)

drivers/perf/fsl_imx9_ddr_perf.c

30

#define MX95_PMCFG_ID_MASK GENMASK(9, 0)

drivers/perf/fsl_imx9_ddr_perf.c

31

#define MX95_PMCFG_ID GENMASK(25, 16)

drivers/perf/fsl_imx9_ddr_perf.c

50

#define PMLCA_EVENT GENMASK(22, 16)

drivers/perf/fsl_imx9_ddr_perf.c

56

#define CONFIG_EVENT_MASK GENMASK(7, 0)

drivers/perf/fsl_imx9_ddr_perf.c

57

#define CONFIG_COUNTER_MASK GENMASK(23, 16)

drivers/perf/hisilicon/hisi_pcie_pmu.c

187

return hisi_pcie_get_event(event) & GENMASK(15, 0);

drivers/perf/hisilicon/hisi_pcie_pmu.c

90

return FIELD_GET(GENMASK(_hi, _lo), event->attr._config); \

drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c

60

#define DDRC_UNIMPLEMENTED_REG GENMASK(31, 0)

drivers/perf/hisilicon/hisi_uncore_hha_pmu.c

47

#define HHA_SRCID_CMD GENMASK(16, 6)

drivers/perf/hisilicon/hisi_uncore_hha_pmu.c

48

#define HHA_SRCID_MSK GENMASK(30, 20)

drivers/perf/hisilicon/hisi_uncore_hha_pmu.c

50

#define HHA_EVTYPE_MASK GENMASK(7, 0)

drivers/perf/hisilicon/hisi_uncore_mn_pmu.c

31

#define HISI_MN_EVTYPE_MASK GENMASK(7, 0)

drivers/perf/hisilicon/hisi_uncore_noc_pmu.c

27

#define NOC_PMU_EVENT_CTRL_TYPE GENMASK(4, 0)

drivers/perf/hisilicon/hisi_uncore_noc_pmu.c

32

#define NOC_PMU_EVENT_CTRL_CHANNEL GENMASK(10, 8)

drivers/perf/hisilicon/hisi_uncore_pmu.h

46

#define HISI_EVENTID_MASK GENMASK(7, 0)

drivers/perf/hisilicon/hisi_uncore_uc_pmu.c

25

#define HISI_UC_TRACETAG_REQ_MSK GENMASK(9, 7)

drivers/perf/hisilicon/hisi_uncore_uc_pmu.c

30

#define HISI_UC_SRCID_MSK GENMASK(14, 1)

drivers/perf/hisilicon/hisi_uncore_uc_pmu.c

33

#define HISI_UC_EVENT_URING_MSK GENMASK(28, 27)

drivers/perf/hisilicon/hisi_uncore_uc_pmu.c

37

#define HISI_UC_EVTYPE_MASK GENMASK(7, 0)

drivers/perf/qcom_l2_pmu.c

58

#define L2PMRESR_GROUP_MASK GENMASK(7, 0)

drivers/perf/qcom_l2_pmu.c

927

l2_counter_present_mask = GENMASK(l2cache_pmu->num_counters - 2, 0) |

drivers/phy/allwinner/phy-sun50i-usb3.c

45

#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)

drivers/phy/allwinner/phy-sun50i-usb3.c

47

#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)

drivers/phy/allwinner/phy-sun50i-usb3.c

49

#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)

drivers/phy/allwinner/phy-sun50i-usb3.c

51

#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)

drivers/phy/allwinner/phy-sun50i-usb3.c

53

#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

100

#define SUN6I_DPHY_ANA3_EN_VTTD_MASK GENMASK(31, 28)

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

227

u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

334

u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

94

#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK GENMASK(27, 24)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

19

#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

22

#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

23

#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

27

#define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

34

#define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

35

#define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

39

#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)

drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

40

#define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)

drivers/phy/amlogic/phy-meson-axg-pcie.c

18

#define MESON_PCIE_PORT_SEL GENMASK(3, 2)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

21

#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

22

#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

26

#define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

29

#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

30

#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)

drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

31

#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

102

#define PHY_CTRL_R18_MPLL_LKW_SEL GENMASK(1, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

103

#define PHY_CTRL_R18_MPLL_LK_W GENMASK(5, 2)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

104

#define PHY_CTRL_R18_MPLL_LK_S GENMASK(11, 6)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

107

#define PHY_CTRL_R18_MPLL_PFD_GAIN GENMASK(15, 14)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

108

#define PHY_CTRL_R18_MPLL_ROU GENMASK(18, 16)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

109

#define PHY_CTRL_R18_MPLL_DATA_SEL GENMASK(21, 19)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

110

#define PHY_CTRL_R18_MPLL_BIAS_ADJ GENMASK(23, 22)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

111

#define PHY_CTRL_R18_MPLL_BB_MODE GENMASK(25, 24)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

112

#define PHY_CTRL_R18_MPLL_ALPHA GENMASK(28, 26)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

113

#define PHY_CTRL_R18_MPLL_ADJ_LDO GENMASK(30, 29)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

119

#define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 GENMASK(3, 1)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

125

#define PHY_CTRL_R20_USB2_DMON_SEL_3_0 GENMASK(12, 9)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

127

#define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 GENMASK(15, 14)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

128

#define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

130

#define PHY_CTRL_R20_USB2_BGR_VREF_4_0 GENMASK(28, 24)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

131

#define PHY_CTRL_R20_USB2_BGR_DBG_1_0 GENMASK(30, 29)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

139

#define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

140

#define PHY_CTRL_R21_BYPASS_UTMI_CNTR GENMASK(15, 6)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

141

#define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

27

#define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

28

#define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

29

#define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

32

#define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

33

#define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

34

#define PHY_CTRL_R4_CALIB_CODE_23_16 GENMASK(23, 16)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

39

#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

40

#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

51

#define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

54

#define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

69

#define PHY_CTRL_R14_I_RPU_SW2_EN GENMASK(3, 2)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

73

#define PHY_CTRL_R14_BYPASS_CTRL_7_0 GENMASK(15, 8)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

74

#define PHY_CTRL_R14_BYPASS_CTRL_15_8 GENMASK(23, 16)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

78

#define PHY_CTRL_R16_MPLL_M GENMASK(8, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

79

#define PHY_CTRL_R16_MPLL_N GENMASK(14, 10)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

84

#define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

93

#define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

95

#define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

96

#define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

98

#define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24)

drivers/phy/amlogic/phy-meson-g12a-usb2.c

99

#define PHY_CTRL_R17_MPLL_FILTER_PVT1 GENMASK(31, 28)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

22

#define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

23

#define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

26

#define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

27

#define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

28

#define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

29

#define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

30

#define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

31

#define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

33

#define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

36

#define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

37

#define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

38

#define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

39

#define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

44

#define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

49

#define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

37

#define U2P_R0_FSEL_MASK GENMASK(19, 17)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

38

#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

40

#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

56

#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

57

#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

58

#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

59

#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

60

#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

61

#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

62

#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

63

#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

64

#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

68

#define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

69

#define U2P_R2_TESTADDR_MASK GENMASK(11, 8)

drivers/phy/amlogic/phy-meson-gxl-usb2.c

72

#define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)

drivers/phy/amlogic/phy-meson8-hdmi-tx.c

26

#define HHI_HDMI_PHY_CNTL0_HDMI_CTL1 GENMASK(31, 16)

drivers/phy/amlogic/phy-meson8-hdmi-tx.c

27

#define HHI_HDMI_PHY_CNTL0_HDMI_CTL0 GENMASK(15, 0)

drivers/phy/amlogic/phy-meson8b-usb2.c

103

#define REG_TUNE_TX_RES_TUNE_MASK GENMASK(1, 0)

drivers/phy/amlogic/phy-meson8b-usb2.c

104

#define REG_TUNE_TX_HSXV_TUNE_MASK GENMASK(3, 2)

drivers/phy/amlogic/phy-meson8b-usb2.c

105

#define REG_TUNE_TX_VREF_TUNE_MASK GENMASK(7, 4)

drivers/phy/amlogic/phy-meson8b-usb2.c

106

#define REG_TUNE_TX_RISE_TUNE_MASK GENMASK(9, 8)

drivers/phy/amlogic/phy-meson8b-usb2.c

108

#define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK GENMASK(12, 11)

drivers/phy/amlogic/phy-meson8b-usb2.c

109

#define REG_TUNE_TX_FSLS_TUNE_MASK GENMASK(16, 13)

drivers/phy/amlogic/phy-meson8b-usb2.c

110

#define REG_TUNE_SQRX_TUNE_MASK GENMASK(19, 17)

drivers/phy/amlogic/phy-meson8b-usb2.c

111

#define REG_TUNE_OTG_TUNE GENMASK(22, 20)

drivers/phy/amlogic/phy-meson8b-usb2.c

112

#define REG_TUNE_COMP_DIS_TUNE GENMASK(25, 23)

drivers/phy/amlogic/phy-meson8b-usb2.c

23

#define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)

drivers/phy/amlogic/phy-meson8b-usb2.c

24

#define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)

drivers/phy/amlogic/phy-meson8b-usb2.c

31

#define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)

drivers/phy/amlogic/phy-meson8b-usb2.c

42

#define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)

drivers/phy/amlogic/phy-meson8b-usb2.c

43

#define REG_CTRL_FSEL_MASK GENMASK(24, 22)

drivers/phy/amlogic/phy-meson8b-usb2.c

45

#define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)

drivers/phy/amlogic/phy-meson8b-usb2.c

93

#define REG_TEST_DATA_IN_MASK GENMASK(3, 0)

drivers/phy/amlogic/phy-meson8b-usb2.c

94

#define REG_TEST_EN_MASK GENMASK(7, 4)

drivers/phy/amlogic/phy-meson8b-usb2.c

95

#define REG_TEST_ADDR_MASK GENMASK(11, 8)

drivers/phy/amlogic/phy-meson8b-usb2.c

98

#define REG_TEST_VA_TEST_EN_B_MASK GENMASK(15, 14)

drivers/phy/amlogic/phy-meson8b-usb2.c

99

#define REG_TEST_DATA_OUT_MASK GENMASK(19, 16)

drivers/phy/apple/atc.c

101

#define AUSPLL_FREQ_REFCLK GENMASK(1, 0)

drivers/phy/apple/atc.c

104

#define AUS_VREG_TRIM GENMASK(6, 2)

drivers/phy/apple/atc.c

107

#define AUS_UNK_A20_TX_CAL_CODE GENMASK(23, 20)

drivers/phy/apple/atc.c

117

#define CIO3PLL_DCO_COARSEBIN_EFUSE0 GENMASK(6, 0)

drivers/phy/apple/atc.c

118

#define CIO3PLL_DCO_COARSEBIN_EFUSE1 GENMASK(23, 17)

drivers/phy/apple/atc.c

121

#define CIO3PLL_DLL_CAL_START_CAPCODE GENMASK(18, 17)

drivers/phy/apple/atc.c

124

#define CIO3PLL_DTC_VREG_ADJUST GENMASK(16, 14)

drivers/phy/apple/atc.c

130

#define ACIOPHY_CFG0_RX_SMALL_OV GENMASK(9, 8)

drivers/phy/apple/atc.c

131

#define ACIOPHY_CFG0_RX_BIG_OV GENMASK(13, 12)

drivers/phy/apple/atc.c

132

#define ACIOPHY_CFG0_RX_CLAMP_OV GENMASK(17, 16)

drivers/phy/apple/atc.c

135

#define ACIOPHY_CROSSBAR_PROTOCOL GENMASK(4, 0)

drivers/phy/apple/atc.c

143

#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA GENMASK(16, 5)

drivers/phy/apple/atc.c

150

#define ACIOPHY_LANE_MODE_RX0 GENMASK(2, 0)

drivers/phy/apple/atc.c

151

#define ACIOPHY_LANE_MODE_TX0 GENMASK(5, 3)

drivers/phy/apple/atc.c

152

#define ACIOPHY_LANE_MODE_RX1 GENMASK(8, 6)

drivers/phy/apple/atc.c

153

#define ACIOPHY_LANE_MODE_TX1 GENMASK(11, 9)

drivers/phy/apple/atc.c

181

#define ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN GENMASK(13, 10)

drivers/phy/apple/atc.c

184

#define ACIOPHY_SLEEP_CTRL_TX_BIG_OV GENMASK(3, 2)

drivers/phy/apple/atc.c

185

#define ACIOPHY_SLEEP_CTRL_TX_SMALL_OV GENMASK(7, 6)

drivers/phy/apple/atc.c

186

#define ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV GENMASK(11, 10)

drivers/phy/apple/atc.c

189

#define ACIOPHY_PLL_APB_REQ_OV_SEL GENMASK(21, 13)

drivers/phy/apple/atc.c

210

#define DPTX_PCLK1_SELECT GENMASK(6, 4)

drivers/phy/apple/atc.c

211

#define DPTX_PCLK2_SELECT GENMASK(9, 7)

drivers/phy/apple/atc.c

212

#define DPRX_PCLK_SELECT GENMASK(12, 10)

drivers/phy/apple/atc.c

256

#define LN_DTVREG_ADJUST GENMASK(31, 27)

drivers/phy/apple/atc.c

290

#define LN_TX_CAL_CODE GENMASK(29, 25)

drivers/phy/apple/atc.c

294

#define LN_TX_MARGIN GENMASK(19, 15)

drivers/phy/apple/atc.c

298

#define LN_TX_MARGIN_P1 GENMASK(26, 23)

drivers/phy/apple/atc.c

300

#define LN_TX_MARGIN_P1_LSB GENMASK(29, 28)

drivers/phy/apple/atc.c

304

#define LN_TX_P1_CODE GENMASK(3, 0)

drivers/phy/apple/atc.c

306

#define LN_TX_P1_LSB_CODE GENMASK(6, 5)

drivers/phy/apple/atc.c

308

#define LN_TX_MARGIN_PRE GENMASK(10, 8)

drivers/phy/apple/atc.c

310

#define LN_TX_MARGIN_PRE_LSB GENMASK(13, 12)

drivers/phy/apple/atc.c

312

#define LN_TX_PRE_LSB_CODE GENMASK(16, 15)

drivers/phy/apple/atc.c

314

#define LN_TX_PRE_CODE GENMASK(21, 18)

drivers/phy/apple/atc.c

322

#define LN_TX_CLK_DLY_CTRL_TAPGEN GENMASK(27, 25)

drivers/phy/apple/atc.c

331

#define LN_VREF_ADJUST_GRAY GENMASK(11, 7)

drivers/phy/apple/atc.c

333

#define LN_VREF_BIAS_SEL GENMASK(14, 13)

drivers/phy/apple/atc.c

339

#define LN_VREF_LPBKIN_DATA GENMASK(29, 28)

drivers/phy/apple/atc.c

360

#define LN_TXA_CAL_CTRL GENMASK(18, 1)

drivers/phy/apple/atc.c

362

#define LN_TXA_CAL_CTRL_BASE GENMASK(23, 20)

drivers/phy/apple/atc.c

369

#define LN_TXA_MARGIN GENMASK(18, 1)

drivers/phy/apple/atc.c

375

#define LN_TXA_MARGIN_POST GENMASK(10, 1)

drivers/phy/apple/atc.c

381

#define LN_TXA_MARGIN_PRE GENMASK(21, 16)

drivers/phy/apple/atc.c

404

#define LPDPTX_BLK_AUX_RXOFFSET GENMASK(25, 22)

drivers/phy/apple/atc.c

410

#define LPDPTX_AUX_MARGIN_RCAL_TXSWING GENMASK(10, 6)

drivers/phy/apple/atc.c

416

#define LPDPTX_CFG_PMA_PHYS_ADJ GENMASK(22, 20)

drivers/phy/apple/atc.c

425

#define LPDPTX_TXTERM_CODE GENMASK(9, 5)

drivers/phy/apple/atc.c

438

#define PIPEHANDLER_MUX_CTRL_CLK GENMASK(5, 3)

drivers/phy/apple/atc.c

439

#define PIPEHANDLER_MUX_CTRL_DATA GENMASK(2, 0)

drivers/phy/apple/atc.c

460

#define PIPEHANDLER_NATIVE_POWER_DOWN GENMASK(3, 0)

drivers/phy/apple/atc.c

53

#define AUSPLL_APB_CMD_OVERRIDE_CMD GENMASK(27, 3)

drivers/phy/apple/atc.c

56

#define AUSPLL_FD_FREQ_COUNT_TARGET GENMASK(9, 0)

drivers/phy/apple/atc.c

58

#define AUSPLL_FD_REV_DIVN GENMASK(13, 11)

drivers/phy/apple/atc.c

59

#define AUSPLL_FD_KI_MAN GENMASK(17, 14)

drivers/phy/apple/atc.c

60

#define AUSPLL_FD_KI_EXP GENMASK(21, 18)

drivers/phy/apple/atc.c

61

#define AUSPLL_FD_KP_MAN GENMASK(25, 22)

drivers/phy/apple/atc.c

62

#define AUSPLL_FD_KP_EXP GENMASK(29, 26)

drivers/phy/apple/atc.c

63

#define AUSPLL_FD_KPKI_SCALE_HBW GENMASK(31, 30)

drivers/phy/apple/atc.c

66

#define AUSPLL_FD_FBDIVN_FRAC_DEN GENMASK(13, 0)

drivers/phy/apple/atc.c

67

#define AUSPLL_FD_FBDIVN_FRAC_NUM GENMASK(27, 14)

drivers/phy/apple/atc.c

70

#define AUSPLL_FD_SDM_SSC_STEP GENMASK(7, 0)

drivers/phy/apple/atc.c

72

#define AUSPLL_FD_PCLK_DIV_SEL GENMASK(13, 9)

drivers/phy/apple/atc.c

73

#define AUSPLL_FD_LFSDM_DIV GENMASK(15, 14)

drivers/phy/apple/atc.c

74

#define AUSPLL_FD_LFCLK_CTRL GENMASK(19, 16)

drivers/phy/apple/atc.c

75

#define AUSPLL_FD_VCLK_OP_DIVN GENMASK(21, 20)

drivers/phy/apple/atc.c

79

#define AUSPLL_RODCO_ENCAP_EFUSE GENMASK(10, 9)

drivers/phy/apple/atc.c

80

#define AUSPLL_RODCO_BIAS_ADJUST_EFUSE GENMASK(14, 12)

drivers/phy/apple/atc.c

83

#define AUSPLL_DLL_START_CAPCODE GENMASK(18, 17)

drivers/phy/apple/atc.c

91

#define AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI GENMASK(20, 16)

drivers/phy/apple/atc.c

97

#define AUSPLL_DTC_VREG_ADJUST GENMASK(16, 14)

drivers/phy/broadcom/phy-brcm-sata.c

387

tmp = GENMASK(15, 12);

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

101

#define BDC_EC_AXIRDA_RTS_MASK GENMASK(31, 28)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

21

#define PIARBCTL_MISC_SATA_PRIORITY_MASK GENMASK(3, 0)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

22

#define PIARBCTL_MISC_CAM0_MEM_PAGE_MASK GENMASK(7, 4)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

23

#define PIARBCTL_MISC_CAM1_MEM_PAGE_MASK GENMASK(11, 8)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

24

#define PIARBCTL_MISC_USB_MEM_PAGE_MASK GENMASK(15, 12)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

25

#define PIARBCTL_MISC_USB_PRIORITY_MASK GENMASK(19, 16)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

56

#define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK GENMASK(1, 0)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

58

#define USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK GENMASK(7, 0)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

67

#define USB_CTRL_P0_U2PHY_CFG2_TXVREFTUNE0_MASK GENMASK(20, 17)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

69

#define USB_CTRL_P0_U2PHY_CFG2_TXRESTUNE0_MASK GENMASK(24, 23)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

71

#define USB_CTRL_P0_U2PHY_CFG2_TXPREEMPAMPTUNE0_MASK GENMASK(26, 25)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

83

#define USB_PHY_UTMI_CTL_1_PHY_MODE_MASK GENMASK(3, 2)

drivers/phy/broadcom/phy-brcm-usb-init.c

40

#define USB_CTRL_SETUP_OC_DISABLE_MASK GENMASK(29, 28) /* option */

drivers/phy/broadcom/phy-brcm-usb-init.c

43

#define USB_CTRL_SETUP_OC3_DISABLE_MASK GENMASK(31, 30) /* option */

drivers/phy/broadcom/phy-brcm-usb-init.c

49

#define USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK GENMASK(11, 7) /* option */

drivers/phy/broadcom/phy-brcm-usb-init.c

60

#define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK GENMASK(21, 20) /* option */

drivers/phy/broadcom/phy-brcm-usb-init.c

63

#define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK GENMASK(29, 28) /* option */

drivers/phy/broadcom/phy-brcm-usb-init.c

79

#define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK GENMASK(1, 0) /* option */

drivers/phy/cadence/cdns-dphy-rx.c

25

#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1)

drivers/phy/cadence/cdns-dphy-rx.c

31

#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)

drivers/phy/cadence/cdns-dphy-rx.c

32

#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)

drivers/phy/cadence/cdns-dphy.c

33

#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1)

drivers/phy/cadence/cdns-dphy.c

52

#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)

drivers/phy/cadence/cdns-dphy.c

53

#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)

drivers/phy/cadence/cdns-dphy.c

64

#define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0)

drivers/phy/cadence/cdns-dphy.c

65

#define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8)

drivers/phy/cadence/cdns-dphy.c

66

#define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16)

drivers/phy/cadence/phy-cadence-salvo.c

106

#define RX_USB2_DISCONN_MASK GENMASK(7, 6)

drivers/phy/cadence/phy-cadence-torrent.c

325

#define REFCLK0_MASK GENMASK(18, 15)

drivers/phy/cadence/phy-cadence-torrent.c

327

#define REFCLK1_MASK GENMASK(14, 11)

drivers/phy/cadence/phy-cadence-torrent.c

329

#define LINK0_MASK GENMASK(10, 7)

drivers/phy/cadence/phy-cadence-torrent.c

331

#define LINK1_MASK GENMASK(6, 3)

drivers/phy/cadence/phy-cadence-torrent.c

333

#define SSC_MASK GENMASK(2, 0)

drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c

26

#define CCM_MASK GENMASK(7, 5)

drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c

29

#define CA_MASK GENMASK(4, 2)

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

27

#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6)

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

34

#define ANA_AUX_TX_LVL GENMASK(3, 0)

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

40

#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

17

#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

20

#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

37

#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

38

#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

39

#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

40

#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

41

#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

44

#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

51

#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

70

#define TCA_GCFG_OP_MODE GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

78

#define TCA_TCPC_MUX_CONTRL GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

93

#define TCA_PSTATE_PIPE0_POWER_DOWN GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

33

#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

34

#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

35

#define HSIO_MODE_MASK GENMASK(20, 17)

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

38

#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)

drivers/phy/freescale/phy-fsl-imx8qm-hsio.c

48

#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

22

#define M_MASK GENMASK(18, 17)

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

24

#define CCM_MASK GENMASK(16, 14)

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

26

#define CA_MASK GENMASK(13, 11)

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

28

#define TST_MASK GENMASK(10, 5)

drivers/phy/freescale/phy-fsl-lynx-28g.c

111

#define LNaRGCR0_N_RATE GENMASK(26, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

121

#define LNaRGCR1_ENTER_IDLE_FLT_SEL GENMASK(26, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

122

#define LNaRGCR1_EXIT_IDLE_FLT_SEL GENMASK(22, 20)

drivers/phy/freescale/phy-fsl-lynx-28g.c

123

#define LNaRGCR1_DATA_LOST_TH_SEL GENMASK(18, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

124

#define LNaRGCR1_EXT_REC_CLK_SEL GENMASK(10, 8)

drivers/phy/freescale/phy-fsl-lynx-28g.c

128

#define LNaRGCR1_PWR_MGT GENMASK(2, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

132

#define LNaRECR0_EQ_GAINK2_HF_OV GENMASK(28, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

134

#define LNaRECR0_EQ_GAINK3_MF_OV GENMASK(20, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

137

#define LNaRECR0_EQ_GAINK4_LF_OV GENMASK(4, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

141

#define LNaRECR1_EQ_BLW_OV GENMASK(28, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

143

#define LNaRECR1_EQ_OFFSET_OV GENMASK(21, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

147

#define LNaRECR2_EQ_BOOST GENMASK(29, 28)

drivers/phy/freescale/phy-fsl-lynx-28g.c

148

#define LNaRECR2_EQ_BLW_SEL GENMASK(25, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

149

#define LNaRECR2_EQ_ZERO GENMASK(17, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

150

#define LNaRECR2_EQ_IND GENMASK(13, 12)

drivers/phy/freescale/phy-fsl-lynx-28g.c

151

#define LNaRECR2_EQ_BIN_DATA_AVG_TC GENMASK(5, 4)

drivers/phy/freescale/phy-fsl-lynx-28g.c

152

#define LNaRECR2_SPARE_IN GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

157

#define LNaRECR3_EQ_GAINK2_HF_STAT GENMASK(28, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

158

#define LNaRECR3_EQ_GAINK3_MF_STAT GENMASK(20, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

159

#define LNaRECR3_SPARE_OUT GENMASK(13, 12)

drivers/phy/freescale/phy-fsl-lynx-28g.c

160

#define LNaRECR3_EQ_GAINK4_LF_STAT GENMASK(4, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

163

#define LNaRECR4_BLW_STAT GENMASK(28, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

164

#define LNaRECR4_EQ_OFFSET_STAT GENMASK(21, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

165

#define LNaRECR4_EQ_BIN_DATA_SEL GENMASK(15, 12)

drivers/phy/freescale/phy-fsl-lynx-28g.c

166

#define LNaRECR4_EQ_BIN_DATA GENMASK(8, 0) /* bit 9 is reserved */

drivers/phy/freescale/phy-fsl-lynx-28g.c

178

#define LNaRCCR0_CAL_AC3_OV GENMASK(11, 8)

drivers/phy/freescale/phy-fsl-lynx-28g.c

189

#define LNaRSCCR0_SMP_AUTOZ_CTRL GENMASK(19, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

190

#define LNaRSCCR0_SMP_AUTOZ_D1R GENMASK(13, 12)

drivers/phy/freescale/phy-fsl-lynx-28g.c

191

#define LNaRSCCR0_SMP_AUTOZ_D1F GENMASK(9, 8)

drivers/phy/freescale/phy-fsl-lynx-28g.c

192

#define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4)

drivers/phy/freescale/phy-fsl-lynx-28g.c

193

#define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

196

#define LNaTTLCR0_TTL_FLT_SEL GENMASK(29, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

200

#define LNaTTLCR0_CDR_OV GENMASK(18, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

202

#define LNaTTLCR0_CDR_MIN_SMP_ON GENMASK(1, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

206

#define LNaTCSR0_SD_LPBK_SEL GENMASK(29, 28)

drivers/phy/freescale/phy-fsl-lynx-28g.c

209

#define LNaPSS_TYPE GENMASK(30, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

217

#define MDEV_PORT GENMASK(31, 27)

drivers/phy/freescale/phy-fsl-lynx-28g.c

48

#define PLLnCR0_REFCLK_SEL GENMASK(20, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

56

#define PLLnCR1_FRATE_SEL GENMASK(28, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

64

#define LNaGCR0_PROTO_SEL GENMASK(7, 3)

drivers/phy/freescale/phy-fsl-lynx-28g.c

67

#define LNaGCR0_IF_WIDTH GENMASK(2, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

703

*val = (tmp >> pccr.shift) & GENMASK(pccr.width - 1, 0);

drivers/phy/freescale/phy-fsl-lynx-28g.c

721

mask = GENMASK(pccr.width - 1, 0) << pccr.shift;

drivers/phy/freescale/phy-fsl-lynx-28g.c

82

#define LNaTGCR0_N_RATE GENMASK(26, 24)

drivers/phy/freescale/phy-fsl-lynx-28g.c

88

#define LNaTECR0_EQ_TYPE GENMASK(30, 28)

drivers/phy/freescale/phy-fsl-lynx-28g.c

90

#define LNaTECR0_EQ_PREQ GENMASK(19, 16)

drivers/phy/freescale/phy-fsl-lynx-28g.c

92

#define LNaTECR0_EQ_POST1Q GENMASK(12, 8)

drivers/phy/freescale/phy-fsl-lynx-28g.c

93

#define LNaTECR0_EQ_AMP_RED GENMASK(5, 0)

drivers/phy/freescale/phy-fsl-lynx-28g.c

97

#define LNaTECR1_EQ_ADPT_EQ GENMASK(29, 24)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

19

#define REG01_PMS_P_MASK GENMASK(3, 0)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

20

#define REG03_PMS_S_MASK GENMASK(7, 4)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

21

#define REG12_CK_DIV_MASK GENMASK(5, 4)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

23

#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

25

#define REG14_TOL_MASK GENMASK(7, 4)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

26

#define REG14_RP_CODE_MASK GENMASK(3, 1)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

27

#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

30

#define REG21_PMS_S_MASK GENMASK(3, 0)

drivers/phy/hisilicon/phy-hi3670-pcie.c

117

#define DEBOUNCE_WAITCFG_IN GENMASK(23, 20)

drivers/phy/hisilicon/phy-hi3670-pcie.c

118

#define DEBOUNCE_WAITCFG_OUT GENMASK(16, 13)

drivers/phy/hisilicon/phy-hi3670-pcie.c

142

#define PCIE_OE_BYPASS GENMASK(29, 28)

drivers/phy/hisilicon/phy-hi3670-pcie.c

43

#define PCIE_OUTPUT_PULL_BITS GENMASK(3, 0)

drivers/phy/hisilicon/phy-hi3670-pcie.c

69

#define EYE_PARM0_MASK GENMASK(8, 6)

drivers/phy/hisilicon/phy-hi3670-pcie.c

70

#define EYE_PARM1_MASK GENMASK(11, 8)

drivers/phy/hisilicon/phy-hi3670-pcie.c

71

#define EYE_PARM2_MASK GENMASK(5, 0)

drivers/phy/hisilicon/phy-hi3670-pcie.c

72

#define EYE_PARM3_MASK GENMASK(12, 7)

drivers/phy/hisilicon/phy-hi3670-pcie.c

73

#define EYE_PARM4_MASK GENMASK(14, 9)

drivers/phy/hisilicon/phy-hi3670-pcie.c

93

#define PCIE_FNPLL_FBDIV_MASK GENMASK(27, 16)

drivers/phy/hisilicon/phy-hi3670-pcie.c

94

#define PCIE_FNPLL_FRACDIV_MASK GENMASK(23, 0)

drivers/phy/hisilicon/phy-hi3670-pcie.c

95

#define PCIE_FNPLL_POSTDIV1_MASK GENMASK(10, 8)

drivers/phy/hisilicon/phy-hi3670-pcie.c

96

#define PCIE_FNPLL_POSTDIV2_MASK GENMASK(14, 12)

drivers/phy/hisilicon/phy-hi3670-usb3.c

106

#define GCFG_OP_MODE GENMASK(1, 0)

drivers/phy/hisilicon/phy-hi3670-usb3.c

111

#define TCPC_MUX_CONTROL_MASK GENMASK(1, 0)

drivers/phy/hisilicon/phy-hi3670-usb3.c

116

#define VBUS_CTRL_POWERPRESENT_OVERRD GENMASK(3, 2)

drivers/phy/hisilicon/phy-hi3670-usb3.c

117

#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0)

drivers/phy/hisilicon/phy-hi3670-usb3.c

71

#define CTRL7_USB2_REFCLKSEL_MASK GENMASK(4, 3)

drivers/phy/hisilicon/phy-hi3670-usb3.c

77

#define CFG54_USB31PHY_CR_ADDR_MASK GENMASK(31, 16)

drivers/phy/hisilicon/phy-hi3670-usb3.c

89

#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16)

drivers/phy/hisilicon/phy-hisi-inno-usb2.c

28

#define PHY_TEST_DATA GENMASK(7, 0)

drivers/phy/hisilicon/phy-hisi-inno-usb2.c

30

#define PHY0_TEST_ADDR GENMASK(15, 8)

drivers/phy/hisilicon/phy-hisi-inno-usb2.c

32

#define PHY0_TEST_PORT GENMASK(18, 16)

drivers/phy/hisilicon/phy-hisi-inno-usb2.c

36

#define PHY1_TEST_ADDR GENMASK(11, 8)

drivers/phy/hisilicon/phy-histb-combphy.c

31

#define COMBPHY_TEST_DATA_MASK GENMASK(23, 20)

drivers/phy/hisilicon/phy-histb-combphy.c

33

#define COMBPHY_TEST_ADDR_MASK GENMASK(16, 12)

drivers/phy/ingenic/phy-ingenic-usb.c

36

#define USBPCR_IDPULLUP_MASK GENMASK(29, 28)

drivers/phy/ingenic/phy-ingenic-usb.c

41

#define USBPCR_COMPDISTUNE_MASK GENMASK(19, 17)

drivers/phy/ingenic/phy-ingenic-usb.c

44

#define USBPCR_OTGTUNE_MASK GENMASK(16, 14)

drivers/phy/ingenic/phy-ingenic-usb.c

47

#define USBPCR_SQRXTUNE_MASK GENMASK(13, 11)

drivers/phy/ingenic/phy-ingenic-usb.c

51

#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, 7)

drivers/phy/ingenic/phy-ingenic-usb.c

58

#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, 4)

drivers/phy/ingenic/phy-ingenic-usb.c

62

#define USBPCR_TXRISETUNE_MASK GENMASK(5, 4)

drivers/phy/ingenic/phy-ingenic-usb.c

65

#define USBPCR_TXVREFTUNE_MASK GENMASK(3, 0)

drivers/phy/intel/phy-intel-keembay-emmc.c

22

#define OTAP_DLY_SEL_MASK GENMASK(26, 23)

drivers/phy/intel/phy-intel-keembay-emmc.c

27

#define SEL_FREQ_MASK GENMASK(12, 10)

drivers/phy/intel/phy-intel-keembay-usb.c

33

#define USS_CPR_MASK GENMASK(6, 0)

drivers/phy/intel/phy-intel-lgm-combo.c

28

#define ADAPT_REQ_MSK GENMASK(5, 4)

drivers/phy/intel/phy-intel-lgm-emmc.c

20

#define DR_TY_MASK GENMASK(30, 28)

drivers/phy/intel/phy-intel-lgm-emmc.c

23

#define OTAPDLYSEL_MASK GENMASK(13, 10)

drivers/phy/intel/phy-intel-lgm-emmc.c

37

#define FRQSEL_MASK GENMASK(24, 22)

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c

32

#define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c

38

#define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK GENMASK(6, 4)

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c

50

#define PCIE_PHY_PLL_A_CTRL3_MMD_MASK GENMASK(15, 13)

drivers/phy/marvell/phy-berlin-sata.c

123

regval &= ~GENMASK(7, 4);

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

102

#define GS2_RSVD_6_0_MASK GENMASK(6, 0)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

123

#define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

129

#define PRD_TXMARGIN_MASK GENMASK(3, 1)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

131

#define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

137

#define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

152

#define MODE_REFDIV_MASK GENMASK(5, 4)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

161

#define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

163

#define PLL_READY_DLY_MASK GENMASK(7, 5)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

167

#define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

168

#define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

170

#define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

199

#define GEN_RX_SEL_MASK GENMASK(25, 22)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

201

#define GEN_TX_SEL_MASK GENMASK(29, 26)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

55

#define REF_FREF_SEL_MASK GENMASK(4, 0)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

61

#define COMPHY_MODE_MASK GENMASK(7, 5)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

69

#define SPEED_PLL_MASK GENMASK(7, 2)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

73

#define SEL_DATA_WIDTH_MASK GENMASK(11, 10)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

84

#define PHY_GEN_MAX_MASK GENMASK(11, 10)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

91

#define GS2_TX_SSC_AMP_MASK GENMASK(15, 9)

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

93

#define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7)

drivers/phy/marvell/phy-mvebu-a3700-utmi.c

24

#define PLL_REF_DIV_MASK GENMASK(6, 0)

drivers/phy/marvell/phy-mvebu-a3700-utmi.c

27

#define PLL_FB_DIV_MASK GENMASK(24, 16)

drivers/phy/marvell/phy-mvebu-a3700-utmi.c

30

#define PLL_SEL_LPFR_MASK GENMASK(29, 28)

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

138

#define COMPHY_FW_POL_MASK GENMASK(1, 0)

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

140

#define COMPHY_FW_SPEED_MASK GENMASK(7, 2)

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

148

#define COMPHY_FW_PORT_MASK GENMASK(11, 8)

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

150

#define COMPHY_FW_MODE_MASK GENMASK(16, 12)

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

152

#define COMPHY_FW_WIDTH_MASK GENMASK(20, 18)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

36

#define PLL_REFDIV_MASK GENMASK(6, 0)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

39

#define PLL_FBDIV_MASK GENMASK(24, 16)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

41

#define PLL_SEL_LPFR_MASK GENMASK(29, 28)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

45

#define IMPCAL_VTH_MASK GENMASK(10, 8)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

51

#define DRV_EN_LS_MASK GENMASK(15, 12)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

53

#define IMP_SEL_LS_MASK GENMASK(19, 16)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

55

#define TX_AMP_MASK GENMASK(22, 20)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

62

#define SQ_AMP_CAL_MASK GENMASK(2, 0)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

72

#define VDAT_MASK GENMASK(9, 8)

drivers/phy/marvell/phy-mvebu-cp110-utmi.c

75

#define VSRC_MASK GENMASK(11, 10)

drivers/phy/mediatek/phy-mtk-dp.c

37

#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)

drivers/phy/mediatek/phy-mtk-dp.c

38

#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29)

drivers/phy/mediatek/phy-mtk-dp.c

44

#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3)

drivers/phy/mediatek/phy-mtk-dp.c

45

#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9)

drivers/phy/mediatek/phy-mtk-dp.c

47

#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29)

drivers/phy/mediatek/phy-mtk-dp.c

54

#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12)

drivers/phy/mediatek/phy-mtk-dp.c

59

#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10)

drivers/phy/mediatek/phy-mtk-dp.c

60

#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19)

drivers/phy/mediatek/phy-mtk-dp.c

61

#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28)

drivers/phy/mediatek/phy-mtk-dp.c

68

#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9)

drivers/phy/mediatek/phy-mtk-dp.c

69

#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18)

drivers/phy/mediatek/phy-mtk-dp.c

76

#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

11

#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

12

#define RG_HDMITX_EN_SER_MASK GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

13

#define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

14

#define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

15

#define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

16

#define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

19

#define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

21

#define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

26

#define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

31

#define RG_HDMITX_RESERVE_MASK GENMASK(31, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

34

#define RG_HTPLL_BR_MASK GENMASK(1, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

35

#define RG_HTPLL_BC_MASK GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

36

#define RG_HTPLL_BP_MASK GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

37

#define RG_HTPLL_IR_MASK GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

38

#define RG_HTPLL_IC_MASK GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

39

#define RG_HTPLL_POSDIV_MASK GENMASK(17, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

40

#define RG_HTPLL_PREDIV_MASK GENMASK(19, 18)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

41

#define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

43

#define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

48

#define RG_HTPLL_DIVEN_MASK GENMASK(30, 28)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

12

#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

13

#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

14

#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

15

#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

16

#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

17

#define RG_HDMITX_PLL_IR GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

18

#define RG_HDMITX_PLL_IC GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

19

#define RG_HDMITX_PLL_BP GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

20

#define RG_HDMITX_PLL_BR GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

21

#define RG_HDMITX_PLL_BC GENMASK(1, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

23

#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

25

#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

26

#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

28

#define RG_HDMITX_PLL_BAND GENMASK(21, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

33

#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

40

#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

42

#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

46

#define RG_HDMITX_SER_EN GENMASK(31, 28)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

47

#define RG_HDMITX_PRD_EN GENMASK(27, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

48

#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

49

#define RG_HDMITX_DRV_EN GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

50

#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

54

#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

60

#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

61

#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

62

#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

63

#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

65

#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

66

#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

67

#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

68

#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

70

#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

71

#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

72

#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

73

#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

75

#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

76

#define RG_HDMITX_SER_DIN GENMASK(25, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

77

#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

78

#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

79

#define RG_HDMITX_RESERVE GENMASK(7, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

81

#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

82

#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

83

#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

84

#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

282

fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

100

#define RG_HDMITXPLL_PREDIV GENMASK(29, 28)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

110

#define REG_HDMITXPLL_DIV GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

19

#define REG_TXC_DIV GENMASK(31, 30)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

22

#define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

23

#define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

24

#define RG_HDMITX21_DRV_EN GENMASK(27, 24)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

25

#define RG_HDMITX21_SER_EN GENMASK(31, 28)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

28

#define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

29

#define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

30

#define RG_HDMITX21_DRV_IBIAS_D2 GENMASK(31, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

33

#define RG_HDMITXPLL_REF_CK_SEL GENMASK(2, 1)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

36

#define RG_HDMITX21_BIAS_PE_BG_VREF_SEL GENMASK(16, 15)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

40

#define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

41

#define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

42

#define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

43

#define RG_HDMITX21_DRV_IMP_CLK_EN1 GENMASK(31, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

48

#define RG_HDMITX21_SLDO_EN GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

60

#define RG_HDMITX21_INTR_CAL GENMASK(22, 18)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

61

#define RG_HDMITX21_TX_POSDIV GENMASK(27, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

66

#define RG_HDMITX21_SLDO_VREF_SEL GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

69

#define RG_HDMITXPLL_HREN GENMASK(13, 12)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

71

#define RG_HDMITXPLL_LVR_SEL GENMASK(27, 26)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

76

#define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

77

#define RG_HDMITXPLL_RESERVE_BIT3_2 GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

78

#define RG_HDMITXPLL_RESERVE_BIT12_11 GENMASK(12, 11)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

83

#define RG_HDMITXPLL_BC GENMASK(28, 27)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

84

#define RG_HDMITXPLL_IC GENMASK(26, 22)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

85

#define RG_HDMITXPLL_BR GENMASK(21, 19)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

86

#define RG_HDMITXPLL_IR GENMASK(18, 14)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

87

#define RG_HDMITXPLL_BP GENMASK(13, 10)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

92

#define RG_HDMITXPLL_FBKDIV_LOW GENMASK(31, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

98

#define RG_HDMITXPLL_POSDIV GENMASK(23, 22)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h

99

#define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

30

#define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

31

#define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

32

#define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

33

#define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

34

#define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

35

#define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

36

#define RG_CSI1A_L0_EQ_IS GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

37

#define RG_CSI1A_L0_EQ_BW GENMASK(7, 6)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

38

#define RG_CSI1A_L1_EQ_IS GENMASK(21, 20)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

39

#define RG_CSI1A_L1_EQ_BW GENMASK(23, 22)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

40

#define RG_CSI1A_L2_EQ_IS GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

41

#define RG_CSI1A_L2_EQ_BW GENMASK(7, 6)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

47

#define RG_CSIXA_RESERVE GENMASK(31, 24)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

50

#define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

51

#define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

52

#define RG_CSIXA_CPHY_SPARE GENMASK(31, 16)

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h

55

#define CSR_CSI_RST_MODE GENMASK(17, 16)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

13

#define RG_DSI_BCLK_SEL GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

14

#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

15

#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

31

#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

38

#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

39

#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

42

#define RG_DSI_PRESERVE GENMASK(15, 13)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

47

#define RG_DSI_BG_DIV GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

50

#define RG_DSI_V12_SEL GENMASK(7, 5)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

51

#define RG_DSI_V10_SEL GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

52

#define RG_DSI_V072_SEL GENMASK(13, 11)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

53

#define RG_DSI_V04_SEL GENMASK(16, 14)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

54

#define RG_DSI_V032_SEL GENMASK(19, 17)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

55

#define RG_DSI_V02_SEL GENMASK(22, 20)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

59

#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

60

#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

64

#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

65

#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

66

#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

67

#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

79

#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

84

#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

22

#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

30

#define RG_DSI_PLL_IBIAS GENMASK(11, 10)

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

45

#define RG_DSI_PLL_POSDIV GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-pcie.c

19

#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)

drivers/phy/mediatek/phy-mtk-pcie.c

25

#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)

drivers/phy/mediatek/phy-mtk-pcie.c

27

#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-pcie.c

31

#define EFUSE_LN_RX_SEL GENMASK(3, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

100

#define P2C_RG_DATAIN GENMASK(13, 10)

drivers/phy/mediatek/phy-mtk-tphy.c

103

#define P2C_RG_XCVRSEL GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-tphy.c

133

#define P3A_RG_IEXT_INTR GENMASK(15, 10)

drivers/phy/mediatek/phy-mtk-tphy.c

134

#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)

drivers/phy/mediatek/phy-mtk-tphy.c

137

#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)

drivers/phy/mediatek/phy-mtk-tphy.c

140

#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)

drivers/phy/mediatek/phy-mtk-tphy.c

143

#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)

drivers/phy/mediatek/phy-mtk-tphy.c

146

#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

147

#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)

drivers/phy/mediatek/phy-mtk-tphy.c

148

#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)

drivers/phy/mediatek/phy-mtk-tphy.c

151

#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)

drivers/phy/mediatek/phy-mtk-tphy.c

152

#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)

drivers/phy/mediatek/phy-mtk-tphy.c

155

#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)

drivers/phy/mediatek/phy-mtk-tphy.c

156

#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)

drivers/phy/mediatek/phy-mtk-tphy.c

159

#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

162

#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

165

#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

168

#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

171

#define P3D_RG_FWAKE_TH GENMASK(21, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

175

#define P3D_RG_TX_IMPEL GENMASK(28, 24)

drivers/phy/mediatek/phy-mtk-tphy.c

179

#define P3D_RG_RX_IMPEL GENMASK(28, 24)

drivers/phy/mediatek/phy-mtk-tphy.c

185

#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)

drivers/phy/mediatek/phy-mtk-tphy.c

186

#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

189

#define P3D_RG_PHY_MODE GENMASK(2, 1)

drivers/phy/mediatek/phy-mtk-tphy.c

193

#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)

drivers/phy/mediatek/phy-mtk-tphy.c

196

#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

203

#define P2F_RG_MONCLK_SEL GENMASK(27, 26)

drivers/phy/mediatek/phy-mtk-tphy.c

205

#define P2F_RG_CYCLECNT GENMASK(23, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

219

#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)

drivers/phy/mediatek/phy-mtk-tphy.c

220

#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

224

#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)

drivers/phy/mediatek/phy-mtk-tphy.c

228

#define RG_TG_MAX_MSK GENMASK(20, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

230

#define RG_T2_MAX_MSK GENMASK(13, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

232

#define RG_TG_MIN_MSK GENMASK(7, 5)

drivers/phy/mediatek/phy-mtk-tphy.c

234

#define RG_T2_MIN_MSK GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

238

#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

241

#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)

drivers/phy/mediatek/phy-mtk-tphy.c

243

#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

247

#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)

drivers/phy/mediatek/phy-mtk-tphy.c

248

#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

252

#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

255

#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)

drivers/phy/mediatek/phy-mtk-tphy.c

258

#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

262

#define RG_PHY_SW_TYPE GENMASK(3, 0)

drivers/phy/mediatek/phy-mtk-tphy.c

52

#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)

drivers/phy/mediatek/phy-mtk-tphy.c

56

#define PA1_RG_INTR_CAL GENMASK(23, 19)

drivers/phy/mediatek/phy-mtk-tphy.c

57

#define PA1_RG_VRT_SEL GENMASK(14, 12)

drivers/phy/mediatek/phy-mtk-tphy.c

58

#define PA1_RG_TERM_SEL GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-tphy.c

61

#define PA2_RG_U2PLL_BW GENMASK(21, 19)

drivers/phy/mediatek/phy-mtk-tphy.c

66

#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)

drivers/phy/mediatek/phy-mtk-tphy.c

70

#define PA6_RG_U2_PRE_EMP GENMASK(31, 30)

drivers/phy/mediatek/phy-mtk-tphy.c

73

#define PA6_RG_U2_DISCTH GENMASK(7, 4)

drivers/phy/mediatek/phy-mtk-tphy.c

74

#define PA6_RG_U2_SQTH GENMASK(3, 0)

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

27

#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x))

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

28

#define XTP_PCS_MODE_MASK GENMASK(17, 16)

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

29

#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x))

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

32

#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12)

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

34

#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

55

#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1)

drivers/phy/mediatek/phy-mtk-xfi-tphy.c

56

#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x))

drivers/phy/mediatek/phy-mtk-xsphy.c

41

#define P2F_RG_CYCLECNT GENMASK(23, 0)

drivers/phy/mediatek/phy-mtk-xsphy.c

53

#define P2A1_RG_INTR_CAL GENMASK(23, 19)

drivers/phy/mediatek/phy-mtk-xsphy.c

54

#define P2A1_RG_VRT_SEL GENMASK(14, 12)

drivers/phy/mediatek/phy-mtk-xsphy.c

55

#define P2A1_RG_TERM_SEL GENMASK(10, 8)

drivers/phy/mediatek/phy-mtk-xsphy.c

59

#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)

drivers/phy/mediatek/phy-mtk-xsphy.c

73

#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)

drivers/phy/mediatek/phy-mtk-xsphy.c

76

#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-xsphy.c

79

#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)

drivers/phy/mediatek/phy-mtk-xsphy.c

88

#define RG_PHY_SW_TYPE GENMASK(3, 0)

drivers/phy/microchip/lan966x_serdes.c

14

#define PLL_CONF_MASK GENMASK(4, 3)

drivers/phy/microchip/lan966x_serdes_regs.h

131

#define HSIO_MPLL_CFG_MPLL_MULTIPLIER GENMASK(6, 0)

drivers/phy/microchip/lan966x_serdes_regs.h

169

(((x) << 15) & GENMASK(15, 15))

drivers/phy/microchip/lan966x_serdes_regs.h

175

(((x) << 14) & GENMASK(14, 14))

drivers/phy/microchip/lan966x_serdes_regs.h

179

#define HSIO_HW_CFG_RGMII_ENA GENMASK(13, 12)

drivers/phy/microchip/lan966x_serdes_regs.h

181

(((x) << 12) & GENMASK(13, 12))

drivers/phy/microchip/lan966x_serdes_regs.h

187

(((x) << 11) & GENMASK(11, 11))

drivers/phy/microchip/lan966x_serdes_regs.h

193

(((x) << 10) & GENMASK(10, 10))

drivers/phy/microchip/lan966x_serdes_regs.h

197

#define HSIO_HW_CFG_GMII_ENA GENMASK(9, 2)

drivers/phy/microchip/lan966x_serdes_regs.h

199

(((x) << 2) & GENMASK(9, 2))

drivers/phy/microchip/lan966x_serdes_regs.h

203

#define HSIO_HW_CFG_QSGMII_ENA GENMASK(1, 0)

drivers/phy/microchip/lan966x_serdes_regs.h

205

((x) & GENMASK(1, 0))

drivers/phy/microchip/lan966x_serdes_regs.h

212

#define HSIO_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)

drivers/phy/microchip/lan966x_serdes_regs.h

32

#define HSIO_SD_CFG_TX_RATE GENMASK(17, 16)

drivers/phy/microchip/lan966x_serdes_regs.h

80

#define HSIO_SD_CFG_RX_RATE GENMASK(7, 6)

drivers/phy/microchip/sparx5_serdes_regs.h

1022

#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1086

#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1174

#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

118

#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1209

#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1220

#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1237

#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1272

#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1300

#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1329

#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1352

#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1358

#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1369

#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1421

#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1432

#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1443

#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1460

#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1471

#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1477

#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1488

#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1494

#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1505

#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1557

#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1563

#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1580

#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1614

#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1625

#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1648

#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1659

#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1682

#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

170

#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1735

#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1746

#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1781

#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1851

#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1862

#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1891

#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

1955

#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

1990

#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2001

#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2012

#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2023

#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2052

#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2063

#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2086

#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2103

#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2109

#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2220

#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2231

#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2242

#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2253

#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2339

#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2355

#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2513

#define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

258

#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2629

#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2639

#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2704

#define SD_LANE_SD_LANE_CFG_TX_REF_SEL GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2710

#define SD_LANE_SD_LANE_CFG_RX_REF_SEL GENMASK(7, 6)

drivers/phy/microchip/sparx5_serdes_regs.h

275

#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2750

#define SD_LANE_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)

drivers/phy/microchip/sparx5_serdes_regs.h

2760

#define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2789

#define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

2799

#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2805

#define SD_LANE_M_STAT_MISC_M_LOCK_CNT GENMASK(31, 24)

drivers/phy/microchip/sparx5_serdes_regs.h

2856

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE GENMASK(7, 5)

drivers/phy/microchip/sparx5_serdes_regs.h

2886

#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV GENMASK(15, 12)

drivers/phy/microchip/sparx5_serdes_regs.h

2898

#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY GENMASK(21, 17)

drivers/phy/microchip/sparx5_serdes_regs.h

2928

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)

drivers/phy/microchip/sparx5_serdes_regs.h

2939

#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

2945

#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL GENMASK(5, 3)

drivers/phy/microchip/sparx5_serdes_regs.h

2951

#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL GENMASK(8, 6)

drivers/phy/microchip/sparx5_serdes_regs.h

2957

#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)

drivers/phy/microchip/sparx5_serdes_regs.h

2963

#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV GENMASK(13, 11)

drivers/phy/microchip/sparx5_serdes_regs.h

2969

#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV GENMASK(16, 14)

drivers/phy/microchip/sparx5_serdes_regs.h

2975

#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)

drivers/phy/microchip/sparx5_serdes_regs.h

2981

#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)

drivers/phy/microchip/sparx5_serdes_regs.h

2987

#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL GENMASK(25, 24)

drivers/phy/microchip/sparx5_serdes_regs.h

2993

#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL GENMASK(28, 26)

drivers/phy/microchip/sparx5_serdes_regs.h

2999

#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL GENMASK(31, 29)

drivers/phy/microchip/sparx5_serdes_regs.h

3022

#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)

drivers/phy/microchip/sparx5_serdes_regs.h

3033

#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

304

#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

338

#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

349

#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

360

#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

395

#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

406

#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

441

#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

452

#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

458

#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

469

#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

480

#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

486

#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

49

#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

503

#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

555

#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

561

#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

572

#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

578

#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

589

#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

595

#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

606

#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

659

#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

670

#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

687

#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

693

#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

721

#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

732

#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

743

#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

749

#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

760

#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

783

#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

818

#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

929

#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0)

drivers/phy/microchip/sparx5_serdes_regs.h

96

#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)

drivers/phy/microchip/sparx5_serdes_regs.h

987

#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

102

#define CSR_2L_PXP_TXPLL_LPF_BWR GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

103

#define CSR_2L_PXP_TXPLL_LPF_BWC GENMASK(12, 8)

drivers/phy/phy-airoha-pcie-regs.h

104

#define CSR_2L_PXP_TXPLL_KBAND_CODE GENMASK(31, 24)

drivers/phy/phy-airoha-pcie-regs.h

107

#define CSR_2L_PXP_TXPLL_KBAND_DIV GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

108

#define CSR_2L_PXP_TXPLL_KBAND_KFC GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

109

#define CSR_2L_PXP_TXPLL_KBAND_KF GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

110

#define CSR_2L_PXP_txpll_KBAND_KS GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

114

#define CSR_2L_PXP_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

121

#define CSR_2L_PXP_TXPLL_REFIN_DIV GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

122

#define CSR_2L_PXP_TXPLL_RST_DLY GENMASK(10, 8)

drivers/phy/phy-airoha-pcie-regs.h

126

#define CSR_2L_PXP_TXPLL_SDM_DI_LS GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

128

#define CSR_2L_PXP_TXPLL_SDM_ORD GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

13

#define CSR_2L_PXP_CMN_TRIM_MASK GENMASK(28, 24)

drivers/phy/phy-airoha-pcie-regs.h

132

#define CSR_2L_PXP_TXPLL_TCL_AMP_GAIN GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

135

#define CSR_2L_PXP_TXPLL_TCL_AMP_VREF GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

139

#define CSR_2L_PXP_TXPLL_TCL_LPF_BW GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

140

#define CSR_2L_PXP_TXPLL_VCO_CFIX GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

144

#define CSR_2L_PXP_TXPLL_VCO_SCAPWR GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

151

#define CSR_2L_PXP_TXPLL_SSC_DELTA1 GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

152

#define CSR_2L_PXP_TXPLL_SSC_DELTA GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

155

#define CSR_2L_PXP_txpll_SSC_PERIOD GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

161

#define CSR_2L_PXP_TXPLL_SPARE_L GENMASK(31, 24)

drivers/phy/phy-airoha-pcie-regs.h

164

#define CSR_2L_PXP_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

168

#define CSR_2L_PXP_CLKTX0_AMP GENMASK(10, 8)

drivers/phy/phy-airoha-pcie-regs.h

169

#define CSR_2L_PXP_CLKTX0_OFFSET GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

17

#define CSR_2L_PXP_JCPLL_CHP_IBIAS GENMASK(21, 16)

drivers/phy/phy-airoha-pcie-regs.h

170

#define CSR_2L_PXP_CLKTX0_SR GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

174

#define CSR_2L_PXP_CLKTX0_IMP_SEL GENMASK(20, 16)

drivers/phy/phy-airoha-pcie-regs.h

175

#define CSR_2L_PXP_CLKTX1_AMP GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

178

#define CSR_2L_PXP_CLKTX1_OFFSET GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

179

#define CSR_2L_PXP_CLKTX1_SR GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

18

#define CSR_2L_PXP_JCPLL_CHP_IOFST GENMASK(29, 24)

drivers/phy/phy-airoha-pcie-regs.h

183

#define CSR_2L_PXP_CLKTX1_IMP_SEL GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

186

#define CSR_2L_PXP_PLL_RESERVE_MASK GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

200

#define CSR_2L_PXP_VOS_PNINV GENMASK(19, 18)

drivers/phy/phy-airoha-pcie-regs.h

201

#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE GENMASK(22, 20)

drivers/phy/phy-airoha-pcie-regs.h

202

#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

205

#define CSR_2L_PXP_RX0_PHYCK_SEL GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

21

#define CSR_2L_PXP_JCPLL_LPF_BR GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

213

#define CSR_2L_PXP_CDR0_LPF_TOP_LIM GENMASK(26, 8)

drivers/phy/phy-airoha-pcie-regs.h

219

#define CSR_2L_PXP_CDR0_PR_BETA_SEL GENMASK(19, 16)

drivers/phy/phy-airoha-pcie-regs.h

22

#define CSR_2L_PXP_JCPLL_LPF_BC GENMASK(12, 8)

drivers/phy/phy-airoha-pcie-regs.h

220

#define CSR_2L_PXP_CDR0_PR_KBAND_DIV GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

223

#define CSR_2L_PXP_CDR0_PR_VREG_IBAND GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

224

#define CSR_2L_PXP_CDR0_PR_VREG_CKBUF GENMASK(10, 8)

drivers/phy/phy-airoha-pcie-regs.h

227

#define CSR_2L_PXP_CDR0_PR_CKREF_DIV GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

23

#define CSR_2L_PXP_JCPLL_LPF_BP GENMASK(20, 16)

drivers/phy/phy-airoha-pcie-regs.h

231

#define CSR_2L_PXP_CDR0_PR_RESERVE0 GENMASK(19, 16)

drivers/phy/phy-airoha-pcie-regs.h

235

#define CSR_2L_PXP_CDR0_PR_CKREF_DIV1 GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

24

#define CSR_2L_PXP_JCPLL_LPF_BWR GENMASK(28, 24)

drivers/phy/phy-airoha-pcie-regs.h

241

#define CSR_2L_PXP_RX0_SIGDET_LPF_CTRL GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

242

#define CSR_2L_PXP_RX0_SIGDET_PEAK GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

245

#define CSR_2L_PXP_RX0_SIGDET_VTH_SEL GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

254

#define CSR_2L_PXP_RX0_PR_OSCAL_VGA1IOS GENMASK(29, 24)

drivers/phy/phy-airoha-pcie-regs.h

257

#define CSR_2L_PXP_RX0_PR_OSCAL_VGA1VOS GENMASK(5, 0)

drivers/phy/phy-airoha-pcie-regs.h

258

#define CSR_2L_PXP_RX0_PR_OSCAL_VGA2IOS GENMASK(13, 8)

drivers/phy/phy-airoha-pcie-regs.h

263

#define CSR_2L_PXP_RX1_PHYCK_SEL GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

27

#define CSR_2L_PXP_JCPLL_LPF_BWC GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

271

#define CSR_2L_PXP_CDR1_PR_BETA_SEL GENMASK(19, 16)

drivers/phy/phy-airoha-pcie-regs.h

272

#define CSR_2L_PXP_CDR1_PR_KBAND_DIV GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

276

#define CSR_2L_PXP_CDR1_PR_RESERVE0 GENMASK(19, 16)

drivers/phy/phy-airoha-pcie-regs.h

279

#define CSR_2L_PXP_CDR1_LPF_TOP_LIM GENMASK(26, 8)

drivers/phy/phy-airoha-pcie-regs.h

28

#define CSR_2L_PXP_JCPLL_KBAND_CODE GENMASK(23, 16)

drivers/phy/phy-airoha-pcie-regs.h

285

#define CSR_2L_PXP_CDR1_PR_VREG_IBAND GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

286

#define CSR_2L_PXP_CDR1_PR_VREG_CKBUF GENMASK(10, 8)

drivers/phy/phy-airoha-pcie-regs.h

289

#define CSR_2L_PXP_CDR1_PR_CKREF_DIV GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

29

#define CSR_2L_PXP_JCPLL_KBAND_DIV GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

293

#define CSR_2L_PXP_CDR1_PR_CKREF_DIV1 GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

299

#define CSR_2L_PXP_RX1_SIGDET_LPF_CTRL GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

302

#define CSR_2L_PXP_RX1_SIGDET_PEAK GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

303

#define CSR_2L_PXP_RX1_SIGDET_VTH_SEL GENMASK(20, 16)

drivers/phy/phy-airoha-pcie-regs.h

312

#define CSR_2L_PXP_RX1_PR_OSCAL_VGA1IOS GENMASK(5, 0)

drivers/phy/phy-airoha-pcie-regs.h

313

#define CSR_2L_PXP_RX1_PR_OSCAL_VGA1VOS GENMASK(13, 8)

drivers/phy/phy-airoha-pcie-regs.h

314

#define CSR_2L_PXP_RX1_PR_OSCAL_VGA2IOS GENMASK(21, 16)

drivers/phy/phy-airoha-pcie-regs.h

32

#define CSR_2L_PXP_JCPLL_KBAND_KFC GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

327

#define PCIE_PLL_FT_LOCK_CYCLECNT GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

328

#define PCIE_PLL_FT_UNLOCK_CYCLECNT GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

33

#define CSR_2L_PXP_JCPLL_KBAND_KF GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

331

#define PCIE_LOCK_TARGET_BEG GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

332

#define PCIE_LOCK_TARGET_END GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

335

#define PCIE_UNLOCK_TARGET_BEG GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

336

#define PCIE_UNLOCK_TARGET_END GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

339

#define PCIE_FREQLOCK_DET_EN GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

34

#define CSR_2L_PXP_JCPLL_KBAND_KS GENMASK(17, 16)

drivers/phy/phy-airoha-pcie-regs.h

340

#define PCIE_LOCK_LOCKTH GENMASK(11, 8)

drivers/phy/phy-airoha-pcie-regs.h

341

#define PCIE_UNLOCK_LOCKTH GENMASK(15, 12)

drivers/phy/phy-airoha-pcie-regs.h

345

#define PCIE_CAL_OUT_OS GENMASK(11, 8)

drivers/phy/phy-airoha-pcie-regs.h

348

#define PCIE_SIGDET_WIN_NONVLD_TIMES GENMASK(28, 24)

drivers/phy/phy-airoha-pcie-regs.h

355

#define PCIE_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

38

#define CSR_2L_PXP_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

388

#define PCIE_RO_FL_OUT GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

391

#define PCIE_FORCE_DA_PXP_CDR_PR_IDAC GENMASK(10, 0)

drivers/phy/phy-airoha-pcie-regs.h

396

#define PCIE_FORCE_DA_PXP_TXPLL_SDM_PCW GENMASK(30, 0)

drivers/phy/phy-airoha-pcie-regs.h

402

#define PCIE_FORCE_DA_PXP_JCPLL_SDM_PCW GENMASK(30, 0)

drivers/phy/phy-airoha-pcie-regs.h

43

#define CSR_2L_PXP_JCPLL_REFIN_DIV GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

439

#define PCIE_FLL_IDAC_PCIEG1 GENMASK(10, 0)

drivers/phy/phy-airoha-pcie-regs.h

440

#define PCIE_FLL_IDAC_PCIEG2 GENMASK(26, 16)

drivers/phy/phy-airoha-pcie-regs.h

443

#define PCIE_FLL_IDAC_PCIEG3 GENMASK(10, 0)

drivers/phy/phy-airoha-pcie-regs.h

447

#define PCIE_FORCE_DA_PXP_RX_FE_GAIN_CTRL GENMASK(1, 0)

drivers/phy/phy-airoha-pcie-regs.h

455

#define PCIE_FORCE_PMA_RX_SPEED GENMASK(7, 4)

drivers/phy/phy-airoha-pcie-regs.h

46

#define CSR_2L_PXP_JCPLL_RST_DLY GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

461

#define PCIE_PXP_RX_VTH_SEL_PCIE_G1 GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

462

#define PCIE_PXP_RX_VTH_SEL_PCIE_G2 GENMASK(12, 8)

drivers/phy/phy-airoha-pcie-regs.h

463

#define PCIE_PXP_RX_VTH_SEL_PCIE_G3 GENMASK(20, 16)

drivers/phy/phy-airoha-pcie-regs.h

466

#define PCIE_PCP_RX_REV0_PCIE_GEN1 GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

469

#define PCIE_PCP_RX_REV0_PCIE_GEN2 GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

470

#define PCIE_PCP_RX_REV0_PCIE_GEN3 GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

479

#define PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL GENMASK(7, 0)

drivers/phy/phy-airoha-pcie-regs.h

480

#define PCIE_XTP_RXDET_EN_STB_T_SEL GENMASK(15, 8)

drivers/phy/phy-airoha-pcie-regs.h

481

#define PCIE_XTP_RXDET_FINISH_STB_T_SEL GENMASK(23, 16)

drivers/phy/phy-airoha-pcie-regs.h

482

#define PCIE_XTP_TXPD_TX_DATA_EN_DLY GENMASK(27, 24)

drivers/phy/phy-airoha-pcie-regs.h

484

#define PCIE_XTP_RXDET_LATCH_STB_T_SEL GENMASK(31, 29)

drivers/phy/phy-airoha-pcie-regs.h

488

#define PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT GENMASK(7, 0)

drivers/phy/phy-airoha-pcie-regs.h

49

#define CSR_2L_PXP_JCPLL_SDM_DI_LS GENMASK(25, 24)

drivers/phy/phy-airoha-pcie-regs.h

490

#define PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

57

#define CSR_2L_PXP_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)

drivers/phy/phy-airoha-pcie-regs.h

58

#define CSR_2L_PXP_JCPLL_TCL_AMP_VREF GENMASK(28, 24)

drivers/phy/phy-airoha-pcie-regs.h

62

#define CSR_2L_PXP_JCPLL_TCL_LPF_BW GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

65

#define CSR_2L_PXP_JCPLL_VCO_CFIX GENMASK(9, 8)

drivers/phy/phy-airoha-pcie-regs.h

67

#define CSR_2L_PXP_JCPLL_VCO_SCAPWR GENMASK(26, 24)

drivers/phy/phy-airoha-pcie-regs.h

70

#define CSR_2L_PXP_JCPLL_VCO_TCLVAR GENMASK(2, 0)

drivers/phy/phy-airoha-pcie-regs.h

78

#define CSR_2L_PXP_JCPLL_SSC_DELTA1 GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

79

#define CSR_2L_PXP_JCPLL_SSC_DELTA GENMASK(31, 16)

drivers/phy/phy-airoha-pcie-regs.h

82

#define CSR_2L_PXP_JCPLL_SSC_PERIOD GENMASK(15, 0)

drivers/phy/phy-airoha-pcie-regs.h

85

#define CSR_2L_PXP_JCPLL_SPARE_LOW GENMASK(31, 24)

drivers/phy/phy-airoha-pcie-regs.h

88

#define CSR_2L_PXP_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)

drivers/phy/phy-airoha-pcie-regs.h

93

#define CSR_2L_PXP_TXPLL_CHP_IBIAS GENMASK(29, 24)

drivers/phy/phy-airoha-pcie-regs.h

96

#define CSR_2L_PXP_TXPLL_CHP_IOFST GENMASK(5, 0)

drivers/phy/phy-airoha-pcie-regs.h

97

#define CSR_2L_PXP_TXPLL_LPF_BR GENMASK(12, 8)

drivers/phy/phy-airoha-pcie-regs.h

98

#define CSR_2L_PXP_TXPLL_LPF_BC GENMASK(20, 16)

drivers/phy/phy-airoha-pcie-regs.h

99

#define CSR_2L_PXP_TXPLL_LPF_BP GENMASK(28, 24)

drivers/phy/phy-google-usb.c

24

#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8)

drivers/phy/phy-google-usb.c

28

#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13)

drivers/phy/phy-lgm-usb.c

24

#define TCPC_MUX_CTL GENMASK(1, 0)

drivers/phy/phy-snps-eusb2.c

102

#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)

drivers/phy/phy-snps-eusb2.c

104

#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)

drivers/phy/phy-snps-eusb2.c

105

#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)

drivers/phy/phy-snps-eusb2.c

108

#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)

drivers/phy/phy-snps-eusb2.c

109

#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)

drivers/phy/phy-snps-eusb2.c

110

#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)

drivers/phy/phy-snps-eusb2.c

137

#define APB_REG_ADDR_MASK GENMASK(7, 0)

drivers/phy/phy-snps-eusb2.c

140

#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)

drivers/phy/phy-snps-eusb2.c

143

#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)

drivers/phy/phy-snps-eusb2.c

146

#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)

drivers/phy/phy-snps-eusb2.c

149

#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)

drivers/phy/phy-snps-eusb2.c

17

#define USB_PHY_RST_MASK GENMASK(1, 0)

drivers/phy/phy-snps-eusb2.c

18

#define UTMI_PORT_RST_MASK GENMASK(5, 4)

drivers/phy/phy-snps-eusb2.c

28

#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8)

drivers/phy/phy-snps-eusb2.c

36

#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8)

drivers/phy/phy-snps-eusb2.c

44

#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1)

drivers/phy/phy-snps-eusb2.c

51

#define OPMODE_MASK GENMASK(4, 3)

drivers/phy/phy-snps-eusb2.c

62

#define FSEL_MASK GENMASK(6, 4)

drivers/phy/phy-snps-eusb2.c

67

#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)

drivers/phy/phy-snps-eusb2.c

70

#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)

drivers/phy/phy-snps-eusb2.c

75

#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)

drivers/phy/phy-snps-eusb2.c

79

#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)

drivers/phy/phy-snps-eusb2.c

89

#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)

drivers/phy/phy-snps-eusb2.c

90

#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)

drivers/phy/phy-snps-eusb2.c

93

#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)

drivers/phy/phy-snps-eusb2.c

94

#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)

drivers/phy/phy-snps-eusb2.c

97

#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)

drivers/phy/phy-spacemit-k1-pcie.c

105

#define CLKSEL GENMASK(31, 29)

drivers/phy/phy-spacemit-k1-pcie.c

111

#define FREF_SEL GENMASK(15, 13)

drivers/phy/phy-spacemit-k1-pcie.c

113

#define SSC_DEP_SEL GENMASK(19, 16)

drivers/phy/phy-spacemit-k1-pcie.c

123

#define AFE_RTERM_REG GENMASK(11, 8)

drivers/phy/phy-spacemit-k1-pcie.c

129

#define CFG_REFCLK_MODE GENMASK(9, 8)

drivers/phy/phy-spacemit-k1-pcie.c

134

#define TX_RTERM_REG GENMASK(15, 12)

drivers/phy/phy-spacemit-k1-pcie.c

142

#define RTERM_VALUE_RX GENMASK(3, 0)

drivers/phy/phy-spacemit-k1-pcie.c

143

#define RTERM_VALUE_TX GENMASK(7, 4)

drivers/phy/phy-spacemit-k1-pcie.c

94

#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

24

#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

28

#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

30

#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

32

#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

37

#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

39

#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

41

#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)

drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c

45

#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

100

#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

101

#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

106

#define SSPHY_MPLL_MASK GENMASK(8, 5)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

66

#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

67

#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

68

#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

69

#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

90

#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

95

#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

97

#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)

drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

31

#define FSEL GENMASK(6, 4)

drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

48

#define HSTX_PE GENMASK(3, 2)

drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

51

#define HSTX_SWING GENMASK(3, 0)

drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

54

#define HSTX_SLEW GENMASK(2, 0)

drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

57

#define PLL_LOCK_TIME GENMASK(1, 0)

drivers/phy/qualcomm/phy-qcom-m31.c

61

#define HSTX_SLEW_RATE_400PS GENMASK(2, 0)

drivers/phy/qualcomm/phy-qcom-m31.c

62

#define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)

drivers/phy/qualcomm/phy-qcom-m31.c

63

#define ODT_VALUE_38_02_OHM GENMASK(7, 6)

drivers/phy/qualcomm/phy-qcom-qusb2.c

66

#define IMP_RES_OFFSET_MASK GENMASK(5, 0)

drivers/phy/qualcomm/phy-qcom-qusb2.c

70

#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)

drivers/phy/qualcomm/phy-qcom-qusb2.c

74

#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)

drivers/phy/qualcomm/phy-qcom-qusb2.c

78

#define HSTX_TRIM_MASK GENMASK(7, 4)

drivers/phy/qualcomm/phy-qcom-qusb2.c

81

#define PREEMPHASIS_EN_MASK GENMASK(1, 0)

drivers/phy/qualcomm/phy-qcom-qusb2.c

85

#define HSDISC_TRIM_MASK GENMASK(1, 0)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

22

#define OPMODE_MASK GENMASK(4, 3)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

36

#define FSEL_MASK GENMASK(6, 4)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

65

#define REFCLK_SEL_MASK GENMASK(1, 0)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

68

#define HS_DISCONNECT_MASK GENMASK(2, 0)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

69

#define SQUELCH_DETECTOR_MASK GENMASK(7, 5)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

71

#define HS_AMPLITUDE_MASK GENMASK(3, 0)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

73

#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

75

#define HS_RISE_FALL_MASK GENMASK(1, 0)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

76

#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

77

#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)

drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

79

#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)

drivers/phy/ralink/phy-mt7621-pci.c

24

#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)

drivers/phy/ralink/phy-mt7621-pci.c

28

#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)

drivers/phy/ralink/phy-mt7621-pci.c

35

#define RG_PE1_H_PLL_BC GENMASK(23, 22)

drivers/phy/ralink/phy-mt7621-pci.c

36

#define RG_PE1_H_PLL_BP GENMASK(21, 18)

drivers/phy/ralink/phy-mt7621-pci.c

37

#define RG_PE1_H_PLL_IR GENMASK(15, 12)

drivers/phy/ralink/phy-mt7621-pci.c

38

#define RG_PE1_H_PLL_IC GENMASK(11, 8)

drivers/phy/ralink/phy-mt7621-pci.c

39

#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)

drivers/phy/ralink/phy-mt7621-pci.c

40

#define RG_PE1_PLL_DIVEN GENMASK(3, 1)

drivers/phy/ralink/phy-mt7621-pci.c

43

#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)

drivers/phy/ralink/phy-mt7621-pci.c

46

#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)

drivers/phy/ralink/phy-mt7621-pci.c

49

#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)

drivers/phy/ralink/phy-mt7621-pci.c

50

#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)

drivers/phy/ralink/phy-mt7621-pci.c

56

#define RG_PE1_H_PLL_BR GENMASK(18, 16)

drivers/phy/ralink/phy-mt7621-pci.c

59

#define RG_PE1_MSTCKDIV GENMASK(7, 6)

drivers/phy/renesas/phy-rcar-gen3-usb2.c

53

#define USB2_AHB_BUS_CTR_MBL_MASK GENMASK(1, 0)

drivers/phy/renesas/phy-rcar-gen3-usb2.c

76

#define USB2_OBINTSTA_CLEAR GENMASK(31, 0)

drivers/phy/renesas/phy-rcar-gen3-usb2.c

83

#define USB2_VBCTRL_VBSTA_MASK GENMASK(31, 28)

drivers/phy/renesas/phy-rcar-gen3-usb2.c

85

#define USB2_VBCTRL_VBLVL_MASK GENMASK(23, 20)

drivers/phy/renesas/phy-rzg3e-usb3.c

36

#define USB3_TEST_UTMICTRL2_CTRL_MASK GENMASK(9, 8)

drivers/phy/renesas/phy-rzg3e-usb3.c

37

#define USB3_TEST_UTMICTRL2_MODE_MASK GENMASK(1, 0)

drivers/phy/renesas/phy-rzg3e-usb3.c

39

#define USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK GENMASK(2, 1)

drivers/phy/renesas/phy-rzg3e-usb3.c

41

#define USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

198

GENMASK(priv->config.lanes - 1, 0));

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

270

val = FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_MASK, GENMASK(priv->config.lanes - 1, 0)) |

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

309

GENMASK(priv->config.lanes - 1, 0));

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

38

#define CSIDPHY_CTRL_LANE_ENABLE_MASK GENMASK(5, 2)

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

43

#define CSIDPHY_CTRL_PWRCTL_UNDEFINED GENMASK(7, 5)

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

55

#define CSIDPHY_THS_SETTLE_MASK GENMASK(6, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

110

#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

113

#define PLL_MODE_SEL_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

117

#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

120

#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

138

#define T_LPX_CNT_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

143

#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

146

#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

149

#define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

152

#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

155

#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

161

#define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

164

#define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

167

#define T_CLK_PRE_CNT_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

170

#define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

172

#define T_TA_GO_CNT_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

177

#define T_TA_SURE_CNT_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

180

#define T_TA_WAIT_CNT_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

191

#define MODE_ENABLE_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

196

#define LVDS_LANE_EN_MASK GENMASK(7, 3)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

26

#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

44

#define LANE_EN_MASK GENMASK(6, 2)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

50

#define POWER_WORK_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

66

#define REG_PREDIV_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

69

#define REG_FBDIV_LO_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

72

#define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

74

#define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

77

#define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

79

#define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

82

#define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

84

#define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

96

#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

100

#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

102

#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

104

#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

137

#define RK3328_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

144

#define RK3328_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

149

#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

151

#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

153

#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

157

#define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

159

#define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

163

#define RK3328_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

165

#define RK3328_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

170

#define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

179

#define RK3328_POST_PLL_POST_DIV_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

207

#define RK3328_ESD_DETECT_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

213

#define RK3328_TMDS_TERM_RESIST_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

23

#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

50

#define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

56

#define RK3228_PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

61

#define RK3228_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

64

#define RK3228_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

67

#define RK3228_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

69

#define RK3228_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

72

#define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

74

#define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

76

#define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

82

#define RK3228_POST_PLL_PRE_DIV_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

89

#define RK3228_POST_PLL_POST_DIV_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

93

#define RK3228_TMDS_CH_TA_ENABLE GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1523

ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1533

ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1536

ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1563

ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1573

ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1576

ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1579

ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

1585

ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

275

mask = GENMASK(reg->bitend, reg->bitstart);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

286

unsigned int mask = GENMASK(reg->bitend, reg->bitstart);

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

941

ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

949

uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

114

#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

115

#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

119

#define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

124

#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

135

#define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

232

mask = GENMASK(reg->bitend, reg->bitstart);

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

243

mask = GENMASK(cfg->pipe_phy_status.bitend,

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

28

#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

30

#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

36

#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

43

#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

45

#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

47

#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

55

#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

59

#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

67

#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

72

#define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

75

#define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

89

#define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

99

#define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-pcie.c

24

#define PHY_CFG_DATA_MASK GENMASK(10, 7)

drivers/phy/rockchip/phy-rockchip-pcie.c

25

#define PHY_CFG_ADDR_MASK GENMASK(6, 1)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

110

#define REG_645M_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

122

#define I_MUX_SEL_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

130

#define S_MASK GENMASK(10, 8)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

132

#define P_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

136

#define M_MASK GENMASK(9, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

139

#define MRR_MASK GENMASK(13, 8)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

141

#define MFR_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

150

#define PLL_LOCK_CNT(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

152

#define PLL_STB_CNT(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

160

#define T_PHY_READY(x) FIELD_PREP(GENMASK(15, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

162

#define EDGE_CON(x) FIELD_PREP(GENMASK(14, 12), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

165

#define RES_UP(x) FIELD_PREP(GENMASK(7, 4), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

166

#define RES_DN(x) FIELD_PREP(GENMASK(3, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

169

#define HS_VREG_AMP_ICON(x) FIELD_PREP(GENMASK(1, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

172

#define T_LPX(x) FIELD_PREP(GENMASK(11, 4), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

174

#define T_CLK_ZERO(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

175

#define T_CLK_PREPARE(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

177

#define T_HS_EXIT(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

178

#define T_CLK_TRAIL(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

180

#define T_CLK_POST(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

182

#define T_ULPS_EXIT(x) FIELD_PREP(GENMASK(9, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

184

#define SKEW_CAL_RUN_TIME(x) FIELD_PREP(GENMASK(15, 12), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

186

#define SKEW_CAL_INIT_RUN_TIME(x) FIELD_PREP(GENMASK(11, 8), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

187

#define SKEW_CAL_INIT_WAIT_TIME(x) FIELD_PREP(GENMASK(7, 4), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

239

#define T_LP_EXIT_SKEW(x) FIELD_PREP(GENMASK(3, 2), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

240

#define T_LP_ENTRY_SKEW(x) FIELD_PREP(GENMASK(1, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

241

#define T_HS_ZERO(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

242

#define T_HS_PREPARE(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

243

#define T_HS_EXIT(x) FIELD_PREP(GENMASK(15, 8), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

244

#define T_HS_TRAIL(x) FIELD_PREP(GENMASK(7, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

245

#define T_TA_GET(x) FIELD_PREP(GENMASK(7, 4), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

246

#define T_TA_GO(x) FIELD_PREP(GENMASK(3, 0), x)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

25

#define I_RES_CNTL_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

35

#define I_DEV_SEL_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

43

#define I_VBG_SEL_MASK GENMASK(9, 8)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

49

#define I_BGR_VREF_SEL_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

55

#define I_LADDER_SEL_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

72

#define REG_325M_MASK GENMASK(14, 12)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

82

#define REG_LP_400M_MASK GENMASK(10, 8)

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

92

#define REG_400M_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

107

#define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

1078

GENMASK(6, 0),

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

1079

GENMASK(7, 0),

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

1084

GENMASK(6, 0),

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

1085

GENMASK(7, 0),

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

113

#define ROPLL_SDM_NUM_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

115

#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

117

#define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

118

#define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

120

#define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

122

#define ROPLL_SDC_NUM_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

124

#define ROPLL_SDC_DENO_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

131

#define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

133

#define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

135

#define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

142

#define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

144

#define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

148

#define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

150

#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

151

#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

159

#define DP_TX_LINK_BW_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

165

#define SSC_EN_MASK GENMASK(7, 6)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

179

#define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

181

#define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

1915

FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0)));

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

192

#define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

194

#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

196

#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

204

#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

209

#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

210

#define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

212

#define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

213

#define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

215

#define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

216

#define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

218

#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

220

#define FAST_PULSE_TIME_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

222

#define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

224

#define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

227

#define SB_AFC_TOL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

229

#define SB_AFC_STB_NUM_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

231

#define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

233

#define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

235

#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

250

#define DATA_BUS_WIDTH_MASK GENMASK(2, 1)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

262

#define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

265

#define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

268

#define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

270

#define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

271

#define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

275

#define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

278

#define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

280

#define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

281

#define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

283

#define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

285

#define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

286

#define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

288

#define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

299

#define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

301

#define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

61

#define LCPLL_SDC_N_MASK GENMASK(3, 1)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

63

#define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

65

#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

74

#define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

75

#define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

77

#define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

78

#define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

82

#define ROPLL_PMS_MDIV_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

84

#define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

86

#define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

87

#define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

89

#define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

90

#define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

92

#define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-snps-pcie3.c

49

#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)

drivers/phy/rockchip/phy-rockchip-snps-pcie3.c

50

#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)

drivers/phy/rockchip/phy-rockchip-typec.c

122

#define CMN_CALIB_CODE_MASK GENMASK(CMN_CALIB_CODE_WIDTH, 0)

drivers/phy/rockchip/phy-rockchip-typec.c

126

#define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)

drivers/phy/rockchip/phy-rockchip-usb.c

40

#define UOC_CON3_UTMI_XCVRSEELCT_MASK GENMASK(4, 3)

drivers/phy/rockchip/phy-rockchip-usb.c

42

#define UOC_CON3_UTMI_OPMODE_MASK GENMASK(2, 1)

drivers/phy/rockchip/phy-rockchip-usbdp.c

112

_RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable)

drivers/phy/rockchip/phy-rockchip-usbdp.c

37

#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))

drivers/phy/rockchip/phy-rockchip-usbdp.c

38

#define DP_LANE_SEL_ALL GENMASK(7, 0)

drivers/phy/rockchip/phy-rockchip-usbdp.c

44

#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)

drivers/phy/rockchip/phy-rockchip-usbdp.c

45

#define CMN_DP_LANE_EN_ALL GENMASK(3, 0)

drivers/phy/rockchip/phy-rockchip-usbdp.c

48

#define CMN_DP_TX_LINK_BW GENMASK(6, 5)

drivers/phy/samsung/phy-exynos5-usbdrd.c

105

#define PHYCLKRST_REFCLKSEL GENMASK(3, 2)

drivers/phy/samsung/phy-exynos5-usbdrd.c

116

#define PHYREG0_CR_DATA_IN GENMASK(17, 2)

drivers/phy/samsung/phy-exynos5-usbdrd.c

121

#define PHYREG0_CR_DATA_OUT GENMASK(16, 1)

drivers/phy/samsung/phy-exynos5-usbdrd.c

126

#define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26)

drivers/phy/samsung/phy-exynos5-usbdrd.c

128

#define PHYPARAM0_TXVREFTUNE GENMASK(25, 22)

drivers/phy/samsung/phy-exynos5-usbdrd.c

129

#define PHYPARAM0_TXRISETUNE GENMASK(21, 20)

drivers/phy/samsung/phy-exynos5-usbdrd.c

130

#define PHYPARAM0_TXRESTUNE GENMASK(19, 18)

drivers/phy/samsung/phy-exynos5-usbdrd.c

132

#define PHYPARAM0_TXPREEMPAMPTUNE GENMASK(16, 15)

drivers/phy/samsung/phy-exynos5-usbdrd.c

133

#define PHYPARAM0_TXHSXVTUNE GENMASK(14, 13)

drivers/phy/samsung/phy-exynos5-usbdrd.c

134

#define PHYPARAM0_TXFSLSTUNE GENMASK(12, 9)

drivers/phy/samsung/phy-exynos5-usbdrd.c

135

#define PHYPARAM0_SQRXTUNE GENMASK(8, 6)

drivers/phy/samsung/phy-exynos5-usbdrd.c

136

#define PHYPARAM0_OTGTUNE GENMASK(5, 3)

drivers/phy/samsung/phy-exynos5-usbdrd.c

137

#define PHYPARAM0_COMPDISTUNE GENMASK(2, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

140

#define PHYPARAM1_PCS_TXDEEMPH GENMASK(4, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

185

#define PHYPCSVAL_PCS_RX_LOS_MASK GENMASK(9, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

188

#define PHYPARAM2_TX_VBOOST_LVL GENMASK(6, 4)

drivers/phy/samsung/phy-exynos5-usbdrd.c

189

#define PHYPARAM2_LOS_BIAS GENMASK(2, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

198

#define HSPHYPLLTUNE_PLL_I_TUNE GENMASK(5, 4)

drivers/phy/samsung/phy-exynos5-usbdrd.c

199

#define HSPHYPLLTUNE_PLL_P_TUNE GENMASK(3, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

207

#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4)

drivers/phy/samsung/phy-exynos5-usbdrd.c

210

#define LINKPORT_HOST_NUM_U3 GENMASK(19, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

211

#define LINKPORT_HOST_NUM_U2 GENMASK(15, 12)

drivers/phy/samsung/phy-exynos5-usbdrd.c

228

#define SSPPLLCTL_FSEL GENMASK(2, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

246

#define HSPPARACON_TXVREF GENMASK(31, 28)

drivers/phy/samsung/phy-exynos5-usbdrd.c

247

#define HSPPARACON_TXRISE GENMASK(25, 24)

drivers/phy/samsung/phy-exynos5-usbdrd.c

248

#define HSPPARACON_TXRES GENMASK(22, 21)

drivers/phy/samsung/phy-exynos5-usbdrd.c

250

#define HSPPARACON_TXPREEMPAMP GENMASK(19, 18)

drivers/phy/samsung/phy-exynos5-usbdrd.c

251

#define HSPPARACON_TXHSXV GENMASK(17, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

252

#define HSPPARACON_TXFSLS GENMASK(15, 12)

drivers/phy/samsung/phy-exynos5-usbdrd.c

253

#define HSPPARACON_SQRX GENMASK(10, 8)

drivers/phy/samsung/phy-exynos5-usbdrd.c

254

#define HSPPARACON_OTG GENMASK(6, 4)

drivers/phy/samsung/phy-exynos5-usbdrd.c

255

#define HSPPARACON_COMPDIS GENMASK(2, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

274

#define HSPPLLTUNE_FSEL GENMASK(18, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

284

#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

293

#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

308

#define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12)

drivers/phy/samsung/phy-exynos5-usbdrd.c

309

#define SECPMACTL_PMA_LCPLL_REF_CLK_SEL GENMASK(11, 10)

drivers/phy/samsung/phy-exynos5-usbdrd.c

310

#define SECPMACTL_PMA_REF_FREQ_SEL GENMASK(9, 8)

drivers/phy/samsung/phy-exynos5-usbdrd.c

323

#define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

354

#define NS_VEC_NS_REQ GENMASK(31, 24)

drivers/phy/samsung/phy-exynos5-usbdrd.c

356

#define NS_VEC_SEL_TIMEOUT GENMASK(21, 20)

drivers/phy/samsung/phy-exynos5-usbdrd.c

357

#define NS_VEC_INV_MASK GENMASK(19, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

358

#define NS_VEC_COND_MASK GENMASK(11, 8)

drivers/phy/samsung/phy-exynos5-usbdrd.c

359

#define NS_VEC_EXP_COND GENMASK(3, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

389

#define EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE GENMASK(29, 24)

drivers/phy/samsung/phy-exynos5-usbdrd.c

400

#define RX_CONTROL_DEBUG_NUM_COM_FOUND GENMASK(3, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

403

#define LOCAL_COEF_PMA_CENTER_COEF GENMASK(21, 16)

drivers/phy/samsung/phy-exynos5-usbdrd.c

404

#define LOCAL_COEF_LF GENMASK(13, 8)

drivers/phy/samsung/phy-exynos5-usbdrd.c

405

#define LOCAL_COEF_FS GENMASK(5, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

408

#define HS_TX_COEF_MAP_0_SSTX_DEEMP GENMASK(17, 12)

drivers/phy/samsung/phy-exynos5-usbdrd.c

409

#define HS_TX_COEF_MAP_0_SSTX_LEVEL GENMASK(11, 6)

drivers/phy/samsung/phy-exynos5-usbdrd.c

410

#define HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT GENMASK(5, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

56

#define HSP_MISC_RES_TUNE GENMASK(1, 0)

drivers/phy/samsung/phy-exynos5-usbdrd.c

66

#define LINKSYSTEM_FLADJ GENMASK(6, 1)

drivers/phy/samsung/phy-exynos5-usbdrd.c

87

#define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23)

drivers/phy/samsung/phy-exynos5-usbdrd.c

88

#define PHYCLKRST_SSC_RANGE GENMASK(22, 21)

drivers/phy/samsung/phy-exynos5-usbdrd.c

92

#define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11)

drivers/phy/samsung/phy-exynos5-usbdrd.c

98

#define PHYCLKRST_FSEL_PIPE GENMASK(10, 8)

drivers/phy/samsung/phy-exynos5-usbdrd.c

99

#define PHYCLKRST_FSEL_UTMI GENMASK(7, 5)

drivers/phy/socionext/phy-uniphier-ahci.c

40

#define CKCTRL0_NCY_MASK GENMASK(8, 4)

drivers/phy/socionext/phy-uniphier-ahci.c

41

#define CKCTRL0_NCY5_MASK GENMASK(3, 2)

drivers/phy/socionext/phy-uniphier-ahci.c

42

#define CKCTRL0_PRESCALE_MASK GENMASK(1, 0)

drivers/phy/socionext/phy-uniphier-ahci.c

44

#define CKCTRL1_LOS_LVL_MASK GENMASK(20, 16)

drivers/phy/socionext/phy-uniphier-ahci.c

45

#define CKCTRL1_TX_LVL_MASK GENMASK(12, 8)

drivers/phy/socionext/phy-uniphier-ahci.c

47

#define RXTXCTRL_RX_EQ_VALL_MASK GENMASK(31, 29)

drivers/phy/socionext/phy-uniphier-ahci.c

48

#define RXTXCTRL_RX_DPLL_MODE_MASK GENMASK(28, 26)

drivers/phy/socionext/phy-uniphier-ahci.c

49

#define RXTXCTRL_TX_ATTEN_MASK GENMASK(14, 12)

drivers/phy/socionext/phy-uniphier-ahci.c

50

#define RXTXCTRL_TX_BOOST_MASK GENMASK(11, 8)

drivers/phy/socionext/phy-uniphier-ahci.c

51

#define RXTXCTRL_TX_EDGERATE_MASK GENMASK(3, 2)

drivers/phy/socionext/phy-uniphier-ahci.c

62

#define TXCTRL0_AMP_G3_MASK GENMASK(22, 16)

drivers/phy/socionext/phy-uniphier-ahci.c

63

#define TXCTRL0_AMP_G2_MASK GENMASK(14, 8)

drivers/phy/socionext/phy-uniphier-ahci.c

64

#define TXCTRL0_AMP_G1_MASK GENMASK(6, 0)

drivers/phy/socionext/phy-uniphier-ahci.c

66

#define TXCTRL1_DEEMPH_G3_MASK GENMASK(21, 16)

drivers/phy/socionext/phy-uniphier-ahci.c

67

#define TXCTRL1_DEEMPH_G2_MASK GENMASK(13, 8)

drivers/phy/socionext/phy-uniphier-ahci.c

68

#define TXCTRL1_DEEMPH_G1_MASK GENMASK(5, 0)

drivers/phy/socionext/phy-uniphier-ahci.c

70

#define RXCTRL_LOS_LVL_MASK GENMASK(20, 16)

drivers/phy/socionext/phy-uniphier-ahci.c

71

#define RXCTRL_LOS_BIAS_MASK GENMASK(10, 8)

drivers/phy/socionext/phy-uniphier-ahci.c

72

#define RXCTRL_RX_EQ_MASK GENMASK(2, 0)

drivers/phy/socionext/phy-uniphier-pcie.c

23

#define PORT_SEL_MASK GENMASK(11, 9)

drivers/phy/socionext/phy-uniphier-pcie.c

27

#define TESTI_DAT_MASK GENMASK(13, 6)

drivers/phy/socionext/phy-uniphier-pcie.c

28

#define TESTI_ADR_MASK GENMASK(5, 1)

drivers/phy/socionext/phy-uniphier-pcie.c

33

#define TESTO_DAT_MASK GENMASK(7, 0)

drivers/phy/socionext/phy-uniphier-pcie.c

45

#define SC_US3SRCSEL_2LANE GENMASK(9, 8)

drivers/phy/socionext/phy-uniphier-pcie.c

50

#define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */

drivers/phy/socionext/phy-uniphier-pcie.c

53

#define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */

drivers/phy/socionext/phy-uniphier-pcie.c

56

#define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */

drivers/phy/socionext/phy-uniphier-usb3hs.c

179

u32 field_mask = GENMASK(p->field.msb, p->field.lsb);

drivers/phy/socionext/phy-uniphier-usb3hs.c

27

#define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28)

drivers/phy/socionext/phy-uniphier-usb3hs.c

28

#define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26)

drivers/phy/socionext/phy-uniphier-usb3hs.c

29

#define HSPHY_CFG0_SWING_MASK GENMASK(17, 16)

drivers/phy/socionext/phy-uniphier-usb3hs.c

30

#define HSPHY_CFG0_SEL_T_MASK GENMASK(15, 12)

drivers/phy/socionext/phy-uniphier-usb3hs.c

31

#define HSPHY_CFG0_RTERM_MASK GENMASK(7, 6)

drivers/phy/socionext/phy-uniphier-usb3hs.c

39

#define HSPHY_CFG1_ADR_MASK GENMASK(27, 16)

drivers/phy/socionext/phy-uniphier-usb3hs.c

40

#define HSPHY_CFG1_DAT_MASK GENMASK(23, 16)

drivers/phy/socionext/phy-uniphier-usb3ss.c

25

#define TESTI_DAT_MASK GENMASK(13, 6)

drivers/phy/socionext/phy-uniphier-usb3ss.c

26

#define TESTI_ADR_MASK GENMASK(5, 1)

drivers/phy/socionext/phy-uniphier-usb3ss.c

30

#define TESTO_DAT_MASK GENMASK(7, 0)

drivers/phy/socionext/phy-uniphier-usb3ss.c

82

u8 field_mask = GENMASK(p->field.msb, p->field.lsb);

drivers/phy/spacemit/phy-k1-usb2.c

55

#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)

drivers/phy/spacemit/phy-k1-usb2.c

56

#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)

drivers/phy/spacemit/phy-k1-usb2.c

62

#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13)

drivers/phy/st/phy-stm32-combophy.c

28

#define STM32MP25_PCIEPRG_IMPCTRL_OHM GENMASK(3, 1)

drivers/phy/st/phy-stm32-combophy.c

29

#define STM32MP25_PCIEPRG_IMPCTRL_VSWING GENMASK(5, 4)

drivers/phy/st/phy-stm32-combophy.c

36

#define SYSCFG_COMBOPHY_CR1_MPLLMULT GENMASK(7, 1)

drivers/phy/st/phy-stm32-combophy.c

37

#define SYSCFG_COMBOPHY_CR1_REFCLKSEL GENMASK(16, 8)

drivers/phy/st/phy-stm32-combophy.c

43

#define SYSCFG_COMBOPHY_CR4_RX0_EQ GENMASK(2, 0)

drivers/phy/st/phy-stm32-combophy.c

62

#define SYSCFG_COMBOPHY_CR2_MODESEL GENMASK(1, 0)

drivers/phy/st/phy-stm32-combophy.c

72

#define COMBOPHY_PROP_CNTRL GENMASK(7, 4)

drivers/phy/st/phy-stm32-usbphyc.c

124

#define MINREV GENMASK(3, 0)

drivers/phy/st/phy-stm32-usbphyc.c

125

#define MAJREV GENMASK(7, 4)

drivers/phy/st/phy-stm32-usbphyc.c

28

#define PLLNDIV GENMASK(6, 0)

drivers/phy/st/phy-stm32-usbphyc.c

29

#define PLLFRACIN GENMASK(25, 10)

drivers/phy/st/phy-stm32-usbphyc.c

41

#define STM32_USBPHYC_MON_OUT GENMASK(3, 0)

drivers/phy/st/phy-stm32-usbphyc.c

42

#define STM32_USBPHYC_MON_SEL GENMASK(8, 4)

drivers/phy/st/phy-stm32-usbphyc.c

56

#define HSDRVCHKITRM GENMASK(12, 9)

drivers/phy/st/phy-stm32-usbphyc.c

57

#define HSDRVCHKZTRM GENMASK(14, 13)

drivers/phy/st/phy-stm32-usbphyc.c

58

#define OTPCOMP GENMASK(19, 15)

drivers/phy/st/phy-stm32-usbphyc.c

59

#define SQLCHCTL GENMASK(21, 20)

drivers/phy/st/phy-stm32-usbphyc.c

61

#define HSRXOFF GENMASK(24, 23)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

29

#define STF_DPHY_LANE_SWAP_CLK GENMASK(22, 20)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

30

#define STF_DPHY_LANE_SWAP_CLK1 GENMASK(25, 23)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

31

#define STF_DPHY_LANE_SWAP_LAN0 GENMASK(28, 26)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

32

#define STF_DPHY_LANE_SWAP_LAN1 GENMASK(31, 29)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

34

#define STF_DPHY_LANE_SWAP_LAN2 GENMASK(2, 0)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

35

#define STF_DPHY_LANE_SWAP_LAN3 GENMASK(5, 3)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

36

#define STF_DPHY_PLL_CLK_SEL GENMASK(21, 12)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

37

#define STF_DPHY_PRECOUNTER_IN_CLK GENMASK(29, 22)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

39

#define STF_DPHY_PRECOUNTER_IN_CLK1 GENMASK(7, 0)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

40

#define STF_DPHY_PRECOUNTER_IN_LAN0 GENMASK(15, 8)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

41

#define STF_DPHY_PRECOUNTER_IN_LAN1 GENMASK(23, 16)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

42

#define STF_DPHY_PRECOUNTER_IN_LAN2 GENMASK(31, 24)

drivers/phy/starfive/phy-jh7110-dphy-rx.c

44

#define STF_DPHY_PRECOUNTER_IN_LAN3 GENMASK(7, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

28

#define STF_DPHY_CFG_L0_SWAP_SEL GENMASK(14, 12)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

29

#define STF_DPHY_CFG_L1_SWAP_SEL GENMASK(17, 15)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

30

#define STF_DPHY_CFG_L2_SWAP_SEL GENMASK(20, 18)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

31

#define STF_DPHY_CFG_L3_SWAP_SEL GENMASK(23, 21)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

32

#define STF_DPHY_CFG_L4_SWAP_SEL GENMASK(26, 24)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

34

#define STF_DPHY_RG_CDTX_L0N_HSTX_RES GENMASK(23, 19)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

35

#define STF_DPHY_RG_CDTX_L0P_HSTX_RES GENMASK(28, 24)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

37

#define STF_DPHY_RG_CDTX_L1P_HSTX_RES GENMASK(9, 5)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

38

#define STF_DPHY_RG_CDTX_L2N_HSTX_RES GENMASK(14, 10)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

39

#define STF_DPHY_RG_CDTX_L2P_HSTX_RES GENMASK(19, 15)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

40

#define STF_DPHY_RG_CDTX_L3N_HSTX_RES GENMASK(24, 20)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

41

#define STF_DPHY_RG_CDTX_L3P_HSTX_RES GENMASK(29, 25)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

43

#define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

44

#define STF_DPHY_RG_CDTX_L4P_HSTX_RES GENMASK(9, 5)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

45

#define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

47

#define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

50

#define STF_DPHY_RG_CDTX_PLL_PRE_DIV GENMASK(12, 11)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

54

#define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

55

#define STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME GENMASK(15, 8)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

56

#define STF_DPHY_RG_CLANE_HS_PRE_TIME GENMASK(23, 16)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

57

#define STF_DPHY_RG_CLANE_HS_TRAIL_TIME GENMASK(31, 24)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

59

#define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

60

#define STF_DPHY_RG_DLANE_HS_PRE_TIME GENMASK(15, 8)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

61

#define STF_DPHY_RG_DLANE_HS_TRAIL_TIME GENMASK(23, 16)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

62

#define STF_DPHY_RG_DLANE_HS_ZERO_TIME GENMASK(31, 24)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

64

#define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

65

#define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

67

#define STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL GENMASK(2, 1)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

68

#define STF_DPHY_SCFG_PPI_C_READY_SEL GENMASK(4, 3)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

70

#define STF_DPHY_REFCLK_IN_SEL GENMASK(28, 26)

drivers/phy/starfive/phy-jh7110-dphy-tx.c

78

#define STF_DPHY_LSHIFT_16(x) (FIELD_PREP(GENMASK(23, 16), (x)))

drivers/phy/starfive/phy-jh7110-dphy-tx.c

79

#define STF_DPHY_LSHIFT_8(x) (FIELD_PREP(GENMASK(15, 8), (x)))

drivers/phy/starfive/phy-jh7110-pcie.c

29

#define PCIE_PHY_MODE_MASK GENMASK(21, 20)

drivers/phy/starfive/phy-jh7110-pcie.c

30

#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2)

drivers/phy/starfive/phy-jh7110-pcie.c

32

#define PCIE_USB3_RATE_MASK GENMASK(6, 5)

drivers/phy/sunplus/phy-sunplus-usb2.c

24

#define HIGH_MASK_BITS GENMASK(31, 16)

drivers/phy/sunplus/phy-sunplus-usb2.c

25

#define LOW_MASK_BITS GENMASK(15, 0)

drivers/phy/sunplus/phy-sunplus-usb2.c

39

#define J_TBCWAIT_MASK GENMASK(6, 5)

drivers/phy/sunplus/phy-sunplus-usb2.c

41

#define J_TVDM_SRC_DIS_MASK GENMASK(4, 3)

drivers/phy/sunplus/phy-sunplus-usb2.c

43

#define J_TVDM_SRC_EN_MASK GENMASK(2, 1)

drivers/phy/sunplus/phy-sunplus-usb2.c

47

#define IBG_TRIM0_MASK GENMASK(7, 5)

drivers/phy/sunplus/phy-sunplus-usb2.c

49

#define J_VDATREE_TRIM_MASK GENMASK(4, 1)

drivers/phy/sunplus/phy-sunplus-usb2.c

52

#define PROB_MASK GENMASK(5, 3)

drivers/phy/tegra/xusb-tegra210.c

224

#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK GENMASK(5, 4)

drivers/phy/tegra/xusb-tegra210.c

225

#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL GENMASK(5, 4)

drivers/phy/tegra/xusb-tegra210.c

229

#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK GENMASK(13, 12)

drivers/phy/tegra/xusb-tegra210.c

230

#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL GENMASK(13, 12)

drivers/phy/ti/phy-am654-serdes.c

335

GENMASK((a), (b)), (val) << (b))

drivers/phy/ti/phy-am654-serdes.c

84

#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)

drivers/phy/ti/phy-ti-pipe3.c

103

#define MEM_EQLEV_MASK GENMASK(31, 16)

drivers/phy/ti/phy-ti-pipe3.c

105

#define MEM_EQFTC_MASK GENMASK(15, 11)

drivers/phy/ti/phy-ti-pipe3.c

107

#define MEM_EQCTL_MASK GENMASK(10, 7)

drivers/phy/ti/phy-ti-pipe3.c

115

#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)

drivers/phy/ti/phy-ti-pipe3.c

50

#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)

drivers/phy/ti/phy-ti-pipe3.c

53

#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)

drivers/phy/ti/phy-ti-pipe3.c

63

#define INTERFACE_MASK GENMASK(31, 27)

drivers/phy/ti/phy-ti-pipe3.c

70

#define LOSD_MASK GENMASK(17, 14)

drivers/phy/ti/phy-ti-pipe3.c

72

#define MEM_PLLDIV GENMASK(6, 5)

drivers/phy/ti/phy-ti-pipe3.c

75

#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)

drivers/phy/ti/phy-ti-pipe3.c

79

#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)

drivers/phy/ti/phy-ti-pipe3.c

83

#define MEM_HS_RATE_MASK GENMASK(28, 27)

drivers/phy/ti/phy-ti-pipe3.c

89

#define MEM_CDR_LBW_MASK GENMASK(22, 21)

drivers/phy/ti/phy-ti-pipe3.c

91

#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)

drivers/phy/ti/phy-ti-pipe3.c

93

#define MEM_CDR_STL_MASK GENMASK(18, 16)

drivers/phy/ti/phy-ti-pipe3.c

95

#define MEM_CDR_THR_MASK GENMASK(15, 13)

drivers/phy/ti/phy-tusb1210.c

32

#define TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK GENMASK(3, 0)

drivers/phy/ti/phy-tusb1210.c

33

#define TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK GENMASK(5, 4)

drivers/phy/xilinx/phy-zynqmp.c

149

#define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1118

#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1119

#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1120

#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1121

#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

467

#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

528

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

530

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

532

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

688

#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

689

#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

690

#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1022

#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1023

#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1024

#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1025

#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1540

#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1543

#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1546

#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1549

#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1866

#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1867

#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1868

#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1869

#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

515

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

517

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

519

{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

59

#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

693

#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

694

#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

695

#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

696

#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1584

#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1585

#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1586

#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1587

#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1588

#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1589

#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1590

#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2610

{ PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2612

{ PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2614

{ PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2616

{ PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2618

{ PIN_CONFIG_DRIVE_STRENGTH, { D22, A23 }, SCU458, GENMASK(9, 8)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2620

{ PIN_CONFIG_DRIVE_STRENGTH, { E21, B21 }, SCU458, GENMASK(11, 10)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2624

{ PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2627

{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2719

{ PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2720

{ PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2721

{ PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

2722

{ PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},

drivers/pinctrl/bcm/pinctrl-bcm6318.c

26

#define BCM6328_MUX_MASK GENMASK(1, 0)

drivers/pinctrl/bcm/pinctrl-bcm6318.c

28

#define BCM6328_PAD_MASK GENMASK(3, 0)

drivers/pinctrl/bcm/pinctrl-bcm6328.c

27

#define BCM6328_MUX_MASK GENMASK(1, 0)

drivers/pinctrl/berlin/berlin.c

165

mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1,

drivers/pinctrl/cix/pinctrl-sky1-base.c

29

#define SKY1_MUX_MASK GENMASK(8, 7)

drivers/pinctrl/cix/pinctrl-sky1-base.c

31

#define SKY1_PULLCONF_MASK GENMASK(6, 5)

drivers/pinctrl/cix/pinctrl-sky1-base.c

34

#define SKY1_DS_MASK GENMASK(3, 0)

drivers/pinctrl/cix/pinctrl-sky1-base.c

37

#define CIX_PIN_FUN_MASK GENMASK(1, 0)

drivers/pinctrl/intel/pinctrl-baytrail.c

44

#define BYT_TRIG_MASK GENMASK(26, 24)

drivers/pinctrl/intel/pinctrl-baytrail.c

53

#define BYT_PULL_STR_MASK GENMASK(10, 9)

drivers/pinctrl/intel/pinctrl-baytrail.c

58

#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)

drivers/pinctrl/intel/pinctrl-baytrail.c

61

#define BYT_PIN_MUX GENMASK(2, 0)

drivers/pinctrl/intel/pinctrl-baytrail.c

64

#define BYT_DIR_MASK GENMASK(2, 1)

drivers/pinctrl/intel/pinctrl-baytrail.c

73

#define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)

drivers/pinctrl/intel/pinctrl-cherryview.c

1505

chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));

drivers/pinctrl/intel/pinctrl-cherryview.c

41

#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28)

drivers/pinctrl/intel/pinctrl-cherryview.c

44

#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20)

drivers/pinctrl/intel/pinctrl-cherryview.c

49

#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16)

drivers/pinctrl/intel/pinctrl-cherryview.c

52

#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8)

drivers/pinctrl/intel/pinctrl-cherryview.c

63

#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)

drivers/pinctrl/intel/pinctrl-cherryview.c

68

#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0)

drivers/pinctrl/intel/pinctrl-intel.c

111

#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)

drivers/pinctrl/intel/pinctrl-intel.c

37

#define REVID_MASK GENMASK(31, 16)

drivers/pinctrl/intel/pinctrl-intel.c

41

#define CAPLIST_ID_MASK GENMASK(23, 16)

drivers/pinctrl/intel/pinctrl-intel.c

47

#define CAPLIST_NEXT_MASK GENMASK(15, 0)

drivers/pinctrl/intel/pinctrl-intel.c

53

#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))

drivers/pinctrl/intel/pinctrl-intel.c

60

#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)

drivers/pinctrl/intel/pinctrl-intel.c

72

#define PADCFG0_PMODE_MASK GENMASK(13, 10)

drivers/pinctrl/intel/pinctrl-intel.c

75

#define PADCFG0_GPIODIS_MASK GENMASK(9, 8)

drivers/pinctrl/intel/pinctrl-intel.c

88

#define PADCFG1_TERM_MASK GENMASK(12, 10)

drivers/pinctrl/intel/pinctrl-lynxpoint.c

176

#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */

drivers/pinctrl/intel/pinctrl-lynxpoint.c

182

#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */

drivers/pinctrl/intel/pinctrl-tangier.c

40

#define BUFCFG_PINMODE_MASK GENMASK(2, 0)

drivers/pinctrl/intel/pinctrl-tangier.c

43

#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)

drivers/pinctrl/intel/pinctrl-tangier.c

50

#define BUFCFG_Px_EN_MASK GENMASK(9, 8)

drivers/pinctrl/intel/pinctrl-tangier.c

54

#define BUFCFG_OVINEN_MASK GENMASK(13, 12)

drivers/pinctrl/intel/pinctrl-tangier.c

57

#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)

drivers/pinctrl/intel/pinctrl-tangier.c

60

#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)

drivers/pinctrl/intel/pinctrl-tangier.c

63

#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)

drivers/pinctrl/mediatek/pinctrl-airoha.c

114

#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)

drivers/pinctrl/mediatek/pinctrl-airoha.c

117

#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)

drivers/pinctrl/mediatek/pinctrl-airoha.c

120

#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)

drivers/pinctrl/mediatek/pinctrl-airoha.c

123

#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)

drivers/pinctrl/mediatek/pinctrl-airoha.c

126

#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)

drivers/pinctrl/mediatek/pinctrl-airoha.c

2304

u32 mask = GENMASK(2 * offset + 1, 2 * offset);

drivers/pinctrl/mediatek/pinctrl-airoha.c

2341

u32 mask = GENMASK(2 * offset + 1, 2 * offset);

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

22

#define MPFS_PINCTRL_PAD_MUX_MASK GENMASK(3, 0)

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

24

#define MPFS_PINCTRL_IOCFG_MASK GENMASK(14, 0)

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

25

#define MPFS_PINCTRL_IBUFMD_MASK GENMASK(2, 0)

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

26

#define MPFS_PINCTRL_DRV_MASK GENMASK(6, 3)

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

32

#define MPFS_PINCTRL_PULL_MASK GENMASK(11, 10)

drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c

38

#define MPFS_PINCTRL_BANK_VOLTAGE_MASK GENMASK(19, 16)

drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c

142

PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)),

drivers/pinctrl/nuvoton/pinctrl-ma35.c

285

regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,

drivers/pinctrl/nuvoton/pinctrl-ma35.c

392

regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);

drivers/pinctrl/nuvoton/pinctrl-ma35.c

55

#define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

57

#define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

63

#define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2)

drivers/pinctrl/nuvoton/pinctrl-ma35.c

79

#define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4)

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1285

#define DRIVE_STRENGTH_MASK GENMASK(15, 8)

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1289

#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0))

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1290

#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0))

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2123

dbncp_val_mod = dbncp_val & GENMASK(3, 0);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

2124

if (dbncp_val_mod > GENMASK(2, 0))

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

84

#define NPCM8XX_DEBOUNCE_VAL_MASK GENMASK(23, 4)

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

317

ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;

drivers/pinctrl/nxp/pinctrl-s32cc.c

32

#define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT)

drivers/pinctrl/nxp/pinctrl-s32cc.c

34

#define S32_MSCR_SSS_MASK GENMASK(2, 0)

drivers/pinctrl/nxp/pinctrl-s32cc.c

37

#define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14)

drivers/pinctrl/nxp/pinctrl-s32cc.c

60

return pinmux & GENMASK(3, 0);

drivers/pinctrl/pinctrl-amd.h

80

#define FUNCTION_MASK GENMASK(1, 0)

drivers/pinctrl/pinctrl-amd.h

81

#define FUNCTION_INVALID GENMASK(7, 0)

drivers/pinctrl/pinctrl-apple-gpio.c

47

#define REG_GPIOx_MODE GENMASK(3, 1)

drivers/pinctrl/pinctrl-apple-gpio.c

55

#define REG_GPIOx_PERIPH GENMASK(6, 5)

drivers/pinctrl/pinctrl-apple-gpio.c

56

#define REG_GPIOx_PULL GENMASK(8, 7)

drivers/pinctrl/pinctrl-apple-gpio.c

62

#define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)

drivers/pinctrl/pinctrl-apple-gpio.c

64

#define REG_GPIOx_GRP GENMASK(18, 16)

drivers/pinctrl/pinctrl-apple-gpio.c

66

#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)

drivers/pinctrl/pinctrl-at91-pio4.c

39

#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)

drivers/pinctrl/pinctrl-at91-pio4.c

48

#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)

drivers/pinctrl/pinctrl-at91-pio4.c

50

#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)

drivers/pinctrl/pinctrl-aw9523.c

50

#define AW9523_GCR_ISEL_MASK GENMASK(0, 1)

drivers/pinctrl/pinctrl-axp209.c

32

#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)

drivers/pinctrl/pinctrl-cy8c95x0.c

1385

switch (ret & GENMASK(7, 4)) {

drivers/pinctrl/pinctrl-cy8c95x0.c

70

#define CY8C95X0_GPIO_MASK GENMASK(7, 0)

drivers/pinctrl/pinctrl-eic7700.c

34

#define EIC7700_DS GENMASK(6, 3)

drivers/pinctrl/pinctrl-eic7700.c

36

#define EIC7700_FUNC_SEL GENMASK(18, 16)

drivers/pinctrl/pinctrl-eic7700.c

39

#define EIC7700_PINCONF GENMASK(7, 0)

drivers/pinctrl/pinctrl-eic7700.c

43

#define EIC7700_MS GENMASK(1, 0)

drivers/pinctrl/pinctrl-ep93xx.c

92

#define PADS_MASK (GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) | BIT(4))

drivers/pinctrl/pinctrl-equilibrium.c

502

mask = GENMASK(1, 0) << offset;

drivers/pinctrl/pinctrl-eyeq5.c

71

#define EQ5P_DS_MASK GENMASK(1, 0)

drivers/pinctrl/pinctrl-gemini.c

107

#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)

drivers/pinctrl/pinctrl-gemini.c

127

#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))

drivers/pinctrl/pinctrl-gemini.c

1701

.driving_mask = GENMASK(21, 20),

drivers/pinctrl/pinctrl-gemini.c

1718

.driving_mask = GENMASK(17, 16),

drivers/pinctrl/pinctrl-gemini.c

1727

.driving_mask = GENMASK(19, 18),

drivers/pinctrl/pinctrl-gemini.c

1735

.driving_mask = GENMASK(23, 22),

drivers/pinctrl/pinctrl-gemini.c

2309

.mask = GENMASK(_hb, _lb) \

drivers/pinctrl/pinctrl-gemini.c

752

.driving_mask = GENMASK(21, 20),

drivers/pinctrl/pinctrl-gemini.c

768

.driving_mask = GENMASK(17, 16),

drivers/pinctrl/pinctrl-gemini.c

776

.driving_mask = GENMASK(19, 18),

drivers/pinctrl/pinctrl-gemini.c

784

.driving_mask = GENMASK(23, 22),

drivers/pinctrl/pinctrl-ingenic.c

174

(!(enabled_socs & GENMASK(version - 1, 0))

drivers/pinctrl/pinctrl-ingenic.c

3567

unsigned int mask = GENMASK(1, 0) << idx * 2;

drivers/pinctrl/pinctrl-ingenic.c

3871

unsigned int mask = GENMASK(1, 0) << idx * 2;

drivers/pinctrl/pinctrl-k210.c

31

#define K210_PC_DRIVE_MASK GENMASK(11, 8)

drivers/pinctrl/pinctrl-k210.c

42

#define K210_PC_MODE_MASK GENMASK(23, 12)

drivers/pinctrl/pinctrl-k210.c

75

#define K210_PG_FUNC GENMASK(7, 0)

drivers/pinctrl/pinctrl-k210.c

77

#define K210_PG_PIN GENMASK(22, 16)

drivers/pinctrl/pinctrl-k230.c

36

#define K230_PC_DS GENMASK(4, 1)

drivers/pinctrl/pinctrl-k230.c

39

#define K230_PC_BIAS GENMASK(6, 5)

drivers/pinctrl/pinctrl-k230.c

44

#define K230_PC_SEL GENMASK(13, 11)

drivers/pinctrl/pinctrl-keembay.c

33

#define KEEMBAY_GPIO_MODE_PULLUP_MASK GENMASK(13, 12)

drivers/pinctrl/pinctrl-keembay.c

34

#define KEEMBAY_GPIO_MODE_DRIVE_MASK GENMASK(8, 7)

drivers/pinctrl/pinctrl-keembay.c

35

#define KEEMBAY_GPIO_MODE_INV_MASK GENMASK(5, 4)

drivers/pinctrl/pinctrl-keembay.c

36

#define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0)

drivers/pinctrl/pinctrl-microchip-sgpio.c

632

priv->ports |= GENMASK(end, start);

drivers/pinctrl/pinctrl-microchip-sgpio.c

65

#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)

drivers/pinctrl/pinctrl-microchip-sgpio.c

66

#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)

drivers/pinctrl/pinctrl-microchip-sgpio.c

67

#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)

drivers/pinctrl/pinctrl-microchip-sgpio.c

71

#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)

drivers/pinctrl/pinctrl-microchip-sgpio.c

72

#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)

drivers/pinctrl/pinctrl-microchip-sgpio.c

73

#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)

drivers/pinctrl/pinctrl-microchip-sgpio.c

77

#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)

drivers/pinctrl/pinctrl-microchip-sgpio.c

78

#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)

drivers/pinctrl/pinctrl-microchip-sgpio.c

79

#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)

drivers/pinctrl/pinctrl-ocelot.c

2008

.drive_bits = GENMASK(1, 0),

drivers/pinctrl/pinctrl-ocelot.c

2026

.drive_bits = GENMASK(1, 0),

drivers/pinctrl/pinctrl-ocelot.c

2043

.drive_bits = GENMASK(1, 0),

drivers/pinctrl/pinctrl-ocelot.c

2060

.drive_bits = GENMASK(1, 0),

drivers/pinctrl/pinctrl-pef2256.c

26

#define PEF2256_12_PC_RPC_MASK GENMASK(6, 4)

drivers/pinctrl/pinctrl-pef2256.c

35

#define PEF2256_12_PC_XPC_MASK GENMASK(4, 0)

drivers/pinctrl/pinctrl-pef2256.c

45

#define PEF2256_2X_PC_RPC_MASK GENMASK(7, 4)

drivers/pinctrl/pinctrl-pef2256.c

58

#define PEF2256_2X_PC_XPC_MASK GENMASK(3, 0)

drivers/pinctrl/pinctrl-rk805.c

271

#define RK806_PWRCTRL1_FUN GENMASK(2, 0)

drivers/pinctrl/pinctrl-rk805.c

272

#define RK806_PWRCTRL2_FUN GENMASK(6, 4)

drivers/pinctrl/pinctrl-rk805.c

273

#define RK806_PWRCTRL3_FUN GENMASK(2, 0)

drivers/pinctrl/pinctrl-rockchip.c

48

(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))

drivers/pinctrl/pinctrl-rp1.c

31

#define RP1_INT_MASK GENMASK(3, 0)

drivers/pinctrl/pinctrl-stmfx.c

626

pctl->gpio_valid_mask = GENMASK(15, 0);

drivers/pinctrl/pinctrl-stmfx.c

631

pctl->gpio_valid_mask |= GENMASK(19, 16);

drivers/pinctrl/pinctrl-stmfx.c

637

pctl->gpio_valid_mask |= GENMASK(23, 20);

drivers/pinctrl/pinctrl-th1520.c

41

#define TH1520_PADCFG_DS GENMASK(3, 0)

drivers/pinctrl/pinctrl-th1520.c

48

#define TH1520_PAD_MUXDATA GENMASK(29, 0)

drivers/pinctrl/pinctrl-th1520.c

607

value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);

drivers/pinctrl/pinctrl-th1520.c

756

value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);

drivers/pinctrl/pinctrl-th1520.c

781

if ((muxdata & GENMASK(4, 0)) == muxtype)

drivers/pinctrl/pinctrl-th1520.c

790

mask = GENMASK(3, 0) << shift;

drivers/pinctrl/pinctrl-th1520.c

83

return 4 * (pin & GENMASK(2, 0));

drivers/pinctrl/pinctrl-zynqmp.c

51

#define VERSAL_PINCTRL_ATTR_NODETYPE_MASK GENMASK(19, 14)

drivers/pinctrl/qcom/pinctrl-lpass-lpi.h

22

#define LPI_SLEW_RATE_MASK GENMASK(1, 0)

drivers/pinctrl/qcom/pinctrl-lpass-lpi.h

24

#define LPI_GPIO_PULL_MASK GENMASK(1, 0)

drivers/pinctrl/qcom/pinctrl-lpass-lpi.h

25

#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)

drivers/pinctrl/qcom/pinctrl-lpass-lpi.h

26

#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)

drivers/pinctrl/qcom/pinctrl-msm.c

1041

u32 intr_target_mask = GENMASK(2, 0);

drivers/pinctrl/qcom/pinctrl-msm.c

1078

intr_target_mask = GENMASK(g->intr_target_width - 1, 0);

drivers/pinctrl/qcom/pinctrl-msm.c

170

mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);

drivers/pinctrl/qcom/tlmm-test.c

36

#define MSM_PULL_MASK GENMASK(2, 0)

drivers/pinctrl/realtek/pinctrl-rtd.c

424

mask = GENMASK(p_off + sconfig_desc->pdrive_maskbits - 1, p_off);

drivers/pinctrl/realtek/pinctrl-rtd.c

441

mask = GENMASK(n_off + sconfig_desc->ndrive_maskbits - 1, n_off);

drivers/pinctrl/realtek/pinctrl-rtd.c

453

mask = GENMASK(sconfig_desc->dcycle_offset +

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1002

[RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1014

[RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1030

[RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1034

[RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1039

[RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1044

[RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1048

[RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1053

[RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1057

[RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1062

[RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1066

[RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1070

[RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1083

[RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1097

[RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1110

[RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1123

[RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1133

[RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1138

[RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1142

[RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1147

[RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1157

[RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1168

[RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1178

[RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1187

[RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1196

[RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1202

[RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1207

[RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1212

[RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1218

[RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1222

[RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1226

[RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1229

[RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1232

[RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1235

[RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1240

[RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1245

[RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1250

[RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1255

[RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1259

[RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1263

[RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1267

[RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1271

[RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1275

[RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1279

[RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

1284

[RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

749

[RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

754

[RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

758

[RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

763

[RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

768

[RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

773

[RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

778

[RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

783

[RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

789

[RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

794

[RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

799

[RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

804

[RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

809

[RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

813

[RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

820

[RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

826

[RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

830

[RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

835

[RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

840

[RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

845

[RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

850

[RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

854

[RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

858

[RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

863

[RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

869

[RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

873

[RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

877

[RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

882

[RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

887

[RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

894

[RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

898

[RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

903

[RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

909

[RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

914

[RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

919

[RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

924

[RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

928

[RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

934

[RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

945

[RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

955

[RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

963

[RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

969

[RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

986

[RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1003

[RTD1319D_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x10, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1010

[RTD1319D_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x10, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1018

[RTD1319D_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x10, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1024

[RTD1319D_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x10, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1029

[RTD1319D_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x10, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1035

[RTD1319D_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x14, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1039

[RTD1319D_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x14, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1043

[RTD1319D_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0x14, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1050

[RTD1319D_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x14, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1058

[RTD1319D_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x14, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1064

[RTD1319D_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x14, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1068

[RTD1319D_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x14, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1072

[RTD1319D_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x14, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1080

[RTD1319D_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x18, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1092

[RTD1319D_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x18, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1103

[RTD1319D_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x18, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1111

[RTD1319D_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x18, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1118

[RTD1319D_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x18, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1135

[RTD1319D_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x18, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1152

[RTD1319D_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x18, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1164

[RTD1319D_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x18, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1182

[RTD1319D_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x1c, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1186

[RTD1319D_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x1c, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1190

[RTD1319D_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x1c, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1194

[RTD1319D_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x1c, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1198

[RTD1319D_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x1c, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1202

[RTD1319D_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x1c, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1206

[RTD1319D_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x1c, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1210

[RTD1319D_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x1c, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1217

[RTD1319D_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x20, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1221

[RTD1319D_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x20, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1225

[RTD1319D_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x20, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1229

[RTD1319D_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x20, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1233

[RTD1319D_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x20, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1238

[RTD1319D_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x20, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1242

[RTD1319D_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x20, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1247

[RTD1319D_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x20, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1252

[RTD1319D_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x24, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1256

[RTD1319D_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x24, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1271

[RTD1319D_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x24, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1286

[RTD1319D_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x24, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1301

[RTD1319D_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x24, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1316

[RTD1319D_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x24, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1330

[RTD1319D_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x24, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1338

[RTD1319D_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x24, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1347

[RTD1319D_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x28, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1356

[RTD1319D_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1360

[RTD1319D_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1364

[RTD1319D_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1367

[RTD1319D_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1370

[RTD1319D_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1373

[RTD1319D_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1378

[RTD1319D_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1383

[RTD1319D_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1388

[RTD1319D_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1393

[RTD1319D_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1397

[RTD1319D_ISO_EJTAG_SECPU_LOC] = RTK_PIN_MUX(ejtag_secpu_loc, 0x124, GENMASK(20, 18),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1403

[RTD1319D_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1407

[RTD1319D_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1411

[RTD1319D_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1415

[RTD1319D_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1419

[RTD1319D_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1423

[RTD1319D_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1428

[RTD1319D_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1431

[RTD1319D_ISO_SC0_LOC] = RTK_PIN_MUX(sc0_loc, 0x188, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

1435

[RTD1319D_ISO_SC1_LOC] = RTK_PIN_MUX(sc1_loc, 0x188, GENMASK(11, 10),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

806

[RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

811

[RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

815

[RTD1319D_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

820

[RTD1319D_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

825

[RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

830

[RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

835

[RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

840

[RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

846

[RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

851

[RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

856

[RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

861

[RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

866

[RTD1319D_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x4, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

871

[RTD1319D_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x4, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

875

[RTD1319D_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x4, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

879

[RTD1319D_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x4, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

884

[RTD1319D_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x8, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

887

[RTD1319D_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x8, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

890

[RTD1319D_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x8, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

903

[RTD1319D_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x8, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

916

[RTD1319D_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x8, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

927

[RTD1319D_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x8, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

936

[RTD1319D_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x8, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

945

[RTD1319D_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x8, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

949

[RTD1319D_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0xc, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

954

[RTD1319D_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0xc, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

959

[RTD1319D_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0xc, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

964

[RTD1319D_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0xc, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

969

[RTD1319D_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0xc, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

973

[RTD1319D_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0xc, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

977

[RTD1319D_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0xc, GENMASK(27, 24),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

982

[RTD1319D_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0xc, GENMASK(31, 28),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

988

[RTD1319D_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x10, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

992

[RTD1319D_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x10, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1319d.c

996

[RTD1319D_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x10, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1006

[RTD1619B_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x8, GENMASK(26, 24),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1010

[RTD1619B_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(28, 27),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1013

[RTD1619B_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x8, GENMASK(30, 29),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1017

[RTD1619B_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x8, GENMASK(31, 31),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1020

[RTD1619B_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1024

[RTD1619B_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1029

[RTD1619B_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0xc, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1035

[RTD1619B_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0xc, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1040

[RTD1619B_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0xc, GENMASK(8, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1043

[RTD1619B_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0xc, GENMASK(9, 9),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1045

[RTD1619B_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0xc, GENMASK(12, 10),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1051

[RTD1619B_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0xc, GENMASK(17, 13),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1064

[RTD1619B_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0xc, GENMASK(22, 18),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1076

[RTD1619B_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0xc, GENMASK(25, 23),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1082

[RTD1619B_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0xc, GENMASK(28, 26),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1087

[RTD1619B_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x10, GENMASK(4, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1105

[RTD1619B_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x10, GENMASK(9, 5),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1123

[RTD1619B_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x10, GENMASK(13, 10),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1136

[RTD1619B_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x10, GENMASK(18, 14),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1154

[RTD1619B_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x10, GENMASK(20, 19),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1157

[RTD1619B_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x10, GENMASK(22, 21),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1160

[RTD1619B_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x10, GENMASK(24, 23),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1163

[RTD1619B_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x10, GENMASK(26, 25),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1166

[RTD1619B_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x10, GENMASK(28, 27),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1169

[RTD1619B_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x10, GENMASK(30, 29),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1172

[RTD1619B_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x10, GENMASK(31, 31),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1175

[RTD1619B_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1179

[RTD1619B_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(2, 2),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1182

[RTD1619B_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x14, GENMASK(3, 3),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1185

[RTD1619B_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x14, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1189

[RTD1619B_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x14, GENMASK(6, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1192

[RTD1619B_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x14, GENMASK(8, 7),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1196

[RTD1619B_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x14, GENMASK(9, 9),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1199

[RTD1619B_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x14, GENMASK(11, 10),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1203

[RTD1619B_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x14, GENMASK(12, 12),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1207

[RTD1619B_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x14, GENMASK(13, 13),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1210

[RTD1619B_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x14, GENMASK(17, 14),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1218

[RTD1619B_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x14, GENMASK(21, 18),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1226

[RTD1619B_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x14, GENMASK(25, 22),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1234

[RTD1619B_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x14, GENMASK(29, 26),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1242

[RTD1619B_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x18, GENMASK(3, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1247

[RTD1619B_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x18, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1251

[RTD1619B_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x18, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1256

[RTD1619B_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x18, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1260

[RTD1619B_ISO_GPIO_65] = RTK_PIN_MUX(gpio_65, 0x18, GENMASK(10, 10),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1262

[RTD1619B_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x18, GENMASK(14, 11),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1267

[RTD1619B_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x18, GENMASK(18, 15),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1272

[RTD1619B_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x18, GENMASK(22, 19),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1277

[RTD1619B_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x18, GENMASK(26, 23),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1284

[RTD1619B_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x18, GENMASK(29, 27),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1289

[RTD1619B_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x1c, GENMASK(2, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1300

[RTD1619B_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x1c, GENMASK(6, 3),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1311

[RTD1619B_ISO_GPIO_73] = RTK_PIN_MUX(gpio_73, 0x1c, GENMASK(10, 7),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1320

[RTD1619B_ISO_GPIO_74] = RTK_PIN_MUX(gpio_74, 0x1c, GENMASK(14, 11),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1329

[RTD1619B_ISO_GPIO_75] = RTK_PIN_MUX(gpio_75, 0x1c, GENMASK(18, 15),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1338

[RTD1619B_ISO_GPIO_76] = RTK_PIN_MUX(gpio_76, 0x1c, GENMASK(22, 19),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1348

[RTD1619B_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1352

[RTD1619B_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1356

[RTD1619B_ISO_SDIO_LOC] = RTK_PIN_MUX(sdio_loc, 0x120, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1360

[RTD1619B_ISO_HI_LOC] = RTK_PIN_MUX(hi_loc, 0x120, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1363

[RTD1619B_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1366

[RTD1619B_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1369

[RTD1619B_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1373

GENMASK(13, 13),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1377

GENMASK(14, 14),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1381

GENMASK(15, 15),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1385

GENMASK(16, 16),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1388

[RTD1619B_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1393

[RTD1619B_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1398

[RTD1619B_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1403

[RTD1619B_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1406

[RTD1619B_ISO_ISO_GSPI_LOC] = RTK_PIN_MUX(iso_gspi_loc, 0x120, GENMASK(29, 28),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1410

[RTD1619B_ISO_EJTAG_VE3_LOC] = RTK_PIN_MUX(ejtag_ve3_loc, 0x124, GENMASK(20, 18),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1415

[RTD1619B_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x124, GENMASK(23, 21),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

1420

[RTD1619B_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x124, GENMASK(26, 24),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

825

[RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(1, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

828

[RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(3, 2),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

830

[RTD1619B_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(5, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

833

[RTD1619B_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(7, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

837

[RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(9, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

841

[RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(11, 10),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

845

[RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(13, 12),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

849

[RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(15, 14),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

853

[RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x0, GENMASK(17, 16),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

857

[RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x0, GENMASK(19, 18),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

861

[RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x0, GENMASK(21, 20),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

864

[RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x0, GENMASK(23, 22),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

867

[RTD1619B_ISO_SPI_CE_N] = RTK_PIN_MUX(spi_ce_n, 0x0, GENMASK(25, 24),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

872

[RTD1619B_ISO_SPI_SCK] = RTK_PIN_MUX(spi_sck, 0x0, GENMASK(27, 26),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

876

[RTD1619B_ISO_SPI_SO] = RTK_PIN_MUX(spi_so, 0x0, GENMASK(29, 28),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

880

[RTD1619B_ISO_SPI_SI] = RTK_PIN_MUX(spi_si, 0x0, GENMASK(31, 30),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

885

[RTD1619B_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(0, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

887

[RTD1619B_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(3, 1),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

891

[RTD1619B_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x4, GENMASK(7, 4),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

902

[RTD1619B_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x4, GENMASK(11, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

913

[RTD1619B_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x4, GENMASK(15, 12),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

923

[RTD1619B_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x4, GENMASK(19, 16),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

933

[RTD1619B_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(23, 20),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

943

[RTD1619B_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(24, 24),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

945

[RTD1619B_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x4, GENMASK(27, 25),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

950

[RTD1619B_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x4, GENMASK(30, 28),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

955

[RTD1619B_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(2, 0),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

960

[RTD1619B_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(5, 3),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

966

[RTD1619B_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(6, 6),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

969

[RTD1619B_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(7, 7),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

972

[RTD1619B_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(10, 8),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

977

[RTD1619B_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(12, 11),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

981

[RTD1619B_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x8, GENMASK(13, 13),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

984

[RTD1619B_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x8, GENMASK(14, 14),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

987

[RTD1619B_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x8, GENMASK(17, 15),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

993

[RTD1619B_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x8, GENMASK(20, 18),

drivers/pinctrl/realtek/pinctrl-rtd1619b.c

999

[RTD1619B_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x8, GENMASK(23, 21),

drivers/pinctrl/renesas/core.c

1241

GENMASK(info->data_regs[i].reg_width - 1, 0));

drivers/pinctrl/renesas/core.c

884

GENMASK(cfg_reg->reg_width - 1, 0));

drivers/pinctrl/renesas/core.c

942

GENMASK(field->offset + field->size - 1,

drivers/pinctrl/renesas/pinctrl-rza1.c

60

#define MUX_PIN_ID_MASK GENMASK(15, 0)

drivers/pinctrl/renesas/pinctrl-rza1.c

61

#define MUX_FUNC_MASK GENMASK(31, 16)

drivers/pinctrl/renesas/pinctrl-rza2.c

36

#define MUX_PIN_ID_MASK GENMASK(15, 0)

drivers/pinctrl/renesas/pinctrl-rza2.c

37

#define MUX_FUNC_MASK GENMASK(31, 16)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

43

#define MUX_PIN_ID_MASK GENMASK(15, 0)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

44

#define MUX_FUNC_MASK GENMASK(31, 16)

drivers/pinctrl/renesas/pinctrl-rzt2h.c

48

#define PM_MASK GENMASK(1, 0)

drivers/pinctrl/renesas/pinctrl-rzt2h.c

61

#define MUX_PIN_ID_MASK GENMASK(15, 0)

drivers/pinctrl/renesas/pinctrl-rzt2h.c

62

#define MUX_FUNC_MASK GENMASK(23, 16)

drivers/pinctrl/renesas/pinctrl-rzv2m.c

40

#define MUX_PIN_ID_MASK GENMASK(15, 0)

drivers/pinctrl/renesas/pinctrl-rzv2m.c

41

#define MUX_FUNC_MASK GENMASK(31, 16)

drivers/pinctrl/renesas/pinctrl-rzv2m.c

50

#define PIN_CFG_GRP_MASK GENMASK(2, 0)

drivers/pinctrl/renesas/pinctrl-rzv2m.c

64

#define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x))

drivers/pinctrl/renesas/pinctrl-rzv2m.c

65

#define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x))

drivers/pinctrl/renesas/pinctrl-rzv2m.c

66

#define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))

drivers/pinctrl/renesas/pinctrl-rzv2m.c

78

#define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x))

drivers/pinctrl/renesas/pinctrl-rzv2m.c

79

#define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x))

drivers/pinctrl/renesas/pinctrl-rzv2m.c

80

#define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))

drivers/pinctrl/renesas/pinctrl.c

492

val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);

drivers/pinctrl/renesas/pinctrl.c

527

val &= ~GENMASK(offset + size - 1, offset);

drivers/pinctrl/renesas/sh_pfc.h

33

#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)

drivers/pinctrl/sophgo/pinctrl-cv18xx.c

236

#define PIN_IO_DRIVE GENMASK(7, 5)

drivers/pinctrl/sophgo/pinctrl-cv18xx.c

237

#define PIN_IO_SCHMITT GENMASK(9, 8)

drivers/pinctrl/sophgo/pinctrl-cv18xx.c

36

return (value >> 16) & GENMASK(7, 0);

drivers/pinctrl/sophgo/pinctrl-cv18xx.c

41

return (value >> 24) & GENMASK(7, 0);

drivers/pinctrl/sophgo/pinctrl-cv18xx.h

44

#define CV1800_PIN_IO_TYPE GENMASK(2, 1)

drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c

32

#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0)

drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c

36

#define PIN_IO_PULL_UP_MASK GENMASK(3, 2)

drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c

38

#define PIN_IO_MUX GENMASK(5, 4)

drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c

39

#define PIN_IO_DRIVE GENMASK(9, 6)

drivers/pinctrl/spacemit/pinctrl-k1.c

238

return value & GENMASK(15, 0);

drivers/pinctrl/spacemit/pinctrl-k1.c

37

#define PAD_MUX GENMASK(2, 0)

drivers/pinctrl/spacemit/pinctrl-k1.c

42

#define PAD_SLEW_RATE GENMASK(12, 11)

drivers/pinctrl/spacemit/pinctrl-k1.c

44

#define PAD_SCHMITT_K1 GENMASK(9, 8)

drivers/pinctrl/spacemit/pinctrl-k1.c

45

#define PAD_DRIVE_K1 GENMASK(12, 10)

drivers/pinctrl/spacemit/pinctrl-k1.c

47

#define PAD_DRIVE_K3 GENMASK(12, 9)

drivers/pinctrl/spacemit/pinctrl-k1.h

26

#define K1_PIN_IO_TYPE GENMASK(2, 1)

drivers/pinctrl/sprd/pinctrl-sprd.c

47

#define SLEEP_MODE_MASK GENMASK(5, 0)

drivers/pinctrl/sprd/pinctrl-sprd.c

58

#define DRIVE_STRENGTH_MASK GENMASK(3, 0)

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

128

#define PAD_SLEW_RATE_MASK GENMASK(11, 9)

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

139

#define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0)

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

175

return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

180

return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

185

return (v >> 8) & GENMASK(7, 0);

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

469

dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

470

doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c

141

.dout_mask = GENMASK(3, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c

143

.doen_mask = GENMASK(2, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c

145

.gpi_mask = GENMASK(3, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c

410

.dout_mask = GENMASK(6, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c

412

.doen_mask = GENMASK(5, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c

414

.gpi_mask = GENMASK(6, 0),

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

42

#define JH7110_PADCFG_DS_MASK GENMASK(2, 1)

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

57

return (v & GENMASK(31, 24)) >> 24;

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

62

return (v & GENMASK(23, 16)) >> 16;

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

67

return (v & GENMASK(15, 10)) >> 10;

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

72

return (v & GENMASK(9, 8)) >> 8;

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

77

return v & GENMASK(7, 0);

drivers/pinctrl/stm32/pinctrl-stm32-hdp.c

37

#define HDP_MUX_MASK(n) (GENMASK(3, 0) << HDP_MUX_SHIFT(n))

drivers/pinctrl/stm32/pinctrl-stm32.c

1146

val &= ~GENMASK(offset * 2 + 1, offset * 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

1167

val &= GENMASK(offset * 2 + 1, offset * 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

1192

val &= ~GENMASK(offset * 2 + 1, offset * 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

1213

val &= GENMASK(offset * 2 + 1, offset * 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

1331

val &= ~GENMASK(delay_shift + 3, delay_shift);

drivers/pinctrl/stm32/pinctrl-stm32.c

1356

val &= GENMASK(delay_shift + 3, delay_shift);

drivers/pinctrl/stm32/pinctrl-stm32.c

73

#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)

drivers/pinctrl/stm32/pinctrl-stm32.c

77

#define STM32_GPIO_SEMCR_SEMCID_MASK GENMASK(5, 4)

drivers/pinctrl/stm32/pinctrl-stm32.c

82

#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)

drivers/pinctrl/stm32/pinctrl-stm32.c

957

val &= ~GENMASK(alt_shift + 3, alt_shift);

drivers/pinctrl/stm32/pinctrl-stm32.c

962

val &= ~GENMASK(pin * 2 + 1, pin * 2);

drivers/pinctrl/stm32/pinctrl-stm32.c

984

val &= GENMASK(alt_shift + 3, alt_shift);

drivers/pinctrl/stm32/pinctrl-stm32.c

988

val &= GENMASK(pin * 2 + 1, pin * 2);

drivers/pinctrl/sunplus/sppctl.c

202

offset &= GENMASK(31, 2);

drivers/pinctrl/sunplus/sppctl.c

237

mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT;

drivers/pinctrl/sunplus/sppctl.c

856

pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);

drivers/pinctrl/sunplus/sppctl.c

875

pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);

drivers/pinctrl/sunplus/sppctl.c

876

pin_type = FIELD_GET(GENMASK(23, 16), dt_pin);

drivers/pinctrl/sunplus/sppctl.c

877

pin_func = FIELD_GET(GENMASK(15, 8), dt_pin);

drivers/pinctrl/sunplus/sppctl.c

888

*configs = FIELD_GET(GENMASK(7, 0), dt_pin);

drivers/pinctrl/sunplus/sppctl.h

28

#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16)

drivers/pinctrl/sunplus/sppctl.h

29

#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

85

#define IO_BIAS_MASK GENMASK(3, 0)

drivers/pinctrl/sunxi/pinctrl-sunxi.h

92

#define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0)

drivers/pinctrl/visconti/pinctrl-common.c

21

#define DSEL_MASK GENMASK(3, 0)

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

164

VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

165

VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

166

VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

167

VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

168

VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

169

VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

170

VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

171

VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

172

VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

173

VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

174

VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

175

VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

176

VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

177

VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

178

VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

179

VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

180

VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

181

VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

182

VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

183

VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

184

VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

185

VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

186

VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

187

VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

188

VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

189

VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

190

VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

191

VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

192

VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

193

VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

194

VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

195

VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

196

VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

197

VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

198

VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

199

VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

200

VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

201

VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

202

VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

203

VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

204

VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

205

VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

206

VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

207

VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

208

VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

209

VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

210

VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

281

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

282

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

283

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

284

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

285

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

286

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

287

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

288

tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

289

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

290

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

291

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

292

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

293

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

294

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

295

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

296

tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

297

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

298

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

299

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

300

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

301

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

302

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

303

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

304

tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

305

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

306

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

307

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

308

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

309

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

310

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

311

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)),

drivers/pinctrl/visconti/pinctrl-tmpv7700.c

312

tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)),

drivers/platform/cznic/turris-omnia-mcu-base.c

296

mcu->features &= GENMASK(15, 0);

drivers/platform/mellanox/mlx-platform.c

258

#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4)

drivers/platform/mellanox/mlx-platform.c

260

#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)

drivers/platform/mellanox/mlx-platform.c

261

#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)

drivers/platform/mellanox/mlx-platform.c

262

#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

263

#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

264

#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0)

drivers/platform/mellanox/mlx-platform.c

265

#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0)

drivers/platform/mellanox/mlx-platform.c

266

#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

267

#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)

drivers/platform/mellanox/mlx-platform.c

268

#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

269

#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0)

drivers/platform/mellanox/mlx-platform.c

270

#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0)

drivers/platform/mellanox/mlx-platform.c

271

#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)

drivers/platform/mellanox/mlx-platform.c

272

#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

273

#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)

drivers/platform/mellanox/mlx-platform.c

274

#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)

drivers/platform/mellanox/mlx-platform.c

275

#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)

drivers/platform/mellanox/mlx-platform.c

276

#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0)

drivers/platform/mellanox/mlx-platform.c

277

#define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1)

drivers/platform/mellanox/mlx-platform.c

278

#define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0)

drivers/platform/mellanox/mlx-platform.c

290

#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)

drivers/platform/mellanox/mlx-platform.c

300

#define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)

drivers/platform/mellanox/mlx-platform.c

303

#define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0)

drivers/platform/mellanox/mlx-platform.c

306

#define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1)

drivers/platform/mellanox/mlx-platform.c

349

#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)

drivers/platform/mellanox/mlx-platform.c

350

#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))

drivers/platform/mellanox/mlx-platform.c

352

#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)

drivers/platform/mellanox/mlx-platform.c

354

#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)

drivers/platform/mellanox/mlx-platform.c

355

#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))

drivers/platform/mellanox/mlx-platform.c

356

#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))

drivers/platform/mellanox/mlx-platform.c

357

#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))

drivers/platform/mellanox/mlx-platform.c

3942

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

3948

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

3954

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

3961

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

3968

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

3974

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

3980

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

3986

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

3992

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

3998

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4004

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4010

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4016

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4022

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4028

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4034

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4040

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4046

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4052

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4074

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4080

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4086

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4093

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4100

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4106

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4112

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4118

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4124

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4130

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4136

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4142

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4148

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4154

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4160

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4166

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4172

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4178

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4184

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4206

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4212

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4218

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4224

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4230

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4236

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4243

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4250

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4257

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4264

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlx-platform.c

4271

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4277

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4283

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4289

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4295

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4301

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4307

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4313

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4319

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4325

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4332

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4338

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4344

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4351

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4358

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4364

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4370

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4376

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4382

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4388

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4394

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4400

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4406

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4412

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4418

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4424

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4430

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4436

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4442

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4448

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4454

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4460

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4466

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4472

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4478

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4484

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4490

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4496

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4502

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4515

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4521

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4527

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4533

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4539

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4559

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4565

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4571

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4577

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4583

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4596

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4603

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

4609

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4615

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4621

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

4627

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

4633

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

4639

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

4645

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

4651

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

4657

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

4663

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4670

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4676

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4682

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4688

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4703

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

4709

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drivers/platform/mellanox/mlx-platform.c

4715

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drivers/platform/mellanox/mlx-platform.c

4721

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drivers/platform/mellanox/mlx-platform.c

4727

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drivers/platform/mellanox/mlx-platform.c

4734

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drivers/platform/mellanox/mlx-platform.c

4741

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drivers/platform/mellanox/mlx-platform.c

4748

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drivers/platform/mellanox/mlx-platform.c

4755

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drivers/platform/mellanox/mlx-platform.c

4761

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drivers/platform/mellanox/mlx-platform.c

4767

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drivers/platform/mellanox/mlx-platform.c

4773

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drivers/platform/mellanox/mlx-platform.c

4779

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drivers/platform/mellanox/mlx-platform.c

4785

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drivers/platform/mellanox/mlx-platform.c

4791

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drivers/platform/mellanox/mlx-platform.c

4797

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drivers/platform/mellanox/mlx-platform.c

4803

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drivers/platform/mellanox/mlx-platform.c

4809

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drivers/platform/mellanox/mlx-platform.c

4815

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drivers/platform/mellanox/mlx-platform.c

4821

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drivers/platform/mellanox/mlx-platform.c

4827

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drivers/platform/mellanox/mlx-platform.c

4833

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drivers/platform/mellanox/mlx-platform.c

4839

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drivers/platform/mellanox/mlx-platform.c

4845

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drivers/platform/mellanox/mlx-platform.c

4851

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drivers/platform/mellanox/mlx-platform.c

4857

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drivers/platform/mellanox/mlx-platform.c

4863

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drivers/platform/mellanox/mlx-platform.c

4869

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drivers/platform/mellanox/mlx-platform.c

4875

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drivers/platform/mellanox/mlx-platform.c

4881

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drivers/platform/mellanox/mlx-platform.c

4887

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drivers/platform/mellanox/mlx-platform.c

4893

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drivers/platform/mellanox/mlx-platform.c

4899

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drivers/platform/mellanox/mlx-platform.c

4905

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drivers/platform/mellanox/mlx-platform.c

4911

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drivers/platform/mellanox/mlx-platform.c

4924

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drivers/platform/mellanox/mlx-platform.c

4930

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drivers/platform/mellanox/mlx-platform.c

4936

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drivers/platform/mellanox/mlx-platform.c

4942

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drivers/platform/mellanox/mlx-platform.c

4948

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drivers/platform/mellanox/mlx-platform.c

4961

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drivers/platform/mellanox/mlx-platform.c

4967

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drivers/platform/mellanox/mlx-platform.c

4973

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drivers/platform/mellanox/mlx-platform.c

4979

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drivers/platform/mellanox/mlx-platform.c

4985

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drivers/platform/mellanox/mlx-platform.c

4998

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drivers/platform/mellanox/mlx-platform.c

5005

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drivers/platform/mellanox/mlx-platform.c

5011

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drivers/platform/mellanox/mlx-platform.c

5017

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drivers/platform/mellanox/mlx-platform.c

5023

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drivers/platform/mellanox/mlx-platform.c

5029

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drivers/platform/mellanox/mlx-platform.c

5035

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drivers/platform/mellanox/mlx-platform.c

5041

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drivers/platform/mellanox/mlx-platform.c

5056

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drivers/platform/mellanox/mlx-platform.c

5062

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drivers/platform/mellanox/mlx-platform.c

5068

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drivers/platform/mellanox/mlx-platform.c

5074

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drivers/platform/mellanox/mlx-platform.c

5080

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drivers/platform/mellanox/mlx-platform.c

5087

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drivers/platform/mellanox/mlx-platform.c

5094

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drivers/platform/mellanox/mlx-platform.c

5101

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drivers/platform/mellanox/mlx-platform.c

5108

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drivers/platform/mellanox/mlx-platform.c

5114

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drivers/platform/mellanox/mlx-platform.c

5120

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drivers/platform/mellanox/mlx-platform.c

5126

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drivers/platform/mellanox/mlx-platform.c

5132

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drivers/platform/mellanox/mlx-platform.c

5138

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drivers/platform/mellanox/mlx-platform.c

5144

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drivers/platform/mellanox/mlx-platform.c

5150

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drivers/platform/mellanox/mlx-platform.c

5156

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drivers/platform/mellanox/mlx-platform.c

5162

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drivers/platform/mellanox/mlx-platform.c

5168

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drivers/platform/mellanox/mlx-platform.c

5174

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drivers/platform/mellanox/mlx-platform.c

5180

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drivers/platform/mellanox/mlx-platform.c

5186

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drivers/platform/mellanox/mlx-platform.c

5192

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drivers/platform/mellanox/mlx-platform.c

5198

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drivers/platform/mellanox/mlx-platform.c

5204

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drivers/platform/mellanox/mlx-platform.c

5210

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drivers/platform/mellanox/mlx-platform.c

5216

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drivers/platform/mellanox/mlx-platform.c

5222

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drivers/platform/mellanox/mlx-platform.c

5228

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drivers/platform/mellanox/mlx-platform.c

5234

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drivers/platform/mellanox/mlx-platform.c

5240

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drivers/platform/mellanox/mlx-platform.c

5246

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drivers/platform/mellanox/mlx-platform.c

5252

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drivers/platform/mellanox/mlx-platform.c

5258

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drivers/platform/mellanox/mlx-platform.c

5264

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drivers/platform/mellanox/mlx-platform.c

5270

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drivers/platform/mellanox/mlx-platform.c

5276

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drivers/platform/mellanox/mlx-platform.c

5282

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drivers/platform/mellanox/mlx-platform.c

5288

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drivers/platform/mellanox/mlx-platform.c

5294

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drivers/platform/mellanox/mlx-platform.c

5300

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drivers/platform/mellanox/mlx-platform.c

5313

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drivers/platform/mellanox/mlx-platform.c

5319

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drivers/platform/mellanox/mlx-platform.c

5325

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drivers/platform/mellanox/mlx-platform.c

5331

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drivers/platform/mellanox/mlx-platform.c

5337

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drivers/platform/mellanox/mlx-platform.c

5343

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drivers/platform/mellanox/mlx-platform.c

5349

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drivers/platform/mellanox/mlx-platform.c

5355

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drivers/platform/mellanox/mlx-platform.c

5361

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drivers/platform/mellanox/mlx-platform.c

5367

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drivers/platform/mellanox/mlx-platform.c

5373

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drivers/platform/mellanox/mlx-platform.c

5379

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drivers/platform/mellanox/mlx-platform.c

5385

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drivers/platform/mellanox/mlx-platform.c

5391

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drivers/platform/mellanox/mlx-platform.c

5397

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drivers/platform/mellanox/mlx-platform.c

5403

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drivers/platform/mellanox/mlx-platform.c

5409

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drivers/platform/mellanox/mlx-platform.c

5415

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drivers/platform/mellanox/mlx-platform.c

5421

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drivers/platform/mellanox/mlx-platform.c

5427

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drivers/platform/mellanox/mlx-platform.c

5434

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drivers/platform/mellanox/mlx-platform.c

5440

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drivers/platform/mellanox/mlx-platform.c

5453

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drivers/platform/mellanox/mlx-platform.c

5459

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drivers/platform/mellanox/mlx-platform.c

5465

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drivers/platform/mellanox/mlx-platform.c

5471

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drivers/platform/mellanox/mlx-platform.c

5477

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drivers/platform/mellanox/mlx-platform.c

5483

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drivers/platform/mellanox/mlx-platform.c

5489

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drivers/platform/mellanox/mlx-platform.c

5495

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drivers/platform/mellanox/mlx-platform.c

5501

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drivers/platform/mellanox/mlx-platform.c

5507

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drivers/platform/mellanox/mlx-platform.c

5513

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drivers/platform/mellanox/mlx-platform.c

5519

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drivers/platform/mellanox/mlx-platform.c

5525

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drivers/platform/mellanox/mlx-platform.c

5540

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drivers/platform/mellanox/mlx-platform.c

5546

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drivers/platform/mellanox/mlx-platform.c

5553

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drivers/platform/mellanox/mlx-platform.c

5559

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drivers/platform/mellanox/mlx-platform.c

5565

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drivers/platform/mellanox/mlx-platform.c

5571

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drivers/platform/mellanox/mlx-platform.c

5577

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drivers/platform/mellanox/mlx-platform.c

5583

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drivers/platform/mellanox/mlx-platform.c

5589

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drivers/platform/mellanox/mlx-platform.c

5595

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drivers/platform/mellanox/mlx-platform.c

5601

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drivers/platform/mellanox/mlx-platform.c

5607

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drivers/platform/mellanox/mlx-platform.c

5613

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drivers/platform/mellanox/mlx-platform.c

5619

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drivers/platform/mellanox/mlx-platform.c

5625

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drivers/platform/mellanox/mlx-platform.c

5631

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drivers/platform/mellanox/mlx-platform.c

5637

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drivers/platform/mellanox/mlx-platform.c

5643

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drivers/platform/mellanox/mlx-platform.c

5649

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drivers/platform/mellanox/mlx-platform.c

5655

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drivers/platform/mellanox/mlx-platform.c

5661

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drivers/platform/mellanox/mlx-platform.c

5667

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drivers/platform/mellanox/mlx-platform.c

5673

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drivers/platform/mellanox/mlx-platform.c

5679

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drivers/platform/mellanox/mlx-platform.c

5685

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drivers/platform/mellanox/mlx-platform.c

5698

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drivers/platform/mellanox/mlx-platform.c

5704

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drivers/platform/mellanox/mlx-platform.c

5710

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drivers/platform/mellanox/mlx-platform.c

5716

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drivers/platform/mellanox/mlx-platform.c

5722

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drivers/platform/mellanox/mlx-platform.c

5728

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drivers/platform/mellanox/mlx-platform.c

5734

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drivers/platform/mellanox/mlx-platform.c

5749

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drivers/platform/mellanox/mlx-platform.c

5755

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drivers/platform/mellanox/mlx-platform.c

5761

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drivers/platform/mellanox/mlx-platform.c

5767

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drivers/platform/mellanox/mlx-platform.c

5774

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drivers/platform/mellanox/mlx-platform.c

5781

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drivers/platform/mellanox/mlx-platform.c

5788

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drivers/platform/mellanox/mlx-platform.c

5794

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drivers/platform/mellanox/mlx-platform.c

5800

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drivers/platform/mellanox/mlx-platform.c

5806

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drivers/platform/mellanox/mlx-platform.c

5812

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drivers/platform/mellanox/mlx-platform.c

5818

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drivers/platform/mellanox/mlx-platform.c

5824

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drivers/platform/mellanox/mlx-platform.c

5830

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drivers/platform/mellanox/mlx-platform.c

5836

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drivers/platform/mellanox/mlx-platform.c

5842

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drivers/platform/mellanox/mlx-platform.c

5848

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drivers/platform/mellanox/mlx-platform.c

5854

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drivers/platform/mellanox/mlx-platform.c

5860

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drivers/platform/mellanox/mlx-platform.c

5866

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drivers/platform/mellanox/mlx-platform.c

5872

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drivers/platform/mellanox/mlx-platform.c

5878

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drivers/platform/mellanox/mlx-platform.c

5884

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drivers/platform/mellanox/mlx-platform.c

5890

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drivers/platform/mellanox/mlx-platform.c

5896

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drivers/platform/mellanox/mlx-platform.c

5902

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drivers/platform/mellanox/mlx-platform.c

5908

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drivers/platform/mellanox/mlx-platform.c

5914

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drivers/platform/mellanox/mlx-platform.c

5920

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drivers/platform/mellanox/mlx-platform.c

5926

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drivers/platform/mellanox/mlx-platform.c

5932

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drivers/platform/mellanox/mlx-platform.c

5938

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drivers/platform/mellanox/mlx-platform.c

5944

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drivers/platform/mellanox/mlx-platform.c

5950

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drivers/platform/mellanox/mlx-platform.c

5956

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drivers/platform/mellanox/mlx-platform.c

5962

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drivers/platform/mellanox/mlx-platform.c

5968

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drivers/platform/mellanox/mlx-platform.c

5981

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drivers/platform/mellanox/mlx-platform.c

5994

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drivers/platform/mellanox/mlx-platform.c

6000

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drivers/platform/mellanox/mlx-platform.c

6006

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drivers/platform/mellanox/mlx-platform.c

6012

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drivers/platform/mellanox/mlx-platform.c

6018

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drivers/platform/mellanox/mlx-platform.c

6024

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drivers/platform/mellanox/mlx-platform.c

6030

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drivers/platform/mellanox/mlx-platform.c

6036

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drivers/platform/mellanox/mlx-platform.c

6042

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drivers/platform/mellanox/mlx-platform.c

6048

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drivers/platform/mellanox/mlx-platform.c

6054

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

6060

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drivers/platform/mellanox/mlx-platform.c

6066

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drivers/platform/mellanox/mlx-platform.c

6072

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drivers/platform/mellanox/mlx-platform.c

6085

.mask = GENMASK(1, 0),

drivers/platform/mellanox/mlx-platform.c

6092

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlx-platform.c

6098

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlx-platform.c

6104

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

6110

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

6116

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

6122

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

6128

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlx-platform.c

6134

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlx-platform.c

6140

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6153

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

6159

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

6165

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlx-platform.c

6171

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlx-platform.c

6177

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlx-platform.c

6183

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6190

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6196

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6202

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6208

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6239

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6248

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6256

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6264

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6272

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6280

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6288

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6296

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6304

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6312

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6320

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6328

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6336

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6343

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6368

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6376

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6384

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6392

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6400

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6408

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6416

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6424

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6432

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6440

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6448

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6456

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6464

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6472

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6480

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6488

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6496

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6504

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6512

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6520

.mask = GENMASK(7, 0),

drivers/platform/mellanox/mlx-platform.c

6563

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

6634

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlx-platform.c

6712

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlxbf-pmc.c

74

#define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0 GENMASK(5, 0)

drivers/platform/mellanox/mlxbf-pmc.c

75

#define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1 GENMASK(13, 8)

drivers/platform/mellanox/mlxbf-pmc.c

76

#define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2 GENMASK(21, 16)

drivers/platform/mellanox/mlxbf-pmc.c

77

#define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3 GENMASK(29, 24)

drivers/platform/mellanox/mlxbf-pmc.c

79

#define MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4 GENMASK(5, 0)

drivers/platform/mellanox/mlxbf-pmc.c

81

#define MLXBF_PMC_L3C_PERF_CNT_LOW_VAL GENMASK(31, 0)

drivers/platform/mellanox/mlxbf-pmc.c

82

#define MLXBF_PMC_L3C_PERF_CNT_HIGH_VAL GENMASK(24, 0)

drivers/platform/mellanox/mlxbf-pmc.c

86

#define MLXBF_PMC_CRSPACE_PERFSEL0 GENMASK(23, 16)

drivers/platform/mellanox/mlxbf-pmc.c

87

#define MLXBF_PMC_CRSPACE_PERFSEL1 GENMASK(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo.c

104

#define VRING_DROP_DESC_MAX_LEN GENMASK(15, 0)

drivers/platform/mellanox/mlxreg-dpu.c

102

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlxreg-dpu.c

109

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-dpu.c

115

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlxreg-dpu.c

121

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlxreg-dpu.c

127

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlxreg-dpu.c

133

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlxreg-dpu.c

139

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlxreg-dpu.c

145

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlxreg-dpu.c

151

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlxreg-dpu.c

157

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlxreg-dpu.c

163

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlxreg-dpu.c

169

.bit = GENMASK(3, 0),

drivers/platform/mellanox/mlxreg-dpu.c

182

.mask = GENMASK(3, 0),

drivers/platform/mellanox/mlxreg-dpu.c

188

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlxreg-dpu.c

78

#define MLXREG_DPU_VOLTREG_UPD_MASK GENMASK(5, 4)

drivers/platform/mellanox/mlxreg-dpu.c

96

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-hotplug.c

277

item->mask = GENMASK((regval & item->mask) - 1, 0);

drivers/platform/mellanox/mlxreg-lc.c

252

.mask = GENMASK(7, 4),

drivers/platform/mellanox/mlxreg-lc.c

257

.mask = GENMASK(7, 4),

drivers/platform/mellanox/mlxreg-lc.c

272

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-lc.c

278

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-lc.c

284

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlxreg-lc.c

291

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlxreg-lc.c

298

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-lc.c

304

.bit = GENMASK(7, 0),

drivers/platform/mellanox/mlxreg-lc.c

310

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlxreg-lc.c

316

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/mlxreg-lc.c

322

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlxreg-lc.c

328

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/mlxreg-lc.c

334

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlxreg-lc.c

340

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlxreg-lc.c

346

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/mlxreg-lc.c

352

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlxreg-lc.c

359

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/mlxreg-lc.c

366

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/mlxreg-lc.c

372

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/mlxreg-lc.c

379

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/mlxreg-lc.c

386

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/mlxreg-lc.c

393

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlxreg-lc.c

400

.bit = GENMASK(15, 0),

drivers/platform/mellanox/mlxreg-lc.c

726

regval = (regval & GENMASK(7, 0)) << 8 | (lsb & GENMASK(7, 0));

drivers/platform/mellanox/nvsw-sn2201.c

112

#define NVSW_SN2201_CPLD_ASIC_MASK GENMASK(3, 1)

drivers/platform/mellanox/nvsw-sn2201.c

113

#define NVSW_SN2201_CPLD_PSU_MASK GENMASK(1, 0)

drivers/platform/mellanox/nvsw-sn2201.c

114

#define NVSW_SN2201_CPLD_PWR_MASK GENMASK(1, 0)

drivers/platform/mellanox/nvsw-sn2201.c

115

#define NVSW_SN2201_CPLD_FAN_MASK GENMASK(3, 0)

drivers/platform/mellanox/nvsw-sn2201.c

705

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

710

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

715

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

720

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

725

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

730

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

735

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

740

.mask = GENMASK(3, 0),

drivers/platform/mellanox/nvsw-sn2201.c

745

.mask = GENMASK(3, 0),

drivers/platform/mellanox/nvsw-sn2201.c

750

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

755

.mask = GENMASK(7, 4),

drivers/platform/mellanox/nvsw-sn2201.c

760

.mask = GENMASK(3, 0),

drivers/platform/mellanox/nvsw-sn2201.c

765

.mask = GENMASK(3, 0),

drivers/platform/mellanox/nvsw-sn2201.c

779

.bit = GENMASK(7, 0),

drivers/platform/mellanox/nvsw-sn2201.c

785

.bit = GENMASK(7, 0),

drivers/platform/mellanox/nvsw-sn2201.c

791

.bit = GENMASK(15, 0),

drivers/platform/mellanox/nvsw-sn2201.c

798

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/nvsw-sn2201.c

804

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/nvsw-sn2201.c

810

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/nvsw-sn2201.c

816

.mask = GENMASK(4, 3),

drivers/platform/mellanox/nvsw-sn2201.c

823

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/nvsw-sn2201.c

829

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/nvsw-sn2201.c

835

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/nvsw-sn2201.c

841

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/nvsw-sn2201.c

847

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/nvsw-sn2201.c

853

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/nvsw-sn2201.c

859

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/nvsw-sn2201.c

865

.mask = GENMASK(7, 0) & ~BIT(3),

drivers/platform/mellanox/nvsw-sn2201.c

871

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/nvsw-sn2201.c

877

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/nvsw-sn2201.c

883

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/nvsw-sn2201.c

889

.mask = GENMASK(7, 0) & ~BIT(7),

drivers/platform/mellanox/nvsw-sn2201.c

895

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/nvsw-sn2201.c

901

.mask = GENMASK(7, 0) & ~BIT(2),

drivers/platform/mellanox/nvsw-sn2201.c

907

.mask = GENMASK(7, 0) & ~BIT(4),

drivers/platform/mellanox/nvsw-sn2201.c

913

.mask = GENMASK(7, 0) & ~BIT(5),

drivers/platform/mellanox/nvsw-sn2201.c

919

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mellanox/nvsw-sn2201.c

925

.mask = GENMASK(7, 0) & ~BIT(0),

drivers/platform/mellanox/nvsw-sn2201.c

931

.mask = GENMASK(7, 0) & ~BIT(1),

drivers/platform/mellanox/nvsw-sn2201.c

946

.mask = GENMASK(7, 1),

drivers/platform/mellanox/nvsw-sn2201.c

963

.mask = GENMASK(7, 1),

drivers/platform/mellanox/nvsw-sn2201.c

969

.mask = GENMASK(7, 0) & ~BIT(6),

drivers/platform/mips/ls2k-reset.c

27

writel(GENMASK(12, 10) | BIT(13), base + PM1_CNT);

drivers/platform/olpc/olpc-xo175-ec.c

196

#define EC_ALL_EVENTS GENMASK(15, 0)

drivers/platform/surface/surface3_power.c

150

#define MSHW0011_EV_2_5_MASK GENMASK(8, 0)

drivers/platform/x86/acer-wmi.c

85

#define ACER_GAMING_FAN_BEHAVIOR_SET_CPU_MODE_MASK GENMASK(17, 16)

drivers/platform/x86/acer-wmi.c

86

#define ACER_GAMING_FAN_BEHAVIOR_SET_GPU_MODE_MASK GENMASK(23, 22)

drivers/platform/x86/acer-wmi.c

87

#define ACER_GAMING_FAN_BEHAVIOR_GET_CPU_MODE_MASK GENMASK(9, 8)

drivers/platform/x86/acer-wmi.c

88

#define ACER_GAMING_FAN_BEHAVIOR_GET_GPU_MODE_MASK GENMASK(15, 14)

drivers/platform/x86/amd/hsmp/acpi.c

276

#define DDR_MAX_BW_MASK GENMASK(31, 20)

drivers/platform/x86/amd/hsmp/acpi.c

277

#define DDR_UTIL_BW_MASK GENMASK(19, 8)

drivers/platform/x86/amd/hsmp/acpi.c

278

#define DDR_UTIL_BW_PERC_MASK GENMASK(7, 0)

drivers/platform/x86/amd/hsmp/acpi.c

279

#define FW_VER_MAJOR_MASK GENMASK(23, 16)

drivers/platform/x86/amd/hsmp/acpi.c

280

#define FW_VER_MINOR_MASK GENMASK(15, 8)

drivers/platform/x86/amd/hsmp/acpi.c

281

#define FW_VER_DEBUG_MASK GENMASK(7, 0)

drivers/platform/x86/amd/hsmp/acpi.c

282

#define FMAX_MASK GENMASK(31, 16)

drivers/platform/x86/amd/hsmp/acpi.c

283

#define FMIN_MASK GENMASK(15, 0)

drivers/platform/x86/amd/hsmp/acpi.c

284

#define FREQ_LIMIT_MASK GENMASK(31, 16)

drivers/platform/x86/amd/hsmp/acpi.c

285

#define FREQ_SRC_IND_MASK GENMASK(15, 0)

drivers/platform/x86/amd/pmc/pmc.c

211

dev->smu_program = (val >> 24) & GENMASK(7, 0);

drivers/platform/x86/amd/pmc/pmc.c

212

dev->major = (val >> 16) & GENMASK(7, 0);

drivers/platform/x86/amd/pmc/pmc.c

213

dev->minor = (val >> 8) & GENMASK(7, 0);

drivers/platform/x86/amd/pmc/pmc.c

214

dev->rev = (val >> 0) & GENMASK(7, 0);

drivers/platform/x86/amd/pmc/pmc.h

36

#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)

drivers/platform/x86/amd/pmc/pmc.h

37

#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)

drivers/platform/x86/amd/pmf/core.c

300

low = phys_addr & GENMASK(31, 0);

drivers/platform/x86/amd/pmf/core.c

34

#define AMD_PMF_BASE_ADDR_LO_MASK GENMASK(15, 0)

drivers/platform/x86/amd/pmf/core.c

35

#define AMD_PMF_BASE_ADDR_HI_MASK GENMASK(31, 20)

drivers/platform/x86/amd/pmf/pmf.h

124

#define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7)

drivers/platform/x86/asus-armoury.c

41

#define ASUS_MINI_LED_MODE_MASK GENMASK(1, 0)

drivers/platform/x86/dell/alienware-wmi-wmax.c

50

#define AWCC_THERMAL_MODE_MASK GENMASK(3, 0)

drivers/platform/x86/dell/alienware-wmi-wmax.c

51

#define AWCC_THERMAL_TABLE_MASK GENMASK(7, 4)

drivers/platform/x86/dell/alienware-wmi-wmax.c

52

#define AWCC_RESOURCE_ID_MASK GENMASK(7, 0)

drivers/platform/x86/dell/dell-pc.c

109

#define DELL_ACC_GET_FIELD GENMASK(19, 16)

drivers/platform/x86/dell/dell-pc.c

110

#define DELL_ACC_SET_FIELD GENMASK(11, 8)

drivers/platform/x86/dell/dell-pc.c

111

#define DELL_THERMAL_SUPPORTED GENMASK(3, 0)

drivers/platform/x86/dell/dell-wmi-ddv.c

46

#define SBS_MANUFACTURE_YEAR_MASK GENMASK(15, 9)

drivers/platform/x86/dell/dell-wmi-ddv.c

47

#define SBS_MANUFACTURE_MONTH_MASK GENMASK(8, 5)

drivers/platform/x86/dell/dell-wmi-ddv.c

48

#define SBS_MANUFACTURE_DAY_MASK GENMASK(4, 0)

drivers/platform/x86/dell/dell-wmi-ddv.c

50

#define MA_FAILURE_MODE_MASK GENMASK(11, 8)

drivers/platform/x86/dell/dell-wmi-ddv.c

55

#define MA_PERMANENT_FAILURE_CODE_MASK GENMASK(13, 12)

drivers/platform/x86/dell/dell-wmi-ddv.c

61

#define MA_OVERHEAT_FAILURE_CODE_MASK GENMASK(15, 12)

drivers/platform/x86/dell/dell-wmi-ddv.c

66

#define MA_OVERCURRENT_FAILURE_CODE_MASK GENMASK(15, 12)

drivers/platform/x86/intel/int3472/discrete.c

31

#define INT3472_GPIO_DSM_TYPE GENMASK(7, 0)

drivers/platform/x86/intel/int3472/discrete.c

32

#define INT3472_GPIO_DSM_PIN GENMASK(15, 8)

drivers/platform/x86/intel/int3472/discrete.c

33

#define INT3472_GPIO_DSM_SENSOR_ON_VAL GENMASK(31, 24)

drivers/platform/x86/intel/pmc/core.c

1209

int level = lpm_pri & GENMASK(3, 0);

drivers/platform/x86/intel/pmc/core.c

741

ltr_ign = pmc->ltr_ign | GENMASK(pmc->map->ltr_ignore_max, 0);

drivers/platform/x86/intel/pmc/core.h

193

#define LTR_DECODED_VAL GENMASK(9, 0)

drivers/platform/x86/intel/pmc/core.h

194

#define LTR_DECODED_SCALE GENMASK(12, 10)

drivers/platform/x86/intel/pmc/core.h

21

#define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0)

drivers/platform/x86/intel/pmt/class.h

19

#define GET_BIR(v) ((v) & GENMASK(2, 0))

drivers/platform/x86/intel/pmt/class.h

20

#define GET_ADDRESS(v) ((v) & GENMASK(31, 3))

drivers/platform/x86/intel/pmt/crashlog.c

32

#define GET_ACCESS(v) ((v) & GENMASK(3, 0))

drivers/platform/x86/intel/pmt/crashlog.c

33

#define GET_TYPE(v) (((v) & GENMASK(7, 4)) >> 4)

drivers/platform/x86/intel/pmt/crashlog.c

34

#define GET_VERSION(v) (((v) & GENMASK(19, 16)) >> 16)

drivers/platform/x86/intel/pmt/crashlog.c

54

#define TYPE1_VER0_TRIGGER_MASK GENMASK(31, 28)

drivers/platform/x86/intel/pmt/discovery.c

38

#define DT_TBIR GENMASK(2, 0)

drivers/platform/x86/intel/pmt/telemetry.c

33

#define TELEM_ACCESS(v) ((v) & GENMASK(3, 0))

drivers/platform/x86/intel/pmt/telemetry.c

34

#define TELEM_TYPE(v) (((v) & GENMASK(7, 4)) >> 4)

drivers/platform/x86/intel/pmt/telemetry.c

36

#define TELEM_SIZE(v) (((v) & GENMASK(27, 12)) >> 10)

drivers/platform/x86/intel/punit_ipc.c

27

#define CMD_ERRCODE_MASK GENMASK(7, 0)

drivers/platform/x86/intel/sdsi.c

47

#define SDSI_SOCKET_ID GENMASK(3, 0)

drivers/platform/x86/intel/sdsi.c

66

#define CTRL_OWNER GENMASK(5, 4)

drivers/platform/x86/intel/sdsi.c

71

#define CTRL_STATUS GENMASK(15, 8)

drivers/platform/x86/intel/sdsi.c

72

#define CTRL_PACKET_SIZE GENMASK(31, 16)

drivers/platform/x86/intel/sdsi.c

73

#define CTRL_MSG_SIZE GENMASK(63, 48)

drivers/platform/x86/intel/sdsi.c

76

#define DT_ACCESS_TYPE GENMASK(3, 0)

drivers/platform/x86/intel/sdsi.c

77

#define DT_SIZE GENMASK(27, 12)

drivers/platform/x86/intel/sdsi.c

78

#define DT_TBIR GENMASK(2, 0)

drivers/platform/x86/intel/sdsi.c

79

#define DT_OFFSET(v) ((v) & GENMASK(31, 3))

drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c

117

pcu_base &= GENMASK(10, 0);

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

776

clos_assoc.clos = val & GENMASK(SST_CLOS_ASSOC_BITS_PER_CPU - 1, 0);

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

805

_mask = GENMASK((start + width - 1), start);\

drivers/platform/x86/lenovo/ideapad-laptop.c

154

#define KBD_BL_COMMAND_TYPE GENMASK(7, 4)

drivers/platform/x86/lenovo/ideapad-laptop.c

156

#define KBD_BL_GET_BRIGHTNESS GENMASK(15, 1)

drivers/platform/x86/lenovo/ideapad-laptop.c

157

#define KBD_BL_SET_BRIGHTNESS GENMASK(19, 16)

drivers/platform/x86/lenovo/thinkpad_acpi.c

11094

#define PORT_STATUS GENMASK(7, 4)

drivers/platform/x86/lenovo/thinkpad_acpi.c

11095

#define LID_STATUS GENMASK(11, 8)

drivers/platform/x86/lenovo/thinkpad_acpi.c

11096

#define BASE_STATUS GENMASK(15, 12)

drivers/platform/x86/lenovo/thinkpad_acpi.c

11097

#define POS_STATUS GENMASK(3, 2)

drivers/platform/x86/lenovo/thinkpad_acpi.c

11098

#define PANEL_STATUS GENMASK(1, 0)

drivers/platform/x86/lenovo/wmi-capdata.h

15

#define LWMI_ATTR_DEV_ID_MASK GENMASK(31, 24)

drivers/platform/x86/lenovo/wmi-capdata.h

16

#define LWMI_ATTR_FEAT_ID_MASK GENMASK(23, 16)

drivers/platform/x86/lenovo/wmi-capdata.h

17

#define LWMI_ATTR_MODE_ID_MASK GENMASK(15, 8)

drivers/platform/x86/lenovo/wmi-capdata.h

18

#define LWMI_ATTR_TYPE_ID_MASK GENMASK(7, 0)

drivers/platform/x86/lg-laptop.c

81

#define FAN_MODE_LOWER GENMASK(1, 0)

drivers/platform/x86/lg-laptop.c

82

#define FAN_MODE_UPPER GENMASK(5, 4)

drivers/platform/x86/msi-wmi-platform.c

40

#define MSI_PLATFORM_EC_MINOR_MASK GENMASK(3, 0)

drivers/platform/x86/msi-wmi-platform.c

41

#define MSI_PLATFORM_EC_MAJOR_MASK GENMASK(5, 4)

drivers/platform/x86/panasonic-laptop.c

849

key = result & GENMASK(6, 0);

drivers/platform/x86/portwell-ec.c

104

.in_mask = GENMASK(4, 0),

drivers/platform/x86/portwell-ec.c

98

.temp_mask = GENMASK(PORTWELL_HWMON_TEMP_NUM - 1, 0),

drivers/platform/x86/portwell-ec.c

99

.in_mask = GENMASK(PORTWELL_HWMON_VOLT_NUM - 1, 0),

drivers/platform/x86/serial-multi-instantiate.c

20

#define IRQ_RESOURCE_TYPE GENMASK(1, 0)

drivers/platform/x86/silicom-platform.c

38

#define MEC_PORT_CHANNEL_MASK GENMASK(2, 0)

drivers/platform/x86/silicom-platform.c

39

#define MEC_PORT_DWORD_OFFSET GENMASK(31, 3)

drivers/platform/x86/silicom-platform.c

40

#define MEC_DATA_OFFSET_MASK GENMASK(1, 0)

drivers/platform/x86/silicom-platform.c

41

#define MEC_PORT_OFFSET_MASK GENMASK(7, 2)

drivers/platform/x86/silicom-platform.c

43

#define MEC_TEMP_LOC GENMASK(31, 16)

drivers/platform/x86/silicom-platform.c

44

#define MEC_VERSION_LOC GENMASK(15, 8)

drivers/platform/x86/silicom-platform.c

45

#define MEC_VERSION_MAJOR GENMASK(15, 14)

drivers/platform/x86/silicom-platform.c

46

#define MEC_VERSION_MINOR GENMASK(13, 8)

drivers/platform/x86/uniwill/uniwill-acpi.c

151

#define FAN_LEVEL_MASK GENMASK(2, 0)

drivers/platform/x86/uniwill/uniwill-acpi.c

228

#define KBD_TURBO_LEVEL_MASK GENMASK(3, 2)

drivers/platform/x86/uniwill/uniwill-acpi.c

230

#define KBD_BRIGHTNESS GENMASK(7, 5)

drivers/platform/x86/uniwill/uniwill-acpi.c

245

#define POWER_LED_MASK GENMASK(1, 0)

drivers/platform/x86/uniwill/uniwill-acpi.c

258

#define CHARGE_CTRL_MASK GENMASK(6, 0)

drivers/pmdomain/amlogic/meson-ee-pwrc.c

130

{ __reg, GENMASK(1, 0) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

131

{ __reg, GENMASK(3, 2) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

132

{ __reg, GENMASK(5, 4) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

133

{ __reg, GENMASK(7, 6) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

134

{ __reg, GENMASK(9, 8) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

135

{ __reg, GENMASK(11, 10) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

136

{ __reg, GENMASK(13, 12) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

137

{ __reg, GENMASK(15, 14) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

138

{ __reg, GENMASK(17, 16) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

139

{ __reg, GENMASK(19, 18) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

140

{ __reg, GENMASK(21, 20) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

141

{ __reg, GENMASK(23, 22) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

142

{ __reg, GENMASK(25, 24) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

143

{ __reg, GENMASK(27, 26) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

144

{ __reg, GENMASK(29, 28) }, \

drivers/pmdomain/amlogic/meson-ee-pwrc.c

145

{ __reg, GENMASK(31, 30) }

drivers/pmdomain/amlogic/meson-ee-pwrc.c

176

{ HHI_MEM_PD_REG0, GENMASK(3, 2) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

180

{ HHI_MEM_PD_REG0, GENMASK(1, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

194

{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

195

{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

196

{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

197

{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

207

{ HHI_MEM_PD_REG0, GENMASK(31, 30) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

211

{ HHI_MEM_PD_REG0, GENMASK(29, 26) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

215

{ HHI_MEM_PD_REG0, GENMASK(25, 18) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

219

{ HHI_MEM_PD_REG0, GENMASK(5, 4) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

223

{ HHI_MEM_PD_REG0, GENMASK(5, 4) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

224

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

225

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

226

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

227

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

228

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

229

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

230

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

231

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

232

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

233

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

234

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

235

{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

239

{ G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

240

{ G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

244

{ G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) },

drivers/pmdomain/amlogic/meson-ee-pwrc.c

245

{ G12A_HHI_ISP_MEM_PD_REG1, GENMASK(31, 0) },

drivers/pmdomain/apple/pmgr-pwrstate.c

22

#define APPLE_PMGR_PS_AUTO GENMASK(27, 24)

drivers/pmdomain/apple/pmgr-pwrstate.c

23

#define APPLE_PMGR_PS_MIN GENMASK(19, 16)

drivers/pmdomain/apple/pmgr-pwrstate.c

28

#define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4)

drivers/pmdomain/apple/pmgr-pwrstate.c

29

#define APPLE_PMGR_PS_TARGET GENMASK(3, 0)

drivers/pmdomain/imx/gpcv2.c

168

#define IMX8MM_GPU_HSK_PWRDNACKN GENMASK(29, 27)

drivers/pmdomain/imx/gpcv2.c

172

#define IMX8MM_GPU_HSK_PWRDNREQN GENMASK(11, 9)

drivers/pmdomain/imx/imx8m-blk-ctrl.c

665

#define LCDIF_1_RD_HURRY GENMASK(15, 13)

drivers/pmdomain/imx/imx8m-blk-ctrl.c

666

#define LCDIF_0_RD_HURRY GENMASK(12, 10)

drivers/pmdomain/imx/imx8m-blk-ctrl.c

669

#define ISI_V_WR_HURRY GENMASK(28, 26)

drivers/pmdomain/imx/imx8m-blk-ctrl.c

670

#define ISI_U_WR_HURRY GENMASK(25, 23)

drivers/pmdomain/imx/imx8m-blk-ctrl.c

671

#define ISI_Y_WR_HURRY GENMASK(22, 20)

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

29

#define P_PLL_MASK GENMASK(5, 0)

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

30

#define M_PLL_MASK GENMASK(15, 6)

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

307

#define HDMI_LCDIF_NOC_HURRY_MASK GENMASK(14, 12)

drivers/pmdomain/imx/imx8mp-blk-ctrl.c

31

#define S_PLL_MASK GENMASK(18, 16)

drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c

13

#define AIROHA_AVS_OP_MASK GENMASK(1, 0)

drivers/pmdomain/mediatek/mt6735-pm-domains.h

20

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

32

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

44

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

45

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

56

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

57

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

68

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

69

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

77

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

78

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

86

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6735-pm-domains.h

87

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

100

.sram_pdn_ack_bits = GENMASK(21, 16),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

23

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

24

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

32

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

33

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

41

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

42

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

50

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

51

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

63

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

64

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

72

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

73

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

81

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

90

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

91

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt6795-pm-domains.h

99

.sram_pdn_bits = GENMASK(13, 8),

drivers/pmdomain/mediatek/mt6893-pm-domains.h

24

#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21, 19)

drivers/pmdomain/mediatek/mt6893-pm-domains.h

25

#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6, 5)

drivers/pmdomain/mediatek/mt6893-pm-domains.h

26

#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22, 21)

drivers/pmdomain/mediatek/mt6893-pm-domains.h

28

#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19, 17)

drivers/pmdomain/mediatek/mt6893-pm-domains.h

37

#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30, 28)

drivers/pmdomain/mediatek/mt6893-pm-domains.h

38

#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31, 29)

drivers/pmdomain/mediatek/mt8167-pm-domains.h

26

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

27

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

40

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

41

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

50

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

51

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

73

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

74

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

82

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

83

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8167-pm-domains.h

91

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

101

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

102

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

110

.sram_pdn_bits = GENMASK(13, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

111

.sram_pdn_ack_bits = GENMASK(21, 16),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

23

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

24

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

32

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

33

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

41

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

42

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

50

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

51

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

63

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

64

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

72

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

73

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

81

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

82

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8173-pm-domains.h

91

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

107

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

108

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

133

.sram_pdn_bits = GENMASK(9, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

134

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

164

.sram_pdn_bits = GENMASK(9, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

165

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

190

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

191

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

206

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

207

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

222

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

223

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

23

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

24

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

253

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

254

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

275

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

276

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

58

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

59

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

68

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

69

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

77

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

78

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

86

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8183-pm-domains.h

87

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

108

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

109

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

117

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

118

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

126

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

127

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

135

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

136

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

144

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

145

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

153

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

154

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

189

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

190

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

210

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

211

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

23

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

231

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

232

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

24

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

252

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

253

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

273

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

274

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

294

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

295

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

315

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

316

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

324

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

325

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

360

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

361

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

369

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

370

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

378

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

379

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

66

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

67

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

76

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8192-pm-domains.h

77

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

103

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

104

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

120

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

121

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

137

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

138

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

147

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

148

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

189

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

190

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

199

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

200

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

209

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

210

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

219

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

220

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

229

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

230

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

239

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

240

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

27

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

275

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

276

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

28

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

301

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

302

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

327

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

328

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

353

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

354

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

370

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

371

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

387

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

388

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

397

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

398

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

423

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

424

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

455

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

456

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

477

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

478

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

48

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

49

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

499

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

500

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

526

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

527

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

548

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

549

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

570

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

571

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

580

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

581

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

602

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

603

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

639

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

640

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

649

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

650

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

659

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

660

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

93

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8195-pm-domains.h

94

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8196-pm-domains.h

67

.ext_buck_iso_mask = GENMASK(1, 0),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

126

.sram_pdn_bits = GENMASK(9, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

127

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

141

.sram_pdn_bits = GENMASK(9, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

142

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

155

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

156

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

167

.sram_pdn_bits = GENMASK(14, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

168

.sram_pdn_ack_bits = GENMASK(21, 15),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

182

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

183

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

47

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

48

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

79

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

80

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

91

.sram_pdn_bits = GENMASK(12, 8),

drivers/pmdomain/mediatek/mt8365-pm-domains.h

92

.sram_pdn_ack_bits = GENMASK(17, 13),

drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c

32

#define PWR_ACK_M GENMASK(31, 30)

drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c

38

#define GHPM_STATE_M GENMASK(7, 0)

drivers/pmdomain/mediatek/mtk-scpsys.c

569

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

578

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

579

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

587

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

588

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

596

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

597

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

605

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

613

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

614

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

622

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

623

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

644

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

645

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

653

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

654

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

662

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

663

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

671

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

672

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

680

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

681

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

689

.sram_pdn_bits = GENMASK(10, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

690

.sram_pdn_ack_bits = GENMASK(14, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

698

.sram_pdn_bits = GENMASK(10, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

699

.sram_pdn_ack_bits = GENMASK(14, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

707

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

708

.sram_pdn_ack_bits = GENMASK(16, 16),

drivers/pmdomain/mediatek/mtk-scpsys.c

717

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

718

.sram_pdn_ack_bits = GENMASK(16, 16),

drivers/pmdomain/mediatek/mtk-scpsys.c

726

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

727

.sram_pdn_ack_bits = GENMASK(16, 16),

drivers/pmdomain/mediatek/mtk-scpsys.c

735

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

736

.sram_pdn_ack_bits = GENMASK(16, 16),

drivers/pmdomain/mediatek/mtk-scpsys.c

760

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

761

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

768

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

769

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

776

.sram_pdn_bits = GENMASK(9, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

777

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

784

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

785

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

793

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

794

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

809

.sram_pdn_bits = GENMASK(8, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

810

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

834

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

835

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

844

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

845

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

854

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

855

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

890

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

891

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

899

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

900

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

922

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

923

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

930

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

931

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

938

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

939

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

946

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

947

.sram_pdn_ack_bits = GENMASK(12, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

956

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

957

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

964

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

965

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

972

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

973

.sram_pdn_ack_bits = GENMASK(15, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

981

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

989

.sram_pdn_bits = GENMASK(11, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

990

.sram_pdn_ack_bits = GENMASK(13, 12),

drivers/pmdomain/mediatek/mtk-scpsys.c

997

.sram_pdn_bits = GENMASK(13, 8),

drivers/pmdomain/mediatek/mtk-scpsys.c

998

.sram_pdn_ack_bits = GENMASK(21, 16),

drivers/pmdomain/qcom/cpr.c

121

#define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)

drivers/pmdomain/qcom/cpr.c

40

#define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)

drivers/pmdomain/qcom/cpr.c

42

#define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)

drivers/pmdomain/qcom/cpr.c

48

#define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)

drivers/pmdomain/qcom/cpr.c

50

#define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)

drivers/pmdomain/qcom/cpr.c

52

#define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)

drivers/pmdomain/qcom/cpr.c

57

#define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)

drivers/pmdomain/qcom/cpr.c

60

#define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)

drivers/pmdomain/qcom/cpr.c

69

#define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)

drivers/pmdomain/qcom/cpr.c

70

#define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)

drivers/pmdomain/qcom/cpr.c

81

#define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)

drivers/pmdomain/qcom/cpr.c

83

#define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)

drivers/pmdomain/qcom/cpr.c

97

#define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)

drivers/pmdomain/qcom/cpr.c

99

#define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)

drivers/pmdomain/renesas/rcar-gen4-sysc.c

50

#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */

drivers/pmdomain/starfive/jh71xx-pmu.c

39

#define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2)

drivers/pmdomain/starfive/jh71xx-pmu.c

40

#define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4)

drivers/pmdomain/starfive/jh71xx-pmu.c

41

#define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6)

drivers/pmdomain/starfive/jh71xx-pmu.c

42

#define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0)

drivers/pmdomain/sunxi/sun20i-ppu.c

28

#define PD_STATUS_STATE GENMASK(17, 16)

drivers/pmdomain/sunxi/sun55i-pck600.c

38

#define PPU_PWR_STATUS GENMASK(3, 0)

drivers/power/reset/at91-poweroff.c

28

#define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */

drivers/power/reset/at91-reset.c

36

#define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */

drivers/power/reset/at91-reset.c

44

#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */

drivers/power/reset/at91-sama5d2_shdwc.c

40

#define AT91_SHDW_WKUPDBC_MASK GENMASK(26, 24)

drivers/power/reset/at91-sama5d2_shdwc.c

46

#define AT91_SHDW_WKUPIS_MASK GENMASK(31, 16)

drivers/power/reset/at91-sama5d2_shdwc.c

51

#define AT91_SHDW_WKUPEN_MASK GENMASK(15, 0)

drivers/power/reset/at91-sama5d2_shdwc.c

54

#define AT91_SHDW_WKUPT_MASK GENMASK(31, 16)

drivers/power/reset/linkstation-poweroff.c

31

#define LEDMASK GENMASK(11,8)

drivers/power/reset/ocelot-reset.c

37

#define IF_SI_OWNER_MASK GENMASK(1, 0)

drivers/power/reset/qcom-pon.c

39

GENMASK(7, pon->reason_shift),

drivers/power/supply/adp5061.c

39

#define ADP5061_VINX_SET_ILIM_MSK GENMASK(3, 0)

drivers/power/supply/adp5061.c

43

#define ADP5061_TERM_SET_VTRM_MSK GENMASK(7, 2)

drivers/power/supply/adp5061.c

45

#define ADP5061_TERM_SET_CHG_VLIM_MSK GENMASK(1, 0)

drivers/power/supply/adp5061.c

49

#define ADP5061_CHG_CURR_ICHG_MSK GENMASK(6, 2)

drivers/power/supply/adp5061.c

51

#define ADP5061_CHG_CURR_ITRK_DEAD_MSK GENMASK(1, 0)

drivers/power/supply/adp5061.c

57

#define ADP5061_VOLTAGE_TH_VRCH_MSK GENMASK(6, 5)

drivers/power/supply/adp5061.c

59

#define ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK GENMASK(4, 3)

drivers/power/supply/adp5061.c

61

#define ADP5061_VOLTAGE_TH_VWEAK_MSK GENMASK(2, 0)

drivers/power/supply/adp5061.c

78

#define ADP5061_IEND_IEND_MSK GENMASK(7, 5)

drivers/power/supply/axp20x_ac_power.c

29

#define AXP813_VHOLD_MASK GENMASK(5, 3)

drivers/power/supply/axp20x_ac_power.c

34

#define AXP813_CURR_LIMIT_MASK GENMASK(2, 0)

drivers/power/supply/axp20x_battery.c

36

#define AXP717_PWR_STATUS_MASK GENMASK(6, 5)

drivers/power/supply/axp20x_battery.c

45

#define AXP717_BATT_PMU_FAULT_MASK GENMASK(2, 0)

drivers/power/supply/axp20x_battery.c

50

#define AXP209_FG_PERCENT GENMASK(6, 0)

drivers/power/supply/axp20x_battery.c

54

#define AXP20X_CHRG_CTRL1_TGT_VOLT GENMASK(6, 5)

drivers/power/supply/axp20x_battery.c

64

#define AXP717_CHRG_CV_VOLT_MASK GENMASK(2, 0)

drivers/power/supply/axp20x_battery.c

75

#define AXP20X_CHRG_CTRL1_TGT_CURR GENMASK(3, 0)

drivers/power/supply/axp20x_battery.c

76

#define AXP717_ICC_CHARGER_LIM_MASK GENMASK(5, 0)

drivers/power/supply/axp20x_battery.c

78

#define AXP717_ITERM_CHG_LIM_MASK GENMASK(3, 0)

drivers/power/supply/axp20x_battery.c

81

#define AXP20X_V_OFF_MASK GENMASK(2, 0)

drivers/power/supply/axp20x_battery.c

82

#define AXP717_V_OFF_MASK GENMASK(6, 4)

drivers/power/supply/axp20x_usb_power.c

41

#define AXP20X_VBUS_VHOLD_MASK GENMASK(5, 3)

drivers/power/supply/axp20x_usb_power.c

47

#define AXP717_INPUT_VOL_LIMIT_MASK GENMASK(3, 0)

drivers/power/supply/axp20x_usb_power.c

48

#define AXP717_INPUT_CUR_LIMIT_MASK GENMASK(5, 0)

drivers/power/supply/axp20x_usb_power.c

49

#define AXP717_ADC_DATA_MASK GENMASK(14, 0)

drivers/power/supply/bq256xx_charger.c

103

#define BQ256XX_ICHG_MASK GENMASK(5, 0)

drivers/power/supply/bq256xx_charger.c

116

#define BQ256XX_VBUS_STAT_MASK GENMASK(7, 5)

drivers/power/supply/bq256xx_charger.c

123

#define BQ256XX_CHRG_STAT_MASK GENMASK(4, 3)

drivers/power/supply/bq256xx_charger.c

131

#define BQ256XX_CHRG_FAULT_MASK GENMASK(5, 4)

drivers/power/supply/bq256xx_charger.c

137

#define BQ256XX_NTC_FAULT_MASK GENMASK(2, 0)

drivers/power/supply/bq256xx_charger.c

144

#define BQ256XX_WATCHDOG_MASK GENMASK(5, 4)

drivers/power/supply/bq256xx_charger.c

36

#define BQ256XX_IINDPM_MASK GENMASK(4, 0)

drivers/power/supply/bq256xx_charger.c

46

#define BQ256XX_VINDPM_MASK GENMASK(3, 0)

drivers/power/supply/bq256xx_charger.c

53

#define BQ256XX_VBATREG_MASK GENMASK(7, 3)

drivers/power/supply/bq256xx_charger.c

78

#define BQ256XX_ITERM_MASK GENMASK(3, 0)

drivers/power/supply/bq256xx_charger.c

90

#define BQ256XX_IPRECHG_MASK GENMASK(7, 4)

drivers/power/supply/bq25980_charger.h

143

#define BQ25980_BATOCP_MASK GENMASK(6, 0)

drivers/power/supply/bq25980_charger.h

161

#define BQ25980_STAT4_TFLT_MASK GENMASK(5, 1)

drivers/power/supply/bq25980_charger.h

163

#define BQ25980_PRESENT_MASK GENMASK(4, 2)

drivers/power/supply/bq25980_charger.h

172

#define BQ25980_WATCHDOG_MASK GENMASK(4, 3)

drivers/power/supply/cw2015_battery.c

37

#define CW2015_MODE_SLEEP_MASK GENMASK(7, 6)

drivers/power/supply/cw2015_battery.c

45

#define CW2015_MASK_ATHD GENMASK(7, 3)

drivers/power/supply/cw2015_battery.c

46

#define CW2015_MASK_SOC GENMASK(12, 0)

drivers/power/supply/intel_dc_ti_battery.c

55

#define CC_CNTL_SMPL_INTVL GENMASK(5, 4)

drivers/power/supply/intel_dc_ti_battery.c

85

#define CC_TRIM_REVISION GENMASK(3, 0)

drivers/power/supply/intel_dc_ti_battery.c

86

#define CC_GAIN_CORRECTION GENMASK(7, 4)

drivers/power/supply/ltc4162-l-charger.c

413

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

452

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

503

regval &= GENMASK(5, 0);

drivers/power/supply/ltc4162-l-charger.c

55

#define LTC4162L_CHEM_MASK GENMASK(11, 8)

drivers/power/supply/ltc4162-l-charger.c

639

regval &= GENMASK(5, 0);

drivers/power/supply/max1720x_battery.c

50

#define MAX172XX_DEV_NAME_TYPE_MASK GENMASK(3, 0)

drivers/power/supply/max77650-charger.c

20

#define MAX77650_CHG_DETAILS_MASK GENMASK(7, 4)

drivers/power/supply/max77650-charger.c

51

#define MAX77650_CHGIN_DETAILS_MASK GENMASK(3, 2)

drivers/power/supply/mp2629_charger.c

34

#define MP2629_MASK_INPUT_TYPE GENMASK(7, 5)

drivers/power/supply/mp2629_charger.c

35

#define MP2629_MASK_CHARGE_TYPE GENMASK(4, 3)

drivers/power/supply/mp2629_charger.c

36

#define MP2629_MASK_CHARGE_CTRL GENMASK(5, 4)

drivers/power/supply/mp2629_charger.c

37

#define MP2629_MASK_WDOG_CTRL GENMASK(5, 4)

drivers/power/supply/mp2629_charger.c

38

#define MP2629_MASK_IMPEDANCE GENMASK(7, 4)

drivers/power/supply/mp2629_charger.c

40

#define MP2629_INPUTSOURCE_CHANGE GENMASK(7, 5)

drivers/power/supply/mp2629_charger.c

41

#define MP2629_CHARGING_CHANGE GENMASK(4, 3)

drivers/power/supply/mp2629_charger.c

640

GENMASK(6, 5), BIT(6) | BIT(5));

drivers/power/supply/mt6360_charger.c

42

#define MT6360_IINLMTSEL_MASK GENMASK(3, 2)

drivers/power/supply/mt6360_charger.c

45

#define MT6360_IAICR_MASK GENMASK(7, 2)

drivers/power/supply/mt6360_charger.c

49

#define MT6360_VOREG_MASK GENMASK(7, 1)

drivers/power/supply/mt6360_charger.c

51

#define MT6360_VOBST_MASK GENMASK(7, 2)

drivers/power/supply/mt6360_charger.c

54

#define MT6360_VMIVR_MASK GENMASK(7, 1)

drivers/power/supply/mt6360_charger.c

57

#define MT6360_ICHG_MASK GENMASK(7, 2)

drivers/power/supply/mt6360_charger.c

60

#define MT6360_IPREC_MASK GENMASK(3, 0)

drivers/power/supply/mt6360_charger.c

63

#define MT6360_IEOC_MASK GENMASK(7, 4)

drivers/power/supply/mt6360_charger.c

65

#define MT6360_OTG_OC_MASK GENMASK(3, 0)

drivers/power/supply/mt6360_charger.c

70

#define MT6360_USB_STATUS_MASK GENMASK(6, 4)

drivers/power/supply/mt6360_charger.c

73

#define MT6360_CHG_STAT_MASK GENMASK(7, 6)

drivers/power/supply/mt6360_charger.c

77

#define MT6360_VINOVP_MASK GENMASK(6, 5)

drivers/power/supply/mt6370-charger.c

42

#define MT6370_VOBST_MASK GENMASK(7, 2)

drivers/power/supply/mt6370-charger.c

45

#define MT6370_OTG_OC_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

105

#define OTG_RESERVED_MASK GENMASK(7, 6)

drivers/power/supply/qcom_smbx.c

128

#define APSD_RESULT_STATUS_MASK GENMASK(6, 0)

drivers/power/supply/qcom_smbx.c

138

#define UFP_TYPEC_MASK GENMASK(7, 5)

drivers/power/supply/qcom_smbx.c

153

#define DFP_TYPEC_MASK GENMASK(3, 0)

drivers/power/supply/qcom_smbx.c

205

#define VCONN_SOFTSTART_CFG_MASK GENMASK(5, 4)

drivers/power/supply/qcom_smbx.c

237

#define FLOAT_OPTIONS_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

245

#define TAPER_TIMER_SEL_MASK GENMASK(1, 0)

drivers/power/supply/qcom_smbx.c

262

#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

268

#define USBIN_CURRENT_LIMIT_MASK GENMASK(7, 0)

drivers/power/supply/qcom_smbx.c

281

#define USBIN_5V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

284

#define USBIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)

drivers/power/supply/qcom_smbx.c

287

#define ENG_SSUPPLY_IVREF_OTG_SS_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

291

#define DCIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)

drivers/power/supply/qcom_smbx.c

304

#define INPUT_CURRENT_LIMIT_MASK GENMASK(7, 0)

drivers/power/supply/qcom_smbx.c

31

#define STEP_CHARGING_STATUS_MASK GENMASK(5, 3)

drivers/power/supply/qcom_smbx.c

312

#define P_PATH_POWER_PATH_MASK GENMASK(2, 1)

drivers/power/supply/qcom_smbx.c

32

#define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0)

drivers/power/supply/qcom_smbx.c

322

#define SFT_AFTER_WDOG_IRQ_MASK GENMASK(4, 3)

drivers/power/supply/qcom_smbx.c

329

#define SNARL_WDOG_TIMEOUT_MASK GENMASK(6, 4)

drivers/power/supply/qcom_smbx.c

330

#define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2)

drivers/power/supply/qcom_smbx.c

331

#define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0)

drivers/power/supply/qcom_smbx.c

334

#define AICL_RERUN_TIME_MASK GENMASK(1, 0)

drivers/power/supply/qcom_smbx.c

339

#define STAT_PARALLEL_OFF_DG_CFG_MASK GENMASK(5, 4)

drivers/power/supply/qcom_smbx.c

39

#define BAT_TEMP_STATUS_MASK GENMASK(3, 0)

drivers/power/supply/qcom_smbx.c

40

#define BAT_TEMP_STATUS_SOFT_LIMIT_MASK GENMASK(3, 2)

drivers/power/supply/qcom_smbx.c

47

#define CHARGE_CURRENT_POST_JEITA_MASK GENMASK(7, 0)

drivers/power/supply/qcom_smbx.c

73

#define PRE_CHARGE_CURRENT_SETTING_MASK GENMASK(5, 0)

drivers/power/supply/qcom_smbx.c

76

#define FAST_CHARGE_CURRENT_SETTING_MASK GENMASK(7, 0)

drivers/power/supply/qcom_smbx.c

79

#define FLOAT_VOLTAGE_SETTING_MASK GENMASK(7, 0)

drivers/power/supply/rt9467-charger.c

56

#define RT9467_MASK_OTG_CSEL GENMASK(2, 0)

drivers/power/supply/rt9467-charger.c

57

#define RT9467_MASK_OTG_VSEL GENMASK(7, 2)

drivers/power/supply/rt9467-charger.c

59

#define RT9467_MASK_ADC_IN_SEL GENMASK(7, 4)

drivers/power/supply/rt9471.c

45

#define RT9471_OTGCV_MASK GENMASK(7, 6)

drivers/power/supply/rt9471.c

48

#define RT9471_CHGFAULT_MASK GENMASK(4, 1)

drivers/power/supply/sbs-battery.c

58

#define SPEC_INFO_VERSION_MASK GENMASK(7, 4)

drivers/power/supply/sbs-battery.c

885

day = ret & GENMASK(4, 0);

drivers/power/supply/sbs-battery.c

886

month = (ret & GENMASK(8, 5)) >> 5;

drivers/power/supply/sbs-battery.c

887

year = ((ret & GENMASK(15, 9)) >> 9) + 1980;

drivers/power/supply/sbs-manager.c

32

#define SBSM_MASK_BAT_SUPPORTED GENMASK(3, 0)

drivers/power/supply/sbs-manager.c

33

#define SBSM_MASK_CHARGE_BAT GENMASK(7, 4)

drivers/power/supply/sc2731_charger.c

28

#define SC2731_PRECHG_RNG_MASK GENMASK(12, 11)

drivers/power/supply/sc2731_charger.c

30

#define SC2731_TERMINATION_VOL_MASK GENMASK(2, 1)

drivers/power/supply/sc2731_charger.c

32

#define SC2731_TERMINATION_VOL_CAL_MASK GENMASK(8, 3)

drivers/power/supply/sc2731_charger.c

34

#define SC2731_TERMINATION_CUR_MASK GENMASK(2, 0)

drivers/power/supply/sc2731_charger.c

40

#define SC2731_CUR_MASK GENMASK(5, 0)

drivers/power/supply/sc2731_charger.c

44

#define SC2731_CUR_LIMIT_MASK GENMASK(9, 8)

drivers/power/supply/sc27xx_fuel_gauge.c

50

#define SC27XX_FGU_CLBCNT_MASK GENMASK(15, 0)

drivers/power/supply/sc27xx_fuel_gauge.c

52

#define SC27XX_FGU_LOW_OVERLOAD_MASK GENMASK(12, 0)

drivers/power/supply/sc27xx_fuel_gauge.c

54

#define SC27XX_FGU_INT_MASK GENMASK(9, 0)

drivers/power/supply/sc27xx_fuel_gauge.c

58

#define SC27XX_FGU_MODE_AREA_MASK GENMASK(15, 12)

drivers/power/supply/sc27xx_fuel_gauge.c

59

#define SC27XX_FGU_CAP_AREA_MASK GENMASK(11, 0)

drivers/power/supply/sc27xx_fuel_gauge.c

62

#define SC27XX_FGU_FIRST_POWERTON GENMASK(3, 0)

drivers/power/supply/sc27xx_fuel_gauge.c

63

#define SC27XX_FGU_DEFAULT_CAP GENMASK(11, 0)

drivers/power/supply/ucs1002_power.c

57

# define F_ACTIVE_MODE_MASK GENMASK(5, 3)

drivers/power/supply/ucs1002_power.c

80

# define V_SET_ACTIVE_MODE_MASK GENMASK(5, 3)

drivers/power/supply/ucs1002_power.c

89

# define UCS1002_ILIM_SW_MASK GENMASK(3, 0)

drivers/powercap/intel_rapl_common.c

1780

#define RAPL_EVENT_MASK GENMASK(7, 0)

drivers/pps/generators/pps_gen_tio.c

31

#define TIOCTL_EP GENMASK(3, 2)

drivers/ptp/ptp_netc.c

19

#define TMR_CTRL_CK_SEL GENMASK(1, 0)

drivers/ptp/ptp_netc.c

23

#define TMR_CTRL_TCLK_PERIOD GENMASK(25, 16)

drivers/ptp/ptp_netc.c

29

#define TMR_TEVENT_PPEN_ALL GENMASK(7, 5)

drivers/ptp/ptp_netc.c

61

#define FIPER_CTRL_PW(i) (GENMASK(4, 0) << (i) * 8)

drivers/ptp/ptp_netc.c

62

#define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i))

drivers/ptp/ptp_netc.c

73

#define IPBRR0_IP_REV GENMASK(15, 0)

drivers/ptp/ptp_netc.c

80

#define NETC_TMR_DEFAULT_FIPER GENMASK(31, 0)

drivers/ptp/ptp_netc.c

81

#define NETC_TMR_FIPER_MAX_PW GENMASK(4, 0)

drivers/ptp/ptp_ocp.c

106

#define TOD_CTRL_GNSS_MASK GENMASK(3, 0)

drivers/ptp/ptp_ocp.c

1066

#define SMA_SELECT_MASK GENMASK(14, 0)

drivers/ptp/ptp_ocp.c

109

#define TOD_STATUS_UTC_MASK GENMASK(7, 0)

drivers/ptp/ptp_ocp.c

228

#define FREQ_STATUS_MASK GENMASK(23, 0)

drivers/pwm/pwm-airoha.c

33

#define AIROHA_PWM_SGPIO_LED_DATA_DATA GENMASK(16, 0)

drivers/pwm/pwm-airoha.c

36

#define AIROHA_PWM_SGPIO_CLK_DIVR GENMASK(1, 0)

drivers/pwm/pwm-airoha.c

50

#define AIROHA_PWM_GPIO_FLASH_PRD_LOW GENMASK(15, 8)

drivers/pwm/pwm-airoha.c

51

#define AIROHA_PWM_GPIO_FLASH_PRD_HIGH GENMASK(7, 0)

drivers/pwm/pwm-airoha.c

56

#define AIROHA_PWM_GPIO_FLASH_SET_ID GENMASK(2, 0)

drivers/pwm/pwm-airoha.c

63

#define AIROHA_PWM_WAVE_GEN_CYCLE GENMASK(7, 0)

drivers/pwm/pwm-atmel-hlcdc.c

18

#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)

drivers/pwm/pwm-atmel-hlcdc.c

21

#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)

drivers/pwm/pwm-hibvt.c

32

#define PWM_PERIOD_MASK GENMASK(31, 0)

drivers/pwm/pwm-hibvt.c

33

#define PWM_DUTY_MASK GENMASK(31, 0)

drivers/pwm/pwm-imx-tpm.c

36

#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)

drivers/pwm/pwm-imx-tpm.c

38

#define PWM_IMX_TPM_SC_PS GENMASK(2, 0)

drivers/pwm/pwm-imx-tpm.c

39

#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)

drivers/pwm/pwm-imx-tpm.c

52

#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)

drivers/pwm/pwm-imx-tpm.c

58

#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)

drivers/pwm/pwm-imx27.c

31

#define MX3_PWMCR_FWM GENMASK(27, 26)

drivers/pwm/pwm-imx27.c

39

#define MX3_PWMCR_POUTC GENMASK(19, 18)

drivers/pwm/pwm-imx27.c

44

#define MX3_PWMCR_CLKSRC GENMASK(17, 16)

drivers/pwm/pwm-imx27.c

50

#define MX3_PWMCR_PRESCALER GENMASK(15, 4)

drivers/pwm/pwm-imx27.c

54

#define MX3_PWMCR_REPEAT GENMASK(2, 1)

drivers/pwm/pwm-imx27.c

67

#define MX3_PWMSR_FIFOAV GENMASK(2, 0)

drivers/pwm/pwm-intel-lgm.c

31

#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)

drivers/pwm/pwm-intel-lgm.c

34

#define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0)

drivers/pwm/pwm-jz4740.c

40

u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2);

drivers/pwm/pwm-keembay.c

30

#define KMB_PWM_HIGH_MASK GENMASK(31, 16)

drivers/pwm/pwm-keembay.c

31

#define KMB_PWM_LOW_MASK GENMASK(15, 0)

drivers/pwm/pwm-keembay.c

32

#define KMB_PWM_LEADIN_MASK GENMASK(30, 0)

drivers/pwm/pwm-lpss.c

31

#define PWM_ON_TIME_DIV_MASK GENMASK(7, 0)

drivers/pwm/pwm-mc33xs2410.c

36

#define MC33XS2410_GLB_CTRL_MODE GENMASK(7, 6)

drivers/pwm/pwm-mc33xs2410.c

49

#define MC33XS2410_PWM_FREQ_STEP GENMASK(7, 6)

drivers/pwm/pwm-mc33xs2410.c

50

#define MC33XS2410_PWM_FREQ_COUNT GENMASK(5, 0)

drivers/pwm/pwm-mc33xs2410.c

61

#define MC33XS2410_FRAME_IN_ADDR GENMASK(15, 8)

drivers/pwm/pwm-mc33xs2410.c

62

#define MC33XS2410_FRAME_IN_DATA GENMASK(7, 0)

drivers/pwm/pwm-mc33xs2410.c

65

#define MC33XS2410_FRAME_OUT_DATA GENMASK(13, 0)

drivers/pwm/pwm-mediatek.c

25

#define PWMCON_CLKDIV GENMASK(2, 0)

drivers/pwm/pwm-mediatek.c

31

#define PWMDWIDTH_PERIOD GENMASK(12, 0)

drivers/pwm/pwm-mediatek.c

34

#define PWMTHRES_DUTY GENMASK(12, 0)

drivers/pwm/pwm-mediatek.c

408

enabled = readl(pc->regs) & GENMASK(soc->num_pwms - 1, 0);

drivers/pwm/pwm-meson.c

47

#define PWM_LOW_MASK GENMASK(15, 0)

drivers/pwm/pwm-meson.c

48

#define PWM_HIGH_MASK GENMASK(31, 16)

drivers/pwm/pwm-rzg2l-gpt.c

48

#define RZG2L_GTCR_MD GENMASK(18, 16)

drivers/pwm/pwm-rzg2l-gpt.c

49

#define RZG2L_GTCR_TPCS GENMASK(26, 24)

drivers/pwm/pwm-rzg2l-gpt.c

57

#define RZG2L_GTIOR_GTIOA GENMASK(4, 0)

drivers/pwm/pwm-rzg2l-gpt.c

58

#define RZG2L_GTIOR_GTIOB GENMASK(20, 16)

drivers/pwm/pwm-sifive.c

47

#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)

drivers/pwm/pwm-sl28cpld.c

50

#define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0)

drivers/pwm/pwm-sl28cpld.c

52

#define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0)

drivers/pwm/pwm-sprd.c

20

#define SPRD_PWM_MOD_MAX GENMASK(7, 0)

drivers/pwm/pwm-sprd.c

21

#define SPRD_PWM_DUTY_MSK GENMASK(15, 0)

drivers/pwm/pwm-sprd.c

22

#define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0)

drivers/pwm/pwm-sun4i.c

33

#define PWM_PRESCAL_MASK GENMASK(3, 0)

drivers/pwm/pwm-sun4i.c

47

#define PWM_PRD_MASK GENMASK(15, 0)

drivers/pwm/pwm-sun4i.c

49

#define PWM_DTY_MASK GENMASK(15, 0)

drivers/pwm/pwm-sunplus.c

37

#define SP7021_PWM_FREQ_MAX GENMASK(15, 0)

drivers/pwm/pwm-sunplus.c

39

#define SP7021_PWM_DUTY_DD_SEL(ch) FIELD_PREP(GENMASK(9, 8), ch)

drivers/pwm/pwm-sunplus.c

40

#define SP7021_PWM_DUTY_MAX GENMASK(7, 0)

drivers/pwm/pwm-visconti.c

33

#define PIPGM_PWMC_CLK_MASK GENMASK(1, 0)

drivers/pwm/pwm-visconti.c

34

#define PIPGM_PWMC_POLARITY_MASK GENMASK(5, 5)

drivers/ras/amd/atl/access.c

33

#define DF_FICAA_REG_NUM GENMASK(10, 1)

drivers/ras/amd/atl/access.c

34

#define DF_FICAA_FUNC_NUM GENMASK(13, 11)

drivers/ras/amd/atl/access.c

35

#define DF_FICAA_INST_ID GENMASK(23, 16)

drivers/ras/amd/atl/access.c

37

#define DF_FICAA_REG_NUM_LEGACY GENMASK(10, 2)

drivers/ras/amd/atl/core.c

30

dram_limit_addr |= GENMASK(DF_DRAM_BASE_LIMIT_LSB - 1, 0);

drivers/ras/amd/atl/denormalize.c

167

mask = GENMASK(num_intlv_bits - 1, 0);

drivers/ras/amd/atl/denormalize.c

174

mask = GENMASK(num_die_intlv_bits - 1, 0);

drivers/ras/amd/atl/denormalize.c

186

mask = GENMASK(num_socket_intlv_bits - 1, 0);

drivers/ras/amd/atl/denormalize.c

220

mask = GENMASK(num_intlv_bits - 1, 0);

drivers/ras/amd/atl/denormalize.c

236

mask = GENMASK(num_intlv_bits - 1, 0);

drivers/ras/amd/atl/denormalize.c

266

channel_bits = FIELD_GET(GENMASK(3, 0), ctx->coh_st_fabric_id);

drivers/ras/amd/atl/denormalize.c

334

denorm_addr |= (coh_st_id & GENMASK(2, 1)) << 11;

drivers/ras/amd/atl/denormalize.c

342

denorm_addr |= (coh_st_id & GENMASK(1, 0)) << 8;

drivers/ras/amd/atl/denormalize.c

348

denorm_addr |= (coh_st_id & GENMASK(3, 2)) << 10;

drivers/ras/amd/atl/denormalize.c

639

coh_st_id |= GENMASK(2, 1);

drivers/ras/amd/atl/internal.h

369

#define MI300_UMC_MCA_COL GENMASK(5, 1)

drivers/ras/amd/atl/reg_fields.h

109

#define DF2_DIE_ID_MASK GENMASK(15, 8)

drivers/ras/amd/atl/reg_fields.h

110

#define DF3_DIE_ID_MASK GENMASK(18, 16)

drivers/ras/amd/atl/reg_fields.h

111

#define DF4_DIE_ID_MASK GENMASK(15, 0)

drivers/ras/amd/atl/reg_fields.h

129

#define DF2_DIE_ID_SHIFT GENMASK(27, 24)

drivers/ras/amd/atl/reg_fields.h

171

#define DF2_BASE_ADDR GENMASK(31, 12)

drivers/ras/amd/atl/reg_fields.h

172

#define DF4_BASE_ADDR GENMASK(27, 0)

drivers/ras/amd/atl/reg_fields.h

191

#define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)

drivers/ras/amd/atl/reg_fields.h

212

#define DF2_DRAM_LIMIT_ADDR GENMASK(31, 12)

drivers/ras/amd/atl/reg_fields.h

213

#define DF4_DRAM_LIMIT_ADDR GENMASK(27, 0)

drivers/ras/amd/atl/reg_fields.h

273

#define DF2_HI_ADDR_OFFSET GENMASK(31, 20)

drivers/ras/amd/atl/reg_fields.h

274

#define DF3_HI_ADDR_OFFSET GENMASK(31, 12)

drivers/ras/amd/atl/reg_fields.h

277

#define DF4_HI_ADDR_OFFSET GENMASK(31, 1)

drivers/ras/amd/atl/reg_fields.h

317

#define DF2_INTLV_ADDR_SEL GENMASK(10, 8)

drivers/ras/amd/atl/reg_fields.h

318

#define DF3_INTLV_ADDR_SEL GENMASK(11, 9)

drivers/ras/amd/atl/reg_fields.h

319

#define DF4_INTLV_ADDR_SEL GENMASK(2, 0)

drivers/ras/amd/atl/reg_fields.h

340

#define DF2_INTLV_NUM_CHAN GENMASK(7, 4)

drivers/ras/amd/atl/reg_fields.h

341

#define DF3_INTLV_NUM_CHAN GENMASK(5, 2)

drivers/ras/amd/atl/reg_fields.h

342

#define DF3p5_INTLV_NUM_CHAN GENMASK(6, 2)

drivers/ras/amd/atl/reg_fields.h

343

#define DF4_INTLV_NUM_CHAN GENMASK(8, 4)

drivers/ras/amd/atl/reg_fields.h

344

#define DF4p5_INTLV_NUM_CHAN GENMASK(9, 4)

drivers/ras/amd/atl/reg_fields.h

367

#define DF2_INTLV_NUM_DIES GENMASK(11, 10)

drivers/ras/amd/atl/reg_fields.h

368

#define DF3_INTLV_NUM_DIES GENMASK(7, 6)

drivers/ras/amd/atl/reg_fields.h

37

#define DF2_COH_ST_FABRIC_ID GENMASK(19, 8)

drivers/ras/amd/atl/reg_fields.h

370

#define DF4_INTLV_NUM_DIES GENMASK(13, 12)

drivers/ras/amd/atl/reg_fields.h

38

#define DF4p5_COH_ST_FABRIC_ID GENMASK(15, 8)

drivers/ras/amd/atl/reg_fields.h

434

#define DF_LOG2_ADDR_64K_SPACE0 GENMASK(5, 0)

drivers/ras/amd/atl/reg_fields.h

452

#define DF_MAJOR_REVISION GENMASK(27, 24)

drivers/ras/amd/atl/reg_fields.h

470

#define DF_MINOR_REVISION GENMASK(23, 16)

drivers/ras/amd/atl/reg_fields.h

492

#define DF3_NODE_ID_MASK GENMASK(25, 16)

drivers/ras/amd/atl/reg_fields.h

493

#define DF4_NODE_ID_MASK GENMASK(31, 16)

drivers/ras/amd/atl/reg_fields.h

515

#define DF3_NODE_ID_SHIFT GENMASK(3, 0)

drivers/ras/amd/atl/reg_fields.h

555

#define DF4_REMAP_SEL GENMASK(7, 5)

drivers/ras/amd/atl/reg_fields.h

556

#define DF4p5_REMAP_SEL GENMASK(6, 5)

drivers/ras/amd/atl/reg_fields.h

579

#define DF2_SOCKET_ID_MASK GENMASK(23, 16)

drivers/ras/amd/atl/reg_fields.h

580

#define DF3_SOCKET_ID_MASK GENMASK(26, 24)

drivers/ras/amd/atl/reg_fields.h

581

#define DF4_SOCKET_ID_MASK GENMASK(31, 16)

drivers/ras/amd/atl/reg_fields.h

60

#define DF3_COMPONENT_ID_MASK GENMASK(9, 0)

drivers/ras/amd/atl/reg_fields.h

604

#define DF2_SOCKET_ID_SHIFT GENMASK(31, 28)

drivers/ras/amd/atl/reg_fields.h

605

#define DF3_SOCKET_ID_SHIFT GENMASK(9, 8)

drivers/ras/amd/atl/reg_fields.h

606

#define DF4_SOCKET_ID_SHIFT GENMASK(11, 8)

drivers/ras/amd/atl/reg_fields.h

61

#define DF4_COMPONENT_ID_MASK GENMASK(15, 0)

drivers/ras/amd/atl/reg_fields.h

82

#define DF2_DST_FABRIC_ID GENMASK(7, 0)

drivers/ras/amd/atl/reg_fields.h

83

#define DF3_DST_FABRIC_ID GENMASK(9, 0)

drivers/ras/amd/atl/reg_fields.h

84

#define DF3p5_DST_FABRIC_ID GENMASK(11, 0)

drivers/ras/amd/atl/reg_fields.h

85

#define DF4_DST_FABRIC_ID GENMASK(27, 16)

drivers/ras/amd/atl/reg_fields.h

86

#define DF4p5_DST_FABRIC_ID GENMASK(23, 16)

drivers/ras/amd/atl/umc.c

100

#define ADDR_CFG_NUM_ROW_HI GENMASK(15, 12)

drivers/ras/amd/atl/umc.c

102

#define ADDR_SEL_BANK0 GENMASK(3, 0)

drivers/ras/amd/atl/umc.c

103

#define ADDR_SEL_BANK1 GENMASK(7, 4)

drivers/ras/amd/atl/umc.c

104

#define ADDR_SEL_BANK2 GENMASK(11, 8)

drivers/ras/amd/atl/umc.c

105

#define ADDR_SEL_BANK3 GENMASK(15, 12)

drivers/ras/amd/atl/umc.c

106

#define ADDR_SEL_BANK4 GENMASK(20, 16)

drivers/ras/amd/atl/umc.c

107

#define ADDR_SEL_ROW_LO GENMASK(27, 24)

drivers/ras/amd/atl/umc.c

108

#define ADDR_SEL_ROW_HI GENMASK(31, 28)

drivers/ras/amd/atl/umc.c

110

#define COL_SEL_LO_COL0 GENMASK(3, 0)

drivers/ras/amd/atl/umc.c

111

#define COL_SEL_LO_COL1 GENMASK(7, 4)

drivers/ras/amd/atl/umc.c

112

#define COL_SEL_LO_COL2 GENMASK(11, 8)

drivers/ras/amd/atl/umc.c

113

#define COL_SEL_LO_COL3 GENMASK(15, 12)

drivers/ras/amd/atl/umc.c

114

#define COL_SEL_LO_COL4 GENMASK(19, 16)

drivers/ras/amd/atl/umc.c

116

#define ADDR_SEL_2_BANK5 GENMASK(4, 0)

drivers/ras/amd/atl/umc.c

117

#define ADDR_SEL_2_CHAN GENMASK(15, 12)

drivers/ras/amd/atl/umc.c

221

#define MI300_UMC_MCA_BANK GENMASK(9, 6)

drivers/ras/amd/atl/umc.c

222

#define MI300_UMC_MCA_ROW GENMASK(24, 10)

drivers/ras/amd/atl/umc.c

224

#define MI300_UMC_MCA_SID GENMASK(27, 26)

drivers/ras/amd/atl/umc.c

36

#define UMC_ID_MI300 GENMASK(23, 12)

drivers/ras/amd/atl/umc.c

393

#define UMC_CHANNEL_NUM GENMASK(31, 20)

drivers/ras/amd/atl/umc.c

95

#define ADDR_HASH_COL_XOR GENMASK(13, 1)

drivers/ras/amd/atl/umc.c

96

#define ADDR_HASH_ROW_XOR GENMASK(31, 14)

drivers/ras/amd/atl/umc.c

97

#define ADDR_HASH_BANK_XOR GENMASK(5, 0)

drivers/ras/amd/atl/umc.c

99

#define ADDR_CFG_NUM_ROW_LO GENMASK(11, 8)

drivers/regulator/adp5055-regulator.c

323

.vsel_mask = GENMASK(7, 0), \

drivers/regulator/adp5055-regulator.c

43

#define ADP5055_MASK_DIS_DLY GENMASK(6, 4)

drivers/regulator/adp5055-regulator.c

44

#define ADP5055_MASK_EN_DLY GENMASK(2, 0)

drivers/regulator/adp5055-regulator.c

45

#define ADP5055_MASK_DVS_LIM_UPPER GENMASK(7, 4)

drivers/regulator/adp5055-regulator.c

46

#define ADP5055_MASK_DVS_LIM_LOWER GENMASK(3, 0)

drivers/regulator/adp5055-regulator.c

47

#define ADP5055_MASK_FAST_TRANSIENT2 GENMASK(5, 4)

drivers/regulator/adp5055-regulator.c

48

#define ADP5055_MASK_FAST_TRANSIENT1 GENMASK(3, 2)

drivers/regulator/adp5055-regulator.c

49

#define ADP5055_MASK_FAST_TRANSIENT0 GENMASK(1, 0)

drivers/regulator/atc260x-regulator.c

183

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

202

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

221

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

238

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

257

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

287

.vsel_mask = GENMASK(vsel_h, vsel_l), \

drivers/regulator/atc260x-regulator.c

350

.vsel_mask = GENMASK(15, 8), \

drivers/regulator/atc260x-regulator.c

369

.vsel_mask = GENMASK(15, 8), \

drivers/regulator/atc260x-regulator.c

388

.vsel_mask = GENMASK(4, 1), \

drivers/regulator/atc260x-regulator.c

407

.vsel_mask = GENMASK(5, 2), \

drivers/regulator/atc260x-regulator.c

428

.vsel_mask = GENMASK(4, 1), \

drivers/regulator/atc260x-regulator.c

450

.vsel_mask = GENMASK(15, 13), \

drivers/regulator/axp20x-regulator.c

100

#define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

101

#define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)

drivers/regulator/axp20x-regulator.c

102

#define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

103

#define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

104

#define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

105

#define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

106

#define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

107

#define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

108

#define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

109

#define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

110

#define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

111

#define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

112

#define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

113

#define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

138

#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

139

#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

144

#define AXP717_DCDC_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

145

#define AXP717_LDO_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

146

#define AXP717_BOOST_V_OUT_MASK GENMASK(7, 4)

drivers/regulator/axp20x-regulator.c

158

#define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

159

#define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

160

#define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

161

#define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

162

#define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

163

#define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

165

#define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

166

#define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

211

#define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

212

#define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

213

#define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

214

#define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)

drivers/regulator/axp20x-regulator.c

215

#define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

216

#define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

217

#define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

218

#define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

219

#define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

220

#define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

221

#define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

222

#define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

223

#define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

224

#define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

225

#define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

246

#define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)

drivers/regulator/axp20x-regulator.c

280

#define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

284

#define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

285

#define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

286

#define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

287

#define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

288

#define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

289

#define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

29

#define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

290

#define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

291

#define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

292

#define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

293

#define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

294

#define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

295

#define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

296

#define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

297

#define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

298

#define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

299

#define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

30

#define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

300

#define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

301

#define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

302

#define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

303

#define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0)

drivers/regulator/axp20x-regulator.c

304

#define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

38

#define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

42

#define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)

drivers/regulator/axp20x-regulator.c

43

#define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)

drivers/regulator/axp20x-regulator.c

44

#define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4)

drivers/regulator/axp20x-regulator.c

45

#define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)

drivers/regulator/axp20x-regulator.c

46

#define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0)

drivers/regulator/axp20x-regulator.c

47

#define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)

drivers/regulator/axp20x-regulator.c

96

#define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)

drivers/regulator/axp20x-regulator.c

97

#define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)

drivers/regulator/axp20x-regulator.c

98

#define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)

drivers/regulator/axp20x-regulator.c

99

#define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)

drivers/regulator/bcm590xx-regulator.c

23

#define BCM590XX_LDO_VSEL_MASK GENMASK(5, 3)

drivers/regulator/bcm590xx-regulator.c

24

#define BCM590XX_SR_VSEL_MASK GENMASK(5, 0)

drivers/regulator/bd71828-regulator.c

22

#define BD72720_MASK_LDON_HEAD GENMASK(2, 0)

drivers/regulator/fan53555.c

54

#define CTL_SLEW_MASK GENMASK(6, 4)

drivers/regulator/fan53555.c

66

#define TCS_SLEW_MASK GENMASK(4, 3)

drivers/regulator/ltc3589.c

56

#define LTC3589_VRRCR_SW1_RAMP_MASK GENMASK(1, 0)

drivers/regulator/ltc3589.c

57

#define LTC3589_VRRCR_SW2_RAMP_MASK GENMASK(3, 2)

drivers/regulator/ltc3589.c

58

#define LTC3589_VRRCR_SW3_RAMP_MASK GENMASK(5, 4)

drivers/regulator/ltc3589.c

59

#define LTC3589_VRRCR_LDO2_RAMP_MASK GENMASK(7, 6)

drivers/regulator/max77503-regulator.c

22

#define MAX77503_BITS_SOFT_START GENMASK(5, 4)

drivers/regulator/max77503-regulator.c

23

#define MAX77503_BITS_MX_VOUT GENMASK(7, 0)

drivers/regulator/max77650-regulator.c

15

#define MAX77650_REGULATOR_EN_CTRL_MASK GENMASK(3, 0)

drivers/regulator/max77650-regulator.c

18

#define MAX77650_REGULATOR_ENABLED GENMASK(2, 1)

drivers/regulator/max77650-regulator.c

21

#define MAX77650_REGULATOR_V_LDO_MASK GENMASK(6, 0)

drivers/regulator/max77650-regulator.c

22

#define MAX77650_REGULATOR_V_SBB_MASK GENMASK(5, 0)

drivers/regulator/max77650-regulator.c

23

#define MAX77651_REGULATOR_V_SBB1_MASK GENMASK(5, 2)

drivers/regulator/max77650-regulator.c

24

#define MAX77651_REGULATOR_V_SBB1_RANGE_MASK GENMASK(1, 0)

drivers/regulator/max77650-regulator.c

30

#define MAX77650_REGULATOR_CURR_LIM_MASK GENMASK(7, 6)

drivers/regulator/max77675-regulator.c

128

#define MAX77675_CID_MASK GENMASK(4, 0) /* Chip Identification Code mask */

drivers/regulator/max77675-regulator.c

140

#define MAX77675_DRV_SBB_MASK GENMASK(1, 0)

drivers/regulator/max77675-regulator.c

144

#define MAX77675_TV_SBB0_MASK GENMASK(7, 0)

drivers/regulator/max77675-regulator.c

150

#define MAX77675_EN_SBB0_MASK GENMASK(2, 0)

drivers/regulator/max77675-regulator.c

154

#define MAX77675_TV_SBB1_MASK GENMASK(7, 0)

drivers/regulator/max77675-regulator.c

160

#define MAX77675_EN_SBB1_MASK GENMASK(2, 0)

drivers/regulator/max77675-regulator.c

164

#define MAX77675_TV_SBB2_MASK GENMASK(7, 0)

drivers/regulator/max77675-regulator.c

170

#define MAX77675_EN_SBB2_MASK GENMASK(2, 0)

drivers/regulator/max77675-regulator.c

174

#define MAX77675_TV_SBB3_MASK GENMASK(7, 0)

drivers/regulator/max77675-regulator.c

180

#define MAX77675_EN_SBB3_MASK GENMASK(2, 0)

drivers/regulator/max77675-regulator.c

183

#define MAX77675_EN_SBB_MASK GENMASK(2, 0)

drivers/regulator/max77675-regulator.c

41

#define MAX77675_MRT_MASK GENMASK(7, 6) /* Manual Reset Time (bits 7:6) */

drivers/regulator/max77675-regulator.c

49

#define MAX77675_EN_MODE_MASK GENMASK(2, 1) /* nEN Mode (bits 2:1) */

drivers/regulator/max77675-regulator.c

55

#define MAX77675_SFT_CTRL_MASK GENMASK(2, 0) /* Soft Start Control */

drivers/regulator/max77857-regulator.c

29

#define MAX77857_ILIM_MASK GENMASK(2, 0)

drivers/regulator/max77857-regulator.c

30

#define MAX77857_CONT1_FREQ GENMASK(4, 3)

drivers/regulator/max77857-regulator.c

313

.ramp_mask = GENMASK(1, 0),

drivers/regulator/max77857-regulator.c

41

#define MAX77859_VOLTAGE_SEL_MASK GENMASK(9, 0)

drivers/regulator/mcp16502.c

25

#define MCP16502_DVSR GENMASK(3, 2)

drivers/regulator/mt6316-regulator.c

31

#define MT6316_VSEL_MASK GENMASK(8, 0)

drivers/regulator/mt6316-regulator.c

93

return ((val >> 8) & BIT(0)) | ((val & GENMASK(7, 0)) << 1);

drivers/regulator/mt6331-regulator.c

340

MT6331_VDVFS11_CON11, GENMASK(6, 0),

drivers/regulator/mt6331-regulator.c

344

MT6331_VDVFS12_CON11, GENMASK(6, 0),

drivers/regulator/mt6331-regulator.c

348

MT6331_VDVFS13_CON11, GENMASK(6, 0),

drivers/regulator/mt6331-regulator.c

352

MT6331_VDVFS14_CON11, GENMASK(6, 0),

drivers/regulator/mt6331-regulator.c

356

MT6331_VCORE2_CON11, GENMASK(6, 0),

drivers/regulator/mt6331-regulator.c

361

MT6331_ANALDO_CON1, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

363

MT6331_ANALDO_CON2, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

365

MT6331_SYSLDO_CON4, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

367

MT6331_DIGLDO_CON1, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

369

MT6331_ANALDO_CON10, GENMASK(6, 5), MT6331_ANALDO_CON3, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

371

MT6331_ANALDO_CON6, GENMASK(6, 5), MT6331_ANALDO_CON4, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

373

MT6331_DIGLDO_CON17, BIT(6), MT6331_DIGLDO_CON5, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

375

MT6331_DIGLDO_CON20, GENMASK(6, 4), MT6331_DIGLDO_CON12, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

377

MT6331_DIGLDO_CON15, GENMASK(5, 4), MT6331_DIGLDO_CON3, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

379

MT6331_DIGLDO_CON16, BIT(6), MT6331_DIGLDO_CON4, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

381

MT6331_SYSLDO_CON13, GENMASK(5, 3), MT6331_SYSLDO_CON5, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

383

MT6331_DIGLDO_CON21, GENMASK(6, 4), MT6331_DIGLDO_CON8, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

385

MT6331_DIGLDO_CON22, GENMASK(6, 4), MT6331_DIGLDO_CON9, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

387

MT6331_SYSLDO_CON10, GENMASK(5, 3), MT6331_SYSLDO_CON2, GENMASK(1, 0)),

drivers/regulator/mt6331-regulator.c

389

MT6331_ANALDO_CON9, GENMASK(5, 4), 0, 0),

drivers/regulator/mt6331-regulator.c

391

MT6331_DIGLDO_CON14, GENMASK(6, 4), MT6331_DIGLDO_CON2, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

394

MT6331_SYSLDO_CON9, GENMASK(6, 4), MT6331_SYSLDO_CON1, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

397

MT6331_SYSLDO_CON11, GENMASK(4, 3), MT6331_SYSLDO_CON3, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

400

MT6331_DIGLDO_CON19, GENMASK(6, 4), MT6331_DIGLDO_CON6, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

403

MT6331_SYSLDO_CON14, GENMASK(4, 3), MT6331_SYSLDO_CON6, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

406

MT6331_SYSLDO_CON15, GENMASK(4, 3), MT6331_SYSLDO_CON7, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

409

MT6331_DIGLDO_CON18, GENMASK(6, 4), MT6331_DIGLDO_CON7, GENMASK(1, 0),

drivers/regulator/mt6331-regulator.c

412

MT6331_DIGLDO_CON28, GENMASK(14, 12)),

drivers/regulator/mt6331-regulator.c

458

reg_value &= GENMASK(7, 0);

drivers/regulator/mt6332-regulator.c

302

MT6332_EN_STATUS0, MT6332_VDRAM_CON11, GENMASK(6, 0),

drivers/regulator/mt6332-regulator.c

305

MT6332_VDVFS2_CON9, MT6332_VDVFS2_CON11, GENMASK(6, 0),

drivers/regulator/mt6332-regulator.c

308

MT6332_VPA_CON9, MT6332_VPA_CON11, GENMASK(5, 0),

drivers/regulator/mt6332-regulator.c

311

MT6332_VRF1_CON9, MT6332_VRF1_CON11, GENMASK(6, 0),

drivers/regulator/mt6332-regulator.c

314

MT6332_VRF2_CON9, MT6332_VRF2_CON11, GENMASK(6, 0),

drivers/regulator/mt6332-regulator.c

317

MT6332_VSBST_CON8, MT6332_VSBST_CON12, GENMASK(6, 0),

drivers/regulator/mt6332-regulator.c

320

MT6332_LDO_CON9, GENMASK(6, 5), MT6332_LDO_CON1, GENMASK(1, 0)),

drivers/regulator/mt6332-regulator.c

324

MT6332_EN_STATUS0, MT6332_LDO_CON8, GENMASK(15, 9),

drivers/regulator/mt6332-regulator.c

326

MT6332_LDO_CON5, GENMASK(1, 0)),

drivers/regulator/mt6332-regulator.c

327

MT6332_LDO_AO("ldo-vdig18", VDIG18, ldo_volt_table2, MT6332_LDO_CON12, GENMASK(11, 9)),

drivers/regulator/mt6332-regulator.c

373

reg_value &= GENMASK(7, 0);

drivers/regulator/mt6358-regulator.c

127

.vsel_mask = GENMASK(3, 0), \

drivers/regulator/mt6358-regulator.c

183

.vsel_mask = GENMASK(3, 0), \

drivers/regulator/mt6358-regulator.c

228

.vsel_mask = GENMASK(3, 0), \

drivers/regulator/mt6358-regulator.c

82

.vsel_mask = GENMASK(3, 0), \

drivers/regulator/mt6363-regulator.c

475

(opmode_en >> (i * 8)) & GENMASK(7, 0));

drivers/regulator/mt6370-regulator.c

35

#define MT6370_LDOVOUT_MASK GENMASK(3, 0)

drivers/regulator/mt6370-regulator.c

43

#define MT6370_DBSLEW_MASK GENMASK(7, 6)

drivers/regulator/mt6370-regulator.c

44

#define MT6370_DBVOUT_MASK GENMASK(5, 0)

drivers/regulator/pf0900-regulator.c

191

#define SW_RUN_MODE_MASK GENMASK(1, 0)

drivers/regulator/pf0900-regulator.c

192

#define SW_STBY_MODE_MASK GENMASK(3, 2)

drivers/regulator/pf0900-regulator.c

195

#define PF0900_SW_VOL_MASK GENMASK(7, 0)

drivers/regulator/pf0900-regulator.c

200

#define PF0900_VAON_MASK GENMASK(1, 0)

drivers/regulator/pf0900-regulator.c

203

#define PF0900_SW_DVS_MASK GENMASK(4, 3)

drivers/regulator/pf0900-regulator.c

206

#define VLDO_RUN_MASK GENMASK(4, 0)

drivers/regulator/pf0900-regulator.c

370

crc = crc8_j1850(pf0900->addr << 1 | 0x1, reg, FIELD_GET(GENMASK(7, 0), *val));

drivers/regulator/pf0900-regulator.c

371

if (crc != FIELD_GET(GENMASK(15, 8), *val)) {

drivers/regulator/pf0900-regulator.c

375

*val = FIELD_GET(GENMASK(7, 0), *val);

drivers/regulator/pf0900-regulator.c

409

val = FIELD_PREP(GENMASK(15, 8), data[1]) | data[0];

drivers/regulator/pf530x-regulator.c

213

.enable_mask = GENMASK(5, 2),

drivers/regulator/pf530x-regulator.c

214

.enable_val = GENMASK(5, 2),

drivers/regulator/pf530x-regulator.c

72

#define PF530x_DEVICE_FAM_MASK GENMASK(7, 4)

drivers/regulator/pf530x-regulator.c

73

#define PF530x_DEVICE_ID_MASK GENMASK(3, 0)

drivers/regulator/pf530x-regulator.c

75

#define PF530x_STATE_MASK GENMASK(3, 0)

drivers/regulator/pf530x-regulator.c

80

#define PF530X_OTP_STBY_MODE GENMASK(3, 2)

drivers/regulator/pf530x-regulator.c

81

#define PF530X_OTP_RUN_MODE GENMASK(1, 0)

drivers/regulator/pf8x00-regulator.c

115

#define PF8X00_SWXILIM_MASK GENMASK(4, 3)

drivers/regulator/pf8x00-regulator.c

116

#define PF8X00_SWXPHASE_MASK GENMASK(2, 0)

drivers/regulator/pf8x00-regulator.c

125

#define PF8X00_DEVICE_FAM_MASK GENMASK(7, 4)

drivers/regulator/pf8x00-regulator.c

126

#define PF8X00_DEVICE_ID_MASK GENMASK(3, 0)

drivers/regulator/pf9453-regulator.c

124

#define BUCK1_ENMODE_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

127

#define BUCK2_RAMP_MASK GENMASK(7, 6)

drivers/regulator/pf9453-regulator.c

134

#define BUCK2_ENMODE_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

139

#define BUCK3_ENMODE_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

144

#define BUCK4_ENMODE_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

150

#define BUCK1OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

153

#define BUCK2OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

154

#define BUCK2OUT_STBY_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

157

#define BUCK3OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

160

#define BUCK4OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

163

#define LDO1_EN_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

164

#define LDO1OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

167

#define LDO2_EN_MASK GENMASK(1, 0)

drivers/regulator/pf9453-regulator.c

168

#define LDO2OUT_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

171

#define LDOSNVS_EN_MASK GENMASK(0, 0)

drivers/regulator/pf9453-regulator.c

172

#define LDOSNVSCFG1_MASK GENMASK(6, 0)

drivers/regulator/pf9453-regulator.c

185

#define WDOG_B_CFG_MASK GENMASK(7, 6)

drivers/regulator/qcom-labibb-regulator.c

37

#define LAB_VOLTAGE_SET_MASK GENMASK(3, 0)

drivers/regulator/qcom-labibb-regulator.c

38

#define IBB_VOLTAGE_SET_MASK GENMASK(5, 0)

drivers/regulator/qcom-labibb-regulator.c

44

#define LAB_PD_CTL_MASK GENMASK(1, 0)

drivers/regulator/qcom-labibb-regulator.c

51

#define LAB_CURRENT_LIMIT_MASK GENMASK(2, 0)

drivers/regulator/qcom-labibb-regulator.c

52

#define IBB_CURRENT_LIMIT_MASK GENMASK(4, 0)

drivers/regulator/qcom-pm8008-regulator.c

23

#define STEP_RATE_MASK GENMASK(1, 0)

drivers/regulator/qcom-refgen-regulator.c

15

#define REFGEN_BIAS_EN_MASK GENMASK(2, 0)

drivers/regulator/qcom-refgen-regulator.c

20

#define REFGEN_BG_CTRL_MASK GENMASK(2, 1)

drivers/regulator/qcom_usb_vbus-regulator.c

19

#define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0)

drivers/regulator/raa215300.c

32

#define RAA215300_INT_MASK_1_ALL GENMASK(5, 0)

drivers/regulator/raa215300.c

33

#define RAA215300_INT_MASK_2_ALL GENMASK(3, 0)

drivers/regulator/raa215300.c

34

#define RAA215300_INT_MASK_3_ALL GENMASK(5, 0)

drivers/regulator/raa215300.c

36

#define RAA215300_INT_MASK_6_ALL GENMASK(7, 0)

drivers/regulator/rpi-panel-v2-regulator.c

26

#define PWM_BL_MASK GENMASK(4, 0)

drivers/regulator/rt4803.c

26

#define RT4803_MODE_MASK GENMASK(1, 0)

drivers/regulator/rt4803.c

27

#define RT4803_VSEL_MASK GENMASK(4, 0)

drivers/regulator/rt4803.c

28

#define RT4803_ILIM_MASK GENMASK(3, 0)

drivers/regulator/rt4831-regulator.c

25

#define RT4831_VOLT_MASK GENMASK(5, 0)

drivers/regulator/rt4831-regulator.c

27

#define RT4831_DSVMODE_MASK GENMASK(7, 5)

drivers/regulator/rt5120-regulator.c

26

#define RT5120_CH1VID_MASK GENMASK(6, 0)

drivers/regulator/rt5133-regulator.c

56

#define RT5133_VENDOR_ID_MASK GENMASK(7, 4)

drivers/regulator/rt5133-regulator.c

67

#define RT5133_STBTDSEL_MASK GENMASK(1, 0)

drivers/regulator/rt5133-regulator.c

70

#define RT5133_LDO_VSEL_MASK GENMASK(7, 5)

drivers/regulator/rt5133-regulator.c

72

#define RT5133_LDO_SOFT_START_MASK GENMASK(1, 0)

drivers/regulator/rt5133-regulator.c

76

#define RT5133_LDO_PGB_EVT_MASK GENMASK(23, 16)

drivers/regulator/rt5133-regulator.c

78

#define RT5133_LDO_OC_EVT_MASK GENMASK(15, 8)

drivers/regulator/rt5133-regulator.c

81

#define RT5133_BASE_EVT_MASK GENMASK(7, 0)

drivers/regulator/rt5133-regulator.c

82

#define RT5133_INTR_CLR_MASK GENMASK(23, 0)

drivers/regulator/rt5190a-regulator.c

28

#define RT5190A_VSEL_MASK GENMASK(6, 0)

drivers/regulator/rt5190a-regulator.c

30

#define RT5190A_BUCK1_DISCHG_MASK GENMASK(1, 0)

drivers/regulator/rt5190a-regulator.c

32

#define RT5190A_OVERVOLT_MASK GENMASK(7, 0)

drivers/regulator/rt5190a-regulator.c

33

#define RT5190A_UNDERVOLT_MASK GENMASK(15, 8)

drivers/regulator/rt5739.c

32

#define RT5739_VSEL_MASK GENMASK(7, 0)

drivers/regulator/rt5739.c

35

#define RT5739_VID_MASK GENMASK(7, 5)

drivers/regulator/rt5739.c

36

#define RT5739_DID_MASK GENMASK(3, 0)

drivers/regulator/rt5759-regulator.c

20

#define RT5759_TSTEP_MASK GENMASK(3, 2)

drivers/regulator/rt5759-regulator.c

21

#define RT5759_VSEL_MASK GENMASK(6, 0)

drivers/regulator/rt5759-regulator.c

27

#define RT5957_OCLVL_MASK GENMASK(7, 6)

drivers/regulator/rt5759-regulator.c

29

#define RT5957_OTLVL_MASK GENMASK(5, 4)

drivers/regulator/rt6160-regulator.c

24

#define RT6160_RAMPRATE_MASK GENMASK(1, 0)

drivers/regulator/rt6160-regulator.c

25

#define RT6160_VID_MASK GENMASK(7, 4)

drivers/regulator/rt6160-regulator.c

26

#define RT6160_VSEL_MASK GENMASK(6, 0)

drivers/regulator/rt6245-regulator.c

20

#define RT6245_VOUT_MASK GENMASK(6, 0)

drivers/regulator/rt6245-regulator.c

21

#define RT6245_SLEW_MASK GENMASK(2, 0)

drivers/regulator/rt6245-regulator.c

23

#define RT6245_CODE_MASK GENMASK(6, 0)

drivers/regulator/rt8092.c

30

#define RT8092_VSEL_MASK GENMASK(6, 0)

drivers/regulator/rt8092.c

37

#define RT8092_VBANK_MASK GENMASK(1, 0)

drivers/regulator/rtmv20-regulator.c

32

#define RTMV20_VID_MASK GENMASK(7, 4)

drivers/regulator/rtmv20-regulator.c

34

#define RTMV20_LDCURR_MASK GENMASK(7, 0)

drivers/regulator/rtmv20-regulator.c

35

#define RTMV20_DELAY_MASK GENMASK(9, 0)

drivers/regulator/rtmv20-regulator.c

36

#define RTMV20_WIDTH_MASK GENMASK(13, 0)

drivers/regulator/rtmv20-regulator.c

37

#define RTMV20_WIDTH2_MASK GENMASK(7, 0)

drivers/regulator/rtmv20-regulator.c

38

#define RTMV20_LBPLVL_MASK GENMASK(3, 0)

drivers/regulator/rtq2134-regulator.c

55

#define RTQ2134_RSPUP_MASK GENMASK(6, 4)

drivers/regulator/rtq2134-regulator.c

58

#define RTQ2134_BUCKDVS_CTRL_MASK GENMASK(1, 0)

drivers/regulator/rtq2208-regulator.c

37

#define RTQ2208_BUCK_NR_MTP_SEL_MASK GENMASK(7, 0)

drivers/regulator/rtq2208-regulator.c

40

#define RTQ2208_BUCK_RSPUP_MASK GENMASK(6, 4)

drivers/regulator/rtq2208-regulator.c

41

#define RTQ2208_BUCK_RSPDN_MASK GENMASK(2, 0)

drivers/regulator/rtq2208-regulator.c

47

#define RTQ2208_BUCK_RAMP_SEL_MASK GENMASK(2, 0)

drivers/regulator/rtq2208-regulator.c

53

#define RTQ2208_MASK_BUCKPH_GROUP1 GENMASK(6, 4)

drivers/regulator/rtq2208-regulator.c

54

#define RTQ2208_MASK_BUCKPH_GROUP2 GENMASK(2, 0)

drivers/regulator/rtq6752-regulator.c

29

#define RTQ6752_VOUT_MASK GENMASK(5, 0)

drivers/regulator/s2mps11.c

1000

PCTRLSEL12, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1002

PCTRLSEL12, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1004

PCTRLSEL13, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1006

PCTRLSEL13, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1047

#define s2mpg11_buck_to_ramp_mask(n) (GENMASK(3, 2) << (((n) % 2) * 4))

drivers/regulator/s2mps11.c

1053

S2MPG11_PMIC_##_vsel_reg, GENMASK(7, 0), \

drivers/regulator/s2mps11.c

1100

BUCK##_num##_CTRL, GENMASK(7, 6), \

drivers/regulator/s2mps11.c

1113

S2MPG11_PMIC_BB_OUT1, GENMASK(6, 0), \

drivers/regulator/s2mps11.c

1139

s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \

drivers/regulator/s2mps11.c

1148

s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \

drivers/regulator/s2mps11.c

1149

L##_num##S_CTRL, GENMASK(7, 6), \

drivers/regulator/s2mps11.c

1157

s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \

drivers/regulator/s2mps11.c

1159

6250, S2MPG11_PMIC_##_r_reg, GENMASK(1, 0), \

drivers/regulator/s2mps11.c

1210

OUT1, GENMASK(7, 6), DVS_RAMP1,

drivers/regulator/s2mps11.c

1211

PCTRLSEL1, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1213

OUT1, GENMASK(7, 6), DVS_RAMP1,

drivers/regulator/s2mps11.c

1214

PCTRLSEL1, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1216

OUT1, GENMASK(7, 6), DVS_RAMP2,

drivers/regulator/s2mps11.c

1217

PCTRLSEL2, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1221

OUT, GENMASK(7, 6), DVS_RAMP3,

drivers/regulator/s2mps11.c

1222

PCTRLSEL2, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1228

OUT1, GENMASK(7, 6), DVS_RAMP4,

drivers/regulator/s2mps11.c

1229

PCTRLSEL3, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1231

OUT1, GENMASK(7, 6), DVS_RAMP5,

drivers/regulator/s2mps11.c

1232

PCTRLSEL3, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1235

s2mpg11_regulator_desc_bucka(D, d, DVS_RAMP6, PCTRLSEL4, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1236

s2mpg11_regulator_desc_bucka(A, a, DVS_RAMP6, PCTRLSEL4, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1238

GENMASK(5, 4), DVS_SYNC_CTRL1,

drivers/regulator/s2mps11.c

1239

PCTRLSEL5, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1241

GENMASK(7, 6), DVS_SYNC_CTRL2,

drivers/regulator/s2mps11.c

1242

PCTRLSEL5, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

1249

PCTRLSEL6, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

1255

PCTRLSEL6, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

697

#define s2mpg10_buck_to_ramp_mask(n) (GENMASK(1, 0) << (((n) % 4) * 2))

drivers/regulator/s2mps11.c

738

S2MPG10_PMIC_B##_num##M_OUT1, GENMASK(7, 0), \

drivers/regulator/s2mps11.c

739

S2MPG10_PMIC_B##_num##M_CTRL, GENMASK(7, 6), \

drivers/regulator/s2mps11.c

856

s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \

drivers/regulator/s2mps11.c

865

s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \

drivers/regulator/s2mps11.c

866

L##_num##M_CTRL, GENMASK(7, 6), \

drivers/regulator/s2mps11.c

874

s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \

drivers/regulator/s2mps11.c

876

6250, S2MPG10_PMIC_##_r_reg, GENMASK(1, 0), \

drivers/regulator/s2mps11.c

927

PCTRLSEL1, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

929

PCTRLSEL1, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

931

PCTRLSEL2, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

933

PCTRLSEL2, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

935

PCTRLSEL3, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

937

PCTRLSEL3, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

939

PCTRLSEL4, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

943

PCTRLSEL4, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

950

CTRL, GENMASK(6, 0),

drivers/regulator/s2mps11.c

953

GENMASK(5, 4), s2mpg10_ldo_ramp_table,

drivers/regulator/s2mps11.c

958

PCTRLSEL5, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

960

PCTRLSEL5, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

962

PCTRLSEL6, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

964

PCTRLSEL6, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

971

CTRL, GENMASK(6, 0),

drivers/regulator/s2mps11.c

972

LDO_CTRL1, GENMASK(4, 3),

drivers/regulator/s2mps11.c

974

GENMASK(7, 6), s2mpg10_ldo_ramp_table,

drivers/regulator/s2mps11.c

976

S2MPG10_PMIC_PCTRLSEL7, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

978

PCTRLSEL7, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

980

PCTRLSEL8, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

982

PCTRLSEL8, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

984

GENMASK(1, 0), DVS_SYNC_CTRL3,

drivers/regulator/s2mps11.c

985

PCTRLSEL9, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

987

GENMASK(3, 2), DVS_SYNC_CTRL4,

drivers/regulator/s2mps11.c

988

PCTRLSEL9, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

990

GENMASK(5, 4), DVS_SYNC_CTRL5,

drivers/regulator/s2mps11.c

991

PCTRLSEL10, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

993

PCTRLSEL10, GENMASK(7, 4)),

drivers/regulator/s2mps11.c

995

GENMASK(7, 6), DVS_SYNC_CTRL6,

drivers/regulator/s2mps11.c

996

PCTRLSEL11, GENMASK(3, 0)),

drivers/regulator/s2mps11.c

998

PCTRLSEL11, GENMASK(7, 4)),

drivers/regulator/sc2731-regulator.c

83

#define SC2731_DCDC_CPU0_VOL_MASK GENMASK(8, 0)

drivers/regulator/sc2731-regulator.c

84

#define SC2731_DCDC_CPU1_VOL_MASK GENMASK(8, 0)

drivers/regulator/sc2731-regulator.c

85

#define SC2731_DCDC_RF_VOL_MASK GENMASK(8, 0)

drivers/regulator/sc2731-regulator.c

86

#define SC2731_LDO_CAMA0_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

87

#define SC2731_LDO_CAMA1_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

88

#define SC2731_LDO_CAMMOT_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

89

#define SC2731_LDO_VLDO_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

90

#define SC2731_LDO_EMMCCORE_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

91

#define SC2731_LDO_SDCORE_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

92

#define SC2731_LDO_SDIO_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

93

#define SC2731_LDO_WIFIPA_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

94

#define SC2731_LDO_USB33_VOL_MASK GENMASK(7, 0)

drivers/regulator/sc2731-regulator.c

95

#define SC2731_LDO_CAMD0_VOL_MASK GENMASK(6, 0)

drivers/regulator/sc2731-regulator.c

96

#define SC2731_LDO_CAMD1_VOL_MASK GENMASK(6, 0)

drivers/regulator/sc2731-regulator.c

97

#define SC2731_LDO_CON_VOL_MASK GENMASK(6, 0)

drivers/regulator/sc2731-regulator.c

98

#define SC2731_LDO_CAMIO_VOL_MASK GENMASK(6, 0)

drivers/regulator/sc2731-regulator.c

99

#define SC2731_LDO_SRAM_VOL_MASK GENMASK(6, 0)

drivers/regulator/spacemit-p1.c

65

#define BUCK_MASK GENMASK(7, 0)

drivers/regulator/spacemit-p1.c

66

#define LDO_MASK GENMASK(6, 0)

drivers/regulator/stm32-vrefbuf.c

23

#define STM32_VRS GENMASK(6, 4)

drivers/regulator/sun20i-regulator.c

62

.vsel_mask = GENMASK(7, 0),

drivers/regulator/sun20i-regulator.c

75

.vsel_mask = GENMASK(15, 8),

drivers/regulator/tps6286x-regulator.c

16

#define TPS6286X_VOUT1_VO1_SET GENMASK(7, 0)

drivers/regulator/tps6287x-regulator.c

22

#define TPS6287X_CTRL1_VRAMP GENMASK(1, 0)

drivers/regulator/tps6287x-regulator.c

26

#define TPS6287X_CTRL2_VRANGE GENMASK(3, 2)

drivers/remoteproc/imx_dsp_rproc.c

823

affected_mask = GENMASK(8 * r, 0);

drivers/remoteproc/imx_dsp_rproc.c

871

affected_mask = GENMASK(8 * r, 0);

drivers/remoteproc/meson_mx_ao_arc.c

24

#define AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU GENMASK(3, 0)

drivers/remoteproc/meson_mx_ao_arc.c

28

#define AO_REMAP_REG1_REMAP_AHB_SRAM_BITS_17_14_FOR_MEDIA_CPU GENMASK(3, 0)

drivers/remoteproc/meson_mx_ao_arc.c

31

#define AO_CPU_CNTL_AHB_SRAM_BITS_31_20 GENMASK(28, 16)

drivers/remoteproc/meson_mx_ao_arc.c

39

#define AO_SECURE_REG0_AHB_SRAM_BITS_19_12 GENMASK(15, 8)

drivers/remoteproc/mtk_common.h

62

#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)

drivers/remoteproc/mtk_scp.c

439

writel(GENMASK(i, 0) & ~reserved_mask, addr);

drivers/remoteproc/mtk_scp.c

449

writel(GENMASK(i, 0) & ~reserved_mask, addr);

drivers/remoteproc/qcom_q6v5_adsp.c

39

#define EVB_MASK GENMASK(27, 4)

drivers/remoteproc/qcom_q6v5_mss.c

118

#define QDSP6V55_MEM_BITS GENMASK(16, 8)

drivers/remoteproc/qcom_q6v5_wcss.c

60

#define QDSS_Q6_MEMORIES GENMASK(15, 0)

drivers/remoteproc/qcom_q6v5_wcss.c

68

#define Q6SS_XO_CBCR GENMASK(5, 3)

drivers/remoteproc/qcom_q6v5_wcss.c

69

#define Q6SS_SLEEP_CBCR GENMASK(5, 2)

drivers/remoteproc/qcom_q6v5_wcss.c

82

#define SSCAON_BUS_MUX_MASK GENMASK(18, 16)

drivers/remoteproc/qcom_wcnss.c

51

#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)

drivers/remoteproc/st_remoteproc.c

264

.bootaddr_mask = GENMASK(28, 1),

drivers/remoteproc/st_remoteproc.c

270

.bootaddr_mask = GENMASK(31, 6),

drivers/remoteproc/st_slim_rproc.c

35

#define SLIM_REV_ID_MIN_MASK GENMASK(15, 8)

drivers/remoteproc/st_slim_rproc.c

37

#define SLIM_REV_ID_MAJ_MASK GENMASK(23, 16)

drivers/resctrl/mpam_devices.c

1337

bm = GENMASK(msb, 0);

drivers/resctrl/mpam_devices.c

1349

u16 dspri = GENMASK(rprops->dspri_wd, 0);

drivers/resctrl/mpam_devices.c

1350

u16 intpri = GENMASK(rprops->intpri_wd, 0);

drivers/resctrl/mpam_devices.c

2407

comp->cfg[i].cpbm = GENMASK(cprops->cpbm_wd - 1, 0);

drivers/resctrl/mpam_devices.c

2409

comp->cfg[i].mbw_pbm = GENMASK(cprops->mbw_pbm_bits - 1, 0);

drivers/resctrl/mpam_devices.c

2411

comp->cfg[i].mbw_max = GENMASK(15, 16 - cprops->bwa_wd);

drivers/resctrl/mpam_internal.h

447

#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

448

#define MPAMF_IDR_PMG_MAX GENMASK(23, 16)

drivers/resctrl/mpam_internal.h

460

#define MPAMF_IDR_RIS_MAX GENMASK(59, 56)

drivers/resctrl/mpam_internal.h

468

#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

471

#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)

drivers/resctrl/mpam_internal.h

472

#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)

drivers/resctrl/mpam_internal.h

479

#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)

drivers/resctrl/mpam_internal.h

485

#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)

drivers/resctrl/mpam_internal.h

490

#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)

drivers/resctrl/mpam_internal.h

493

#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)

drivers/resctrl/mpam_internal.h

496

#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

506

#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

513

#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

516

#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)

drivers/resctrl/mpam_internal.h

517

#define MPAMF_IIDR_REVISION GENMASK(15, 12)

drivers/resctrl/mpam_internal.h

518

#define MPAMF_IIDR_VARIANT GENMASK(19, 16)

drivers/resctrl/mpam_internal.h

519

#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)

drivers/resctrl/mpam_internal.h

522

#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)

drivers/resctrl/mpam_internal.h

523

#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)

drivers/resctrl/mpam_internal.h

526

#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

528

#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)

drivers/resctrl/mpam_internal.h

531

#define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

535

#define MPAMCFG_CMAX_CMAX GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

538

#define MPAMCFG_CMIN_CMIN GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

544

#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

550

#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

557

#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)

drivers/resctrl/mpam_internal.h

558

#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)

drivers/resctrl/mpam_internal.h

561

#define MPAMCFG_PRI_INTPRI GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

562

#define MPAMCFG_PRI_DSPRI GENMASK(31, 16)

drivers/resctrl/mpam_internal.h

568

#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

574

#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

578

#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

579

#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)

drivers/resctrl/mpam_internal.h

582

#define MPAMF_ESR_PARTID_MON GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

583

#define MPAMF_ESR_PMG GENMASK(23, 16)

drivers/resctrl/mpam_internal.h

584

#define MPAMF_ESR_ERRCODE GENMASK(27, 24)

drivers/resctrl/mpam_internal.h

586

#define MPAMF_ESR_RIS GENMASK(35, 32)

drivers/resctrl/mpam_internal.h

611

#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)

drivers/resctrl/mpam_internal.h

616

#define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20)

drivers/resctrl/mpam_internal.h

621

#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)

drivers/resctrl/mpam_internal.h

633

#define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0)

drivers/resctrl/mpam_internal.h

634

#define MSMON_CFG_x_FLT_PMG GENMASK(23, 16)

drivers/resctrl/mpam_internal.h

636

#define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)

drivers/resctrl/mpam_internal.h

649

#define MSMON___VALUE GENMASK(30, 0)

drivers/resctrl/mpam_internal.h

652

#define MSMON___L_VALUE GENMASK(43, 0)

drivers/resctrl/mpam_internal.h

653

#define MSMON___LWD_VALUE GENMASK(62, 0)

drivers/reset/reset-eyeq.c

97

#define ID_DOMAIN_MASK GENMASK(7, 0)

drivers/reset/reset-eyeq.c

98

#define ID_OFFSET_MASK GENMASK(31, 8)

drivers/reset/reset-hsdk.c

47

#define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)

drivers/reset/reset-intel-gw.c

18

#define REG_OFFSET_MASK GENMASK(31, 16)

drivers/reset/reset-intel-gw.c

19

#define BIT_OFFSET_MASK GENMASK(15, 8)

drivers/reset/reset-intel-gw.c

20

#define STAT_BIT_OFFSET_MASK GENMASK(7, 0)

drivers/reset/reset-npcm.c

68

#define NPCM_MASK_RESETS GENMASK(4, 0)

drivers/reset/reset-th1520.c

95

#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0)

drivers/rtc/rtc-ab-eoz9.c

19

#define ABEOZ9_REG_CTRL1_MASK GENMASK(7, 0)

drivers/rtc/rtc-ab-eoz9.c

62

#define ABEOZ9_BIT_ALARM_SEC GENMASK(6, 0)

drivers/rtc/rtc-ab-eoz9.c

64

#define ABEOZ9_BIT_ALARM_MIN GENMASK(6, 0)

drivers/rtc/rtc-ab-eoz9.c

67

#define ABEOZ9_BIT_ALARM_HOURS GENMASK(5, 0)

drivers/rtc/rtc-ab-eoz9.c

69

#define ABEOZ9_BIT_ALARM_DAYS GENMASK(5, 0)

drivers/rtc/rtc-ab-eoz9.c

71

#define ABEOZ9_BIT_ALARM_WEEKDAYS GENMASK(2, 0)

drivers/rtc/rtc-ab-eoz9.c

73

#define ABEOZ9_BIT_ALARM_MONTHS GENMASK(4, 0)

drivers/rtc/rtc-ab-eoz9.c

84

#define ABEOZ9_REG_EEPROM_MASK GENMASK(8, 0)

drivers/rtc/rtc-abx80x.c

100

#define NVMEM_ADDR_UPPER GENMASK(7, 6)

drivers/rtc/rtc-abx80x.c

93

#define ABX8XX_EXTRAM_XADS GENMASK(1, 0)

drivers/rtc/rtc-abx80x.c

99

#define NVMEM_ADDR_LOWER GENMASK(5, 0)

drivers/rtc/rtc-ac100.c

37

#define AC100_RTC_SEC_MASK GENMASK(6, 0)

drivers/rtc/rtc-ac100.c

38

#define AC100_RTC_MIN_MASK GENMASK(6, 0)

drivers/rtc/rtc-ac100.c

39

#define AC100_RTC_HOU_MASK GENMASK(5, 0)

drivers/rtc/rtc-ac100.c

40

#define AC100_RTC_WEE_MASK GENMASK(2, 0)

drivers/rtc/rtc-ac100.c

41

#define AC100_RTC_DAY_MASK GENMASK(5, 0)

drivers/rtc/rtc-ac100.c

42

#define AC100_RTC_MON_MASK GENMASK(4, 0)

drivers/rtc/rtc-ac100.c

43

#define AC100_RTC_YEA_MASK GENMASK(7, 0)

drivers/rtc/rtc-ac100.c

50

#define AC100_ALM_SEC_MASK GENMASK(6, 0)

drivers/rtc/rtc-ac100.c

51

#define AC100_ALM_MIN_MASK GENMASK(6, 0)

drivers/rtc/rtc-ac100.c

52

#define AC100_ALM_HOU_MASK GENMASK(5, 0)

drivers/rtc/rtc-ac100.c

53

#define AC100_ALM_WEE_MASK GENMASK(2, 0)

drivers/rtc/rtc-ac100.c

54

#define AC100_ALM_DAY_MASK GENMASK(5, 0)

drivers/rtc/rtc-ac100.c

55

#define AC100_ALM_MON_MASK GENMASK(4, 0)

drivers/rtc/rtc-ac100.c

56

#define AC100_ALM_YEA_MASK GENMASK(7, 0)

drivers/rtc/rtc-amlogic-a4.c

31

#define RTC_MATCH_COUNTER GENMASK(18, 0)

drivers/rtc/rtc-amlogic-a4.c

32

#define RTC_SEC_ADJUST_CTRL GENMASK(20, 19)

drivers/rtc/rtc-amlogic-a4.c

44

#define RTC_OSCIN_OUT_CFG GENMASK(29, 28)

drivers/rtc/rtc-amlogic-a4.c

45

#define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0)

drivers/rtc/rtc-amlogic-a4.c

46

#define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12)

drivers/rtc/rtc-at91rm9200.c

40

#define AT91_RTC_CORRECTION GENMASK(14, 8) /* Slow clock correction */

drivers/rtc/rtc-at91rm9200.c

44

#define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */

drivers/rtc/rtc-at91rm9200.c

45

#define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */

drivers/rtc/rtc-at91rm9200.c

46

#define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */

drivers/rtc/rtc-at91rm9200.c

50

#define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */

drivers/rtc/rtc-at91rm9200.c

51

#define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */

drivers/rtc/rtc-at91rm9200.c

52

#define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */

drivers/rtc/rtc-at91rm9200.c

53

#define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */

drivers/rtc/rtc-at91rm9200.c

54

#define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */

drivers/rtc/rtc-atcrtc100.c

30

#define ID_MSK GENMASK(31, 8)

drivers/rtc/rtc-atcrtc100.c

34

#define SEC_MSK GENMASK(5, 0)

drivers/rtc/rtc-atcrtc100.c

35

#define MIN_MSK GENMASK(11, 6)

drivers/rtc/rtc-atcrtc100.c

36

#define HOUR_MSK GENMASK(16, 12)

drivers/rtc/rtc-atcrtc100.c

37

#define DAY_MSK GENMASK(31, 17)

drivers/rtc/rtc-cadence.c

62

#define CDNS_RTC_TIME_H GENMASK(7, 0)

drivers/rtc/rtc-cadence.c

63

#define CDNS_RTC_TIME_S GENMASK(14, 8)

drivers/rtc/rtc-cadence.c

64

#define CDNS_RTC_TIME_M GENMASK(22, 16)

drivers/rtc/rtc-cadence.c

65

#define CDNS_RTC_TIME_HR GENMASK(29, 24)

drivers/rtc/rtc-cadence.c

70

#define CDNS_RTC_CAL_DAY GENMASK(2, 0)

drivers/rtc/rtc-cadence.c

71

#define CDNS_RTC_CAL_M GENMASK(7, 3)

drivers/rtc/rtc-cadence.c

72

#define CDNS_RTC_CAL_D GENMASK(13, 8)

drivers/rtc/rtc-cadence.c

73

#define CDNS_RTC_CAL_Y GENMASK(23, 16)

drivers/rtc/rtc-cadence.c

74

#define CDNS_RTC_CAL_C GENMASK(29, 24)

drivers/rtc/rtc-ds1307.c

152

# define M41TXX_M_CALIBRATION GENMASK(4, 0)

drivers/rtc/rtc-isl12022.c

63

#define ISL12022_INT_FO_MASK GENMASK(3, 0)

drivers/rtc/rtc-isl12022.c

67

#define ISL12022_REG_VB85_MASK GENMASK(5, 3)

drivers/rtc/rtc-isl12022.c

68

#define ISL12022_REG_VB75_MASK GENMASK(2, 0)

drivers/rtc/rtc-loongson.c

38

#define TOY_MON GENMASK(31, 26)

drivers/rtc/rtc-loongson.c

39

#define TOY_DAY GENMASK(25, 21)

drivers/rtc/rtc-loongson.c

40

#define TOY_HOUR GENMASK(20, 16)

drivers/rtc/rtc-loongson.c

41

#define TOY_MIN GENMASK(15, 10)

drivers/rtc/rtc-loongson.c

42

#define TOY_SEC GENMASK(9, 4)

drivers/rtc/rtc-loongson.c

43

#define TOY_MSEC GENMASK(3, 0)

drivers/rtc/rtc-loongson.c

46

#define TOY_MATCH_YEAR GENMASK(31, 26)

drivers/rtc/rtc-loongson.c

47

#define TOY_MATCH_MON GENMASK(25, 22)

drivers/rtc/rtc-loongson.c

48

#define TOY_MATCH_DAY GENMASK(21, 17)

drivers/rtc/rtc-loongson.c

49

#define TOY_MATCH_HOUR GENMASK(16, 12)

drivers/rtc/rtc-loongson.c

50

#define TOY_MATCH_MIN GENMASK(11, 6)

drivers/rtc/rtc-loongson.c

51

#define TOY_MATCH_SEC GENMASK(5, 0)

drivers/rtc/rtc-max31335.c

133

#define MAX31335_RTC_CONFIG1_A1AC GENMASK(5, 4)

drivers/rtc/rtc-max31335.c

140

#define MAX31335_RTC_CONFIG2_CLKO_HZ GENMASK(1, 0)

drivers/rtc/rtc-max31335.c

154

#define MAX31335_TIMER_CONFIG_TFS GENMASK(1, 0)

drivers/rtc/rtc-max31335.c

167

#define MAX31335_TRICKLE_REG_TRICKLE GENMASK(3, 1)

drivers/rtc/rtc-max31335.c

173

#define MAX31335_TS_CONFIG_TSINT GENMASK(2, 0)

drivers/rtc/rtc-meson.c

34

#define RTC_ADDR0_DATA GENMASK(31, 24)

drivers/rtc/rtc-meson.c

44

#define RTC_REG4_STATIC_VALUE GENMASK(7, 0)

drivers/rtc/rtc-mpfs.c

158

writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);

drivers/rtc/rtc-mpfs.c

159

writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);

drivers/rtc/rtc-mpfs.c

50

#define MAX_PRESCALER_COUNT GENMASK(25, 0)

drivers/rtc/rtc-mpfs.c

51

#define DATETIME_UPPER_MASK GENMASK(29, 0)

drivers/rtc/rtc-mpfs.c

52

#define ALARM_UPPER_MASK GENMASK(10, 0)

drivers/rtc/rtc-mt7622.c

43

#define RTC_DEBNCE_MASK GENMASK(2, 0)

drivers/rtc/rtc-mt7622.c

56

#define RTC_AL_ALL GENMASK(7, 0)

drivers/rtc/rtc-pcf2123.c

98

#define OFFSET_MASK GENMASK(6, 0) /* Offset value */

drivers/rtc/rtc-pcf2127.c

53

#define PCF2127_CTRL3_PM GENMASK(7, 5)

drivers/rtc/rtc-pcf8523.c

24

#define PCF8523_CONTROL3_PM GENMASK(7, 5)

drivers/rtc/rtc-pcf85363.c

103

#define OSC_CAP_SEL GENMASK(1, 0)

drivers/rtc/rtc-pcf85363.c

97

#define PIN_IO_INTAPM GENMASK(1, 0)

drivers/rtc/rtc-renesas-rtca3.c

24

#define RTCA3_RSECCNT_SEC GENMASK(6, 0)

drivers/rtc/rtc-renesas-rtca3.c

26

#define RTCA3_RMINCNT_MIN GENMASK(6, 0)

drivers/rtc/rtc-renesas-rtca3.c

28

#define RTCA3_RHRCNT_HR GENMASK(5, 0)

drivers/rtc/rtc-renesas-rtca3.c

31

#define RTCA3_RWKCNT_WK GENMASK(2, 0)

drivers/rtc/rtc-renesas-rtca3.c

33

#define RTCA3_RDAYCNT_DAY GENMASK(5, 0)

drivers/rtc/rtc-renesas-rtca3.c

35

#define RTCA3_RMONCNT_MONTH GENMASK(4, 0)

drivers/rtc/rtc-renesas-rtca3.c

37

#define RTCA3_RYRCNT_YEAR GENMASK(7, 0)

drivers/rtc/rtc-renesas-rtca3.c

41

#define RTCA3_RSECAR_SEC GENMASK(6, 0)

drivers/rtc/rtc-renesas-rtca3.c

43

#define RTCA3_RMINAR_MIN GENMASK(6, 0)

drivers/rtc/rtc-renesas-rtca3.c

45

#define RTCA3_RHRAR_HR GENMASK(5, 0)

drivers/rtc/rtc-renesas-rtca3.c

48

#define RTCA3_RWKAR_DAYW GENMASK(2, 0)

drivers/rtc/rtc-renesas-rtca3.c

50

#define RTCA3_RDAYAR_DATE GENMASK(5, 0)

drivers/rtc/rtc-renesas-rtca3.c

52

#define RTCA3_RMONAR_MON GENMASK(4, 0)

drivers/rtc/rtc-renesas-rtca3.c

54

#define RTCA3_RYRAR_YR GENMASK(7, 0)

drivers/rtc/rtc-renesas-rtca3.c

65

#define RTCA3_RCR1_PES GENMASK(7, 4)

drivers/rtc/rtc-renesas-rtca3.c

79

#define RTCA3_RADJ_ADJ GENMASK(5, 0)

drivers/rtc/rtc-renesas-rtca3.c

81

#define RTCA3_RADJ_PMADJ GENMASK(7, 6)

drivers/rtc/rtc-rv3028.c

57

#define RV3028_CLKOUT_FD_MASK GENMASK(2, 0)

drivers/rtc/rtc-rv3028.c

83

#define RV3028_BACKUP_TCR_MASK GENMASK(1,0)

drivers/rtc/rtc-rv3028.c

84

#define RV3028_BACKUP_BSM GENMASK(3,2)

drivers/rtc/rtc-rv3032.c

66

#define RV3032_TLSB_TEMP GENMASK(7, 4)

drivers/rtc/rtc-rv3032.c

68

#define RV3032_CLKOUT2_HFD_MSK GENMASK(4, 0)

drivers/rtc/rtc-rv3032.c

69

#define RV3032_CLKOUT2_FD_MSK GENMASK(6, 5)

drivers/rtc/rtc-rv3032.c

82

#define RV3032_PMU_TCM GENMASK(1, 0)

drivers/rtc/rtc-rv3032.c

83

#define RV3032_PMU_TCR GENMASK(3, 2)

drivers/rtc/rtc-rv3032.c

84

#define RV3032_PMU_BSM GENMASK(5, 4)

drivers/rtc/rtc-rv3032.c

90

#define RV3032_OFFSET_MSK GENMASK(5, 0)

drivers/rtc/rtc-rv8803.c

55

#define RX8803_CTRL_CSEL GENMASK(7, 6)

drivers/rtc/rtc-s32g.c

21

#define RTCC_CLKSEL_MASK GENMASK(13, 12)

drivers/rtc/rtc-s32g.c

29

#define APIVAL_MAX_VAL GENMASK(31, 0)

drivers/rtc/rtc-sc27xx.c

62

#define SPRD_RTC_INT_MASK GENMASK(15, 0)

drivers/rtc/rtc-sc27xx.c

78

#define SPRD_RTC_SEC_MASK GENMASK(5, 0)

drivers/rtc/rtc-sc27xx.c

79

#define SPRD_RTC_MIN_MASK GENMASK(5, 0)

drivers/rtc/rtc-sc27xx.c

80

#define SPRD_RTC_HOUR_MASK GENMASK(4, 0)

drivers/rtc/rtc-sc27xx.c

81

#define SPRD_RTC_DAY_MASK GENMASK(15, 0)

drivers/rtc/rtc-sc27xx.c

84

#define SPRD_RTC_ALMLOCK_MASK GENMASK(7, 0)

drivers/rtc/rtc-sc27xx.c

94

#define SPRD_RTC_POWER_STS_CLEAR GENMASK(7, 0)

drivers/rtc/rtc-spacemit-p1.c

77

t->tm_sec = time[0] & GENMASK(5, 0);

drivers/rtc/rtc-spacemit-p1.c

78

t->tm_min = time[1] & GENMASK(5, 0);

drivers/rtc/rtc-spacemit-p1.c

79

t->tm_hour = time[2] & GENMASK(4, 0);

drivers/rtc/rtc-spacemit-p1.c

80

t->tm_mday = (time[3] & GENMASK(4, 0)) + 1;

drivers/rtc/rtc-spacemit-p1.c

81

t->tm_mon = time[4] & GENMASK(3, 0);

drivers/rtc/rtc-spacemit-p1.c

82

t->tm_year = (time[5] & GENMASK(5, 0)) + 100;

drivers/rtc/rtc-ssd202d.c

44

#define ISO_CTRL_MASK GENMASK(2, 0)

drivers/rtc/rtc-stm32.c

101

#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)

drivers/rtc/rtc-stm32.c

112

#define STM32_RTC_RXCIDCFGR_CID GENMASK(6, 4)

drivers/rtc/rtc-stm32.c

29

#define STM32_RTC_TR_SEC GENMASK(6, 0)

drivers/rtc/rtc-stm32.c

31

#define STM32_RTC_TR_MIN GENMASK(14, 8)

drivers/rtc/rtc-stm32.c

33

#define STM32_RTC_TR_HOUR GENMASK(21, 16)

drivers/rtc/rtc-stm32.c

37

#define STM32_RTC_DR_DATE GENMASK(5, 0)

drivers/rtc/rtc-stm32.c

39

#define STM32_RTC_DR_MONTH GENMASK(12, 8)

drivers/rtc/rtc-stm32.c

41

#define STM32_RTC_DR_WDAY GENMASK(15, 13)

drivers/rtc/rtc-stm32.c

43

#define STM32_RTC_DR_YEAR GENMASK(23, 16)

drivers/rtc/rtc-stm32.c

49

#define STM32_RTC_CR_OSEL GENMASK(22, 21)

drivers/rtc/rtc-stm32.c

66

#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)

drivers/rtc/rtc-stm32.c

68

#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)

drivers/rtc/rtc-stm32.c

72

#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)

drivers/rtc/rtc-stm32.c

75

#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)

drivers/rtc/rtc-stm32.c

78

#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)

drivers/rtc/rtc-stm32.c

82

#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)

drivers/rtc/rtc-stm32.c

85

#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)

drivers/rtc/rtc-stm32.c

93

#define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1)

drivers/rtc/rtc-stm32.c

99

#define STM32_RTC_VERR_MINREV GENMASK(3, 0)

drivers/rtc/rtc-sun6i.c

177

val &= GENMASK(4, 0);

drivers/rtc/rtc-sun6i.c

41

#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)

drivers/rtc/rtc-sunplus.c

42

#define BAT_CHARGE_RSEL_MASK_BIT GENMASK(3 + 16, 2 + 16)

drivers/rtc/rtc-sunplus.c

43

#define BAT_CHARGE_RSEL_MASK GENMASK(3, 2)

drivers/rtc/rtc-sunplus.c

49

#define BAT_CHARGE_DSEL_MASK GENMASK(1, 1)

drivers/slimbus/slimbus.h

29

#define SLIM_MSG_MT_MASK GENMASK(2, 0)

drivers/slimbus/slimbus.h

31

#define SLIM_MSG_RL_MASK GENMASK(4, 0)

drivers/slimbus/slimbus.h

33

#define SLIM_MSG_MC_MASK GENMASK(6, 0)

drivers/slimbus/slimbus.h

35

#define SLIM_MSG_DT_MASK GENMASK(1, 0)

drivers/soc/amlogic/meson-clk-measure.c

17

#define MSR_DURATION GENMASK(15, 0)

drivers/soc/amlogic/meson-clk-measure.c

22

#define MSR_CLK_SRC GENMASK(26, 20)

drivers/soc/amlogic/meson-clk-measure.c

25

#define MSR_VAL_MASK GENMASK(15, 0)

drivers/soc/amlogic/meson-gx-socinfo.c

22

#define SOCINFO_MAJOR GENMASK(31, 24)

drivers/soc/amlogic/meson-gx-socinfo.c

23

#define SOCINFO_PACK GENMASK(23, 16)

drivers/soc/amlogic/meson-gx-socinfo.c

24

#define SOCINFO_MINOR GENMASK(15, 8)

drivers/soc/amlogic/meson-gx-socinfo.c

25

#define SOCINFO_MISC GENMASK(7, 0)

drivers/soc/apple/mailbox.c

75

#define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52)

drivers/soc/apple/mailbox.c

76

#define APPLE_MBOX_MSG1_INCNT GENMASK(51, 48)

drivers/soc/apple/mailbox.c

77

#define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44)

drivers/soc/apple/mailbox.c

78

#define APPLE_MBOX_MSG1_INPTR GENMASK(43, 40)

drivers/soc/apple/mailbox.c

79

#define APPLE_MBOX_MSG1_MSG GENMASK(31, 0)

drivers/soc/apple/sart.c

30

#define APPLE_SART0_CONFIG_FLAGS GENMASK(28, 24)

drivers/soc/apple/sart.c

31

#define APPLE_SART0_CONFIG_SIZE GENMASK(18, 0)

drivers/soc/apple/sart.c

33

#define APPLE_SART0_CONFIG_SIZE_MAX GENMASK(18, 0)

drivers/soc/apple/sart.c

42

#define APPLE_SART2_CONFIG_FLAGS GENMASK(31, 24)

drivers/soc/apple/sart.c

43

#define APPLE_SART2_CONFIG_SIZE GENMASK(23, 0)

drivers/soc/apple/sart.c

45

#define APPLE_SART2_CONFIG_SIZE_MAX GENMASK(23, 0)

drivers/soc/apple/sart.c

60

#define APPLE_SART3_SIZE_MAX GENMASK(29, 0)

drivers/soc/aspeed/aspeed-lpc-snoop.c

40

#define SNPWADR_CH0_MASK GENMASK(15, 0)

drivers/soc/aspeed/aspeed-lpc-snoop.c

42

#define SNPWADR_CH1_MASK GENMASK(31, 16)

drivers/soc/aspeed/aspeed-lpc-snoop.c

45

#define SNPWDR_CH0_MASK GENMASK(7, 0)

drivers/soc/aspeed/aspeed-lpc-snoop.c

47

#define SNPWDR_CH1_MASK GENMASK(15, 8)

drivers/soc/atmel/soc.c

25

#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)

drivers/soc/atmel/soc.c

26

#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)

drivers/soc/atmel/soc.c

28

#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)

drivers/soc/atmel/soc.c

29

#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)

drivers/soc/cirrus/soc-ep93xx.c

33

#define EP93XX_SYSCON_SYSCFG_REV_MASK GENMASK(31, 28)

drivers/soc/fsl/qe/qmc.c

101

#define QMC_TSA_MASK_MASKH GENMASK(13, 12)

drivers/soc/fsl/qe/qmc.c

102

#define QMC_TSA_MASK_MASKL GENMASK(5, 0)

drivers/soc/fsl/qe/qmc.c

105

#define QMC_TSA_CHANNEL_MASK GENMASK(11, 6)

drivers/soc/fsl/qe/qmc.c

113

#define QMC_SPE_CHAMR_MODE_MASK GENMASK(15, 15)

drivers/soc/fsl/qe/qmc.c

120

#define QMC_SPE_CHAMR_HDLC_NOF_MASK GENMASK(3, 0)

drivers/soc/fsl/qe/qmc.c

150

#define QMC_SPE_TRNSYNC_RX_MASK GENMASK(15, 8)

drivers/soc/fsl/qe/qmc.c

152

#define QMC_SPE_TRNSYNC_TX_MASK GENMASK(7, 0)

drivers/soc/fsl/qe/qmc.c

160

#define QMC_INT_CHANNEL_MASK GENMASK(11, 6)

drivers/soc/fsl/qe/qmc.c

189

#define QMC_BD_TX_PAD_MASK GENMASK(3, 0)

drivers/soc/fsl/qe/qmc.c

32

#define SCC_GSMRL_MODE_MASK GENMASK(3, 0)

drivers/soc/fsl/qe/tsa.c

104

#define TSA_CPM1_SICR_SCC2_MASK GENMASK(15, 8)

drivers/soc/fsl/qe/tsa.c

106

#define TSA_CPM1_SICR_SCC3_MASK GENMASK(23, 16)

drivers/soc/fsl/qe/tsa.c

108

#define TSA_CPM1_SICR_SCC4_MASK GENMASK(31, 24)

drivers/soc/fsl/qe/tsa.c

110

#define TSA_CPM1_SICR_SCC_MASK GENMASK(7, 0)

drivers/soc/fsl/qe/tsa.c

113

#define TSA_CPM1_SICR_SCC_RXCS_MASK GENMASK(5, 3)

drivers/soc/fsl/qe/tsa.c

122

#define TSA_CPM1_SICR_SCC_TXCS_MASK GENMASK(2, 0)

drivers/soc/fsl/qe/tsa.c

26

#define TSA_CPM1_SIRAM_ENTRY_CNT_MASK GENMASK(21, 18)

drivers/soc/fsl/qe/tsa.c

28

#define TSA_CPM1_SIRAM_ENTRY_CSEL_MASK GENMASK(24, 22)

drivers/soc/fsl/qe/tsa.c

39

#define TSA_QE_SIRAM_ENTRY_CNT_MASK GENMASK(4, 2)

drivers/soc/fsl/qe/tsa.c

41

#define TSA_QE_SIRAM_ENTRY_CSEL_MASK GENMASK(8, 5)

drivers/soc/fsl/qe/tsa.c

61

#define TSA_CPM1_SIMODE_TDMA_MASK GENMASK(11, 0)

drivers/soc/fsl/qe/tsa.c

63

#define TSA_CPM1_SIMODE_TDMB_MASK GENMASK(27, 16)

drivers/soc/fsl/qe/tsa.c

65

#define TSA_QE_SIMODE_TDM_SAD_MASK GENMASK(15, 12)

drivers/soc/fsl/qe/tsa.c

67

#define TSA_CPM1_SIMODE_TDM_MASK GENMASK(11, 0)

drivers/soc/fsl/qe/tsa.c

68

#define TSA_SIMODE_TDM_SDM_MASK GENMASK(11, 10)

drivers/soc/fsl/qe/tsa.c

73

#define TSA_SIMODE_TDM_RFSD_MASK GENMASK(9, 8)

drivers/soc/fsl/qe/tsa.c

82

#define TSA_SIMODE_TDM_TFSD_MASK GENMASK(1, 0)

drivers/soc/fsl/qe/tsa.c

89

#define TSA_CPM1_SIGMR_RDM_MASK GENMASK(1, 0)

drivers/soc/gemini/soc-gemini.c

20

#define GEMINI_ARB1_BURST_MASK GENMASK(21, 16)

drivers/soc/gemini/soc-gemini.c

23

#define GEMINI_ARB1_PRIO_MASK GENMASK(9, 0)

drivers/soc/mediatek/mt8173-mmsys.h

24

#define MT8173_DPI0_SEL_IN_MASK GENMASK(1, 0)

drivers/soc/mediatek/mt8186-mmsys.h

8

#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)

drivers/soc/mediatek/mt8188-mmsys.h

22

#define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0)

drivers/soc/mediatek/mt8188-mmsys.h

236

MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

26

#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8)

drivers/soc/mediatek/mt8188-mmsys.h

272

MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

275

MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

278

MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

281

MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

284

MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

287

MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

290

MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

293

MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

296

MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

299

MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

302

MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

305

MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8188-mmsys.h

308

MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),

drivers/soc/mediatek/mt8188-mmsys.h

311

MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),

drivers/soc/mediatek/mt8188-mmsys.h

314

MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

317

MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),

drivers/soc/mediatek/mt8188-mmsys.h

320

MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),

drivers/soc/mediatek/mt8188-mmsys.h

323

MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),

drivers/soc/mediatek/mt8188-mmsys.h

37

#define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0)

drivers/soc/mediatek/mt8188-mmsys.h

43

#define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0)

drivers/soc/mediatek/mt8188-mmsys.h

50

#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)

drivers/soc/mediatek/mt8188-mmsys.h

54

#define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4)

drivers/soc/mediatek/mt8188-mmsys.h

61

#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)

drivers/soc/mediatek/mt8188-mmsys.h

65

#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0)

drivers/soc/mediatek/mt8188-mmsys.h

68

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16)

drivers/soc/mediatek/mt8195-mmsys.h

15

#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)

drivers/soc/mediatek/mt8195-mmsys.h

19

#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)

drivers/soc/mediatek/mt8195-mmsys.h

22

#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)

drivers/soc/mediatek/mt8195-mmsys.h

25

#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)

drivers/soc/mediatek/mt8195-mmsys.h

28

#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)

drivers/soc/mediatek/mt8195-mmsys.h

30

#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)

drivers/soc/mediatek/mt8195-mmsys.h

34

#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)

drivers/soc/mediatek/mt8195-mmsys.h

37

#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)

drivers/soc/mediatek/mt8195-mmsys.h

383

MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

386

MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

389

MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

392

MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

395

MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

398

MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

40

#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)

drivers/soc/mediatek/mt8195-mmsys.h

401

MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

404

MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

407

MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

410

MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

413

MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

416

MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),

drivers/soc/mediatek/mt8195-mmsys.h

419

MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),

drivers/soc/mediatek/mt8195-mmsys.h

422

MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),

drivers/soc/mediatek/mt8195-mmsys.h

425

MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

428

MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

43

#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)

drivers/soc/mediatek/mt8195-mmsys.h

431

MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

434

MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),

drivers/soc/mediatek/mt8195-mmsys.h

46

#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)

drivers/soc/mediatek/mt8195-mmsys.h

53

#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)

drivers/soc/mediatek/mt8195-mmsys.h

57

#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)

drivers/soc/mediatek/mt8195-mmsys.h

60

#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)

drivers/soc/mediatek/mt8195-mmsys.h

66

#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)

drivers/soc/mediatek/mt8195-mmsys.h

68

#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)

drivers/soc/mediatek/mt8195-mmsys.h

72

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)

drivers/soc/mediatek/mt8365-mmsys.h

17

#define MT8365_DISP_MS_IN_OUT_MASK GENMASK(3, 0)

drivers/soc/mediatek/mtk-cmdq-helper.c

256

if (mask != GENMASK(31, 0)) {

drivers/soc/mediatek/mtk-cmdq-helper.c

494

if (mask != GENMASK(31, 0)) {

drivers/soc/mediatek/mtk-devapc.c

67

writel(GENMASK(31, 0), reg + 4 * i);

drivers/soc/mediatek/mtk-devapc.c

69

writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),

drivers/soc/mediatek/mtk-devapc.c

82

val = GENMASK(31, 0);

drivers/soc/mediatek/mtk-devapc.c

91

val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,

drivers/soc/mediatek/mtk-devapc.c

94

val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,

drivers/soc/mediatek/mtk-dvfsrc.c

20

#define DVFSRC_V4_BASIC_CTRL_OPP_COUNT GENMASK(26, 20)

drivers/soc/mediatek/mtk-dvfsrc.c

23

#define DVFSRC_V1_LEVEL_TARGET_LEVEL GENMASK(15, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

25

#define DVFSRC_V1_LEVEL_CURRENT_LEVEL GENMASK(31, 16)

drivers/soc/mediatek/mtk-dvfsrc.c

27

#define DVFSRC_V4_LEVEL_TARGET_LEVEL GENMASK(15, 8)

drivers/soc/mediatek/mtk-dvfsrc.c

31

#define DVFSRC_V1_SW_REQ2_DRAM_LEVEL GENMASK(1, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

32

#define DVFSRC_V1_SW_REQ2_VCORE_LEVEL GENMASK(3, 2)

drivers/soc/mediatek/mtk-dvfsrc.c

34

#define DVFSRC_V2_SW_REQ_DRAM_LEVEL GENMASK(3, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

35

#define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4)

drivers/soc/mediatek/mtk-dvfsrc.c

37

#define DVFSRC_V4_SW_REQ_EMI_LEVEL GENMASK(3, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

38

#define DVFSRC_V4_SW_REQ_DRAM_LEVEL GENMASK(15, 12)

drivers/soc/mediatek/mtk-dvfsrc.c

41

#define DVFSRC_V2_VCORE_REQ_VSCP_LEVEL GENMASK(14, 12)

drivers/soc/mediatek/mtk-dvfsrc.c

44

#define DVFSRC_V4_GEAR_TARGET_DRAM GENMASK(7, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

45

#define DVFSRC_V4_GEAR_TARGET_VCORE GENMASK(15, 8)

drivers/soc/mediatek/mtk-dvfsrc.c

50

#define DVFSRC_V4_GEAR_INFO_VCORE GENMASK(3, 0)

drivers/soc/mediatek/mtk-dvfsrc.c

51

#define DVFSRC_V4_GEAR_INFO_EMI GENMASK(7, 4)

drivers/soc/mediatek/mtk-dvfsrc.c

52

#define DVFSRC_V4_GEAR_INFO_DRAM GENMASK(15, 12)

drivers/soc/mediatek/mtk-mmsys.c

197

mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0),

drivers/soc/mediatek/mtk-mmsys.c

243

GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);

drivers/soc/mediatek/mtk-svs.c

1010

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

103

#define SVSB_INTEN_MONVOPEN GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

111

#define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0)

drivers/soc/mediatek/mtk-svs.c

112

#define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12)

drivers/soc/mediatek/mtk-svs.c

115

#define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0)

drivers/soc/mediatek/mtk-svs.c

116

#define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16)

drivers/soc/mediatek/mtk-svs.c

119

#define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

120

#define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

121

#define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

122

#define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24)

drivers/soc/mediatek/mtk-svs.c

1325

val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1;

drivers/soc/mediatek/mtk-svs.c

1326

svsb->dc_voffset_in = val & GENMASK(15, 0);

drivers/soc/mediatek/mtk-svs.c

1333

GENMASK(15, 0);

drivers/soc/mediatek/mtk-svs.c

1371

svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

1892

val &= GENMASK(nbits - 1, 0);

drivers/soc/mediatek/mtk-svs.c

2024

adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);

drivers/soc/mediatek/mtk-svs.c

2025

adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);

drivers/soc/mediatek/mtk-svs.c

2027

o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2028

o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2029

o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2030

o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2031

o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2032

o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);

drivers/soc/mediatek/mtk-svs.c

2034

degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);

drivers/soc/mediatek/mtk-svs.c

2042

o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);

drivers/soc/mediatek/mtk-svs.c

52

#define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0)

drivers/soc/mediatek/mtk-svs.c

57

#define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

58

#define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

61

#define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

62

#define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

63

#define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

66

#define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

67

#define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

76

#define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

77

#define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

78

#define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

79

#define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24)

drivers/soc/mediatek/mtk-svs.c

84

#define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

88

#define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0)

drivers/soc/mediatek/mtk-svs.c

89

#define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8)

drivers/soc/mediatek/mtk-svs.c

90

#define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16)

drivers/soc/mediatek/mtk-svs.c

91

#define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24)

drivers/soc/mediatek/mtk-svs.c

959

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

971

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

993

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/qcom/cmd-db.c

24

#define SLAVE_ID(addr) FIELD_GET(GENMASK(19, 16), addr)

drivers/soc/qcom/cmd-db.c

25

#define VRM_ADDR(addr) FIELD_GET(GENMASK(19, 4), addr)

drivers/soc/qcom/ice.c

120

int major = FIELD_GET(GENMASK(31, 24), regval);

drivers/soc/qcom/ice.c

121

int minor = FIELD_GET(GENMASK(23, 16), regval);

drivers/soc/qcom/ice.c

122

int step = FIELD_GET(GENMASK(15, 0), regval);

drivers/soc/qcom/ice.c

287

qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_0);

drivers/soc/qcom/ice.c

288

qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_1);

drivers/soc/qcom/ice.c

289

qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_2);

drivers/soc/qcom/ice.c

290

qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_3);

drivers/soc/qcom/ice.c

291

qcom_ice_writel(ice, GENMASK(31, 0), QCOM_ICE_REG_HWKM_BANK0_BBAC_4);

drivers/soc/qcom/ice.c

51

#define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28)

drivers/soc/qcom/llcc-qcom.c

35

#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)

drivers/soc/qcom/llcc-qcom.c

36

#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)

drivers/soc/qcom/llcc-qcom.c

40

#define ATTR2_PRIORITY_MASK GENMASK(14, 12)

drivers/soc/qcom/llcc-qcom.c

41

#define ATTR2_PARENT_SCID_MASK GENMASK(21, 16)

drivers/soc/qcom/llcc-qcom.c

47

#define LLCC_LB_CNT_MASK GENMASK(31, 28)

drivers/soc/qcom/ocmem.c

83

#define OCMEM_HW_VERSION_MAJOR(val) FIELD_GET(GENMASK(31, 28), val)

drivers/soc/qcom/ocmem.c

84

#define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val)

drivers/soc/qcom/ocmem.c

85

#define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val)

drivers/soc/qcom/qcom-geni-se.c

163

#define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24)

drivers/soc/qcom/qcom-geni-se.c

164

#define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21)

drivers/soc/qcom/qcom-geni-se.c

172

#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \

drivers/soc/qcom/qcom-geni-se.c

235

#define FW_REV_VERSION_MSK GENMASK(7, 0)

drivers/soc/qcom/qcom-geni-se.c

238

#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)

drivers/soc/qcom/qcom-geni-se.c

250

#define DEFAULT_CGC_EN GENMASK(6, 0)

drivers/soc/qcom/qcom-geni-se.c

271

#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)

drivers/soc/qcom/qcom_aoss.c

41

#define QMP_STATE_UP GENMASK(15, 0)

drivers/soc/qcom/qcom_aoss.c

42

#define QMP_STATE_DOWN GENMASK(31, 16)

drivers/soc/qcom/qcom_stats.c

36

#define DDR_STATS_CP_IDX(data) FIELD_GET(GENMASK(4, 0), data)

drivers/soc/qcom/qcom_stats.c

37

#define DDR_STATS_LPM_NAME(data) FIELD_GET(GENMASK(7, 0), data)

drivers/soc/qcom/qcom_stats.c

38

#define DDR_STATS_TYPE(data) FIELD_GET(GENMASK(15, 8), data)

drivers/soc/qcom/qcom_stats.c

39

#define DDR_STATS_FREQ(data) FIELD_GET(GENMASK(31, 16), data)

drivers/soc/qcom/ramp_controller.c

22

#define RC_CFG_ACK GENMASK(31, 16)

drivers/soc/qcom/spm.c

34

#define SPM_VCTL_VLVL GENMASK(7, 0)

drivers/soc/qcom/spm.c

35

#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0)

drivers/soc/qcom/spm.c

36

#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0)

drivers/soc/qcom/spm.c

37

#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16)

drivers/soc/qcom/spm.c

40

#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17)

drivers/soc/qcom/spm.c

41

#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10)

drivers/soc/renesas/r9a08g045-sysc.c

36

.revision_mask = GENMASK(31, 28),

drivers/soc/renesas/r9a08g045-sysc.c

37

.specific_id_mask = GENMASK(27, 0),

drivers/soc/renesas/r9a09g047-sys.c

25

#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)

drivers/soc/renesas/r9a09g047-sys.c

81

.revision_mask = GENMASK(31, 28),

drivers/soc/renesas/r9a09g047-sys.c

82

.specific_id_mask = GENMASK(27, 0),

drivers/soc/renesas/r9a09g056-sys.c

26

#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)

drivers/soc/renesas/r9a09g056-sys.c

86

.revision_mask = GENMASK(31, 28),

drivers/soc/renesas/r9a09g056-sys.c

87

.specific_id_mask = GENMASK(27, 0),

drivers/soc/renesas/r9a09g057-sys.c

25

#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)

drivers/soc/renesas/r9a09g057-sys.c

89

.revision_mask = GENMASK(31, 28),

drivers/soc/renesas/r9a09g057-sys.c

90

.specific_id_mask = GENMASK(27, 0),

drivers/soc/rockchip/grf.c

140

{ "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(7, 6), 3) },

drivers/soc/rockchip/grf.c

141

{ "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(9, 8), 3) },

drivers/soc/samsung/gs101-pmu.c

16

#define PMUALIVE_MASK GENMASK(13, 0)

drivers/soc/sunxi/sunxi_sram.c

145

val &= GENMASK(sram_data->width - 1, 0);

drivers/soc/sunxi/sunxi_sram.c

252

mask = GENMASK(sram_data->offset + sram_data->width - 1,

drivers/soc/tegra/cbb/tegra194-cbb.c

100

#define CLUSTER_NOC_MSTR_ID GENMASK(21, 18)

drivers/soc/tegra/cbb/tegra194-cbb.c

102

#define CBB_ERR_OPC GENMASK(4, 1)

drivers/soc/tegra/cbb/tegra194-cbb.c

103

#define CBB_ERR_ERRCODE GENMASK(10, 8)

drivers/soc/tegra/cbb/tegra194-cbb.c

104

#define CBB_ERR_LEN1 GENMASK(27, 16)

drivers/soc/tegra/cbb/tegra194-cbb.c

66

#define CBB_NOC_INITFLOW GENMASK(23, 20)

drivers/soc/tegra/cbb/tegra194-cbb.c

67

#define CBB_NOC_TARGFLOW GENMASK(19, 16)

drivers/soc/tegra/cbb/tegra194-cbb.c

68

#define CBB_NOC_TARG_SUBRANGE GENMASK(15, 9)

drivers/soc/tegra/cbb/tegra194-cbb.c

69

#define CBB_NOC_SEQID GENMASK(8, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

71

#define BPMP_NOC_INITFLOW GENMASK(20, 18)

drivers/soc/tegra/cbb/tegra194-cbb.c

72

#define BPMP_NOC_TARGFLOW GENMASK(17, 13)

drivers/soc/tegra/cbb/tegra194-cbb.c

73

#define BPMP_NOC_TARG_SUBRANGE GENMASK(12, 9)

drivers/soc/tegra/cbb/tegra194-cbb.c

74

#define BPMP_NOC_SEQID GENMASK(8, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

76

#define AON_NOC_INITFLOW GENMASK(22, 21)

drivers/soc/tegra/cbb/tegra194-cbb.c

77

#define AON_NOC_TARGFLOW GENMASK(20, 15)

drivers/soc/tegra/cbb/tegra194-cbb.c

78

#define AON_NOC_TARG_SUBRANGE GENMASK(14, 9)

drivers/soc/tegra/cbb/tegra194-cbb.c

79

#define AON_NOC_SEQID GENMASK(8, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

81

#define SCE_NOC_INITFLOW GENMASK(21, 19)

drivers/soc/tegra/cbb/tegra194-cbb.c

82

#define SCE_NOC_TARGFLOW GENMASK(18, 14)

drivers/soc/tegra/cbb/tegra194-cbb.c

83

#define SCE_NOC_TARG_SUBRANGE GENMASK(13, 9)

drivers/soc/tegra/cbb/tegra194-cbb.c

84

#define SCE_NOC_SEQID GENMASK(8, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

86

#define CBB_NOC_AXCACHE GENMASK(3, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

87

#define CBB_NOC_NON_MOD GENMASK(4, 4)

drivers/soc/tegra/cbb/tegra194-cbb.c

88

#define CBB_NOC_AXPROT GENMASK(7, 5)

drivers/soc/tegra/cbb/tegra194-cbb.c

89

#define CBB_NOC_FALCONSEC GENMASK(9, 8)

drivers/soc/tegra/cbb/tegra194-cbb.c

90

#define CBB_NOC_GRPSEC GENMASK(16, 10)

drivers/soc/tegra/cbb/tegra194-cbb.c

91

#define CBB_NOC_VQC GENMASK(18, 17)

drivers/soc/tegra/cbb/tegra194-cbb.c

92

#define CBB_NOC_MSTR_ID GENMASK(22, 19)

drivers/soc/tegra/cbb/tegra194-cbb.c

93

#define CBB_NOC_AXI_ID GENMASK(30, 23)

drivers/soc/tegra/cbb/tegra194-cbb.c

95

#define CLUSTER_NOC_AXCACHE GENMASK(3, 0)

drivers/soc/tegra/cbb/tegra194-cbb.c

96

#define CLUSTER_NOC_AXPROT GENMASK(6, 4)

drivers/soc/tegra/cbb/tegra194-cbb.c

97

#define CLUSTER_NOC_FALCONSEC GENMASK(8, 7)

drivers/soc/tegra/cbb/tegra194-cbb.c

98

#define CLUSTER_NOC_GRPSEC GENMASK(15, 9)

drivers/soc/tegra/cbb/tegra194-cbb.c

99

#define CLUSTER_NOC_VQC GENMASK(17, 16)

drivers/soc/tegra/cbb/tegra234-cbb.c

54

#define FAB_EM_EL_MSTRID GENMASK(29, 24)

drivers/soc/tegra/cbb/tegra234-cbb.c

55

#define FAB_EM_EL_VQC GENMASK(17, 16)

drivers/soc/tegra/cbb/tegra234-cbb.c

56

#define FAB_EM_EL_GRPSEC GENMASK(14, 8)

drivers/soc/tegra/cbb/tegra234-cbb.c

57

#define FAB_EM_EL_FALCONSEC GENMASK(1, 0)

drivers/soc/tegra/cbb/tegra234-cbb.c

59

#define FAB_EM_EL_FABID GENMASK(20, 16)

drivers/soc/tegra/cbb/tegra234-cbb.c

60

#define FAB_EM_EL_TARGETID GENMASK(7, 0)

drivers/soc/tegra/cbb/tegra234-cbb.c

62

#define FAB_EM_EL_ACCESSID GENMASK(7, 0)

drivers/soc/tegra/cbb/tegra234-cbb.c

64

#define FAB_EM_EL_AXCACHE GENMASK(27, 24)

drivers/soc/tegra/cbb/tegra234-cbb.c

65

#define FAB_EM_EL_AXPROT GENMASK(22, 20)

drivers/soc/tegra/cbb/tegra234-cbb.c

66

#define FAB_EM_EL_BURSTLENGTH GENMASK(19, 12)

drivers/soc/tegra/cbb/tegra234-cbb.c

67

#define FAB_EM_EL_BURSTTYPE GENMASK(9, 8)

drivers/soc/tegra/cbb/tegra234-cbb.c

68

#define FAB_EM_EL_BEATSIZE GENMASK(6, 4)

drivers/soc/tegra/cbb/tegra234-cbb.c

69

#define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)

drivers/soc/tegra/cbb/tegra234-cbb.c

71

#define USRBITS_MSTR_ID GENMASK(29, 24)

drivers/soc/tegra/cbb/tegra234-cbb.c

73

#define REQ_SOCKET_ID GENMASK(27, 24)

drivers/soc/tegra/pmc.c

125

#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)

drivers/soc/ti/k3-ringacc.c

24

#define K3_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)

drivers/soc/ti/k3-ringacc.c

25

#define K3_DMARING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)

drivers/soc/ti/k3-ringacc.c

51

#define K3_RINGACC_RT_OCC_MASK GENMASK(20, 0)

drivers/soc/ti/k3-ringacc.c

53

#define K3_DMARING_RT_DB_ENTRY_MASK GENMASK(7, 0)

drivers/soc/ti/k3-ringacc.c

82

#define K3_RINGACC_PROXY_CFG_THREADS_MASK GENMASK(15, 0)

drivers/soc/ti/k3-socinfo.c

26

#define CTRLMMR_WKUP_JTAGID_VARIANT_MASK GENMASK(31, 28)

drivers/soc/ti/k3-socinfo.c

29

#define CTRLMMR_WKUP_JTAGID_PARTNO_MASK GENMASK(27, 12)

drivers/soc/ti/k3-socinfo.c

32

#define CTRLMMR_WKUP_JTAGID_MFG_MASK GENMASK(11, 1)

drivers/soc/ti/knav_dma.c

32

#define DMA_PRIO_MASK GENMASK(3, 0)

drivers/soc/ti/knav_dma.c

35

#define DMA_RX_TIMEOUT_MASK GENMASK(16, 0)

drivers/soc/ti/knav_dma.c

43

#define CHAN_SOP_OFF_MASK GENMASK(9, 0)

drivers/soc/ti/knav_dma.c

45

#define DESC_TYPE_MASK GENMASK(2, 0)

drivers/soc/ti/knav_dma.c

52

#define CHAN_QNUM_MASK GENMASK(14, 0)

drivers/soc/ti/pruss.h

35

#define PRUSS_GPCFG_PRU_GPI_MODE_MASK GENMASK(1, 0)

drivers/soc/ti/pruss.h

39

#define PRUSS_GPCFG_PRU_MUX_SEL_MASK GENMASK(29, 26)

drivers/soundwire/amd_manager.h

124

#define AMD_SDW_MCP_RESP_RDATA GENMASK(14, 7)

drivers/soundwire/amd_manager.h

127

#define AMD_SDW_MCP_CMD_COMMAND GENMASK(14, 12)

drivers/soundwire/amd_manager.h

128

#define AMD_SDW_MCP_CMD_DEV_ADDR GENMASK(11, 8)

drivers/soundwire/amd_manager.h

129

#define AMD_SDW_MCP_CMD_REG_ADDR_HIGH GENMASK(7, 0)

drivers/soundwire/amd_manager.h

130

#define AMD_SDW_MCP_CMD_REG_ADDR_LOW GENMASK(31, 24)

drivers/soundwire/amd_manager.h

131

#define AMD_SDW_MCP_CMD_REG_DATA GENMASK(14, 7)

drivers/soundwire/amd_manager.h

132

#define AMD_SDW_MCP_SLAVE_STAT_0_3 GENMASK(14, 7)

drivers/soundwire/amd_manager.h

134

#define AMD_SDW_MCP_SLAVE_STATUS_MASK GENMASK(1, 0)

drivers/soundwire/amd_manager.h

135

#define AMD_SDW_MCP_SLAVE_STATUS_BITS GENMASK(3, 2)

drivers/soundwire/amd_manager.h

170

#define AMD_DPN_FRAME_FMT_PFM GENMASK(1, 0)

drivers/soundwire/amd_manager.h

171

#define AMD_DPN_FRAME_FMT_PDM GENMASK(3, 2)

drivers/soundwire/amd_manager.h

173

#define AMD_DPN_FRAME_FMT_BLK_GRP_CTRL GENMASK(6, 5)

drivers/soundwire/amd_manager.h

174

#define AMD_DPN_FRAME_FMT_WORD_LEN GENMASK(12, 7)

drivers/soundwire/amd_manager.h

176

#define AMD_DPN_HCTRL_HSTOP GENMASK(3, 0)

drivers/soundwire/amd_manager.h

177

#define AMD_DPN_HCTRL_HSTART GENMASK(7, 4)

drivers/soundwire/amd_manager.h

178

#define AMD_DPN_OFFSET_CTRL_1 GENMASK(7, 0)

drivers/soundwire/amd_manager.h

179

#define AMD_DPN_OFFSET_CTRL_2 GENMASK(15, 8)

drivers/soundwire/amd_manager.h

180

#define AMD_DPN_CH_EN_LCTRL GENMASK(2, 0)

drivers/soundwire/amd_manager.h

181

#define AMD_DPN_CH_EN_CHMASK GENMASK(10, 3)

drivers/soundwire/amd_manager.h

200

#define AMD_SDW0_DEVICE_STATE_MASK GENMASK(1, 0)

drivers/soundwire/amd_manager.h

201

#define AMD_SDW1_DEVICE_STATE_MASK GENMASK(3, 2)

drivers/soundwire/bus.c

116

*bus->assigned = ~GENMASK(SDW_BROADCAST_DEV_NUM, SDW_ENUM_DEV_NUM);

drivers/soundwire/cadence_master.c

100

#define CDNS_MCP_INT_RESERVED2 GENMASK(6, 4)

drivers/soundwire/cadence_master.c

110

#define CDNS_MCP_SLAVE_STAT_MASK GENMASK(1, 0)

drivers/soundwire/cadence_master.c

118

#define CDNS_MCP_SLAVE_STATUS_BITS GENMASK(3, 0)

drivers/soundwire/cadence_master.c

124

#define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(31, 0)

drivers/soundwire/cadence_master.c

125

#define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(15, 0)

drivers/soundwire/cadence_master.c

132

#define CDNS_MCP_RX_FIFO_AVAIL GENMASK(5, 0)

drivers/soundwire/cadence_master.c

141

#define CDNS_MCP_CMD_COMMAND GENMASK(30, 28)

drivers/soundwire/cadence_master.c

142

#define CDNS_MCP_CMD_DEV_ADDR GENMASK(27, 24)

drivers/soundwire/cadence_master.c

143

#define CDNS_MCP_CMD_REG_ADDR GENMASK(23, 8)

drivers/soundwire/cadence_master.c

144

#define CDNS_MCP_CMD_REG_DATA GENMASK(7, 0)

drivers/soundwire/cadence_master.c

149

#define CDNS_MCP_RESP_RDATA GENMASK(15, 8)

drivers/soundwire/cadence_master.c

170

#define CDNS_DPN_CONFIG_BGC GENMASK(17, 16)

drivers/soundwire/cadence_master.c

171

#define CDNS_DPN_CONFIG_WL GENMASK(12, 8)

drivers/soundwire/cadence_master.c

172

#define CDNS_DPN_CONFIG_PORT_DAT GENMASK(3, 2)

drivers/soundwire/cadence_master.c

173

#define CDNS_DPN_CONFIG_PORT_FLOW GENMASK(1, 0)

drivers/soundwire/cadence_master.c

175

#define CDNS_DPN_SAMPLE_CTRL_SI GENMASK(15, 0)

drivers/soundwire/cadence_master.c

177

#define CDNS_DPN_OFFSET_CTRL_1 GENMASK(7, 0)

drivers/soundwire/cadence_master.c

178

#define CDNS_DPN_OFFSET_CTRL_2 GENMASK(15, 8)

drivers/soundwire/cadence_master.c

180

#define CDNS_DPN_HCTRL_HSTOP GENMASK(3, 0)

drivers/soundwire/cadence_master.c

181

#define CDNS_DPN_HCTRL_HSTART GENMASK(7, 4)

drivers/soundwire/cadence_master.c

182

#define CDNS_DPN_HCTRL_LCTRL GENMASK(10, 8)

drivers/soundwire/cadence_master.c

195

#define CDNS_PDI_CONFIG_CHANNEL GENMASK(15, 8)

drivers/soundwire/cadence_master.c

196

#define CDNS_PDI_CONFIG_PORT GENMASK(4, 0)

drivers/soundwire/cadence_master.c

2248

dma_buffer[3] |= frame_counter & GENMASK(3, 0);

drivers/soundwire/cadence_master.c

2302

dma_buffer[3] |= frame_counter & GENMASK(3, 0);

drivers/soundwire/cadence_master.c

2345

header[0] |= GENMASK(7, 6); /* header is active */

drivers/soundwire/cadence_master.c

2424

header[0] |= GENMASK(7, 6); /* header is active */

drivers/soundwire/cadence_master.c

2476

header[0] &= ~GENMASK(7, 6); /* Set inactive flag in BPT/BRA frame heade */

drivers/soundwire/cadence_master.c

2518

frame = (val >> 24) & GENMASK(3, 0);

drivers/soundwire/cadence_master.c

2528

response = (val >> 3) & GENMASK(1, 0);

drivers/soundwire/cadence_master.c

2597

counter &= GENMASK(3, 0);

drivers/soundwire/cadence_master.c

2700

counter &= GENMASK(3, 0);

drivers/soundwire/cadence_master.c

36

#define CDNS_IP_MCP_CONFIG_MCMD_RETRY GENMASK(27, 24)

drivers/soundwire/cadence_master.c

37

#define CDNS_IP_MCP_CONFIG_MPREQ_DELAY GENMASK(20, 16)

drivers/soundwire/cadence_master.c

41

#define CDNS_IP_MCP_CONFIG_OP GENMASK(2, 0)

drivers/soundwire/cadence_master.c

53

#define CDNS_IP_MCP_CONTROL_RST_DELAY GENMASK(10, 8)

drivers/soundwire/cadence_master.c

66

#define CDNS_MCP_FRAME_SHAPE_COL_MASK GENMASK(2, 0)

drivers/soundwire/cadence_master.c

67

#define CDNS_MCP_FRAME_SHAPE_ROW_MASK GENMASK(7, 3)

drivers/soundwire/cadence_master.c

77

#define CDNS_MCP_CLK_MCLKD_MASK GENMASK(7, 0)

drivers/soundwire/cadence_master.c

88

#define CDNS_MCP_INT_RESERVED1 GENMASK(30, 17)

drivers/soundwire/cadence_master.c

94

#define CDNS_MCP_INT_SLAVE_MASK GENMASK(15, 12)

drivers/soundwire/mipi_disco.c

232

addr &= GENMASK(14, 1);

drivers/soundwire/qcom.c

104

#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)

drivers/soundwire/qcom.c

40

#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)

drivers/soundwire/qcom.c

41

#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)

drivers/soundwire/qcom.c

42

#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)

drivers/soundwire/qcom.c

43

#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)

drivers/soundwire/qcom.c

44

#define SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(17, 10)

drivers/soundwire/qcom.c

45

#define SWRM_V3_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(23, 18)

drivers/soundwire/qcom.c

50

#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)

drivers/soundwire/qcom.c

82

#define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)

drivers/soundwire/qcom.c

83

#define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)

drivers/soundwire/qcom.c

89

#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)

drivers/soundwire/qcom.c

94

#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)

drivers/soundwire/qcom.c

95

#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)

drivers/soundwire/qcom.c

99

#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)

drivers/spi/atmel-quadspi.c

121

#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)

drivers/spi/atmel-quadspi.c

123

#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)

drivers/spi/atmel-quadspi.c

136

#define QSPI_IAR_ADDR GENMASK(31, 0)

drivers/spi/atmel-quadspi.c

139

#define QSPI_ICR_INST_MASK GENMASK(7, 0)

drivers/spi/atmel-quadspi.c

141

#define QSPI_ICR_INST_MASK_SAMA7G5 GENMASK(15, 0)

drivers/spi/atmel-quadspi.c

142

#define QSPI_ICR_OPT_MASK GENMASK(23, 16)

drivers/spi/atmel-quadspi.c

146

#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)

drivers/spi/atmel-quadspi.c

161

#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)

drivers/spi/atmel-quadspi.c

167

#define QSPI_IFR_ADDRL_SAMA7G5 GENMASK(11, 10)

drivers/spi/atmel-quadspi.c

172

#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)

drivers/spi/atmel-quadspi.c

180

#define QSPI_IFR_PROTTYP GENMASK(29, 28)

drivers/spi/atmel-quadspi.c

192

#define QSPI_REFRESH_DELAY_COUNTER GENMASK(31, 0)

drivers/spi/atmel-quadspi.c

195

#define QSPI_WRACNT_NBWRA GENMASK(31, 0)

drivers/spi/atmel-quadspi.c

204

#define QSPI_PCALCFG_CLKDIV GENMASK(6, 4)

drivers/spi/atmel-quadspi.c

205

#define QSPI_PCALCFG_CALCNT GENMASK(16, 8)

drivers/spi/atmel-quadspi.c

206

#define QSPI_PCALCFG_CALP GENMASK(27, 24)

drivers/spi/atmel-quadspi.c

207

#define QSPI_PCALCFG_CALN GENMASK(31, 28)

drivers/spi/atmel-quadspi.c

211

#define QSPI_PCALBP_CALPBP GENMASK(11, 8)

drivers/spi/atmel-quadspi.c

212

#define QSPI_PCALBP_CALNBP GENMASK(19, 16)

drivers/spi/atmel-quadspi.c

215

#define QSPI_TOUT_TCNTM GENMASK(15, 0)

drivers/spi/atmel-quadspi.c

221

#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)

drivers/spi/atmel-quadspi.c

226

#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)

drivers/spi/atmel-quadspi.c

87

#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)

drivers/spi/atmel-quadspi.c

91

#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)

drivers/spi/atmel-quadspi.c

94

#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)

drivers/spi/atmel-quadspi.c

96

#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)

drivers/spi/spi-airoha-snfi.c

100

#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)

drivers/spi/spi-airoha-snfi.c

101

#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)

drivers/spi/spi-airoha-snfi.c

108

#define SPI_NFI_SEC_NUM GENMASK(15, 12)

drivers/spi/spi-airoha-snfi.c

130

#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)

drivers/spi/spi-airoha-snfi.c

146

#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)

drivers/spi/spi-airoha-snfi.c

150

#define SPI_NFI_DATA_READ_CMD GENMASK(7, 0)

drivers/spi/spi-airoha-snfi.c

155

#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)

drivers/spi/spi-airoha-snfi.c

162

#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)

drivers/spi/spi-airoha-snfi.c

165

#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)

drivers/spi/spi-airoha-snfi.c

166

#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)

drivers/spi/spi-airoha-snfi.c

38

#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)

drivers/spi/spi-airoha-snfi.c

41

#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)

drivers/spi/spi-airoha-snfi.c

52

#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)

drivers/spi/spi-airoha-snfi.c

53

#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)

drivers/spi/spi-airoha-snfi.c

65

#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)

drivers/spi/spi-airoha-snfi.c

74

#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)

drivers/spi/spi-airoha-snfi.c

77

#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)

drivers/spi/spi-airoha-snfi.c

97

#define SPI_NFI_OPMODE GENMASK(14, 12)

drivers/spi/spi-amd.c

49

#define AMD_SPI_ALT_SPD_MASK GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)

drivers/spi/spi-amd.c

506

GENMASK(7, 0));

drivers/spi/spi-amd.c

51

#define AMD_SPI_SPI100_MASK GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)

drivers/spi/spi-amd.c

525

hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes) + 3);

drivers/spi/spi-amd.c

54

#define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT)

drivers/spi/spi-amd.c

565

*--dma_buf = addr_val & GENMASK(7, 0);

drivers/spi/spi-amd.c

610

hid_regval = (hid_regval & ~GENMASK(7, 0)) | op->cmd.opcode;

drivers/spi/spi-amd.c

618

hid_regval = (hid_regval & ~GENMASK(31, 8)) | (op->addr.val << 16);

drivers/spi/spi-amd.c

624

hid_regval &= ~GENMASK(4, 0);

drivers/spi/spi-amd.c

627

hid_regval &= ~GENMASK(12, 8);

drivers/spi/spi-amd.c

630

hid_regval = (hid_regval & ~GENMASK(20, 16)) | BIT(17);

drivers/spi/spi-amd.c

633

hid_regval &= ~GENMASK(27, 24);

drivers/spi/spi-amd.c

645

hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes / 4) - 1);

drivers/spi/spi-amd.c

811

hid_regval = (hid_regval & GENMASK(31, 8)) | BIT(18) | BIT(19);

drivers/spi/spi-amd.c

816

amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, (hid_regval | GENMASK(13, 12)) & ~BIT(3));

drivers/spi/spi-amlogic-spifc-a1.c

34

#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28)

drivers/spi/spi-amlogic-spifc-a1.c

35

#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20)

drivers/spi/spi-amlogic-spifc-a1.c

37

#define SPIFC_A1_USER_ADDR_MODE GENMASK(18, 17)

drivers/spi/spi-amlogic-spifc-a1.c

38

#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15)

drivers/spi/spi-amlogic-spifc-a1.c

40

#define SPIFC_A1_USER_DOUT_MODE GENMASK(11, 10)

drivers/spi/spi-amlogic-spifc-a1.c

41

#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0)

drivers/spi/spi-amlogic-spifc-a1.c

45

#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29)

drivers/spi/spi-amlogic-spifc-a1.c

46

#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23)

drivers/spi/spi-amlogic-spifc-a1.c

50

#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27)

drivers/spi/spi-amlogic-spifc-a1.c

51

#define SPIFC_A1_USER_DIN_BYTES GENMASK(25, 16)

drivers/spi/spi-amlogic-spifc-a1.c

59

#define SPIFC_A1_TSLCH GENMASK(31, 30)

drivers/spi/spi-amlogic-spifc-a1.c

60

#define SPIFC_A1_TCLSH GENMASK(29, 28)

drivers/spi/spi-amlogic-spifc-a1.c

61

#define SPIFC_A1_TSHWL GENMASK(20, 16)

drivers/spi/spi-amlogic-spifc-a1.c

62

#define SPIFC_A1_TSHSL2 GENMASK(15, 12)

drivers/spi/spi-amlogic-spifc-a1.c

63

#define SPIFC_A1_TSHSL1 GENMASK(11, 8)

drivers/spi/spi-amlogic-spifc-a1.c

64

#define SPIFC_A1_TWHSL GENMASK(7, 0)

drivers/spi/spi-amlogic-spifc-a1.c

69

#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0)

drivers/spi/spi-amlogic-spifc-a4.c

104

#define TXADJ GENMASK(11, 8)

drivers/spi/spi-amlogic-spifc-a4.c

105

#define RXADJ GENMASK(7, 4)

drivers/spi/spi-amlogic-spifc-a4.c

106

#define CMD_LANE GENMASK(3, 2)

drivers/spi/spi-amlogic-spifc-a4.c

107

#define DATA_LANE GENMASK(1, 0)

drivers/spi/spi-amlogic-spifc-a4.c

111

#define RAW_MAX_RW_SIZE_MASK GENMASK(25, 0)

drivers/spi/spi-amlogic-spifc-a4.c

138

#define SFC_XFER_MDOE_MASK GENMASK(6, 2)

drivers/spi/spi-amlogic-spifc-a4.c

45

#define CHIP_SELECT_MASK GENMASK(13, 10)

drivers/spi/spi-amlogic-spifc-a4.c

56

#define IDLE_CYCLE_MASK GENMASK(9, 0)

drivers/spi/spi-amlogic-spifc-a4.c

57

#define EXT_CYCLE_MASK GENMASK(9, 0)

drivers/spi/spi-amlogic-spifc-a4.c

69

#define SEED_MASK GENMASK(14, 0)

drivers/spi/spi-amlogic-spifc-a4.c

84

#define GET_CMD_SIZE(x) (((x) >> 22) & GENMASK(4, 0))

drivers/spi/spi-amlogic-spifc-a4.c

91

#define RAW_SIZE GENMASK(13, 0)

drivers/spi/spi-amlogic-spifc-a4.c

98

#define RAW_EXT_SIZE GENMASK(29, 18)

drivers/spi/spi-amlogic-spifc-a4.c

99

#define ADDR_LANE GENMASK(17, 16)

drivers/spi/spi-amlogic-spisg.c

125

#define LINK_ADDR_ACT GENMASK(5, 3)

drivers/spi/spi-amlogic-spisg.c

127

#define LINK_ADDR_LEN GENMASK(31, 8)

drivers/spi/spi-amlogic-spisg.c

33

#define CFG_SLAVE_SELECT GENMASK(3, 2)

drivers/spi/spi-amlogic-spisg.c

42

#define CFG_BLOCK_NUM GENMASK(19, 0)

drivers/spi/spi-amlogic-spisg.c

43

#define CFG_BLOCK_SIZE GENMASK(22, 20)

drivers/spi/spi-amlogic-spisg.c

45

#define CFG_OP_MODE GENMASK(25, 24)

drivers/spi/spi-amlogic-spisg.c

46

#define CFG_RXD_MODE GENMASK(27, 26)

drivers/spi/spi-amlogic-spisg.c

47

#define CFG_TXD_MODE GENMASK(29, 28)

drivers/spi/spi-amlogic-spisg.c

52

#define CFG_CLK_DIV GENMASK(7, 0)

drivers/spi/spi-amlogic-spisg.c

54

#define CFG_RX_TUNING GENMASK(11, 8)

drivers/spi/spi-amlogic-spisg.c

55

#define CFG_TX_TUNING GENMASK(15, 12)

drivers/spi/spi-amlogic-spisg.c

56

#define CFG_CS_SETUP GENMASK(19, 16)

drivers/spi/spi-amlogic-spisg.c

57

#define CFG_LANE GENMASK(21, 20)

drivers/spi/spi-amlogic-spisg.c

63

#define CFG_READ_TURN GENMASK(28, 27)

drivers/spi/spi-apple.c

28

#define APPLE_SPI_CFG_MODE GENMASK(6, 5)

drivers/spi/spi-apple.c

35

#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15)

drivers/spi/spi-apple.c

39

#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17)

drivers/spi/spi-apple.c

64

#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8)

drivers/spi/spi-apple.c

66

#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24)

drivers/spi/spi-apple.c

89

#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16)

drivers/spi/spi-ar934x.c

30

#define AR934X_SPI_CLK_MASK GENMASK(5, 0)

drivers/spi/spi-aspeed-smc.c

29

#define CTRL_IO_MODE_MASK GENMASK(30, 28)

drivers/spi/spi-aspeed-smc.c

38

#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)

drivers/spi/spi-aspeed-smc.c

40

#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)

drivers/spi/spi-at91-usart.c

41

#define US_MR_CHRL GENMASK(7, 6)

drivers/spi/spi-atcspi200.c

40

#define TRANS_FMT_DATA_LEN_MASK GENMASK(12, 8)

drivers/spi/spi-atcspi200.c

41

#define TRANS_FMT_ADDR_LEN_MASK GENMASK(17, 16)

drivers/spi/spi-atcspi200.c

46

#define TRANS_MODE_MASK GENMASK(27, 24)

drivers/spi/spi-atcspi200.c

52

#define TRANS_RD_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(8, 0), x)

drivers/spi/spi-atcspi200.c

53

#define TRANS_DUMMY_CNT(x) TRANS_FIELD_DECNZ(GENMASK(10, 9), x)

drivers/spi/spi-atcspi200.c

54

#define TRANS_WR_TRANS_CNT(x) TRANS_FIELD_DECNZ(GENMASK(20, 12), x)

drivers/spi/spi-atcspi200.c

55

#define TRANS_DUAL_QUAD(x) FIELD_PREP(GENMASK(23, 22), (x))

drivers/spi/spi-atcspi200.c

73

#define TIMING_SCLK_DIV_MASK GENMASK(7, 0)

drivers/spi/spi-atcspi200.c

77

#define RXFIFO_SIZE(x) FIELD_GET(GENMASK(3, 0), (x))

drivers/spi/spi-atcspi200.c

78

#define TXFIFO_SIZE(x) FIELD_GET(GENMASK(7, 4), (x))

drivers/spi/spi-axi-spi-engine.c

27

#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16)

drivers/spi/spi-axi-spi-engine.c

28

#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0)

drivers/spi/spi-axi-spi-engine.c

56

#define SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_SDO GENMASK(15, 8)

drivers/spi/spi-axi-spi-engine.c

57

#define SPI_ENGINE_SPI_OFFLOAD_MEM_WIDTH_CMD GENMASK(7, 0)

drivers/spi/spi-bcm-qspi.c

117

#define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10)

drivers/spi/spi-bcm-qspi.c

122

#define MSPI_SPCR3_TXRXDAM_MASK GENMASK(4, 2)

drivers/spi/spi-bcm-qspi.c

147

#define ADDR_4MB_MASK GENMASK(22, 0)

drivers/spi/spi-cadence-xspi.c

108

#define CDNS_XSPI_NUM_BANKS GENMASK(25, 24)

drivers/spi/spi-cadence-xspi.c

110

#define CDNS_XSPI_NUM_THREADS GENMASK(3, 0)

drivers/spi/spi-cadence-xspi.c

114

#define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16)

drivers/spi/spi-cadence-xspi.c

115

#define CDNS_XSPI_CTRL_REV GENMASK(7, 0)

drivers/spi/spi-cadence-xspi.c

118

#define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0)

drivers/spi/spi-cadence-xspi.c

119

#define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24)

drivers/spi/spi-cadence-xspi.c

120

#define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0)

drivers/spi/spi-cadence-xspi.c

121

#define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8)

drivers/spi/spi-cadence-xspi.c

122

#define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16)

drivers/spi/spi-cadence-xspi.c

123

#define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24)

drivers/spi/spi-cadence-xspi.c

124

#define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0)

drivers/spi/spi-cadence-xspi.c

125

#define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16)

drivers/spi/spi-cadence-xspi.c

126

#define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28)

drivers/spi/spi-cadence-xspi.c

127

#define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0)

drivers/spi/spi-cadence-xspi.c

128

#define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8)

drivers/spi/spi-cadence-xspi.c

129

#define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12)

drivers/spi/spi-cadence-xspi.c

132

#define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16)

drivers/spi/spi-cadence-xspi.c

133

#define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0)

drivers/spi/spi-cadence-xspi.c

134

#define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20)

drivers/spi/spi-cadence-xspi.c

135

#define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12)

drivers/spi/spi-cadence-xspi.c

136

#define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8)

drivers/spi/spi-cadence-xspi.c

150

#define MODE_NO_OF_BYTES GENMASK(25, 24)

drivers/spi/spi-cadence-xspi.c

204

#define GENERIC_NUM_OF_BYTES GENMASK(27, 24)

drivers/spi/spi-cadence-xspi.c

208

#define GENERIC_BANK_NUM GENMASK(14, 12)

drivers/spi/spi-cadence-xspi.c

253

#define MRVL_XSPI_CLK_DIV GENMASK(4, 1)

drivers/spi/spi-cadence-xspi.c

263

#define MRVL_XFER_CS_N_HOLD GENMASK(9, 6)

drivers/spi/spi-cadence-xspi.c

95

#define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5)

drivers/spi/spi-cs42l43.c

115

*buf = FIELD_GET(GENMASK(7, 0), val);

drivers/spi/spi-cs42l43.c

70

val |= FIELD_PREP(GENMASK(31, 24), *buf);

drivers/spi/spi-dln2.c

179

u8 cs_mask = GENMASK(dln2->host->num_chipselect - 1, 0);

drivers/spi/spi-dw-mmio.c

39

#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)

drivers/spi/spi-dw-mmio.c

66

#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))

drivers/spi/spi-dw.h

102

#define DW_SPI_SR_MASK GENMASK(6, 0)

drivers/spi/spi-dw.h

112

#define DW_SPI_INT_MASK GENMASK(5, 0)

drivers/spi/spi-dw.h

66

#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)

drivers/spi/spi-dw.h

67

#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)

drivers/spi/spi-dw.h

69

#define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4)

drivers/spi/spi-dw.h

75

#define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6)

drivers/spi/spi-dw.h

79

#define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8)

drivers/spi/spi-dw.h

90

#define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0)

drivers/spi/spi-dw.h

91

#define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6)

drivers/spi/spi-dw.h

94

#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)

drivers/spi/spi-dw.h

99

#define DW_SPI_NDF_MASK GENMASK(15, 0)

drivers/spi/spi-fsl-dspi.c

105

#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(2, 0)) * 4))

drivers/spi/spi-fsl-dspi.c

1433

mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));

drivers/spi/spi-fsl-dspi.c

37

#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)

drivers/spi/spi-fsl-dspi.c

39

#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4))

drivers/spi/spi-fsl-dspi.c

40

#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))

drivers/spi/spi-fsl-dspi.c

45

#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))

drivers/spi/spi-fsl-dspi.c

46

#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))

drivers/spi/spi-fsl-dspi.c

47

#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))

drivers/spi/spi-fsl-dspi.c

48

#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))

drivers/spi/spi-fsl-dspi.c

49

#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))

drivers/spi/spi-fsl-dspi.c

50

#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))

drivers/spi/spi-fsl-dspi.c

51

#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))

drivers/spi/spi-fsl-dspi.c

52

#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))

drivers/spi/spi-fsl-dspi.c

85

#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))

drivers/spi/spi-fsl-dspi.c

88

#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))

drivers/spi/spi-fsl-lpspi.c

75

#define CFGR1_PCSPOL_MASK GENMASK(11, 8)

drivers/spi/spi-fsl-lpspi.c

87

#define SR_CLEAR_MASK GENMASK(13, 8)

drivers/spi/spi-fsl-qspi.c

54

#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)

drivers/spi/spi-fsl-qspi.c

59

#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)

drivers/spi/spi-fsl-qspi.c

67

#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)

drivers/spi/spi-fsl-qspi.c

68

#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)

drivers/spi/spi-fsl-qspi.c

69

#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)

drivers/spi/spi-fsl-qspi.c

79

#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)

drivers/spi/spi-fsl-qspi.c

90

#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)

drivers/spi/spi-fsl-qspi.c

96

#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)

drivers/spi/spi-geni-qcom.c

27

#define LOOPBACK_MSK GENMASK(1, 0)

drivers/spi/spi-geni-qcom.c

33

#define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)

drivers/spi/spi-geni-qcom.c

36

#define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)

drivers/spi/spi-geni-qcom.c

42

#define WORD_LEN_MSK GENMASK(9, 0)

drivers/spi/spi-geni-qcom.c

47

#define TRANS_LEN_MSK GENMASK(23, 0)

drivers/spi/spi-geni-qcom.c

52

#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)

drivers/spi/spi-geni-qcom.c

53

#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)

drivers/spi/spi-hisi-kunpeng.c

37

#define CR_LOOP_MASK GENMASK(1, 1)

drivers/spi/spi-hisi-kunpeng.c

38

#define CR_CPOL_MASK GENMASK(2, 2)

drivers/spi/spi-hisi-kunpeng.c

39

#define CR_CPHA_MASK GENMASK(3, 3)

drivers/spi/spi-hisi-kunpeng.c

40

#define CR_DIV_PRE_MASK GENMASK(11, 4)

drivers/spi/spi-hisi-kunpeng.c

41

#define CR_DIV_POST_MASK GENMASK(19, 12)

drivers/spi/spi-hisi-kunpeng.c

42

#define CR_BPW_MASK GENMASK(24, 20)

drivers/spi/spi-hisi-kunpeng.c

43

#define CR_SPD_MODE_MASK GENMASK(25, 25)

drivers/spi/spi-hisi-kunpeng.c

46

#define FIFOC_TX_MASK GENMASK(5, 3)

drivers/spi/spi-hisi-kunpeng.c

47

#define FIFOC_RX_MASK GENMASK(11, 9)

drivers/spi/spi-intel.c

122

#define FLMAP0_NC_MASK GENMASK(9, 8)

drivers/spi/spi-intel.c

124

#define FLMAP0_FCBA_MASK GENMASK(7, 0)

drivers/spi/spi-intel.c

126

#define FLCOMP_C0DEN_MASK GENMASK(3, 0)

drivers/spi/spi-intel.c

56

#define FREG_BASE_MASK GENMASK(14, 0)

drivers/spi/spi-intel.c

58

#define FREG_LIMIT_MASK GENMASK(30, 16)

drivers/spi/spi-intel.c

64

#define PR_LIMIT_MASK GENMASK(30, 16)

drivers/spi/spi-intel.c

66

#define PR_BASE_MASK GENMASK(14, 0)

drivers/spi/spi-lantiq-ssc.c

871

.fifo_size_mask = GENMASK(5, 0),

drivers/spi/spi-lantiq-ssc.c

881

.fifo_size_mask = GENMASK(5, 0),

drivers/spi/spi-lantiq-ssc.c

891

.fifo_size_mask = GENMASK(7, 0),

drivers/spi/spi-ljca.c

25

#define LJCA_SPI_XFER_INDICATOR_ID GENMASK(5, 0)

drivers/spi/spi-loongson-core.c

49

loongson_spi->spcr = (div_tmp & GENMASK(1, 0)) >> 0;

drivers/spi/spi-loongson-core.c

50

loongson_spi->sper = (div_tmp & GENMASK(3, 2)) >> 2;

drivers/spi/spi-loongson-core.c

52

val &= ~GENMASK(1, 0);

drivers/spi/spi-loongson-core.c

56

val &= ~GENMASK(1, 0);

drivers/spi/spi-meson-spicc.c

106

#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */

drivers/spi/spi-meson-spicc.c

109

#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */

drivers/spi/spi-meson-spicc.c

110

#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */

drivers/spi/spi-meson-spicc.c

111

#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */

drivers/spi/spi-meson-spicc.c

116

#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */

drivers/spi/spi-meson-spicc.c

117

#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */

drivers/spi/spi-meson-spicc.c

122

#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */

drivers/spi/spi-meson-spicc.c

127

#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */

drivers/spi/spi-meson-spicc.c

132

#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */

drivers/spi/spi-meson-spicc.c

133

#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */

drivers/spi/spi-meson-spicc.c

150

#define DMA_READ_COUNTER GENMASK(15, 0)

drivers/spi/spi-meson-spicc.c

151

#define DMA_WRITE_COUNTER GENMASK(31, 16)

drivers/spi/spi-meson-spicc.c

157

#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)

drivers/spi/spi-meson-spicc.c

158

#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)

drivers/spi/spi-meson-spicc.c

62

#define SPICC_DRCTL_MASK GENMASK(9, 8)

drivers/spi/spi-meson-spicc.c

66

#define SPICC_CS_MASK GENMASK(13, 12)

drivers/spi/spi-meson-spicc.c

67

#define SPICC_DATARATE_MASK GENMASK(18, 16)

drivers/spi/spi-meson-spicc.c

72

#define SPICC_BITLENGTH_MASK GENMASK(24, 19)

drivers/spi/spi-meson-spicc.c

73

#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)

drivers/spi/spi-meson-spicc.c

87

#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)

drivers/spi/spi-meson-spicc.c

88

#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)

drivers/spi/spi-meson-spicc.c

89

#define SPICC_READ_BURST_MASK GENMASK(14, 11)

drivers/spi/spi-meson-spicc.c

90

#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)

drivers/spi/spi-meson-spicc.c

92

#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)

drivers/spi/spi-meson-spicc.c

93

#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)

drivers/spi/spi-microchip-core-qspi.c

32

#define CONTROL_SAMPLE_MASK GENMASK(12, 11)

drivers/spi/spi-microchip-core-qspi.c

34

#define CONTROL_MODE12_MASK GENMASK(15, 14)

drivers/spi/spi-microchip-core-qspi.c

37

#define CONTROL_MODE12_FULL GENMASK(15, 14)

drivers/spi/spi-microchip-core-qspi.c

39

#define CONTROL_CLKRATE_MASK GENMASK(27, 24)

drivers/spi/spi-microchip-core-qspi.c

45

#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)

drivers/spi/spi-microchip-core-qspi.c

46

#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)

drivers/spi/spi-microchip-core-qspi.c

49

#define FRAMES_IDLE_MASK GENMASK(29, 26)

drivers/spi/spi-microchip-core-qspi.c

75

#define STATUS_MASK GENMASK(8, 0)

drivers/spi/spi-microchip-core-qspi.c

77

#define BYTESUPPER_MASK GENMASK(31, 16)

drivers/spi/spi-microchip-core-qspi.c

78

#define BYTESLOWER_MASK GENMASK(15, 0)

drivers/spi/spi-mpfs.c

47

#define CONTROL_MODE_MASK GENMASK(3, 2)

drivers/spi/spi-mpfs.c

49

#define CONTROL_FRAMECNT_MASK GENMASK(23, 8)

drivers/spi/spi-mpfs.c

77

#define FRAME_SIZE_MASK GENMASK(5, 0)

drivers/spi/spi-mpfs.c

84

#define SSEL_MASK GENMASK(7, 0)

drivers/spi/spi-mt65xx.c

58

#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)

drivers/spi/spi-mt65xx.c

83

#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)

drivers/spi/spi-mt65xx.c

94

#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)

drivers/spi/spi-mt65xx.c

95

#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)

drivers/spi/spi-mt65xx.c

96

#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)

drivers/spi/spi-mt7621.c

43

#define MASTER_RS_CLK_SEL GENMASK(27, 16)

drivers/spi/spi-mt7621.c

45

#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)

drivers/spi/spi-mtk-nor.c

29

#define MTK_NOR_CMD_MASK GENMASK(5, 0)

drivers/spi/spi-mtk-nor.c

61

#define MTK_NOR_IRQ_MASK GENMASK(7, 0)

drivers/spi/spi-mtk-nor.c

76

#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)

drivers/spi/spi-mtk-snfi.c

130

#define NFI_NAND_FSM_7622 GENMASK(28, 24)

drivers/spi/spi-mtk-snfi.c

131

#define NFI_NAND_FSM_7986 GENMASK(29, 23)

drivers/spi/spi-mtk-snfi.c

132

#define NFI_FSM GENMASK(19, 16)

drivers/spi/spi-mtk-snfi.c

140

#define SEC_CNTR GENMASK(16, 12)

drivers/spi/spi-mtk-snfi.c

158

#define MAS_ADDR GENMASK(11, 9)

drivers/spi/spi-mtk-snfi.c

159

#define MAS_RD GENMASK(8, 6)

drivers/spi/spi-mtk-snfi.c

160

#define MAS_WR GENMASK(5, 3)

drivers/spi/spi-mtk-snfi.c

161

#define MAS_RDDLY GENMASK(2, 0)

drivers/spi/spi-mtk-snfi.c

193

#define DATA_READ_MODE GENMASK(18, 16)

drivers/spi/spi-mtk-snfi.c

199

#define DATA_READ_LATCH_LAT GENMASK(9, 8)

drivers/spi/spi-mtk-snfi.c

211

#define SFCK_SAM_DLY GENMASK(5, 0)

drivers/spi/spi-mtk-snfi.c

219

#define SPI_STATE GENMASK(3, 0)

drivers/spi/spi-mxic.c

46

#define INT_STS_ALL GENMASK(31, 0)

drivers/spi/spi-npcm-fiu.c

102

#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)

drivers/spi/spi-npcm-fiu.c

103

#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

104

#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

105

#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

106

#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

109

#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

110

#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

111

#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

112

#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

115

#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

116

#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

117

#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

118

#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

121

#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

122

#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

123

#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

124

#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

127

#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

128

#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

129

#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

130

#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

133

#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

134

#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

135

#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

136

#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

139

#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

140

#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

141

#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

142

#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

145

#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

146

#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

147

#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

148

#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

151

#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

152

#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

153

#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

154

#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

45

#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)

drivers/spi/spi-npcm-fiu.c

46

#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)

drivers/spi/spi-npcm-fiu.c

47

#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)

drivers/spi/spi-npcm-fiu.c

48

#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)

drivers/spi/spi-npcm-fiu.c

49

#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

56

#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)

drivers/spi/spi-npcm-fiu.c

57

#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)

drivers/spi/spi-npcm-fiu.c

58

#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)

drivers/spi/spi-npcm-fiu.c

59

#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)

drivers/spi/spi-npcm-fiu.c

60

#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)

drivers/spi/spi-npcm-fiu.c

68

#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)

drivers/spi/spi-npcm-fiu.c

69

#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)

drivers/spi/spi-npcm-fiu.c

70

#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)

drivers/spi/spi-npcm-fiu.c

71

#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)

drivers/spi/spi-npcm-fiu.c

73

#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)

drivers/spi/spi-npcm-fiu.c

74

#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)

drivers/spi/spi-npcm-fiu.c

75

#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)

drivers/spi/spi-npcm-fiu.c

76

#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)

drivers/spi/spi-npcm-fiu.c

77

#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)

drivers/spi/spi-npcm-fiu.c

91

#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)

drivers/spi/spi-npcm-fiu.c

96

#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)

drivers/spi/spi-npcm-fiu.c

97

#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)

drivers/spi/spi-npcm-fiu.c

98

#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)

drivers/spi/spi-npcm-fiu.c

99

#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)

drivers/spi/spi-npcm-pspi.c

50

#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)

drivers/spi/spi-nxp-fspi.c

329

#define SYS_PLL_RAT GENMASK(6, 2)

drivers/spi/spi-nxp-xspi.c

100

#define XSPI_BFGENCR_ALIGN_MASK GENMASK(24, 22)

drivers/spi/spi-nxp-xspi.c

104

#define XSPI_BFGENCR_SEQID_MASK GENMASK(15, 12)

drivers/spi/spi-nxp-xspi.c

113

#define XSPI_DLLCRA_DLL_REFCNTR_MASK GENMASK(27, 24)

drivers/spi/spi-nxp-xspi.c

114

#define XSPI_DLLCRA_DLLRES_MASK GENMASK(23, 20)

drivers/spi/spi-nxp-xspi.c

115

#define XSPI_DLLCRA_SLV_FINE_MASK GENMASK(19, 16)

drivers/spi/spi-nxp-xspi.c

116

#define XSPI_DLLCRA_SLV_DLY_MASK GENMASK(14, 12)

drivers/spi/spi-nxp-xspi.c

117

#define XSPI_DLLCRA_SLV_DLY_COARSE_MASK GENMASK(11, 8)

drivers/spi/spi-nxp-xspi.c

118

#define XSPI_DLLCRA_SLV_DLY_FINE_MASK GENMASK(7, 5)

drivers/spi/spi-nxp-xspi.c

134

#define XSPI_SFACR_CAS_MASK GENMASK(3, 0)

drivers/spi/spi-nxp-xspi.c

137

#define XSPI_SMPR_DLLFSMPFA_MASK GENMASK(26, 24)

drivers/spi/spi-nxp-xspi.c

144

#define XSPI_RBCT_WMRK_MASK GENMASK(6, 0)

drivers/spi/spi-nxp-xspi.c

157

#define XSPI_TBCT_WMRK_MASK GENMASK(7, 0)

drivers/spi/spi-nxp-xspi.c

165

#define XSPI_SR_ARB_STATE_MASK GENMASK(23, 20)

drivers/spi/spi-nxp-xspi.c

220

#define XSPI_MCREXT_RST_MASK GENMASK(3, 0)

drivers/spi/spi-nxp-xspi.c

224

#define XSPI_FRAD0_WORD2_MD0ACP_MASK GENMASK(2, 0)

drivers/spi/spi-nxp-xspi.c

245

#define XSPI_SFP_TG_IPCR_SEQID_MASK GENMASK(27, 24)

drivers/spi/spi-nxp-xspi.c

248

#define XSPI_SFP_TG_IPCR_IDATSZ_MASK GENMASK(15, 0)

drivers/spi/spi-nxp-xspi.c

66

#define XSPI_MCR_DQS_FA_SEL_MASK GENMASK(25, 24)

drivers/spi/spi-nxp-xspi.c

86

#define XSPI_FLSHCR_TDH_MASK GENMASK(17, 16)

drivers/spi/spi-nxp-xspi.c

87

#define XSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)

drivers/spi/spi-nxp-xspi.c

88

#define XSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)

drivers/spi/spi-nxp-xspi.c

95

#define XSPI_BUF3CR_ADATSZ_MASK GENMASK(17, 8)

drivers/spi/spi-nxp-xspi.c

96

#define XSPI_BUF3CR_MSTRID_MASK GENMASK(3, 0)

drivers/spi/spi-nxp-xspi.c

99

#define XSPI_BFGENCR_SEQID_WR_MASK GENMASK(31, 28)

drivers/spi/spi-pci1xxxx.c

35

#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25))

drivers/spi/spi-pci1xxxx.c

36

#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8))

drivers/spi/spi-pci1xxxx.c

37

#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5))

drivers/spi/spi-pci1xxxx.c

38

#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4))

drivers/spi/spi-pci1xxxx.c

52

#define SPI_PERI_ENBLE_PF_MASK (GENMASK(17, 16))

drivers/spi/spi-pci1xxxx.c

53

#define DEV_REV_MASK (GENMASK(7, 0))

drivers/spi/spi-pxa2xx.c

1026

pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);

drivers/spi/spi-pxa2xx.c

1027

pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);

drivers/spi/spi-pxa2xx.c

1041

pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);

drivers/spi/spi-pxa2xx.c

1054

pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);

drivers/spi/spi-qpic-snand.c

34

#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)

drivers/spi/spi-qpic-snand.c

36

#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)

drivers/spi/spi-rockchip-sfc.c

89

#define SFC_FSR_TXLV_MASK GENMASK(12, 8)

drivers/spi/spi-rockchip-sfc.c

91

#define SFC_FSR_RXLV_MASK GENMASK(20, 16)

drivers/spi/spi-rzv2h-rspi.c

57

#define RSPI_SPCMD_SSLA GENMASK(25, 24)

drivers/spi/spi-rzv2h-rspi.c

58

#define RSPI_SPCMD_SPB GENMASK(20, 16)

drivers/spi/spi-rzv2h-rspi.c

61

#define RSPI_SPCMD_BRDV GENMASK(3, 2)

drivers/spi/spi-rzv2h-rspi.c

69

#define RSPI_SPDCR2_TTRG GENMASK(11, 8)

drivers/spi/spi-rzv2h-rspi.c

70

#define RSPI_SPDCR2_RTRG GENMASK(3, 0)

drivers/spi/spi-rzv2m-csi.c

49

#define CSI_CLKSEL_CKS GENMASK(14, 1)

drivers/spi/spi-rzv2m-csi.c

70

#define CSI_FIFOTRG_R_TRG GENMASK(2, 0)

drivers/spi/spi-rzv2m-csi.c

80

#define CSI_CKS_MAX GENMASK(13, 0)

drivers/spi/spi-rzv2m-csi.c

91

#define CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH GENMASK(1, 0)

drivers/spi/spi-s3c64xx.c

63

#define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11)

drivers/spi/spi-s3c64xx.c

82

#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15)

drivers/spi/spi-s3c64xx.c

83

#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6)

drivers/spi/spi-s3c64xx.c

93

#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)

drivers/spi/spi-sg2044-nor.c

41

#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK GENMASK(1, 0)

drivers/spi/spi-sg2044-nor.c

45

#define SPIFMC_TRAN_CSR_BUS_WIDTH_MASK GENMASK(5, 4)

drivers/spi/spi-sg2044-nor.c

51

#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK GENMASK(10, 8)

drivers/spi/spi-sg2044-nor.c

54

#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK GENMASK(13, 12)

drivers/spi/spi-sn-f-ospi.c

20

#define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30)

drivers/spi/spi-sn-f-ospi.c

21

#define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28)

drivers/spi/spi-sn-f-ospi.c

22

#define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26)

drivers/spi/spi-sn-f-ospi.c

23

#define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24)

drivers/spi/spi-sn-f-ospi.c

39

#define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10)

drivers/spi/spi-sn-f-ospi.c

45

#define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5)

drivers/spi/spi-sn-f-ospi.c

46

#define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2)

drivers/spi/spi-sn-f-ospi.c

47

#define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0)

drivers/spi/spi-sn-f-ospi.c

54

#define OSPI_CLK_CTL_DIV GENMASK(9, 8)

drivers/spi/spi-sn-f-ospi.c

73

#define OSPI_DAT_SIZE_MASK GENMASK(10, 0)

drivers/spi/spi-sprd-adi.c

127

#define WDG_LOAD_MASK GENMASK(15, 0)

drivers/spi/spi-sprd-adi.c

45

#define RD_VALUE_MASK GENMASK(15, 0)

drivers/spi/spi-sprd-adi.c

46

#define RD_ADDR_MASK GENMASK(30, 16)

drivers/spi/spi-sprd-adi.c

85

#define RDBACK_ADDR_MASK_R2 GENMASK(14, 0)

drivers/spi/spi-sprd-adi.c

86

#define RDBACK_ADDR_MASK_R3 GENMASK(16, 2)

drivers/spi/spi-sprd.c

103

#define SPRD_SPI_MODE_MASK GENMASK(5, 3)

drivers/spi/spi-sprd.c

109

#define SPRD_SPI_TX_MAX_LEN_MASK GENMASK(19, 0)

drivers/spi/spi-sprd.c

110

#define SPRD_SPI_TX_LEN_H_MASK GENMASK(3, 0)

drivers/spi/spi-sprd.c

114

#define SPRD_SPI_TX_LEN_L_MASK GENMASK(15, 0)

drivers/spi/spi-sprd.c

117

#define SPRD_SPI_RX_MAX_LEN_MASK GENMASK(19, 0)

drivers/spi/spi-sprd.c

118

#define SPRD_SPI_RX_LEN_H_MASK GENMASK(3, 0)

drivers/spi/spi-sprd.c

122

#define SPRD_SPI_RX_LEN_L_MASK GENMASK(15, 0)

drivers/spi/spi-sprd.c

54

#define SPRD_SPI_CHNL_LEN_MASK GENMASK(4, 0)

drivers/spi/spi-sprd.c

55

#define SPRD_SPI_CSN_MASK GENMASK(11, 8)

drivers/spi/spi-sprd.c

80

#define SPRD_SPI_RTX_MD_MASK GENMASK(13, 12)

drivers/spi/spi-sprd.c

87

#define SPRD_SPI_ONLY_RECV_MASK GENMASK(8, 0)

drivers/spi/spi-stm32-ospi.c

40

#define CR_FMODE_MASK GENMASK(29, 28)

drivers/spi/spi-stm32-ospi.c

48

#define DCR1_DEVSIZE_MASK GENMASK(20, 16)

drivers/spi/spi-stm32-ospi.c

49

#define DCR1_MTYP_MASK GENMASK(26, 24)

drivers/spi/spi-stm32-ospi.c

54

#define DCR2_PRESC_MASK GENMASK(7, 0)

drivers/spi/spi-stm32-ospi.c

75

#define CCR_IMODE_MASK GENMASK(2, 0)

drivers/spi/spi-stm32-ospi.c

77

#define CCR_ISIZE_MASK GENMASK(5, 4)

drivers/spi/spi-stm32-ospi.c

78

#define CCR_ADMODE_MASK GENMASK(10, 8)

drivers/spi/spi-stm32-ospi.c

81

#define CCR_ADSIZE_MASK GENMASK(13, 12)

drivers/spi/spi-stm32-ospi.c

83

#define CCR_DMODE_MASK GENMASK(26, 24)

drivers/spi/spi-stm32-ospi.c

94

#define TCR_DCYC_MASK GENMASK(4, 0)

drivers/spi/spi-stm32-qspi.c

38

#define CR_PRESC_MASK GENMASK(31, 24)

drivers/spi/spi-stm32-qspi.c

41

#define DCR_FSIZE_MASK GENMASK(20, 16)

drivers/spi/spi-stm32-qspi.c

50

#define SR_FLEVEL_MASK GENMASK(13, 8)

drivers/spi/spi-stm32-qspi.c

60

#define CCR_INST_MASK GENMASK(7, 0)

drivers/spi/spi-stm32-qspi.c

61

#define CCR_IMODE_MASK GENMASK(9, 8)

drivers/spi/spi-stm32-qspi.c

62

#define CCR_ADMODE_MASK GENMASK(11, 10)

drivers/spi/spi-stm32-qspi.c

63

#define CCR_ADSIZE_MASK GENMASK(13, 12)

drivers/spi/spi-stm32-qspi.c

64

#define CCR_DCYC_MASK GENMASK(22, 18)

drivers/spi/spi-stm32-qspi.c

65

#define CCR_DMODE_MASK GENMASK(25, 24)

drivers/spi/spi-stm32-qspi.c

66

#define CCR_FMODE_MASK GENMASK(27, 26)

drivers/spi/spi-stm32.c

108

#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)

drivers/spi/spi-stm32.c

109

#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)

drivers/spi/spi-stm32.c

112

#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)

drivers/spi/spi-stm32.c

113

#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)

drivers/spi/spi-stm32.c

116

#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)

drivers/spi/spi-stm32.c

119

#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)

drivers/spi/spi-stm32.c

122

#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)

drivers/spi/spi-stm32.c

123

#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)

drivers/spi/spi-stm32.c

124

#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)

drivers/spi/spi-stm32.c

141

#define STM32H7_SPI_IER_ALL GENMASK(10, 0)

drivers/spi/spi-stm32.c

150

#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)

drivers/spi/spi-stm32.c

154

#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)

drivers/spi/spi-stm32.c

166

#define STM32MP25_SPI_TSIZE_MAX_LIMITED GENMASK(9, 0)

drivers/spi/spi-stm32.c

169

#define STM32MP25_SPI_HWCFGR1_FULLCFG GENMASK(27, 24)

drivers/spi/spi-stm32.c

172

#define STM32MP25_SPI_HWCFGR1_DSCFG GENMASK(19, 16)

drivers/spi/spi-stm32.c

39

#define STM32FX_SPI_CR1_BR GENMASK(5, 3)

drivers/spi/spi-stm32.c

52

#define STM32FX_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)

drivers/spi/spi-stm32.c

62

#define STM32F7_SPI_CR2_DS GENMASK(11, 8)

drivers/spi/spi-stm32.c

77

#define STM32F7_SPI_SR_FRLVL GENMASK(10, 9)

drivers/spi/spi-stm32.c

78

#define STM32F7_SPI_SR_FTLVL GENMASK(12, 11)

drivers/spi/spi-sun6i.c

69

#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)

drivers/spi/spi-sun6i.c

70

#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)

drivers/spi/spi-sun6i.c

86

#define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0)

drivers/spi/spi-sunplus-sp7021.c

28

#define SP7021_SLAVE_DMA_CMD GENMASK(3, 2)

drivers/spi/spi-sunplus-sp7021.c

43

#define SP7021_TX_CNT_MASK GENMASK(11, 8)

drivers/spi/spi-sunplus-sp7021.c

44

#define SP7021_RX_CNT_MASK GENMASK(15, 12)

drivers/spi/spi-sunplus-sp7021.c

45

#define SP7021_TX_LEN_MASK GENMASK(23, 16)

drivers/spi/spi-sunplus-sp7021.c

46

#define SP7021_GET_LEN_MASK GENMASK(31, 24)

drivers/spi/spi-sunplus-sp7021.c

47

#define SP7021_SET_TX_LEN GENMASK(23, 16)

drivers/spi/spi-sunplus-sp7021.c

48

#define SP7021_SET_XFER_LEN GENMASK(31, 24)

drivers/spi/spi-sunplus-sp7021.c

57

#define SP7021_RX_UNIT GENMASK(8, 7)

drivers/spi/spi-sunplus-sp7021.c

58

#define SP7021_TX_UNIT GENMASK(10, 9)

drivers/spi/spi-sunplus-sp7021.c

62

#define SP7021_CLEAN_RW_BYTE GENMASK(10, 7)

drivers/spi/spi-sunplus-sp7021.c

63

#define SP7021_CLEAN_FLUG_MASK GENMASK(15, 11)

drivers/spi/spi-sunplus-sp7021.c

64

#define SP7021_CLK_MASK GENMASK(31, 16)

drivers/spi/spi-uniphier.c

49

#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)

drivers/spi/spi-uniphier.c

55

#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)

drivers/spi/spi-uniphier.c

56

#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)

drivers/spi/spi-uniphier.c

57

#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)

drivers/spi/spi-uniphier.c

60

#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)

drivers/spi/spi-uniphier.c

76

#define SSI_IE_ALL_MASK GENMASK(4, 0)

drivers/spi/spi-uniphier.c

90

#define SSI_FC_TXFTH_MASK GENMASK(11, 8)

drivers/spi/spi-uniphier.c

92

#define SSI_FC_RXFTH_MASK GENMASK(3, 0)

drivers/spi/spi-xtensa-xtfpga.c

58

xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));

drivers/spi/spi-zynq-qspi.c

50

#define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */

drivers/spi/spi-zynq-qspi.c

53

#define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */

drivers/spi/spi-zynq-qspi.c

62

#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */

drivers/spmi/spmi-mtk-pmif.c

34

#define PMIF_RCS_IRQ_MASK GENMASK(7, 0)

drivers/spmi/spmi-mtk-pmif.c

671

mtk_spmi_writel(arb, pbus, GENMASK(31, 0), i);

drivers/spmi/spmi-pmic-arb.c

113

#define PMIC_ARB_PPID_MASK GENMASK(11, 0)

drivers/spmi/spmi-pmic-arb.c

114

#define PMIC_ARB_V8_PPID_MASK GENMASK(12, 0)

drivers/spmi/spmi-pmic-arb.c

119

#define HWIRQ_SID_MASK GENMASK(28, 24)

drivers/spmi/spmi-pmic-arb.c

120

#define HWIRQ_PID_MASK GENMASK(23, 16)

drivers/spmi/spmi-pmic-arb.c

121

#define HWIRQ_IRQID_MASK GENMASK(15, 13)

drivers/spmi/spmi-pmic-arb.c

122

#define HWIRQ_APID_MASK GENMASK(12, 0)

drivers/spmi/spmi-pmic-arb.c

34

#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)

drivers/spmi/spmi-pmic-arb.c

35

#define PMIC_ARB_FEATURES_V8_PERIPH_MASK GENMASK(12, 0)

drivers/staging/axis-fifo/axis-fifo.c

64

#define XLLF_INT_CLEAR_ALL GENMASK(31, 0)

drivers/staging/iio/frequency/ad9832.c

60

#define AD9832_PHASE_MASK GENMASK(10, 9)

drivers/staging/iio/frequency/ad9832.c

68

#define AD9832_CMD_MSK GENMASK(15, 12)

drivers/staging/iio/frequency/ad9832.c

69

#define AD9832_ADD_MSK GENMASK(11, 8)

drivers/staging/iio/frequency/ad9832.c

70

#define AD9832_DAT_MSK GENMASK(7, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-base.c

1386

ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

115

#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

118

#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

121

#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

265

#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

269

#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

312

#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

32

#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

321

#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

362

#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

369

#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

376

#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

384

#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

39

#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

48

#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

50

#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

56

#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

58

#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

75

#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16)

drivers/staging/media/deprecated/atmel/atmel-isc-regs.h

77

#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8))

drivers/staging/media/ipu7/ipu7-buttress-regs.h

385

#define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK GENMASK(4, 0)

drivers/staging/media/ipu7/ipu7-buttress-regs.h

396

#define NDE_VAL_MASK GENMASK(9, 0)

drivers/staging/media/ipu7/ipu7-buttress-regs.h

397

#define NDE_SCALE_MASK GENMASK(12, 10)

drivers/staging/media/ipu7/ipu7-buttress-regs.h

399

#define NDE_RESVEC_MASK GENMASK(19, 16)

drivers/staging/media/ipu7/ipu7-buttress-regs.h

414

#define UCX_CTL_SPARE GENMASK(7, 3)

drivers/staging/media/ipu7/ipu7-buttress-regs.h

415

#define UCX_STS_PWR GENMASK(17, 16)

drivers/staging/media/ipu7/ipu7-buttress.c

1096

#define WRXREQOP_OVRD_VAL_MASK GENMASK(22, 19)

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

289

dwc_csi_write_mask(isys, id, reg, vc & GENMASK(4, 0), hi, lo);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

294

dwc_csi_write_mask(isys, id, reg, dt & GENMASK(5, 0), hi, lo);

drivers/staging/media/meson/vdec/codec_h264.c

25

#define CMD_MASK GENMASK(7, 0)

drivers/staging/media/meson/vdec/codec_h264.c

43

#define PIC_STRUCT_MASK GENMASK(2, 0)

drivers/staging/media/meson/vdec/codec_h264.c

44

#define BUF_IDX_MASK GENMASK(4, 0)

drivers/staging/media/meson/vdec/codec_h264.c

47

#define OFFSET_MASK GENMASK(15, 0)

drivers/staging/media/meson/vdec/codec_h264.c

51

#define MB_TOTAL_MASK GENMASK(15, 0)

drivers/staging/media/meson/vdec/codec_h264.c

52

#define MB_WIDTH_MASK GENMASK(7, 0)

drivers/staging/media/meson/vdec/codec_h264.c

54

#define MAX_REF_MASK GENMASK(6, 0)

drivers/staging/media/meson/vdec/codec_h264.c

56

#define AR_IDC_MASK GENMASK(7, 0)

drivers/staging/media/meson/vdec/codec_mpeg12.c

176

if ((reg & GENMASK(23, 17)) == GENMASK(23, 17))

drivers/staging/media/meson/vdec/codec_mpeg12.c

20

#define MPEG2_SEQ_DAR_MASK GENMASK(3, 0)

drivers/staging/media/starfive/camss/stf-capture.h

23

#define U0_VIN_CHANNEL_SEL_MASK GENMASK(3, 0)

drivers/staging/media/starfive/camss/stf-capture.h

29

#define U0_VIN_PIX_CNT_END_MASK GENMASK(12, 2)

drivers/staging/media/starfive/camss/stf-capture.h

30

#define U0_VIN_PIX_CT_MASK GENMASK(14, 13)

drivers/staging/media/starfive/camss/stf-capture.h

31

#define U0_VIN_PIXEL_HEIGH_BIT_SEL_MAKS GENMASK(16, 15)

drivers/staging/media/starfive/camss/stf-capture.h

46

#define U0_VIN_MIPI_BYTE_EN_ISP0_MASK GENMASK(7, 6)

drivers/staging/media/starfive/camss/stf-capture.h

47

#define U0_VIN_MIPI_CHANNEL_SEL0_MASK GENMASK(11, 8)

drivers/staging/media/starfive/camss/stf-capture.h

49

#define U0_VIN_PIX_NUM_MASK GENMASK(16, 13)

drivers/staging/media/starfive/camss/stf-isp.h

202

#define ISPC_INT_ALL_MASK GENMASK(27, 24)

drivers/staging/media/starfive/camss/stf-isp.h

219

#define CTRL_SAT_MASK GENMASK(31, 28)

drivers/staging/media/starfive/camss/stf-isp.h

34

#define CSI_INTS_MASK GENMASK(17, 16)

drivers/staging/media/starfive/camss/stf-isp.h

79

#define DUMP_BURST_LEN_MASK GENMASK(17, 16)

drivers/staging/media/starfive/camss/stf-isp.h

80

#define DUMP_SD_MASK GENMASK(15, 0)

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

14

(((unsigned long)(v) << (l)) & GENMASK(h, l))

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

230

u32 _lo = _tmp & GENMASK(27, 4); \

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

231

u32 _hi = (_tmp >> 28) & GENMASK(3, 0); \

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

297

#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0))

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

298

#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16))

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

460

#define VE_DEC_H265_STATUS_STCD_TYPE_MASK GENMASK(23, 22)

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

474

#define VE_DEC_H265_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0))

drivers/staging/media/sunxi/cedrus/cedrus_regs.h

98

(((unsigned long)(__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

104

#define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

105

#define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

108

#define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

123

#define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

133

#define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

134

#define SUN6I_ISP_AE_CFG_HORZ_NUM(v) (((v) << 12) & GENMASK(15, 12))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

135

#define SUN6I_ISP_AE_CFG_HIGH_BRI_TH(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

136

#define SUN6I_ISP_AE_CFG_VERT_NUM(v) (((v) << 28) & GENMASK(31, 28))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

139

#define SUN6I_ISP_AE_SIZE_WIDTH(v) ((v) & GENMASK(10, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

140

#define SUN6I_ISP_AE_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(26, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

143

#define SUN6I_ISP_AE_POS_HORZ_START(v) ((v) & GENMASK(10, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

144

#define SUN6I_ISP_AE_POS_VERT_START(v) (((v) << 16) & GENMASK(26, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

149

#define SUN6I_ISP_OB_SIZE_WIDTH(v) ((v) & GENMASK(13, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

150

#define SUN6I_ISP_OB_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(29, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

153

#define SUN6I_ISP_OB_VALID_WIDTH(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

154

#define SUN6I_ISP_OB_VALID_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

157

#define SUN6I_ISP_OB_SRC0_VALID_START_HORZ(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

158

#define SUN6I_ISP_OB_SRC0_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

161

#define SUN6I_ISP_OB_SRC1_VALID_START_HORZ(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

162

#define SUN6I_ISP_OB_SRC1_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

165

#define SUN6I_ISP_OB_SPRITE_WIDTH(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

166

#define SUN6I_ISP_OB_SPRITE_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

169

#define SUN6I_ISP_OB_SPRITE_START_HORZ(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

170

#define SUN6I_ISP_OB_SPRITE_START_VERT(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

180

#define SUN6I_ISP_BDNF_CFG_IN_DIS_MIN(v) ((v) & GENMASK(7, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

181

#define SUN6I_ISP_BDNF_CFG_IN_DIS_MAX(v) (((v) << 16) & GENMASK(23, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

185

GENMASK(4 * (i) + 3, 4 * (i)))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

189

GENMASK(4 * (i) + 3, 4 * (i)))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

194

#define SUN6I_ISP_BAYER_OFFSET0_R(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

195

#define SUN6I_ISP_BAYER_OFFSET0_GR(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

198

#define SUN6I_ISP_BAYER_OFFSET1_GB(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

199

#define SUN6I_ISP_BAYER_OFFSET1_B(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

202

#define SUN6I_ISP_BAYER_GAIN0_R(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

203

#define SUN6I_ISP_BAYER_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

206

#define SUN6I_ISP_BAYER_GAIN1_GB(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

207

#define SUN6I_ISP_BAYER_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

21

#define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

212

#define SUN6I_ISP_WB_GAIN0_R(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

213

#define SUN6I_ISP_WB_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

216

#define SUN6I_ISP_WB_GAIN1_GB(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

217

#define SUN6I_ISP_WB_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

22

#define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

220

#define SUN6I_ISP_WB_CFG_CLIP(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

225

#define SUN6I_ISP_MCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

226

#define SUN6I_ISP_MCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

229

#define SUN6I_ISP_MCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

230

#define SUN6I_ISP_MCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

231

#define SUN6I_ISP_MCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

234

#define SUN6I_ISP_SCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

235

#define SUN6I_ISP_SCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

238

#define SUN6I_ISP_SCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

239

#define SUN6I_ISP_SCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

240

#define SUN6I_ISP_SCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

245

#define SUN6I_ISP_MCH_CFG_OUTPUT_FMT(v) (((v) << 2) & GENMASK(4, 2))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

248

#define SUN6I_ISP_MCH_CFG_STRIDE_Y_DIV4(v) (((v) << 8) & GENMASK(18, 8))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

249

#define SUN6I_ISP_MCH_CFG_STRIDE_UV_DIV4(v) (((v) << 20) & GENMASK(30, 20))

drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h

33

#define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16))

drivers/staging/media/tegra-video/tegra20.c

635

GENMASK(9, 2) << VI_PIN_INPUT_VD_SFT |

drivers/staging/media/tegra-video/tegra20.c

638

GENMASK(9, 2) << VI_DATA_INPUT_SFT);

drivers/staging/media/tegra-video/tegra210.c

109

#define CLK_SETTLE_MASK GENMASK(13, 8)

drivers/staging/media/tegra-video/tegra210.c

110

#define THS_SETTLE_MASK GENMASK(5, 0)

drivers/tee/optee/optee_msg.h

38

#define OPTEE_MSG_ATTR_TYPE_MASK GENMASK(7, 0)

drivers/tee/optee/optee_msg.h

84

#define OPTEE_MSG_ATTR_CACHE_MASK GENMASK(2, 0)

drivers/tee/qcomtee/qcomtee_msg.h

141

#define QCOMTEE_MASK_IB GENMASK(3, 0)

drivers/tee/qcomtee/qcomtee_msg.h

142

#define QCOMTEE_MASK_OB GENMASK(7, 4)

drivers/tee/qcomtee/qcomtee_msg.h

143

#define QCOMTEE_MASK_IO GENMASK(11, 8)

drivers/tee/qcomtee/qcomtee_msg.h

144

#define QCOMTEE_MASK_OO GENMASK(15, 12)

drivers/tee/qcomtee/qcomtee_msg.h

75

#define QCOMTEE_MSG_OBJECT_OP_MASK GENMASK(15, 0)

drivers/tee/tstee/tstee_private.h

33

#define OPCODE_MASK GENMASK(15, 0)

drivers/tee/tstee/tstee_private.h

34

#define IFACE_ID_MASK GENMASK(23, 16)

drivers/thermal/airoha_thermal.c

121

#define EN7581_HOT2NORMAL_THRE GENMASK(11, 0)

drivers/thermal/airoha_thermal.c

123

#define EN7581_HOT_THRE GENMASK(11, 0)

drivers/thermal/airoha_thermal.c

126

#define EN7581_COLD_THRE GENMASK(11, 0)

drivers/thermal/airoha_thermal.c

129

#define EN7581_LOW_OFFSET GENMASK(11, 0)

drivers/thermal/airoha_thermal.c

131

#define EN7581_HIGH_OFFSET GENMASK(11, 0)

drivers/thermal/airoha_thermal.c

133

#define EN7581_MSRCTL3 GENMASK(11, 9)

drivers/thermal/airoha_thermal.c

134

#define EN7581_MSRCTL2 GENMASK(8, 6)

drivers/thermal/airoha_thermal.c

135

#define EN7581_MSRCTL1 GENMASK(5, 3)

drivers/thermal/airoha_thermal.c

136

#define EN7581_MSRCTL0 GENMASK(2, 0)

drivers/thermal/airoha_thermal.c

138

#define EN7581_ADC_VALID_ADDR GENMASK(31, 0)

drivers/thermal/airoha_thermal.c

140

#define EN7581_ADC_VOLT_ADDR GENMASK(31, 0)

drivers/thermal/airoha_thermal.c

150

#define EN7581_ADV_RD_VALID_POS GENMASK(4, 0)

drivers/thermal/airoha_thermal.c

152

#define EN7581_ADC_VOLTAGE_SHIFT GENMASK(4, 0)

drivers/thermal/airoha_thermal.c

167

#define EN7581_ADC_POLL_INTVL GENMASK(31, 0)

drivers/thermal/airoha_thermal.c

17

#define EN7581_MUX_TADC GENMASK(3, 1)

drivers/thermal/airoha_thermal.c

170

#define EN7581_EFUSE_TEMP_OFFSET GENMASK(31, 16)

drivers/thermal/airoha_thermal.c

19

#define EN7581_DOUT_TADC_MASK GENMASK(15, 0)

drivers/thermal/airoha_thermal.c

29

#define EN7581_PERIOD_UNIT GENMASK(9, 0)

drivers/thermal/airoha_thermal.c

31

#define EN7581_FILT_INTERVAL GENMASK(25, 16)

drivers/thermal/airoha_thermal.c

32

#define EN7581_SEN_INTERVAL GENMASK(9, 0)

drivers/thermal/amlogic_thermal.c

39

#define TSENSOR_CFG_REG1_CH_SEL GENMASK(1, 0)

drivers/thermal/amlogic_thermal.c

51

#define TSENSOR_READ_TEMP_MASK GENMASK(15, 0)

drivers/thermal/amlogic_thermal.c

52

#define TSENSOR_TEMP_MASK GENMASK(11, 0)

drivers/thermal/amlogic_thermal.c

55

#define TSENSOR_TRIM_TEMP_MASK GENMASK(14, 0)

drivers/thermal/amlogic_thermal.c

56

#define TSENSOR_TRIM_VERSION_MASK GENMASK(31, 24)

drivers/thermal/amlogic_thermal.c

61

#define TSENSOR_TRIM_CALIB_VALID_MASK (GENMASK(3, 2) | BIT(7))

drivers/thermal/broadcom/bcm2711_thermal.c

27

#define AVS_RO_TEMP_STATUS_DATA_MSK GENMASK(9, 0)

drivers/thermal/broadcom/bcm2835_thermal.c

37

GENMASK(BCM2835_TS_TSENSCTL_CTRL_BITS + \

drivers/thermal/broadcom/bcm2835_thermal.c

47

GENMASK(BCM2835_TS_TSENSCTL_THOLD_BITS + \

drivers/thermal/broadcom/bcm2835_thermal.c

61

GENMASK(BCM2835_TS_TSENSSTAT_DATA_BITS + \

drivers/thermal/broadcom/brcmstb_thermal.c

26

#define AVS_TMON_STATUS_data_msk GENMASK(10, 1)

drivers/thermal/broadcom/brcmstb_thermal.c

33

#define AVS_TMON_RESET_THRESH_msk GENMASK(10, 1)

drivers/thermal/broadcom/brcmstb_thermal.c

43

#define AVS_TMON_INT_THRESH_high_msk GENMASK(26, 17)

drivers/thermal/broadcom/brcmstb_thermal.c

45

#define AVS_TMON_INT_THRESH_low_msk GENMASK(10, 1)

drivers/thermal/imx8mm_thermal.c

26

#define TASR_BUF_SLOPE_MASK GENMASK(19, 16)

drivers/thermal/imx8mm_thermal.c

27

#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */

drivers/thermal/imx8mm_thermal.c

28

#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */

drivers/thermal/imx8mm_thermal.c

31

#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */

drivers/thermal/imx8mm_thermal.c

32

#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */

drivers/thermal/imx8mm_thermal.c

33

#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */

drivers/thermal/imx8mm_thermal.c

34

#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */

drivers/thermal/imx8mm_thermal.c

36

#define TRIM_BJT_CUR_MASK GENMASK(23, 20)

drivers/thermal/imx8mm_thermal.c

37

#define TRIM_BGR_MASK GENMASK(31, 28)

drivers/thermal/imx8mm_thermal.c

38

#define TRIM_VLSB_MASK GENMASK(15, 12)

drivers/thermal/imx8mm_thermal.c

43

#define TRITSR_TEMP0_VAL_MASK GENMASK(7, 0)

drivers/thermal/imx8mm_thermal.c

44

#define TRITSR_TEMP1_VAL_MASK GENMASK(23, 16)

drivers/thermal/imx8mm_thermal.c

46

#define PROBE_SEL_ALL GENMASK(31, 30)

drivers/thermal/imx8mm_thermal.c

50

#define TEMP_VAL_MASK GENMASK(6, 0)

drivers/thermal/imx8mm_thermal.c

54

#define ANA0_BUF_VREF_MASK GENMASK(24, 20)

drivers/thermal/imx8mm_thermal.c

55

#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)

drivers/thermal/imx8mm_thermal.c

56

#define ANA0_HR_MASK GENMASK(15, 8)

drivers/thermal/imx8mm_thermal.c

57

#define ANA0_RT_MASK GENMASK(7, 0)

drivers/thermal/imx8mm_thermal.c

58

#define TRIM2_VLSB_MASK GENMASK(23, 20)

drivers/thermal/imx8mm_thermal.c

59

#define TRIM2_BGR_MASK GENMASK(19, 16)

drivers/thermal/imx8mm_thermal.c

60

#define TRIM2_BJT_CUR_MASK GENMASK(15, 12)

drivers/thermal/imx8mm_thermal.c

61

#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)

drivers/thermal/imx8mm_thermal.c

62

#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)

drivers/thermal/imx8mm_thermal.c

63

#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)

drivers/thermal/imx8mm_thermal.c

64

#define TRIM3_TCA40_0_MASK GENMASK(27, 16)

drivers/thermal/imx8mm_thermal.c

65

#define TRIM4_TCA40_1_MASK GENMASK(31, 20)

drivers/thermal/imx8mm_thermal.c

66

#define TRIM4_TCA105_0_MASK GENMASK(19, 8)

drivers/thermal/imx8mm_thermal.c

67

#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)

drivers/thermal/imx8mm_thermal.c

68

#define TRIM5_TCA105_1_MASK GENMASK(23, 12)

drivers/thermal/imx8mm_thermal.c

69

#define TRIM5_TCA25_1_MASK GENMASK(11, 0)

drivers/thermal/imx91_thermal.c

26

#define IMX91_TMU_CTRL0_THR1_MASK GENMASK(3, 2)

drivers/thermal/imx91_thermal.c

43

#define IMX91_TMU_CTRL1_RES_MASK GENMASK(19, 18)

drivers/thermal/imx91_thermal.c

44

#define IMX91_TMU_CTRL1_MEAS_MODE_MASK GENMASK(25, 24)

drivers/thermal/imx91_thermal.c

50

#define IMX91_TMU_THR_CTRL01_THR1_MASK GENMASK(31, 16)

drivers/thermal/imx91_thermal.c

54

#define IMX91_TMU_DIV_MASK GENMASK(23, 16)

drivers/thermal/imx91_thermal.c

58

#define IMX91_TMU_PUDL_MASK GENMASK(23, 16)

drivers/thermal/imx91_thermal.c

70

#define IMX91_TMU_PERIOD_CTRL_MEAS_MASK GENMASK(23, 0)

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

260

mask = GENMASK(mmio_regs[ret].shift + mmio_regs[ret].bits - 1, mmio_regs[ret].shift);\

drivers/thermal/mediatek/auxadc_thermal.c

575

.apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),

drivers/thermal/mediatek/auxadc_thermal.c

634

.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),

drivers/thermal/mediatek/auxadc_thermal.c

694

.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

106

#define ADC_TM_GEN2_HW_SETTLE_DELAY GENMASK(3, 0)

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

118

#define ADC_TM_GEN2_LOWER_MASK(n) ((n) & GENMASK(7, 0))

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

119

#define ADC_TM_GEN2_UPPER_MASK(n) (((n) & GENMASK(15, 8)) >> 8)

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

93

#define ADC_TM_GEN2_TM_CH_SEL GENMASK(7, 5)

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

94

#define ADC_TM_GEN2_MEAS_INT_SEL GENMASK(3, 2)

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

97

#define ADC_TM_GEN2_CTL_CAL_SEL GENMASK(5, 4)

drivers/thermal/qcom/qcom-spmi-adc-tm5.c

98

#define ADC_TM_GEN2_CTL_DEC_RATIO_MASK GENMASK(3, 2)

drivers/thermal/qcom/qcom-spmi-temp-alarm.c

42

#define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)

drivers/thermal/qcom/qcom-spmi-temp-alarm.c

43

#define STATUS_GEN2_STATE_MASK GENMASK(6, 4)

drivers/thermal/qcom/qcom-spmi-temp-alarm.c

49

#define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)

drivers/thermal/qcom/qcom-spmi-temp-alarm.c

55

#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2)

drivers/thermal/qcom/tsens-8960.c

128

mask = GENMASK(10, 6);

drivers/thermal/qcom/tsens-8960.c

160

mask = GENMASK(priv->num_sensors - 1, 0);

drivers/thermal/qcom/tsens-v2.c

30

#define CONVERSION_SHIFT_MASK GENMASK(24, 23)

drivers/thermal/qcom/tsens-v2.c

31

#define CONVERSION_SLOPE_MASK GENMASK(22, 10)

drivers/thermal/qcom/tsens-v2.c

32

#define CONVERSION_CZERO_MASK GENMASK(9, 0)

drivers/thermal/qoriq_thermal.c

127

*temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;

drivers/thermal/qoriq_thermal.c

130

*temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) *

drivers/thermal/qoriq_thermal.c

133

*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));

drivers/thermal/renesas/rzg2l_thermal.c

36

#define OTPTSUTRIM_MASK GENMASK(11, 0)

drivers/thermal/renesas/rzg3e_thermal.c

43

#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0)

drivers/thermal/renesas/rzg3s_thermal.c

26

#define OTPTSUTRIM_MASK GENMASK(11, 0)

drivers/thermal/sprd_thermal.c

49

#define SPRD_THM_DET_PERIOD_MASK GENMASK(19, 0)

drivers/thermal/sprd_thermal.c

51

#define SPRD_THM_MON_MODE_MASK GENMASK(3, 0)

drivers/thermal/sprd_thermal.c

53

#define SPRD_THM_MON_PERIOD_MASK GENMASK(15, 0)

drivers/thermal/sprd_thermal.c

54

#define SPRD_THM_THRES_MASK GENMASK(19, 0)

drivers/thermal/sprd_thermal.c

55

#define SPRD_THM_INT_CLR_MASK GENMASK(24, 0)

drivers/thermal/st/stm_thermal.c

34

#define HSREF_CLK_DIV_MASK GENMASK(30, 24)

drivers/thermal/st/stm_thermal.c

35

#define TS1_SMP_TIME_MASK GENMASK(19, 16)

drivers/thermal/st/stm_thermal.c

36

#define TS1_INTRIG_SEL_MASK GENMASK(11, 8)

drivers/thermal/st/stm_thermal.c

39

#define TS1_T0_MASK GENMASK(17, 16)

drivers/thermal/st/stm_thermal.c

40

#define TS1_FMT0_MASK GENMASK(15, 0)

drivers/thermal/st/stm_thermal.c

43

#define TS1_RAMP_COEFF_MASK GENMASK(15, 0)

drivers/thermal/st/stm_thermal.c

46

#define TS1_HITTHD_MASK GENMASK(31, 16)

drivers/thermal/st/stm_thermal.c

47

#define TS1_LITTHD_MASK GENMASK(15, 0)

drivers/thermal/st/stm_thermal.c

50

#define TS1_MFREQ_MASK GENMASK(15, 0)

drivers/thermal/st/stm_thermal.c

53

#define ITENR_MASK (GENMASK(2, 0) | GENMASK(6, 4))

drivers/thermal/st/stm_thermal.c

56

#define ICIFR_MASK (GENMASK(2, 0) | GENMASK(6, 4))

drivers/thermal/sun8i_thermal.c

30

#define FT_TEMP_MASK GENMASK(11, 0)

drivers/thermal/sun8i_thermal.c

31

#define TEMP_CALIB_MASK GENMASK(11, 0)

drivers/thermal/sun8i_thermal.c

456

val = GENMASK(7 + tmdev->chip->sensor_num, 8);

drivers/thermal/sun8i_thermal.c

468

val = GENMASK(tmdev->chip->sensor_num - 1, 0);

drivers/thermal/sun8i_thermal.c

51

#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x))

drivers/thermal/sun8i_thermal.c

515

val = GENMASK(tmdev->chip->sensor_num - 1, 0);

drivers/thermal/sun8i_thermal.c

518

val = GENMASK(tmdev->chip->sensor_num - 1, 0);

drivers/thermal/sun8i_thermal.c

52

#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)

drivers/thermal/sun8i_thermal.c

55

#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))

drivers/thermal/sun8i_thermal.c

56

#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)

drivers/thermal/sun8i_thermal.c

58

#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))

drivers/thermal/sun8i_thermal.c

59

#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)

drivers/thermal/tegra/tegra30-tsensor.c

41

#define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8)

drivers/thermal/tegra/tegra30-tsensor.c

42

#define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24)

drivers/thermal/tegra/tegra30-tsensor.c

45

#define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0)

drivers/thermal/tegra/tegra30-tsensor.c

46

#define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16)

drivers/thermal/tegra/tegra30-tsensor.c

49

#define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0)

drivers/thermal/tegra/tegra30-tsensor.c

52

#define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0)

drivers/thermal/tegra/tegra30-tsensor.c

57

#define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16)

drivers/thermal/tegra/tegra30-tsensor.c

62

#define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0)

drivers/thermal/tegra/tegra30-tsensor.c

63

#define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16)

drivers/thermal/uniphier_thermal.c

32

#define EMONREPEAT_PERIOD GENMASK(3, 0)

drivers/thermal/uniphier_thermal.c

40

#define PVTCTLSEL_MASK GENMASK(2, 0)

drivers/thermal/uniphier_thermal.c

46

#define SETALERT_TEMP_OVF (GENMASK(7, 0) << 16)

drivers/thermal/uniphier_thermal.c

47

#define SETALERT_TEMP_OVF_VALUE(val) (((val) & GENMASK(7, 0)) << 16)

drivers/thermal/uniphier_thermal.c

54

#define PMALERTINTCTL_MASK (GENMASK(10, 8) | GENMASK(6, 4) | \

drivers/thermal/uniphier_thermal.c

55

GENMASK(2, 0))

drivers/thermal/uniphier_thermal.c

63

#define TMODSETUP0_VAL(val) (((val) & GENMASK(13, 0)) << 16)

drivers/thermal/uniphier_thermal.c

65

#define TMODSETUP1_VAL(val) ((val) & GENMASK(14, 0))

drivers/thunderbolt/dma_port.c

23

#define MAIL_IN_CMD_MASK GENMASK(31, 28)

drivers/thunderbolt/dma_port.c

29

#define MAIL_IN_DWORDS_MASK GENMASK(27, 24)

drivers/thunderbolt/dma_port.c

31

#define MAIL_IN_ADDRESS_MASK GENMASK(23, 2)

drivers/thunderbolt/dma_port.c

38

#define MAIL_OUT_STATUS_CMD_MASK GENMASK(7, 4)

drivers/thunderbolt/dma_port.c

39

#define MAIL_OUT_STATUS_MASK GENMASK(3, 0)

drivers/thunderbolt/icm.c

31

#define PCIE2CIO_CMD_CS_MASK GENMASK(20, 19)

drivers/thunderbolt/icm.c

33

#define PCIE2CIO_CMD_PORT_MASK GENMASK(18, 13)

drivers/thunderbolt/icm.c

41

#define PHY_PORT_CS1_LINK_STATE_MASK GENMASK(29, 26)

drivers/thunderbolt/nhi_regs.h

109

#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)

drivers/thunderbolt/nhi_regs.h

114

#define REG_CAPS_VERSION_MASK GENMASK(23, 16)

drivers/thunderbolt/nhi_regs.h

127

#define REG_INMAIL_CMD_MASK GENMASK(7, 0)

drivers/thunderbolt/nhi_regs.h

133

#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)

drivers/thunderbolt/nhi_regs.h

160

#define VS_CAP_19_CMD_MASK GENMASK(7, 1)

drivers/thunderbolt/nhi_regs.h

164

#define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)

drivers/thunderbolt/nhi_regs.h

81

#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)

drivers/thunderbolt/sb_regs.h

100

#define USB4_MARGIN_SW_LANES_MASK GENMASK(2, 0)

drivers/thunderbolt/sb_regs.h

104

#define USB4_MARGIN_SW_VT_MASK GENMASK(12, 6)

drivers/thunderbolt/sb_regs.h

105

#define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13)

drivers/thunderbolt/sb_regs.h

108

#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK GENMASK(3, 0)

drivers/thunderbolt/sb_regs.h

109

#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK GENMASK(7, 4)

drivers/thunderbolt/sb_regs.h

110

#define USB4_MARGIN_SW_ERR_COUNTER_LANE_2_MASK GENMASK(11, 8)

drivers/thunderbolt/sb_regs.h

42

#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0)

drivers/thunderbolt/sb_regs.h

53

#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3)

drivers/thunderbolt/sb_regs.h

58

#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6)

drivers/thunderbolt/sb_regs.h

59

#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)

drivers/thunderbolt/sb_regs.h

61

#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK GENMASK(26, 20)

drivers/thunderbolt/sb_regs.h

62

#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)

drivers/thunderbolt/sb_regs.h

64

#define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9)

drivers/thunderbolt/sb_regs.h

68

#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11)

drivers/thunderbolt/sb_regs.h

69

#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16)

drivers/thunderbolt/sb_regs.h

70

#define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21)

drivers/thunderbolt/sb_regs.h

71

#define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26)

drivers/thunderbolt/sb_regs.h

75

#define USB4_MARGIN_CAP_2_MAX_VOLTAGE_OFFSET_MASK GENMASK(8, 3)

drivers/thunderbolt/sb_regs.h

76

#define USB4_MARGIN_CAP_2_VOLTAGE_STEPS_MASK GENMASK(15, 9)

drivers/thunderbolt/sb_regs.h

77

#define USB4_MARGIN_CAP_2_VOLTAGE_INDP_MASK GENMASK(17, 16)

drivers/thunderbolt/sb_regs.h

80

#define USB4_MARGIN_CAP_2_TIME_INDP_MASK GENMASK(19, 18)

drivers/thunderbolt/sb_regs.h

87

#define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5)

drivers/thunderbolt/sb_regs.h

92

#define USB4_MARGIN_HW_RES_MARGIN_MASK GENMASK(6, 0)

drivers/thunderbolt/tb_msgs.h

135

#define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3)

drivers/thunderbolt/tb_msgs.h

177

#define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1)

drivers/thunderbolt/tb_msgs.h

180

#define ICM_PORT_TYPE_MASK GENMASK(23, 0)

drivers/thunderbolt/tb_msgs.h

182

#define ICM_PORT_INDEX_MASK GENMASK(31, 24)

drivers/thunderbolt/tb_msgs.h

195

#define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4)

drivers/thunderbolt/tb_msgs.h

302

#define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0)

drivers/thunderbolt/tb_msgs.h

304

#define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7)

drivers/thunderbolt/tb_msgs.h

351

#define ICM_TR_INFO_SLEVEL_MASK GENMASK(2, 0)

drivers/thunderbolt/tb_msgs.h

352

#define ICM_TR_INFO_PROTO_VERSION_MASK GENMASK(6, 4)

drivers/thunderbolt/tb_msgs.h

355

#define ICM_TR_INFO_BOOT_ACL_MASK GENMASK(12, 7)

drivers/thunderbolt/tb_msgs.h

501

#define ICM_USB4_SWITCH_DATA_LEN_MASK GENMASK(3, 0)

drivers/thunderbolt/tb_msgs.h

522

#define TB_XDOMAIN_LENGTH_MASK GENMASK(5, 0)

drivers/thunderbolt/tb_msgs.h

523

#define TB_XDOMAIN_SN_MASK GENMASK(28, 27)

drivers/thunderbolt/tb_regs.h

194

#define USB4_VERSION_MAJOR_MASK GENMASK(7, 5)

drivers/thunderbolt/tb_regs.h

224

#define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0)

drivers/thunderbolt/tb_regs.h

225

#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)

drivers/thunderbolt/tb_regs.h

246

#define TMU_RTR_CS_0_FREQ_WIND_MASK GENMASK(26, 16)

drivers/thunderbolt/tb_regs.h

250

#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)

drivers/thunderbolt/tb_regs.h

254

#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)

drivers/thunderbolt/tb_regs.h

255

#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)

drivers/thunderbolt/tb_regs.h

258

#define TMU_RTR_CS_15_FREQ_AVG_MASK GENMASK(5, 0)

drivers/thunderbolt/tb_regs.h

259

#define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6)

drivers/thunderbolt/tb_regs.h

260

#define TMU_RTR_CS_15_OFFSET_AVG_MASK GENMASK(17, 12)

drivers/thunderbolt/tb_regs.h

261

#define TMU_RTR_CS_15_ERROR_AVG_MASK GENMASK(23, 18)

drivers/thunderbolt/tb_regs.h

263

#define TMU_RTR_CS_18_DELTA_AVG_CONST_MASK GENMASK(23, 16)

drivers/thunderbolt/tb_regs.h

315

#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)

drivers/thunderbolt/tb_regs.h

316

#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)

drivers/thunderbolt/tb_regs.h

320

#define ADP_CS_5_LCA_MASK GENMASK(28, 22)

drivers/thunderbolt/tb_regs.h

330

#define TMU_ADP_CS_8_REPL_TIMEOUT_MASK GENMASK(14, 0)

drivers/thunderbolt/tb_regs.h

332

#define TMU_ADP_CS_8_REPL_THRESHOLD_MASK GENMASK(25, 16)

drivers/thunderbolt/tb_regs.h

334

#define TMU_ADP_CS_9_REPL_N_MASK GENMASK(7, 0)

drivers/thunderbolt/tb_regs.h

335

#define TMU_ADP_CS_9_DIRSWITCH_N_MASK GENMASK(15, 8)

drivers/thunderbolt/tb_regs.h

336

#define TMU_ADP_CS_9_ADP_TS_INTERVAL_MASK GENMASK(31, 16)

drivers/thunderbolt/tb_regs.h

340

#define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK GENMASK(19, 16)

drivers/thunderbolt/tb_regs.h

342

#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)

drivers/thunderbolt/tb_regs.h

349

#define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0)

drivers/thunderbolt/tb_regs.h

351

#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(5, 4)

drivers/thunderbolt/tb_regs.h

355

#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK GENMASK(7, 6)

drivers/thunderbolt/tb_regs.h

364

#define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)

drivers/thunderbolt/tb_regs.h

369

#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)

drivers/thunderbolt/tb_regs.h

376

#define PORT_CS_1_TARGET_MASK GENMASK(18, 16)

drivers/thunderbolt/tb_regs.h

404

#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)

drivers/thunderbolt/tb_regs.h

408

#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)

drivers/thunderbolt/tb_regs.h

409

#define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)

drivers/thunderbolt/tb_regs.h

412

#define ADP_DP_CS_2_NRD_MLC_MASK GENMASK(2, 0)

drivers/thunderbolt/tb_regs.h

414

#define ADP_DP_CS_2_NRD_MLR_MASK GENMASK(9, 7)

drivers/thunderbolt/tb_regs.h

417

#define ADP_DP_CS_2_GR_MASK GENMASK(12, 11)

drivers/thunderbolt/tb_regs.h

422

#define ADP_DP_CS_2_GROUP_ID_MASK GENMASK(15, 13)

drivers/thunderbolt/tb_regs.h

424

#define ADP_DP_CS_2_CM_ID_MASK GENMASK(19, 16)

drivers/thunderbolt/tb_regs.h

427

#define ADP_DP_CS_2_ESTIMATED_BW_MASK GENMASK(31, 24)

drivers/thunderbolt/tb_regs.h

435

#define DP_STATUS_ALLOCATED_BW_MASK GENMASK(31, 24)

drivers/thunderbolt/tb_regs.h

444

#define ADP_DP_CS_8_REQUESTED_BW_MASK GENMASK(7, 0)

drivers/thunderbolt/tb_regs.h

452

#define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)

drivers/thunderbolt/tb_regs.h

458

#define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)

drivers/thunderbolt/tb_regs.h

485

#define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)

drivers/thunderbolt/tb_regs.h

486

#define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12)

drivers/thunderbolt/tb_regs.h

490

#define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)

drivers/thunderbolt/tb_regs.h

491

#define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12)

drivers/thunderbolt/tb_regs.h

495

#define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)

drivers/thunderbolt/tb_regs.h

497

#define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12)

drivers/thunderbolt/tb_regs.h

531

#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16)

drivers/thunderbolt/tb_regs.h

540

#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2)

drivers/thunderbolt/tb_regs.h

553

#define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0)

drivers/thunderbolt/tb_regs.h

555

#define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10)

drivers/thunderbolt/tb_regs.h

559

#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22)

drivers/thunderbolt/tb_regs.h

567

#define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1)

drivers/thunderbolt/tb_regs.h

568

#define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1)

drivers/thunderbolt/tb_regs.h

569

#define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1)

drivers/thunderbolt/tb_regs.h

570

#define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3)

drivers/thunderbolt/tb_regs.h

575

#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)

drivers/thunderbolt/tb_regs.h

577

#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)

drivers/thunderbolt/tb_regs.h

579

#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)

drivers/thunderbolt/tb_regs.h

582

#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)

drivers/thunderbolt/tb_regs.h

585

#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)

drivers/thunderbolt/usb4.c

21

#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)

drivers/thunderbolt/usb4.c

23

#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)

drivers/thunderbolt/usb4.c

29

#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)

drivers/thunderbolt/usb4.c

31

#define USB4_DROM_SIZE_MASK GENMASK(19, 15)

drivers/thunderbolt/usb4.c

34

#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)

drivers/thunderbolt/usb4.c

36

#define USB4_BA_LENGTH_MASK GENMASK(7, 0)

drivers/thunderbolt/usb4.c

37

#define USB4_BA_INDEX_MASK GENMASK(15, 0)

drivers/thunderbolt/usb4.c

47

#define USB4_BA_VALUE_MASK GENMASK(31, 16)

drivers/tty/n_gsm.c

209

#define PN_D_FIELD_DLCI GENMASK(5, 0)

drivers/tty/n_gsm.c

210

#define PN_I_CL_FIELD_FTYPE GENMASK(3, 0)

drivers/tty/n_gsm.c

211

#define PN_I_CL_FIELD_ADAPTION GENMASK(7, 4)

drivers/tty/n_gsm.c

212

#define PN_P_FIELD_PRIO GENMASK(5, 0)

drivers/tty/n_gsm.c

213

#define PN_T_FIELD_T1 GENMASK(7, 0)

drivers/tty/n_gsm.c

214

#define PN_N_FIELD_N1 GENMASK(15, 0)

drivers/tty/n_gsm.c

215

#define PN_NA_FIELD_N2 GENMASK(7, 0)

drivers/tty/n_gsm.c

216

#define PN_K_FIELD_K GENMASK(2, 0)

drivers/tty/serial/8250/8250_aspeed_vuart.c

26

#define ASPEED_VUART_GCRB_HOST_SIRQ_MASK GENMASK(7, 4)

drivers/tty/serial/8250/8250_dw.c

47

#define DW_UART_IIR_IID GENMASK(3, 0)

drivers/tty/serial/8250/8250_dwlib.c

28

#define DW_UART_ADDR_MASK GENMASK(7, 0)

drivers/tty/serial/8250/8250_dwlib.c

37

#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)

drivers/tty/serial/8250/8250_dwlib.c

49

#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)

drivers/tty/serial/8250/8250_dwlib.c

60

#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)

drivers/tty/serial/8250/8250_exar.c

194

#define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0)

drivers/tty/serial/8250/8250_exar.c

195

#define CTI_EE_MASK_OSC_FREQ GENMASK(31, 0)

drivers/tty/serial/8250/8250_keba.c

52

#define KUART_CAPABILITY_MASK GENMASK(3, 0)

drivers/tty/serial/8250/8250_loongson.c

25

#define LOONGSON_QUOT_FRAC_MASK GENMASK(7, 0)

drivers/tty/serial/8250/8250_loongson.c

26

#define LOONGSON_QUOT_DIV_MASK GENMASK(15, 8)

drivers/tty/serial/8250/8250_ni.c

39

#define NI16550_PMR_CAP_MASK GENMASK(1, 0)

drivers/tty/serial/8250/8250_ni.c

45

#define NI16550_PMR_MODE_MASK GENMASK(4, 4)

drivers/tty/serial/8250/8250_ni.c

59

#define NI16550_PCR_WIRE_MODE_MASK GENMASK(1, 0)

drivers/tty/serial/8250/8250_pci.c

2014

#define MOXA_EVEN_RS_MASK GENMASK(3, 0)

drivers/tty/serial/8250/8250_pci.c

2015

#define MOXA_ODD_RS_MASK GENMASK(7, 4)

drivers/tty/serial/8250/8250_pci1xxxx.c

101

#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8)

drivers/tty/serial/8250/8250_pci1xxxx.c

102

#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8)

drivers/tty/serial/8250/8250_pci1xxxx.c

103

#define FRAC_DIV_TX_END_POINT_MASK GENMASK(23, 20)

drivers/tty/serial/8250/8250_pci1xxxx.c

71

#define UART_DEV_REV_MASK GENMASK(7, 0)

drivers/tty/serial/8250/8250_pci1xxxx.c

85

#define UART_LINE_XMIT_CHECK_MASK GENMASK(6, 5)

drivers/tty/serial/atmel_serial.h

122

#define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */

drivers/tty/serial/atmel_serial.h

128

#define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */

drivers/tty/serial/atmel_serial.h

131

#define ATMEL_US_TG GENMASK(7, 0) /* Timeguard Value */

drivers/tty/serial/atmel_serial.h

139

#define ATMEL_US_TXRDYM(data) FIELD_PREP(GENMASK(1, 0), (data)) /* TX Ready Mode */

drivers/tty/serial/atmel_serial.h

140

#define ATMEL_US_RXRDYM(data) FIELD_PREP(GENMASK(5, 4), (data)) /* RX Ready Mode */

drivers/tty/serial/atmel_serial.h

145

#define ATMEL_US_TXFTHRES(thr) FIELD_PREP(GENMASK(13, 8), (thr)) /* TX FIFO Threshold */

drivers/tty/serial/atmel_serial.h

146

#define ATMEL_US_RXFTHRES(thr) FIELD_PREP(GENMASK(21, 16), (thr)) /* RX FIFO Threshold */

drivers/tty/serial/atmel_serial.h

147

#define ATMEL_US_RXFTHRES2(thr) FIELD_PREP(GENMASK(29, 24), (thr)) /* RX FIFO Threshold2 */

drivers/tty/serial/atmel_serial.h

150

#define ATMEL_US_TXFL(reg) FIELD_GET(GENMASK(5, 0), (reg)) /* TX FIFO Level */

drivers/tty/serial/atmel_serial.h

151

#define ATMEL_US_RXFL(reg) FIELD_GET(GENMASK(21, 16), (reg)) /* RX FIFO Level */

drivers/tty/serial/atmel_serial.h

43

#define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */

drivers/tty/serial/atmel_serial.h

51

#define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */

drivers/tty/serial/atmel_serial.h

57

#define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */

drivers/tty/serial/atmel_serial.h

63

#define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */

drivers/tty/serial/atmel_serial.h

70

#define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */

drivers/tty/serial/atmel_serial.h

75

#define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */

drivers/tty/serial/atmel_serial.h

86

#define ATMEL_US_MAX_ITER_MASK GENMASK(26, 24) /* Max Iterations */

drivers/tty/serial/esp32_acm.c

35

#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR GENMASK(8, 2)

drivers/tty/serial/esp32_acm.c

37

#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT GENMASK(22, 16)

drivers/tty/serial/esp32_uart.c

35

#define ESP32_UART_CLKDIV GENMASK(19, 0)

drivers/tty/serial/esp32_uart.c

36

#define ESP32S3_UART_CLKDIV GENMASK(11, 0)

drivers/tty/serial/esp32_uart.c

38

#define UART_CLKDIV_FRAG GENMASK(23, 20)

drivers/tty/serial/esp32_uart.c

40

#define ESP32_UART_RXFIFO_CNT GENMASK(7, 0)

drivers/tty/serial/esp32_uart.c

41

#define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0)

drivers/tty/serial/esp32_uart.c

45

#define ESP32_UART_TXFIFO_CNT GENMASK(23, 16)

drivers/tty/serial/esp32_uart.c

46

#define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16)

drivers/tty/serial/esp32_uart.c

51

#define UART_BIT_NUM GENMASK(3, 2)

drivers/tty/serial/esp32_uart.c

56

#define UART_STOP_BIT_NUM GENMASK(5, 4)

drivers/tty/serial/esp32_uart.c

72

#define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0)

drivers/tty/serial/esp32_uart.c

73

#define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6)

drivers/tty/serial/esp32_uart.c

74

#define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12)

drivers/tty/serial/esp32_uart.c

75

#define ESP32S3_UART_SCLK_SEL GENMASK(21, 20)

drivers/tty/serial/fsl_lpuart.c

188

#define UARTCTRL_IDLECFG GENMASK(10, 8)

drivers/tty/serial/fsl_lpuart.c

206

#define UARTMODIR_RTSWATER GENMASK(10, 8)

drivers/tty/serial/fsl_lpuart.c

220

#define UARTFIFO_RXIDEN GENMASK(12, 10)

drivers/tty/serial/lantiq.c

60

#define ASC_IRNCR_MASK GENMASK(2, 0)

drivers/tty/serial/ma35d1_serial.c

111

#define MA35_BAUD_MODE_MASK GENMASK(29, 28)

drivers/tty/serial/ma35d1_serial.c

115

#define MA35_BAUD_MASK GENMASK(15, 0)

drivers/tty/serial/ma35d1_serial.c

121

#define MA35_FUN_SEL_MASK GENMASK(2, 0)

drivers/tty/serial/ma35d1_serial.c

49

#define MA35_FCR_RFITL_MASK GENMASK(7, 4) /* RX FIFO Interrupt Trigger Level */

drivers/tty/serial/ma35d1_serial.c

55

#define MA35_FCR_RTSTL_MASK GENMASK(19, 16) /* nRTS Trigger Level */

drivers/tty/serial/ma35d1_serial.c

68

#define MA35_LCR_WLS_MASK GENMASK(1, 0) /* Word Length Selection */

drivers/tty/serial/ma35d1_serial.c

95

#define MA35_FSR_RXPTR_MSK GENMASK(13, 8) /* TX FIFO Pointer mask */

drivers/tty/serial/ma35d1_serial.c

96

#define MA35_FSR_TXPTR_MSK GENMASK(21, 16) /* RX FIFO Pointer mask */

drivers/tty/serial/max310x.c

165

#define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */

drivers/tty/serial/max310x.c

166

#define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */

drivers/tty/serial/max310x.c

171

#define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */

drivers/tty/serial/max310x.c

172

#define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */

drivers/tty/serial/max310x.c

220

#define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */

drivers/tty/serial/max310x.c

221

#define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */

drivers/tty/serial/max310x.c

240

#define MAX310x_REV_MASK GENMASK(7, 3)

drivers/tty/serial/mps2-uart.c

53

#define UARTn_BAUDDIV_MASK GENMASK(20, 0)

drivers/tty/serial/owl-uart.c

32

#define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)

drivers/tty/serial/owl-uart.c

38

#define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)

drivers/tty/serial/owl-uart.c

63

#define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)

drivers/tty/serial/qcom_geni_serial.c

56

#define RX_WORD_LEN_MASK GENMASK(9, 0)

drivers/tty/serial/qcom_geni_serial.c

59

#define RX_STALE_CNT GENMASK(23, 0)

drivers/tty/serial/qcom_geni_serial.c

94

#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)

drivers/tty/serial/qcom_geni_serial.c

96

#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)

drivers/tty/serial/rsci.c

103

#define FCR_RTRG4_0 GENMASK(20, 16)

drivers/tty/serial/rsci.c

104

#define FCR_TTRG GENMASK(12, 8)

drivers/tty/serial/rsci.c

131

#define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */

drivers/tty/serial/rsci.c

38

#define RDR_RDAT_MSK GENMASK(8, 0)

drivers/tty/serial/sc16is7xx.c

1335

s->gpio_valid_mask = GENMASK(7, 0);

drivers/tty/serial/sc16is7xx.c

1338

s->gpio_valid_mask = GENMASK(3, 0);

drivers/tty/serial/sc16is7xx.c

1341

s->gpio_valid_mask = GENMASK(7, 4);

drivers/tty/serial/sc16is7xx.c

99

#define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */

drivers/tty/serial/sh-sci-common.h

40

#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)

drivers/tty/serial/sprd_serial.c

47

#define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)

drivers/tty/serial/sprd_serial.c

48

#define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)

drivers/tty/serial/sprd_serial.c

92

#define THLD_RX_FULL_MASK GENMASK(6, 0)

drivers/tty/serial/sprd_serial.c

96

#define SPRD_CLKD0_MASK GENMASK(15, 0)

drivers/tty/serial/sprd_serial.c

98

#define SPRD_CLKD1_MASK GENMASK(20, 16)

drivers/tty/serial/stm32-usart.c

237

usartdiv = usartdiv & GENMASK(15, 0);

drivers/tty/serial/stm32-usart.c

241

usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))

drivers/tty/serial/stm32-usart.h

100

#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))

drivers/tty/serial/stm32-usart.h

106

#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */

drivers/tty/serial/stm32-usart.h

113

#define USART_CR2_STOP_MASK GENMASK(13, 12)

drivers/tty/serial/stm32-usart.h

121

#define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */

drivers/tty/serial/stm32-usart.h

123

#define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */

drivers/tty/serial/stm32-usart.h

142

#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */

drivers/tty/serial/stm32-usart.h

143

#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */

drivers/tty/serial/stm32-usart.h

148

#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */

drivers/tty/serial/stm32-usart.h

151

#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */

drivers/tty/serial/stm32-usart.h

155

#define USART_GTPR_PSC_MASK GENMASK(7, 0)

drivers/tty/serial/stm32-usart.h

156

#define USART_GTPR_GT_MASK GENMASK(15, 8)

drivers/tty/serial/stm32-usart.h

159

#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */

drivers/tty/serial/stm32-usart.h

160

#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */

drivers/tty/serial/stm32-usart.h

182

#define USART_PRESC GENMASK(3, 0) /* H7 */

drivers/tty/serial/stm32-usart.h

186

#define USART_HWCFGR1_CFG8 GENMASK(31, 28) /* MP1 */

drivers/tty/serial/stm32-usart.h

68

#define USART_DR_MASK GENMASK(8, 0)

drivers/tty/serial/stm32-usart.h

71

#define USART_BRR_DIV_F_MASK GENMASK(3, 0)

drivers/tty/serial/stm32-usart.h

72

#define USART_BRR_DIV_M_MASK GENMASK(15, 4)

drivers/tty/serial/stm32-usart.h

95

#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */

drivers/tty/serial/stm32-usart.h

96

#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */

drivers/tty/serial/sunplus-uart.c

56

#define SUP_UART_LSR_BRK_ERROR_BITS GENMASK(5, 2)

drivers/tty/vt/consolemap.c

195

#define UNI_DIR_BITS GENMASK(15, 11)

drivers/tty/vt/consolemap.c

196

#define UNI_ROW_BITS GENMASK(10, 6)

drivers/tty/vt/consolemap.c

197

#define UNI_GLYPH_BITS GENMASK( 5, 0)

drivers/tty/vt/vt.c

2967

GENMASK(ASCII_SHIFTIN, ASCII_BELL) | BIT(ASCII_CANCEL) |

drivers/ufs/core/ufs-mcq.c

20

#define MAX_QUEUE_SUP GENMASK(7, 0)

drivers/ufs/core/ufs-mcq.c

21

#define QCFGPTR GENMASK(23, 16)

drivers/ufs/core/ufs-mcq.c

28

#define MCQ_CFG_MAC_MASK GENMASK(16, 8)

drivers/ufs/core/ufs-mcq.c

284

BUILD_BUG_ON(sizeof(struct utp_transfer_cmd_desc) & GENMASK(6, 0));

drivers/ufs/host/ufs-exynos.c

121

#define ALLOW_PRE_FETCH GENMASK(22, 21)

drivers/ufs/host/ufs-exynos.c

122

#define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */

drivers/ufs/host/ufs-exynos.c

124

#define ALLOW_READ_CAPACITY GENMASK(16, 15)

drivers/ufs/host/ufs-exynos.c

127

#define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7)

drivers/ufs/host/ufs-exynos.c

131

#define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */

drivers/ufs/host/ufs-exynos.c

805

#define UFS_HW_VER_MAJOR_MASK GENMASK(15, 8)

drivers/ufs/host/ufs-qcom.c

32

#define MCQ_QCFGPTR_MASK GENMASK(7, 0)

drivers/ufs/host/ufs-qcom.h

131

#define TEST_BUS_SEL GENMASK(22, 19)

drivers/ufs/host/ufs-qcom.h

145

#define ESI_VEC_MASK GENMASK(22, 12)

drivers/ufs/host/ufs-qcom.h

148

#define MAX_HS_GEAR_MASK GENMASK(6, 4)

drivers/ufs/host/ufs-qcom.h

152

#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */

drivers/ufs/host/ufs-qcom.h

169

#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16)

drivers/ufs/host/ufs-qcom.h

170

#define CLK_1US_CYCLES_MASK GENMASK(7, 0)

drivers/ufs/host/ufs-qcom.h

173

#define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)

drivers/ufs/host/ufs-qcom.h

20

#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)

drivers/ufs/host/ufs-qcom.h

21

#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)

drivers/ufs/host/ufs-qcom.h

22

#define UFS_HW_VER_STEP_MASK GENMASK(15, 0)

drivers/ufs/host/ufs-qcom.h

23

#define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4)

drivers/ufs/host/ufs-qcom.h

29

#define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0)

drivers/ufs/host/ufs-qcom.h

33

#define DL_VS_CLK_CFG_MASK GENMASK(9, 0)

drivers/ufs/host/ufshcd-pci.c

220

#define INTEL_LTR_SCALE_MASK GENMASK(11, 10)

drivers/ufs/host/ufshcd-pci.c

223

#define INTEL_LTR_VALUE_MASK GENMASK(9, 0)

drivers/usb/cdns3/cdns3-gadget.h

1021

#define TRB_TYPE_BITMASK GENMASK(15, 10)

drivers/usb/cdns3/cdns3-gadget.h

1063

#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)

drivers/usb/cdns3/cdns3-gadget.h

1068

#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))

drivers/usb/cdns3/cdns3-gadget.h

1069

#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)

drivers/usb/cdns3/cdns3-gadget.h

1072

#define TRB_LEN(p) ((p) & GENMASK(16, 0))

drivers/usb/cdns3/cdns3-gadget.h

1075

#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))

drivers/usb/cdns3/cdns3-gadget.h

1076

#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)

drivers/usb/cdns3/cdns3-gadget.h

1079

#define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24))

drivers/usb/cdns3/cdns3-gadget.h

1080

#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)

drivers/usb/cdns3/cdns3-gadget.h

1083

#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))

drivers/usb/cdns3/cdns3-gadget.h

228

#define USB_STS_USBSPEED_MASK GENMASK(6, 4)

drivers/usb/cdns3/cdns3-gadget.h

311

#define USB_STS_LPMST_MASK GENMASK(19, 18)

drivers/usb/cdns3/cdns3-gadget.h

348

#define USB_STS_LST_MASK GENMASK(29, 26)

drivers/usb/cdns3/cdns3-gadget.h

386

#define USB_CMD_FADDR_MASK GENMASK(7, 1)

drivers/usb/cdns3/cdns3-gadget.h

393

#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)

drivers/usb/cdns3/cdns3-gadget.h

403

#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)

drivers/usb/cdns3/cdns3-gadget.h

409

#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)

drivers/usb/cdns3/cdns3-gadget.h

418

#define USB_ITPN_MASK GENMASK(13, 0)

drivers/usb/cdns3/cdns3-gadget.h

423

#define USB_LPM_HIRD_MASK GENMASK(3, 0)

drivers/usb/cdns3/cdns3-gadget.h

530

#define EP_SEL_EPNO_MASK GENMASK(3, 0)

drivers/usb/cdns3/cdns3-gadget.h

552

#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)

drivers/usb/cdns3/cdns3-gadget.h

563

#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)

drivers/usb/cdns3/cdns3-gadget.h

567

#define EP_CFG_MULT_MASK GENMASK(15, 14)

drivers/usb/cdns3/cdns3-gadget.h

571

#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)

drivers/usb/cdns3/cdns3-gadget.h

574

#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)

drivers/usb/cdns3/cdns3-gadget.h

603

#define EP_CMD_TDL_MASK GENMASK(15, 9)

drivers/usb/cdns3/cdns3-gadget.h

609

#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)

drivers/usb/cdns3/cdns3-gadget.h

648

#define EP_STS_SPSMST_MASK GENMASK(18, 17)

drivers/usb/cdns3/cdns3-gadget.h

656

#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)

drivers/usb/cdns3/cdns3-gadget.h

666

#define EP_STS_SID_MASK GENMASK(15, 0)

drivers/usb/cdns3/cdns3-gadget.h

755

#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)

drivers/usb/cdns3/cdns3-gadget.h

769

#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)

drivers/usb/cdns3/cdns3-gadget.h

783

#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)

drivers/usb/cdns3/cdns3-gadget.h

797

#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)

drivers/usb/cdns3/cdns3-gadget.h

807

#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)

drivers/usb/cdns3/cdns3-gadget.h

821

#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)

drivers/usb/cdns3/cdns3-gadget.h

873

#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))

drivers/usb/cdns3/cdns3-gadget.h

888

#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))

drivers/usb/cdns3/cdns3-gadget.h

901

#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))

drivers/usb/cdns3/cdns3-gadget.h

903

#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))

drivers/usb/cdns3/cdns3-gadget.h

915

#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))

drivers/usb/cdns3/cdns3-gadget.h

920

#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)

drivers/usb/cdns3/cdns3-gadget.h

921

#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))

drivers/usb/cdns3/cdns3-gadget.h

932

#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))

drivers/usb/cdns3/cdns3-gadget.h

960

#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))

drivers/usb/cdns3/cdns3-gadget.h

962

#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)

drivers/usb/cdns3/cdns3-imx.c

37

#define SW_RESET_MASK GENMASK(31, 26)

drivers/usb/cdns3/cdns3-imx.c

85

#define PS_MASK GENMASK(1, 0)

drivers/usb/cdns3/cdns3-starfive.c

25

#define USB_STRAP_MASK GENMASK(18, 16)

drivers/usb/cdns3/cdns3-starfive.c

30

#define USB_MISC_CFG_MASK GENMASK(23, 20)

drivers/usb/cdns3/cdns3-ti.c

36

#define USBSS_W1_MODESTRAP_MASK GENMASK(18, 17)

drivers/usb/cdns3/cdns3-ti.c

41

#define USBSS1_STATIC_PLL_REF_SEL_MASK GENMASK(8, 5)

drivers/usb/cdns3/cdns3-ti.c

43

#define USBSS1_STATIC_LOOPBACK_MODE_MASK GENMASK(4, 3)

drivers/usb/cdns3/cdns3-ti.c

45

#define USBSS1_STATIC_VBUS_SEL_MASK GENMASK(2, 1)

drivers/usb/cdns3/cdnsp-ep0.c

197

temp = readl(&pdev->active_port->regs->portpmsc) & ~GENMASK(31, 28);

drivers/usb/cdns3/cdnsp-gadget.h

1001

#define GET_PORT_ID(p) (((p) & GENMASK(31, 24)) >> 24)

drivers/usb/cdns3/cdnsp-gadget.h

1002

#define SET_PORT_ID(p) (((p) << 24) & GENMASK(31, 24))

drivers/usb/cdns3/cdnsp-gadget.h

1007

#define TRB_LEN(p) ((p) & GENMASK(16, 0))

drivers/usb/cdns3/cdnsp-gadget.h

1010

#define GET_TD_SIZE(p) (((p) & GENMASK(21, 17)) >> 17)

drivers/usb/cdns3/cdnsp-gadget.h

1017

#define TRB_INTR_TARGET(p) (((p) << 22) & GENMASK(31, 22))

drivers/usb/cdns3/cdnsp-gadget.h

1018

#define GET_INTR_TARGET(p) (((p) & GENMASK(31, 22)) >> 22)

drivers/usb/cdns3/cdnsp-gadget.h

1052

#define TRB_SETUPID_BITMASK GENMASK(9, 8)

drivers/usb/cdns3/cdnsp-gadget.h

1066

#define TRB_FRAME_ID(p) (((p) << 20) & GENMASK(30, 20))

drivers/usb/cdns3/cdnsp-gadget.h

1080

#define TRB_TYPE_BITMASK GENMASK(15, 10)

drivers/usb/cdns3/cdnsp-gadget.h

237

#define CMD_RING_RSVD_BITS GENMASK(5, 0)

drivers/usb/cdns3/cdnsp-gadget.h

241

#define MAX_DEVS GENMASK(7, 0)

drivers/usb/cdns3/cdnsp-gadget.h

257

#define PORT_PLS_MASK GENMASK(8, 5)

drivers/usb/cdns3/cdnsp-gadget.h

283

#define DEV_SPEED_MASK GENMASK(13, 10)

drivers/usb/cdns3/cdnsp-gadget.h

335

#define PORT_U1_TIMEOUT_MASK GENMASK(7, 0)

drivers/usb/cdns3/cdnsp-gadget.h

338

#define PORT_U2_TIMEOUT_MASK GENMASK(14, 8)

drivers/usb/cdns3/cdnsp-gadget.h

342

#define PORT_L1S_MASK GENMASK(2, 0)

drivers/usb/cdns3/cdnsp-gadget.h

351

#define PORT_BESL(p) (((p) << 4) & GENMASK(7, 4))

drivers/usb/cdns3/cdnsp-gadget.h

355

#define PORT_RRBESL(p) (((p) & GENMASK(20, 17)) >> 17)

drivers/usb/cdns3/cdnsp-gadget.h

357

#define PORT_TEST_MODE_MASK GENMASK(31, 28)

drivers/usb/cdns3/cdnsp-gadget.h

399

#define IMOD_INTERVAL_MASK GENMASK(15, 0)

drivers/usb/cdns3/cdnsp-gadget.h

401

#define IMOD_COUNTER_MASK GENMASK(31, 16)

drivers/usb/cdns3/cdnsp-gadget.h

406

#define ERST_SIZE_MASK GENMASK(31, 16)

drivers/usb/cdns3/cdnsp-gadget.h

413

#define ERST_DESI_MASK GENMASK(2, 0)

drivers/usb/cdns3/cdnsp-gadget.h

416

#define ERST_PTR_MASK GENMASK(3, 0)

drivers/usb/cdns3/cdnsp-gadget.h

454

#define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0))

drivers/usb/cdns3/cdnsp-gadget.h

455

#define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0))

drivers/usb/cdns3/cdnsp-gadget.h

528

#define CHICKEN_APB_TIMEOUT_SET(p, val) (((p) & ~GENMASK(21, 0)) | (val))

drivers/usb/cdns3/cdnsp-gadget.h

602

#define DEV_SPEED GENMASK(23, 20)

drivers/usb/cdns3/cdnsp-gadget.h

605

#define LAST_CTX_MASK ((unsigned int)GENMASK(31, 27))

drivers/usb/cdns3/cdnsp-gadget.h

617

#define DEV_ADDR_MASK GENMASK(7, 0)

drivers/usb/cdns3/cdnsp-gadget.h

619

#define SLOT_STATE GENMASK(31, 27)

drivers/usb/cdns3/cdnsp-gadget.h

665

#define EP_STATE_MASK GENMASK(3, 0)

drivers/usb/cdns3/cdnsp-gadget.h

674

#define EP_MULT(p) (((p) << 8) & GENMASK(9, 8))

drivers/usb/cdns3/cdnsp-gadget.h

675

#define CTX_TO_EP_MULT(p) (((p) & GENMASK(9, 8)) >> 8)

drivers/usb/cdns3/cdnsp-gadget.h

679

#define EP_INTERVAL(p) (((p) << 16) & GENMASK(23, 16))

drivers/usb/cdns3/cdnsp-gadget.h

68

#define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0))

drivers/usb/cdns3/cdnsp-gadget.h

680

#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) & GENMASK(23, 16)) >> 16))

drivers/usb/cdns3/cdnsp-gadget.h

681

#define CTX_TO_EP_INTERVAL(p) (((p) & GENMASK(23, 16)) >> 16)

drivers/usb/cdns3/cdnsp-gadget.h

682

#define EP_MAXPSTREAMS_MASK GENMASK(14, 10)

drivers/usb/cdns3/cdnsp-gadget.h

70

#define HC_VERSION(p) (((p) >> 16) & GENMASK(15, 1))

drivers/usb/cdns3/cdnsp-gadget.h

701

#define MAX_BURST(p) (((p) << 8) & GENMASK(15, 8))

drivers/usb/cdns3/cdnsp-gadget.h

702

#define CTX_TO_MAX_BURST(p) (((p) & GENMASK(15, 8)) >> 8)

drivers/usb/cdns3/cdnsp-gadget.h

703

#define MAX_PACKET(p) (((p) << 16) & GENMASK(31, 16))

drivers/usb/cdns3/cdnsp-gadget.h

704

#define MAX_PACKET_MASK GENMASK(31, 16)

drivers/usb/cdns3/cdnsp-gadget.h

705

#define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16)

drivers/usb/cdns3/cdnsp-gadget.h

708

#define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0))

drivers/usb/cdns3/cdnsp-gadget.h

709

#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) << 16) & GENMASK(31, 16))

drivers/usb/cdns3/cdnsp-gadget.h

710

#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) & GENMASK(23, 16)) >> 16) << 24)

drivers/usb/cdns3/cdnsp-gadget.h

711

#define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16)

drivers/usb/cdns3/cdnsp-gadget.h

712

#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24)

drivers/usb/cdns3/cdnsp-gadget.h

74

#define HCS_ENDPOINTS_MASK GENMASK(7, 0)

drivers/usb/cdns3/cdnsp-gadget.h

757

#define SCT_FOR_CTX(p) (((p) << 1) & GENMASK(3, 1))

drivers/usb/cdns3/cdnsp-gadget.h

88

#define HCC_EXT_CAPS(p) (((p) & GENMASK(31, 16)) >> 16)

drivers/usb/cdns3/cdnsp-gadget.h

880

#define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0))

drivers/usb/cdns3/cdnsp-gadget.h

915

#define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0))

drivers/usb/cdns3/cdnsp-gadget.h

916

#define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0))

drivers/usb/cdns3/cdnsp-gadget.h

921

#define TRB_TO_EP_ID(p) (((p) & GENMASK(20, 16)) >> 16)

drivers/usb/cdns3/cdnsp-gadget.h

93

#define DBOFF_MASK GENMASK(31, 2)

drivers/usb/cdns3/cdnsp-gadget.h

959

#define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0))

drivers/usb/cdns3/cdnsp-gadget.h

96

#define RTSOFF_MASK GENMASK(31, 5)

drivers/usb/cdns3/cdnsp-gadget.h

961

#define TRB_FH_TO_DEVICE_ADDRESS(p) (((p) << 25) & GENMASK(31, 25))

drivers/usb/cdns3/cdnsp-gadget.h

963

#define TRB_FH_TO_NOT_TYPE(p) (((p) << 4) & GENMASK(7, 4))

drivers/usb/cdns3/cdnsp-gadget.h

965

#define TRB_FH_TO_INTERFACE(p) (((p) << 8) & GENMASK(15, 8))

drivers/usb/cdns3/cdnsp-gadget.h

973

#define TRB_TO_SLOT_ID(p) (((p) & GENMASK(31, 24)) >> 24)

drivers/usb/cdns3/cdnsp-gadget.h

974

#define SLOT_ID_FOR_TRB(p) (((p) << 24) & GENMASK(31, 24))

drivers/usb/cdns3/cdnsp-gadget.h

979

#define EP_ID_FOR_TRB(p) ((((p) + 1) << 16) & GENMASK(20, 16))

drivers/usb/cdns3/cdnsp-gadget.h

986

#define TRB_TO_STREAM_ID(p) ((((p) & GENMASK(31, 16)) >> 16))

drivers/usb/cdns3/cdnsp-gadget.h

987

#define STREAM_ID_FOR_TRB(p) ((((p)) << 16) & GENMASK(31, 16))

drivers/usb/cdns3/drd.h

107

#define CDNS_RID(p) ((p) & GENMASK(15, 0))

drivers/usb/cdns3/drd.h

110

#define CDNS_DID(p) ((p) & GENMASK(31, 0))

drivers/usb/cdns3/drd.h

170

#define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12)

drivers/usb/cdns3/drd.h

187

#define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0)

drivers/usb/cdns3/drd.h

188

#define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3)

drivers/usb/cdns3/drd.h

83

#define OTG_CDNSP_CHECK_DID(did) (((did) & GENMASK(31, 8)) == 0x00040300)

drivers/usb/cdns3/drd.h

86

#define OTG_CDNS3_CHECK_DID(did) (((did) & GENMASK(31, 8)) == 0x00040200)

drivers/usb/chipidea/ulpi.c

48

return hw_read(ci, OP_ULPI_VIEWPORT, GENMASK(15, 8)) >> 8;

drivers/usb/dwc2/hw.h

226

#define GSNPSID_ID_MASK GENMASK(31, 16)

drivers/usb/dwc3/core.h

254

#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19)

drivers/usb/dwc3/core.h

413

#define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8)

drivers/usb/dwc3/core.h

415

#define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24)

drivers/usb/dwc3/dwc3-am62.c

102

#define PHY_PLL_REFCLK_MASK GENMASK(3, 0)

drivers/usb/dwc3/dwc3-am62.c

46

#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)

drivers/usb/dwc3/dwc3-am62.c

51

#define USBSS_CORE_OPERATIONAL_MODE_MASK GENMASK(13, 12)

drivers/usb/dwc3/dwc3-apple.c

123

#define APPLE_DWC3_CIO_PENDING_HP_TIMER GENMASK(23, 16)

drivers/usb/dwc3/dwc3-apple.c

125

#define APPLE_DWC3_CIO_PM_LC_TIMER GENMASK(15, 8)

drivers/usb/dwc3/dwc3-apple.c

127

#define APPLE_DWC3_CIO_PM_ENTRY_TIMER GENMASK(7, 0)

drivers/usb/dwc3/dwc3-google.c

26

#define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0)

drivers/usb/dwc3/dwc3-google.c

27

#define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3)

drivers/usb/dwc3/dwc3-google.c

31

#define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4)

drivers/usb/dwc3/dwc3-imx8mp.c

39

#define USB_WAKEUP_EN_MASK GENMASK(5, 0)

drivers/usb/dwc3/dwc3-meson-g12a.c

58

#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)

drivers/usb/dwc3/dwc3-meson-g12a.c

59

#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)

drivers/usb/dwc3/dwc3-meson-g12a.c

65

#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)

drivers/usb/dwc3/dwc3-meson-g12a.c

66

#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)

drivers/usb/dwc3/dwc3-meson-g12a.c

67

#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)

drivers/usb/dwc3/dwc3-meson-g12a.c

71

#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)

drivers/usb/dwc3/dwc3-meson-g12a.c

72

#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)

drivers/usb/dwc3/dwc3-meson-g12a.c

75

#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)

drivers/usb/dwc3/dwc3-meson-g12a.c

76

#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)

drivers/usb/dwc3/dwc3-meson-g12a.c

80

#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)

drivers/usb/dwc3/dwc3-meson-g12a.c

81

#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)

drivers/usb/dwc3/dwc3-meson-g12a.c

87

#define USB_R4_MEM_PD_MASK GENMASK(3, 2)

drivers/usb/dwc3/dwc3-meson-g12a.c

93

#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)

drivers/usb/dwc3/dwc3-meson-g12a.c

98

#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)

drivers/usb/dwc3/dwc3-meson-g12a.c

99

#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)

drivers/usb/gadget/function/uvc_configfs.c

68

if (num != (num & GENMASK((size * 8) - 1, 0)))

drivers/usb/gadget/udc/aspeed-vhub/core.c

211

port_mask = GENMASK(vhub->max_ports, 1);

drivers/usb/gadget/udc/aspeed-vhub/core.c

220

epn_mask = GENMASK(vhub->max_epns - 1, 0);

drivers/usb/gadget/udc/aspeed-vhub/core.c

332

vhub->port_irq_mask = GENMASK(VHUB_IRQ_DEV1_BIT + vhub->max_ports - 1,

drivers/usb/gadget/udc/aspeed-vhub/dev.c

124

val &= ~GENMASK(10, 8);

drivers/usb/gadget/udc/aspeed-vhub/hub.c

229

val &= ~GENMASK(10, 8);

drivers/usb/gadget/udc/aspeed_udc.c

70

#define UDC_CFG_ADDR_MASK GENMASK(6, 0)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

154

#define ENDPRST_EP GENMASK(3, 0)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

250

#define LPMCTRLLL_HIRD GENMASK(7, 4)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

276

#define FIFOCTRL_EP GENMASK(3, 0)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

458

#define TRB_TYPE_BITMASK GENMASK(15, 10)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

482

#define TRB_LEN(p) ((p) & GENMASK(16, 0))

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

483

#define TRB_BURST(p) (((p) << 24) & GENMASK(31, 24))

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

484

#define TRB_FIELD_TO_BURST(p) (((p) & GENMASK(31, 24)) >> 24)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

487

#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

89

#define EPX_CON_BUF GENMASK(1, 0)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

91

#define EPX_CON_TYPE GENMASK(3, 2)

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

99

#define EPX_CON_ISOD GENMASK(5, 4)

drivers/usb/gadget/udc/max3420_udc.c

132

#define CONNECT_HOST GENMASK(4, 3)

drivers/usb/gadget/udc/max3420_udc.c

135

#define UDC_START GENMASK(6, 5)

drivers/usb/gadget/udc/max3420_udc.c

138

#define ENABLE_EP GENMASK(8, 7)

drivers/usb/gadget/udc/max3420_udc.c

141

#define STALL_EP GENMASK(10, 9)

drivers/usb/gadget/udc/max3420_udc.c

145

#define MAX3420_CMD(c) FIELD_PREP(GENMASK(7, 3), c)

drivers/usb/gadget/udc/renesas_usb3.c

104

#define USB_COM_CON_DEV_ADDR_MASK GENMASK(14, USB_COM_CON_DEV_ADDR_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

115

#define USB20_CON_B2_TSTMOD_MASK GENMASK(10, USB20_CON_B2_TSTMOD_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

122

#define USB30_CON_POW_SEL_MASK GENMASK(26, USB30_CON_POW_SEL_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

208

#define PN_MOD_TYPE_MASK GENMASK(5, PN_MOD_TYPE_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

211

#define PN_MOD_EPNUM_MASK GENMASK(3, 0)

drivers/usb/gadget/udc/renesas_usb3.c

216

#define PN_RAMMAP_RAMAREA_MASK GENMASK(31, PN_RAMMAP_RAMAREA_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

223

#define PN_RAMMAP_MPKT_MASK GENMASK(26, PN_RAMMAP_MPKT_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

227

#define PN_RAMMAP_RAMIF_MASK GENMASK(15, PN_RAMMAP_RAMIF_SHIFT)

drivers/usb/gadget/udc/renesas_usb3.c

230

#define PN_RAMMAP_BASEAD_MASK GENMASK(13, 0)

drivers/usb/gadget/udc/renesas_usb3.c

291

#define USB3_PRD1_SIZE_MASK GENMASK(15, 0)

drivers/usb/gadget/udc/renesas_usb3.c

88

#define DMA_CON_PIPE_NO_MASK GENMASK(12, DMA_CON_PIPE_NO_SHIFT)

drivers/usb/gadget/udc/tegra-xudc.c

103

#define MFINDEX_FRAME_MASK GENMASK(13, 3)

drivers/usb/gadget/udc/tegra-xudc.c

105

#define PORTPM_L1S_MASK GENMASK(1, 0)

drivers/usb/gadget/udc/tegra-xudc.c

112

#define PORTPM_U2TIMEOUT_MASK GENMASK(15, 8)

drivers/usb/gadget/udc/tegra-xudc.c

113

#define PORTPM_U1TIMEOUT_MASK GENMASK(23, 16)

drivers/usb/gadget/udc/tegra-xudc.c

128

#define DEVNOTIF_LO_TYPE_MASK GENMASK(7, 4)

drivers/usb/gadget/udc/tegra-xudc.c

142

#define HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK GENMASK(29, 0)

drivers/usb/gadget/udc/tegra-xudc.c

147

#define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0)

drivers/usb/gadget/udc/tegra-xudc.c

150

#define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

154

#define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0)

drivers/usb/gadget/udc/tegra-xudc.c

158

#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

162

#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

166

#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

170

#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

174

#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

178

#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

182

#define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0)

drivers/usb/gadget/udc/tegra-xudc.c

194

#define CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK GENMASK(31, 0)

drivers/usb/gadget/udc/tegra-xudc.c

198

#define CFG_DEV_FE_PORTREGSEL_MASK GENMASK(1, 0)

drivers/usb/gadget/udc/tegra-xudc.c

210

#define XUSB_DEV_CFG_4_BASE_ADDR_MASK GENMASK(31, 15)

drivers/usb/gadget/udc/tegra-xudc.c

35

#define DB_TARGET_MASK GENMASK(15, 8)

drivers/usb/gadget/udc/tegra-xudc.c

37

#define DB_STREAMID_MASK GENMASK(31, 16)

drivers/usb/gadget/udc/tegra-xudc.c

41

#define ERSTSZ_ERSTXSZ_MASK GENMASK(15, 0)

drivers/usb/gadget/udc/tegra-xudc.c

58

#define CTRL_DEVADDR_MASK GENMASK(30, 24)

drivers/usb/gadget/udc/tegra-xudc.c

65

#define RT_IMOD_IMODI_MASK GENMASK(15, 0)

drivers/usb/gadget/udc/tegra-xudc.c

67

#define RT_IMOD_IMODC_MASK GENMASK(31, 16)

drivers/usb/gadget/udc/tegra-xudc.c

74

#define PORTSC_PLS_MASK GENMASK(8, 5)

drivers/usb/gadget/udc/tegra-xudc.c

84

#define PORTSC_PS_MASK GENMASK(13, 10)

drivers/usb/host/ehci-mv.c

215

status &= ~GENMASK(31, 30);

drivers/usb/host/ehci-orion.c

30

#define USB_MODE_MASK GENMASK(1, 0)

drivers/usb/host/xhci-histb.c

29

#define USB3_DEEMPHASIS_MASK GENMASK(2, 1)

drivers/usb/host/xhci-mtk.c

73

#define ITP_DELTA_CLK_MASK GENMASK(5, 1)

drivers/usb/host/xhci-mtk.c

75

#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)

drivers/usb/host/xhci-mtk.c

78

#define SCH3_RXFIFO_DEPTH_MASK GENMASK(21, 20)

drivers/usb/host/xhci-mtk.c

83

#define XSEOF_OFFSET_MASK GENMASK(11, 0)

drivers/usb/host/xhci-pci-renesas.c

24

#define RENESAS_FW_VERSION_FIELD GENMASK(23, 7)

drivers/usb/host/xhci-pci-renesas.c

29

#define RENESAS_FW_STATUS_RESULT GENMASK(6, 4)

drivers/usb/host/xhci-pci-renesas.c

39

#define RENESAS_ROM_STATUS_RESULT GENMASK(6, 4)

drivers/usb/host/xhci-pci-renesas.c

449

status &= GENMASK(6, 4);

drivers/usb/mtu3/mtu3_hw_regs.h

104

#define LV1IECR_MSK GENMASK(31, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

121

#define EP0_MAXPKTSZ_MSK GENMASK(9, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

133

#define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

172

#define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

216

#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

271

#define DEV_ADDR_MSK GENMASK(30, 24)

drivers/usb/mtu3/mtu3_hw_regs.h

351

#define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)

drivers/usb/mtu3/mtu3_hw_regs.h

353

#define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)

drivers/usb/mtu3/mtu3_hw_regs.h

354

#define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

369

#define LINK_ERROR_COUNT GENMASK(15, 0)

drivers/usb/mtu3/mtu3_hw_regs.h

372

#define DEV_NOTIF_TYPE_SPECIFIC_LOW_MSK GENMASK(31, 8)

drivers/usb/mtu3/mtu3_hw_regs.h

376

#define DEV_NOTIF_TYPE_MSK GENMASK(7, 4)

drivers/usb/mtu3/mtu3_hw_regs.h

439

#define WTCHRP_MSK GENMASK(19, 16)

drivers/usb/mtu3/mtu3_hw_regs.h

445

#define LPM_BESL GENMASK(3, 0)

drivers/usb/musb/mediatek.c

30

#define MTK_TOGGLE_EN GENMASK(15, 0)

drivers/usb/musb/mediatek.c

37

#define DMA_INTR_STATUS_MSK GENMASK(7, 0)

drivers/usb/musb/mediatek.c

38

#define DMA_INTR_UNMASK_SET_MSK GENMASK(31, 24)

drivers/usb/renesas_usbhs/common.c

276

u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0);

drivers/usb/serial/cp210x.c

477

#define CP210X_SERIAL_DTR_MASK GENMASK(1, 0)

drivers/usb/serial/cp210x.c

492

#define CP210X_SERIAL_RTS_MASK GENMASK(7, 6)

drivers/usb/serial/cp210x.c

537

#define CP210X_SCI_GPIO_MODE_MASK GENMASK(11, 9)

drivers/usb/serial/cp210x.c

540

#define CP210X_ECI_GPIO_MODE_MASK GENMASK(3, 2)

drivers/usb/serial/cp210x.c

543

#define CP210X_GPIO_MODE_MASK GENMASK(11, 8)

drivers/usb/serial/f81232.c

100

#define F81534A_TRIGGER_MASK GENMASK(3, 2)

drivers/usb/serial/f81232.c

97

#define F81232_CLK_MASK GENMASK(1, 0)

drivers/usb/serial/f81534.c

108

#define F81534_PORT_CONF_MODE_MASK GENMASK(1, 0)

drivers/usb/serial/f81534.c

136

#define F81534_CLK_MASK GENMASK(2, 1)

drivers/usb/serial/mos7840.c

148

#define MCS_PORT_MASK GENMASK(2, 0)

drivers/usb/serial/xr_serial.c

518

state = GENMASK(type->reg_width - 1, 0);

drivers/usb/serial/xr_serial.c

70

#define XR_UART_DATA_MASK GENMASK(3, 0)

drivers/usb/serial/xr_serial.c

74

#define XR_UART_PARITY_MASK GENMASK(6, 4)

drivers/usb/serial/xr_serial.c

91

#define XR_GPIO_MODE_SEL_MASK GENMASK(2, 0)

drivers/usb/typec/mux/fsa4480.c

18

#define FSA4480_DEVICE_ID_VENDOR_ID GENMASK(7, 6)

drivers/usb/typec/mux/fsa4480.c

19

#define FSA4480_DEVICE_ID_VERSION_ID GENMASK(5, 3)

drivers/usb/typec/mux/fsa4480.c

20

#define FSA4480_DEVICE_ID_REV_ID GENMASK(2, 0)

drivers/usb/typec/mux/fsa4480.c

38

#define FSA4480_ENABLE_SBU GENMASK(6, 5)

drivers/usb/typec/mux/fsa4480.c

39

#define FSA4480_ENABLE_USB GENMASK(4, 3)

drivers/usb/typec/mux/fsa4480.c

44

#define FSA4480_SEL_SBU_REVERSE GENMASK(6, 5)

drivers/usb/typec/mux/fsa4480.c

45

#define FSA4480_SEL_USB GENMASK(4, 3)

drivers/usb/typec/mux/intel_pmc_mux.c

104

#define IOM_PORT_STATUS_DHPD_HPD_STATUS_MASK GENMASK(13, 12)

drivers/usb/typec/mux/intel_pmc_mux.c

75

#define PMC_USB_ALTMODE_CABLE_SPD(_s_) (((_s_) & GENMASK(2, 0)) << 25)

drivers/usb/typec/mux/intel_pmc_mux.c

79

#define PMC_USB_ALTMODE_TBT_GEN(_g_) (((_g_) & GENMASK(1, 0)) << 28)

drivers/usb/typec/mux/intel_pmc_mux.c

88

#define IOM_PORT_STATUS_ACTIVITY_TYPE_MASK GENMASK(9, 6)

drivers/usb/typec/mux/it5205.c

34

#define IT5205_DP_USB_CTRL_MASK GENMASK(3, 0)

drivers/usb/typec/mux/it5205.c

41

#define IT5205_VREF_SELECT_MASK GENMASK(5, 4)

drivers/usb/typec/mux/it5205.c

47

#define IT5205_OVP_SELECT_MASK GENMASK(5, 4)

drivers/usb/typec/mux/nb7vpq904m.c

35

#define GEN_DEV_SET_OP_MODE_MASK GENMASK(3, 1)

drivers/usb/typec/mux/nb7vpq904m.c

44

#define EQ_SETTING_MASK GENMASK(3, 1)

drivers/usb/typec/mux/nb7vpq904m.c

48

#define OUTPUT_COMPRESSION_MASK GENMASK(2, 1)

drivers/usb/typec/mux/nb7vpq904m.c

52

#define FLAT_GAIN_MASK GENMASK(1, 0)

drivers/usb/typec/mux/nb7vpq904m.c

56

#define LOSS_MATCH_MASK GENMASK(1, 0)

drivers/usb/typec/mux/ptn36502.c

28

#define PTN36502_CHIP_REVISION_BASE_MASK GENMASK(7, 4)

drivers/usb/typec/mux/ptn36502.c

29

#define PTN36502_CHIP_REVISION_METAL_MASK GENMASK(3, 0)

drivers/usb/typec/mux/ptn36502.c

32

#define PTN36502_DP_LINK_CTRL_LANES_MASK GENMASK(3, 2)

drivers/usb/typec/mux/ptn36502.c

35

#define PTN36502_DP_LINK_CTRL_LINK_RATE_MASK GENMASK(1, 0)

drivers/usb/typec/mux/ptn36502.c

40

#define PTN36502_DP_LANE_CTRL_RX_GAIN_MASK GENMASK(6, 4)

drivers/usb/typec/mux/ptn36502.c

42

#define PTN36502_DP_LANE_CTRL_TX_SWING_MASK GENMASK(3, 2)

drivers/usb/typec/mux/ptn36502.c

44

#define PTN36502_DP_LANE_CTRL_PRE_EMPHASIS_MASK GENMASK(1, 0)

drivers/usb/typec/mux/ptn36502.c

48

#define PTN36502_MODE_CTRL1_PLUG_ORIENT_MASK GENMASK(5, 5)

drivers/usb/typec/mux/ptn36502.c

50

#define PTN36502_MODE_CTRL1_AUX_CROSSBAR_MASK GENMASK(3, 3)

drivers/usb/typec/mux/ptn36502.c

52

#define PTN36502_MODE_CTRL1_MODE_MASK GENMASK(2, 0)

drivers/usb/typec/mux/ptn36502.c

59

#define PTN36502_DEVICE_CTRL_AUX_MONITORING_MASK GENMASK(7, 7)

drivers/usb/typec/mux/tusb1046.c

24

#define TUSB1046_GENERAL_CTLSEL GENMASK(1, 0)

drivers/usb/typec/mux/wcd939x-usbss.c

107

#define WCD_USBSS_EQUALIZER1_BW_SETTINGS GENMASK(6, 3)

drivers/usb/typec/mux/wcd939x-usbss.c

113

#define WCD_USBSS_USB_SS_CNTL_USB_SS_MODE GENMASK(2, 0)

drivers/usb/typec/mux/wcd939x-usbss.c

228

{ WCD_USBSS_AUD_COEF_L_K5_0, GENMASK(7, 0), 0x39 },

drivers/usb/typec/mux/wcd939x-usbss.c

229

{ WCD_USBSS_AUD_COEF_R_K5_0, GENMASK(7, 0), 0x39 },

drivers/usb/typec/mux/wcd939x-usbss.c

230

{ WCD_USBSS_GND_COEF_L_K2_0, GENMASK(7, 0), 0xe8 },

drivers/usb/typec/mux/wcd939x-usbss.c

231

{ WCD_USBSS_GND_COEF_L_K4_0, GENMASK(7, 0), 0x73 },

drivers/usb/typec/mux/wcd939x-usbss.c

232

{ WCD_USBSS_GND_COEF_R_K2_0, GENMASK(7, 0), 0xe8 },

drivers/usb/typec/mux/wcd939x-usbss.c

233

{ WCD_USBSS_GND_COEF_R_K4_0, GENMASK(7, 0), 0x73 },

drivers/usb/typec/mux/wcd939x-usbss.c

234

{ WCD_USBSS_RATIO_SPKR_REXT_L_LSB, GENMASK(7, 0), 0x00 },

drivers/usb/typec/mux/wcd939x-usbss.c

235

{ WCD_USBSS_RATIO_SPKR_REXT_L_MSB, GENMASK(6, 0), 0x04 },

drivers/usb/typec/mux/wcd939x-usbss.c

236

{ WCD_USBSS_RATIO_SPKR_REXT_R_LSB, GENMASK(7, 0), 0x00 },

drivers/usb/typec/mux/wcd939x-usbss.c

237

{ WCD_USBSS_RATIO_SPKR_REXT_R_MSB, GENMASK(6, 0), 0x04 },

drivers/usb/typec/mux/wcd939x-usbss.c

51

#define WCD_USBSS_DISP_AUXP_THRESH_DISP_AUXP_OVPON_CM GENMASK(7, 5)

drivers/usb/typec/mux/wcd939x-usbss.c

55

#define WCD_USBSS_DISP_AUXP_CTL_LK_CANCEL_TRK_COEFF GENMASK(2, 0)

drivers/usb/typec/mux/wcd939x-usbss.c

74

#define WCD_USBSS_SWITCH_SELECT0_DNL_SWITCHES GENMASK(5, 4)

drivers/usb/typec/mux/wcd939x-usbss.c

75

#define WCD_USBSS_SWITCH_SELECT0_DPR_SWITCHES GENMASK(3, 2)

drivers/usb/typec/mux/wcd939x-usbss.c

99

#define WCD_USBSS_FUNCTION_ENABLE_SOURCE_SELECT GENMASK(1, 0)

drivers/usb/typec/rt1719.c

29

#define RT1719_REQSRCPDO_MASK GENMASK(2, 0)

drivers/usb/typec/rt1719.c

36

#define RT1719_CC1_STAT GENMASK(9, 8)

drivers/usb/typec/rt1719.c

37

#define RT1719_CC2_STAT GENMASK(11, 10)

drivers/usb/typec/rt1719.c

40

#define RT1719_PDSPECREV_MASK GENMASK(21, 20)

drivers/usb/typec/rt1719.c

41

#define RT1719_SPDOSEL_MASK GENMASK(18, 16)

drivers/usb/typec/rt1719.c

42

#define RT1719_SPDONUM_MASK GENMASK(15, 13)

drivers/usb/typec/rt1719.c

51

#define RT1719_LATPSEL_MASK GENMASK(5, 0)

drivers/usb/typec/rt1719.c

52

#define RT1719_USBINFO_MASK GENMASK(1, 0)

drivers/usb/typec/stusb160x.c

104

#define STUSB160X_SHIFT_LOW_VBUS_LIMIT GENMASK(3, 0)

drivers/usb/typec/stusb160x.c

105

#define STUSB160X_SHIFT_HIGH_VBUS_LIMIT GENMASK(7, 4)

drivers/usb/typec/stusb160x.c

111

#define STUSBXX02_VBUS_DISCHARGE_TIME_TO_PDO GENMASK(3, 0)

drivers/usb/typec/stusb160x.c

112

#define STUSB160X_VBUS_DISCHARGE_TIME_TO_0V GENMASK(7, 4)

drivers/usb/typec/stusb160x.c

122

#define STUSB160X_CC_POWER_MODE GENMASK(2, 0)

drivers/usb/typec/stusb160x.c

126

#define STUSB160X_VBUS_VSAFE0V_THRESHOLD GENMASK(2, 1)

drivers/usb/typec/stusb160x.c

44

#define STUSB160X_ALL_ALERTS GENMASK(6, 4)

drivers/usb/typec/stusb160x.c

54

#define STUSB160X_CC_ATTACHED_MODE GENMASK(7, 5)

drivers/usb/typec/stusb160x.c

69

#define STUSB160X_TYPEC_FSM_STATE GENMASK(4, 0)

drivers/usb/typec/stusb160x.c

70

#define STUSB160X_SINK_POWER_STATE GENMASK(6, 5)

drivers/usb/typec/stusb160x.c

94

#define STUSB160X_CC_CURRENT_ADVERTISED GENMASK(7, 6)

drivers/usb/typec/stusb160x.c

97

#define STUSB160X_CC_VCONN_SWITCH_ILIM GENMASK(3, 0)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

109

#define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

145

#define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

146

#define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

25

#define DETECTED_SNK_TYPE_MASK GENMASK(6, 0)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

26

#define SNK_DAM_MASK GENMASK(6, 4)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

36

#define DETECTED_SRC_TYPE_MASK GENMASK(4, 0)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

74

#define TYPEC_TRY_MODE_MASK GENMASK(4, 3)

drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c

77

#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)

drivers/usb/typec/tcpm/tcpci_maxim.h

23

#define CCLPMODESEL GENMASK(4, 3)

drivers/usb/typec/tcpm/tcpci_maxim.h

26

#define CCRPCTRL GENMASK(2, 0)

drivers/usb/typec/tcpm/tcpci_maxim.h

31

#define CCWTRDEB GENMASK(7, 6)

drivers/usb/typec/tcpm/tcpci_maxim.h

33

#define CCWTRSEL GENMASK(5, 3)

drivers/usb/typec/tcpm/tcpci_maxim.h

36

#define WTRCYCLE GENMASK(0, 0)

drivers/usb/typec/tcpm/tcpci_maxim.h

41

#define ADCINSEL GENMASK(7, 5)

drivers/usb/typec/tipd/tps6598x.h

150

#define TPS_POWER_STATUS_TYPEC_CURRENT_MASK GENMASK(3, 2)

drivers/usb/typec/tipd/tps6598x.h

152

#define TPS_POWER_STATUS_BC12_STATUS_MASK GENMASK(6, 5)

drivers/usb/typec/tipd/tps6598x.h

165

#define TPS25750_POWER_STATUS_CHARGER_DETECT_STATUS_MASK GENMASK(7, 4)

drivers/usb/typec/tipd/tps6598x.h

168

#define TPS25750_POWER_STATUS_CHARGER_ADVERTISE_STATUS_MASK GENMASK(9, 8)

drivers/usb/typec/tipd/tps6598x.h

205

#define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK GENMASK(11, 10)

drivers/usb/typec/tipd/tps6598x.h

208

#define TPS_DATA_STATUS_TBT_CABLE_SPEED_MASK GENMASK(27, 25)

drivers/usb/typec/tipd/tps6598x.h

211

#define TPS_DATA_STATUS_TBT_CABLE_GEN_MASK GENMASK(29, 28)

drivers/usb/typec/tipd/tps6598x.h

231

#define TPS_REG_PD_STATUS_PORT_TYPE_MASK GENMASK(5, 4)

drivers/usb/typec/tipd/tps6598x.h

262

#define TPS_VERSION_HW_VERSION_MASK GENMASK(31, 24)

drivers/usb/typec/tipd/tps6598x.h

33

#define TPS_STATUS_CONN_STATE_MASK GENMASK(3, 1)

drivers/usb/typec/tipd/tps6598x.h

35

#define TPS_STATUS_PP_5V0_SWITCH_MASK GENMASK(9, 8)

drivers/usb/typec/tipd/tps6598x.h

37

#define TPS_STATUS_PP_HV_SWITCH_MASK GENMASK(11, 10)

drivers/usb/typec/tipd/tps6598x.h

39

#define TPS_STATUS_PP_EXT_SWITCH_MASK GENMASK(13, 12)

drivers/usb/typec/tipd/tps6598x.h

41

#define TPS_STATUS_PP_CABLE_SWITCH_MASK GENMASK(15, 14)

drivers/usb/typec/tipd/tps6598x.h

43

#define TPS_STATUS_POWER_SOURCE_MASK GENMASK(19, 18)

drivers/usb/typec/tipd/tps6598x.h

45

#define TPS_STATUS_VBUS_STATUS_MASK GENMASK(21, 20)

drivers/usb/typec/tipd/tps6598x.h

47

#define TPS_STATUS_USB_HOST_PRESENT_MASK GENMASK(23, 22)

drivers/usb/typec/tipd/tps6598x.h

49

#define TPS_STATUS_LEGACY_MASK GENMASK(25, 24)

drivers/usb/typec/tipd/trace.h

100

GENMASK(31, 28)))

drivers/usb/typec/tipd/trace.h

198

#define TPS_DATA_STATUS_FLAGS_MASK (GENMASK(31, 0) ^ (TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK | \

drivers/usb/typec/tipd/trace.h

84

#define TPS6598X_STATUS_FLAGS_MASK (GENMASK(31, 0) ^ (TPS_STATUS_CONN_STATE_MASK | \

drivers/usb/typec/tipd/trace.h

94

#define TPS25750_STATUS_FLAGS_MASK (GENMASK(31, 0) ^ (TPS_STATUS_CONN_STATE_MASK | \

drivers/usb/typec/tipd/trace.h

95

GENMASK(19, 7) | \

drivers/usb/typec/ucsi/trace.c

31

u8 cmd = raw_cmd & GENMASK(7, 0);

drivers/usb/typec/ucsi/ucsi.h

146

#define UCSI_GET_ALTMODE_GET_CONNECTOR_NUMBER(_cmd_) (((_cmd_) >> 24) & GENMASK(6, 0))

drivers/usb/typec/ucsi/ucsi.h

147

#define UCSI_DEFAULT_GET_CONNECTOR_NUMBER(_cmd_) (((_cmd_) >> 16) & GENMASK(6, 0))

drivers/usb/typec/ucsi/ucsi.h

289

#define UCSI_CABLE_PROP_FLAG_PLUG_TYPE(_f_) (((_f_) & GENMASK(4, 3)) >> 3)

drivers/usb/typec/ucsi/ucsi.h

295

#define UCSI_CABLE_PROP_FLAG_PD_MAJOR_REV(_f_) (((_f_) & GENMASK(7, 6)) >> 6)

drivers/usb/typec/ucsi/ucsi.h

51

#define UCSI_CCI_CONNECTOR(_c_) (((_c_) & GENMASK(7, 1)) >> 1)

drivers/usb/typec/ucsi/ucsi.h

52

#define UCSI_CCI_LENGTH(_c_) (((_c_) & GENMASK(15, 8)) >> 8)

drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c

28

#define GAOKUN_CCX_MASK GENMASK(1, 0)

drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c

29

#define GAOKUN_MUX_MASK GENMASK(3, 2)

drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c

31

#define GAOKUN_DPAM_MASK GENMASK(3, 0)

drivers/usb/typec/ucsi/ucsi_yoga_c630.c

27

#define USB_MUX_MUXC GENMASK(1, 0)

drivers/usb/typec/ucsi/ucsi_yoga_c630.c

28

#define USB_MUX_CCST GENMASK(3, 2)

drivers/usb/typec/ucsi/ucsi_yoga_c630.c

29

#define USB_MUX_DPPN GENMASK(7, 4)

drivers/usb/typec/ucsi/ucsi_yoga_c630.c

31

#define USB_MUX_HSFL GENMASK(11, 9)

drivers/usb/typec/wusb3801.c

39

#define WUSB3801_DEVICE_ID_VERSION_ID GENMASK(7, 3)

drivers/usb/typec/wusb3801.c

40

#define WUSB3801_DEVICE_ID_VENDOR_ID GENMASK(2, 0)

drivers/usb/typec/wusb3801.c

43

#define WUSB3801_CTRL0_TRY GENMASK(6, 5)

drivers/usb/typec/wusb3801.c

47

#define WUSB3801_CTRL0_CURRENT GENMASK(4, 3) /* SRC */

drivers/usb/typec/wusb3801.c

51

#define WUSB3801_CTRL0_ROLE GENMASK(2, 1)

drivers/usb/typec/wusb3801.c

61

#define WUSB3801_STAT_CURRENT GENMASK(6, 5) /* SNK */

drivers/usb/typec/wusb3801.c

66

#define WUSB3801_STAT_PARTNER GENMASK(4, 2)

drivers/usb/typec/wusb3801.c

72

#define WUSB3801_STAT_ORIENTATION GENMASK(1, 0)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h

33

#define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h

35

#define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)

drivers/video/backlight/apple_dwi_bl.c

25

#define DWI_BL_CMD_TYPE GENMASK(31, 28)

drivers/video/backlight/apple_dwi_bl.c

27

#define DWI_BL_CMD_DATA GENMASK(10, 0)

drivers/video/backlight/aw99706.c

27

#define AW99706_DIM_MODE_MASK GENMASK(1, 0)

drivers/video/backlight/aw99706.c

30

#define AW99706_SW_FREQ_MASK GENMASK(3, 0)

drivers/video/backlight/aw99706.c

31

#define AW99706_SW_ILMT_MASK GENMASK(5, 4)

drivers/video/backlight/aw99706.c

34

#define AW99706_ILED_MAX_MASK GENMASK(6, 0)

drivers/video/backlight/aw99706.c

39

#define AW99706_BRT_MSB_MASK GENMASK(3, 0)

drivers/video/backlight/aw99706.c

42

#define AW99706_BRT_LSB_MASK GENMASK(7, 0)

drivers/video/backlight/aw99706.c

45

#define AW99706_RAMP_CTL_MASK GENMASK(7, 6)

drivers/video/backlight/cgbc_bl.c

22

#define BLT_PWM_DUTY_MASK GENMASK(6, 0)

drivers/video/backlight/mt6370-backlight.c

26

#define MT6370_VENID_MASK GENMASK(7, 4)

drivers/video/backlight/mt6370-backlight.c

30

#define MT6370_BL_CH_MASK GENMASK(5, 2)

drivers/video/backlight/mt6370-backlight.c

32

#define MT6370_BL_DIM2_COMMON_MASK GENMASK(2, 0)

drivers/video/backlight/mt6370-backlight.c

34

#define MT6370_BL_DIM2_6372_MASK GENMASK(5, 0)

drivers/video/backlight/mt6370-backlight.c

38

#define MT6370_BL_PWM_HYS_SEL_MASK GENMASK(1, 0)

drivers/video/backlight/mt6370-backlight.c

40

#define MT6370_BL_OVP_SEL_MASK GENMASK(6, 5)

drivers/video/backlight/mt6370-backlight.c

43

#define MT6370_BL_OC_SEL_MASK GENMASK(2, 1)

drivers/video/backlight/qcom-wled.c

112

#define WLED5_CTRL_REG_OVP_INT_TIMER_MASK GENMASK(2, 0)

drivers/video/backlight/qcom-wled.c

123

#define WLED5_SINK_REG_MOD_SRC_SEL_MASK GENMASK(1, 0)

drivers/video/backlight/qcom-wled.c

138

#define WLED5_SINK_REG_SYNC_MASK GENMASK(1, 0)

drivers/video/backlight/qcom-wled.c

146

#define WLED5_SINK_REG_SRC_SEL_MASK GENMASK(1, 0)

drivers/video/backlight/qcom-wled.c

335

unsigned int mask = GENMASK(wled->max_string_count - 1, 0);

drivers/video/backlight/qcom-wled.c

44

#define WLED3_CTRL_REG_FREQ_MASK GENMASK(3, 0)

drivers/video/backlight/qcom-wled.c

47

#define WLED3_CTRL_REG_OVP_MASK GENMASK(1, 0)

drivers/video/backlight/qcom-wled.c

48

#define WLED5_CTRL_REG_OVP_MASK GENMASK(3, 0)

drivers/video/backlight/qcom-wled.c

51

#define WLED3_CTRL_REG_ILIMIT_MASK GENMASK(2, 0)

drivers/video/backlight/qcom-wled.c

58

#define WLED3_SINK_REG_CURR_SINK_MASK GENMASK(7, 5)

drivers/video/backlight/qcom-wled.c

68

#define WLED3_SINK_REG_STR_FULL_SCALE_CURR_MASK GENMASK(4, 0)

drivers/video/backlight/qcom-wled.c

90

#define WLED4_SINK_REG_CURR_SINK_MASK GENMASK(7, 4)

drivers/video/backlight/qcom-wled.c

98

#define WLED4_SINK_REG_STR_FULL_SCALE_CURR_MASK GENMASK(3, 0)

drivers/video/backlight/rt4831-backlight.c

20

#define RT4831_BLOVP_MASK GENMASK(7, 5)

drivers/video/backlight/rt4831-backlight.c

24

#define RT4831_BLCH_MASK GENMASK(3, 0)

drivers/video/backlight/rt4831-backlight.c

25

#define RT4831_BLDIML_MASK GENMASK(2, 0)

drivers/video/backlight/rt4831-backlight.c

26

#define RT4831_BLDIMH_MASK GENMASK(10, 3)

drivers/video/backlight/rt4831-backlight.c

28

#define RT4831_BLOCP_MASK GENMASK(1, 0)

drivers/video/fbdev/imxfb.c

102

#define POS_POS_MASK GENMASK(4, 0)

drivers/video/fbdev/imxfb.c

59

#define SIZE_XMAX_MASK GENMASK(25, 20)

drivers/video/fbdev/imxfb.c

61

#define YMAX_MASK_IMX1 GENMASK(8, 0)

drivers/video/fbdev/imxfb.c

62

#define YMAX_MASK_IMX21 GENMASK(9, 0)

drivers/video/fbdev/imxfb.c

65

#define VPW_VPW_MASK GENMASK(9, 0)

drivers/video/fbdev/imxfb.c

71

#define CPOS_CXP_MASK GENMASK(25, 16)

drivers/video/fbdev/imxfb.c

75

#define LCWHB_CW_MASK GENMASK(28, 24)

drivers/video/fbdev/imxfb.c

76

#define LCWHB_CH_MASK GENMASK(20, 16)

drivers/video/fbdev/imxfb.c

77

#define LCWHB_BD_MASK GENMASK(7, 0)

drivers/video/fbdev/imxfb.c

84

#define PCR_BPIX_MASK GENMASK(27, 25)

drivers/video/fbdev/imxfb.c

89

#define PCR_PCD_MASK GENMASK(5, 0)

drivers/video/fbdev/imxfb.c

92

#define HCR_H_WIDTH_MASK GENMASK(31, 26)

drivers/video/fbdev/imxfb.c

93

#define HCR_H_WAIT_1_MASK GENMASK(15, 8)

drivers/video/fbdev/imxfb.c

94

#define HCR_H_WAIT_2_MASK GENMASK(7, 0)

drivers/video/fbdev/imxfb.c

97

#define VCR_V_WIDTH_MASK GENMASK(31, 26)

drivers/video/fbdev/imxfb.c

98

#define VCR_V_WAIT_1_MASK GENMASK(15, 8)

drivers/video/fbdev/imxfb.c

99

#define VCR_V_WAIT_2_MASK GENMASK(7, 0)

drivers/video/fbdev/sis/init.c

3322

#define GENBITSMASK(mask) GENMASK(1?mask,0?mask)

drivers/w1/masters/amd_axi_w1.c

43

#define AXIW1_MAJORVER_MASK GENMASK(23, 8)

drivers/w1/masters/amd_axi_w1.c

44

#define AXIW1_MINORVER_MASK GENMASK(7, 0)

drivers/watchdog/airoha_wdt.c

32

#define WDT_TIMER_VAL GENMASK(31, 0)

drivers/watchdog/aspeed_wdt.c

63

.irq_mask = GENMASK(31, 12),

drivers/watchdog/aspeed_wdt.c

76

.irq_mask = GENMASK(31, 10),

drivers/watchdog/aspeed_wdt.c

89

.irq_mask = GENMASK(31, 10),

drivers/watchdog/intel_oc_wdt.c

19

#define INTEL_OC_WDT_TOV GENMASK(9, 0)

drivers/watchdog/lantiq_wdt.c

48

#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */

drivers/watchdog/lantiq_wdt.c

52

#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */

drivers/watchdog/realtek_otto_wdt.c

42

#define OTTO_WDT_CTRL_PRESCALE GENMASK(30, 29)

drivers/watchdog/realtek_otto_wdt.c

43

#define OTTO_WDT_CTRL_PHASE1 GENMASK(26, 22)

drivers/watchdog/realtek_otto_wdt.c

44

#define OTTO_WDT_CTRL_PHASE2 GENMASK(19, 15)

drivers/watchdog/realtek_otto_wdt.c

45

#define OTTO_WDT_CTRL_RST_MODE GENMASK(1, 0)

drivers/watchdog/renesas_wwdt.c

28

#define WDTA0OVF(x) FIELD_GET(GENMASK(6, 4), x)

drivers/watchdog/renesas_wwdt.c

31

#define WDTA0WS(x) FIELD_GET(GENMASK(1, 0), x)

drivers/watchdog/sbsa_gwdt.c

75

#define SBSA_GWDT_VERSION_MASK GENMASK(3, 0)

drivers/watchdog/sbsa_gwdt.c

78

#define SBSA_GWDT_IMPL_MASK GENMASK(11, 0)

drivers/watchdog/sp5100_tco.h

46

#define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1)

drivers/watchdog/sp5100_tco.h

58

#define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0)

drivers/watchdog/sp5100_tco.h

61

#define SB800_ACPI_MMIO_MASK GENMASK(1, 0)

drivers/watchdog/sp5100_tco.h

75

#define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)

drivers/watchdog/sp5100_tco.h

76

#define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))

drivers/watchdog/sprd_wdt.c

56

#define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0)

drivers/watchdog/stm32_iwdg.c

46

#define RLR_MAX GENMASK(11, 0) /* max value of reload register */

drivers/watchdog/stm32_iwdg.c

52

#define EWCR_EWIT GENMASK(11, 0) /* Watchdog counter window value */

drivers/watchdog/xilinx_wwdt.c

40

#define XWWDT_MAX_COUNT_WINDOW GENMASK(31, 0)

fs/erofs/internal.h

255

return ((nid << 1) & GENMASK_ULL(63, 32)) | (nid & GENMASK(30, 0)) |

fs/f2fs/data.c

457

unsigned int temp_mask = GENMASK(NR_TEMP_TYPE - 1, 0);

fs/f2fs/inode.c

533

GENMASK(COMPRESS_LEVEL_OFFSET - 1, 0);

fs/f2fs/segment.c

5444

wp_sector_off = zone.wp & GENMASK(log_sectors_per_block - 1, 0);

fs/f2fs/super.c

4593

if (sbi->stop_reason[reason] < GENMASK(BITS_PER_BYTE - 1, 0))

fs/resctrl/pseudo_lock.c

33

static unsigned long pseudo_lock_minor_avail = GENMASK(MINORBITS, 0);

include/asm-generic/fprobe.h

20

GENMASK(FPROBE_HEADER_MSB_SIZE_SHIFT - 1, 0)

include/asm-generic/fprobe.h

28

GENMASK(BITS_PER_LONG - 1, FPROBE_HEADER_MSB_SIZE_SHIFT)

include/drm/display/drm_dp.h

1207

# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)

include/drm/display/drm_dp.h

1208

# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0)

include/dt-bindings/pinctrl/k210-fpioa.h

13

#define K210_PCF_MASK GENMASK(7, 0)

include/hyperv/hvgdk_mini.h

1350

#define HV_VTL_MASK GENMASK(3, 0)

include/hyperv/hvgdk_mini.h

385

#define HV_ISOLATION_TYPE GENMASK(3, 0)

include/hyperv/hvgdk_mini.h

387

#define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6)

include/linux/amba/pl080.h

116

#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)

include/linux/amba/pl080.h

118

#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)

include/linux/amba/pl080.h

120

#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)

include/linux/amba/pl080.h

135

#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)

include/linux/amba/pl080.h

137

#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)

include/linux/amba/pl080.h

141

#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)

include/linux/amba/pl080.h

144

#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)

include/linux/amba/pl080.h

146

#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)

include/linux/amba/pl080.h

150

#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)

include/linux/amba/pl080.h

152

#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)

include/linux/amba/pl080.h

171

#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)

include/linux/amba/pl080.h

180

#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)

include/linux/amba/pl080.h

182

#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)

include/linux/amba/pl080.h

184

#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)

include/linux/amba/pl080.h

186

#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)

include/linux/amba/pl080.h

190

#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)

include/linux/amba/pl080.h

193

#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)

include/linux/amba/pl080.h

70

#define PL080_LLI_ADDR_MASK GENMASK(31, 2)

include/linux/amba/pl080.h

75

#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)

include/linux/amba/pl080.h

84

#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)

include/linux/amba/pl080.h

86

#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)

include/linux/amba/pl080.h

88

#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)

include/linux/amba/pl080.h

90

#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)

include/linux/amba/pl080.h

92

#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)

include/linux/amba/pl080.h

93

#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)

include/linux/amba/serial.h

137

#define ST_UART011_DMAWM_RX GENMASK(5, 3)

include/linux/amba/serial.h

145

#define ST_UART011_DMAWM_TX GENMASK(2, 0)

include/linux/amba/serial.h

159

#define UART011_IFLS_RXIFLSEL GENMASK(5, 3)

include/linux/amba/serial.h

165

#define UART011_IFLS_TXIFLSEL GENMASK(2, 0)

include/linux/arm_ffa.h

106

#define FFA_MAJOR_VERSION_MASK GENMASK(30, 16)

include/linux/arm_ffa.h

107

#define FFA_MINOR_VERSION_MASK GENMASK(15, 0)

include/linux/arm_ffa.h

131

#define FFA_FEAT_RXTX_MIN_SZ_MASK GENMASK(1, 0)

include/linux/bitmap.h

488

*map |= GENMASK(start + nbits - 1, start);

include/linux/bitmap.h

504

*map &= ~GENMASK(start + nbits - 1, start);

include/linux/bpf_verifier.h

944

#define BPF_BASE_TYPE_MASK GENMASK(BPF_BASE_TYPE_BITS - 1, 0)

include/linux/brcmphy.h

167

#define BCM_LED_SRC_MASK GENMASK(3, 0)

include/linux/brcmphy.h

237

#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */

include/linux/brcmphy.h

509

#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)

include/linux/brcmphy.h

510

#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)

include/linux/brcmphy.h

511

#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)

include/linux/brcmphy.h

512

#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)

include/linux/cdx/bitfield.h

40

(FIELD_GET(GENMASK(CDX_HIGH_BIT(field), CDX_LOW_BIT(field)), \

include/linux/cdx/bitfield.h

48

(FIELD_PREP(GENMASK(CDX_HIGH_BIT(field), \

include/linux/clk/at91_pmc.h

247

#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20)

include/linux/context_tracking_state.h

68

#define CT_STATE_MASK GENMASK(CT_STATE_END, CT_STATE_START)

include/linux/context_tracking_state.h

69

#define CT_RCU_WATCHING_MASK GENMASK(CT_RCU_WATCHING_END, CT_RCU_WATCHING_START)

include/linux/cper.h

300

#define CPER_ARM_ERR_TYPE_MASK GENMASK(4,1)

include/linux/cper.h

320

#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)

include/linux/cper.h

322

#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)

include/linux/cper.h

324

#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)

include/linux/cper.h

326

#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)

include/linux/cper.h

328

#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)

include/linux/cper.h

330

#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)

include/linux/cper.h

332

#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)

include/linux/cper.h

334

#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)

include/linux/cper.h

336

#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)

include/linux/cper.h

338

#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)

include/linux/cper.h

340

#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)

include/linux/cper.h

342

#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)

include/linux/dma/ti-cppi5.h

102

#define CPPI5_INFO2_DESC_RETP_MASK GENMASK(18, 16)

include/linux/dma/ti-cppi5.h

105

#define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)

include/linux/dma/ti-cppi5.h

108

#define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)

include/linux/dma/ti-cppi5.h

110

#define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)

include/linux/dma/ti-cppi5.h

113

#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)

include/linux/dma/ti-cppi5.h

116

#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)

include/linux/dma/ti-cppi5.h

146

#define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK GENMASK(26, 18)

include/linux/dma/ti-cppi5.h

155

#define CPPI5_INFO0_TRDESC_RLDCNT_MASK GENMASK(28, 20)

include/linux/dma/ti-cppi5.h

159

#define CPPI5_INFO0_TRDESC_RLDIDX_MASK GENMASK(19, 14)

include/linux/dma/ti-cppi5.h

162

#define CPPI5_INFO0_TRDESC_LASTIDX_MASK GENMASK(13, 0)

include/linux/dma/ti-cppi5.h

165

#define CPPI5_INFO1_TRDESC_RECSIZE_MASK GENMASK(26, 24)

include/linux/dma/ti-cppi5.h

59

#define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)

include/linux/dma/ti-cppi5.h

597

#define CPPI5_TR_TYPE_MASK GENMASK(3, 0)

include/linux/dma/ti-cppi5.h

601

#define CPPI5_TR_EVENT_SIZE_MASK GENMASK(7, 6)

include/linux/dma/ti-cppi5.h

603

#define CPPI5_TR_TRIGGER0_MASK GENMASK(9, 8)

include/linux/dma/ti-cppi5.h

605

#define CPPI5_TR_TRIGGER0_TYPE_MASK GENMASK(11, 10)

include/linux/dma/ti-cppi5.h

607

#define CPPI5_TR_TRIGGER1_MASK GENMASK(13, 12)

include/linux/dma/ti-cppi5.h

609

#define CPPI5_TR_TRIGGER1_TYPE_MASK GENMASK(15, 14)

include/linux/dma/ti-cppi5.h

611

#define CPPI5_TR_CMD_ID_MASK GENMASK(23, 16)

include/linux/dma/ti-cppi5.h

613

#define CPPI5_TR_CSF_FLAGS_MASK GENMASK(31, 24)

include/linux/dma/ti-cppi5.h

618

#define CPPI5_TR_CSF_EOL_ADV_MASK GENMASK(6, 4)

include/linux/dma/ti-cppi5.h

71

#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)

include/linux/dma/ti-cppi5.h

73

#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)

include/linux/dma/ti-cppi5.h

76

#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)

include/linux/dma/ti-cppi5.h

78

#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)

include/linux/dma/ti-cppi5.h

80

#define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)

include/linux/dma/ti-cppi5.h

82

#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)

include/linux/dma/ti-cppi5.h

857

#define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK GENMASK(3, 0)

include/linux/dma/ti-cppi5.h

859

#define CPPI5_TR_RESPONSE_STATUS_INFO_MASK GENMASK(7, 4)

include/linux/dma/ti-cppi5.h

86

#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)

include/linux/dma/ti-cppi5.h

861

#define CPPI5_TR_RESPONSE_CMDID_MASK GENMASK(23, 16)

include/linux/dma/ti-cppi5.h

863

#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24)

include/linux/dsa/ksz_common.h

15

#define KSZ_TSTAMP_SEC_MASK GENMASK(31, 30)

include/linux/dsa/ksz_common.h

16

#define KSZ_TSTAMP_NSEC_MASK GENMASK(29, 0)

include/linux/dsa/tag_qca.h

14

#define QCA_HDR_RECV_VERSION GENMASK(15, 14)

include/linux/dsa/tag_qca.h

15

#define QCA_HDR_RECV_PRIORITY GENMASK(13, 11)

include/linux/dsa/tag_qca.h

16

#define QCA_HDR_RECV_TYPE GENMASK(10, 6)

include/linux/dsa/tag_qca.h

18

#define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0)

include/linux/dsa/tag_qca.h

25

#define QCA_HDR_XMIT_VERSION GENMASK(15, 14)

include/linux/dsa/tag_qca.h

26

#define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11)

include/linux/dsa/tag_qca.h

27

#define QCA_HDR_XMIT_CONTROL GENMASK(10, 8)

include/linux/dsa/tag_qca.h

29

#define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0)

include/linux/dsa/tag_qca.h

56

#define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */

include/linux/dsa/tag_qca.h

57

#define QCA_HDR_MGMT_CHECK_CODE GENMASK(31, 29) /* 31, 29 */

include/linux/dsa/tag_qca.h

59

#define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */

include/linux/dsa/tag_qca.h

60

#define QCA_HDR_MGMT_ADDR GENMASK(18, 0) /* 18, 0 */

include/linux/ethtool.h

383

#define ETHTOOL_COALESCE_ALL_PARAMS GENMASK(28, 0)

include/linux/f2fs_fs.h

359

#define OFFSET_BIT_MASK GENMASK(OFFSET_BIT_SHIFT - 1, 0)

include/linux/find.h

130

val = *addr1 & ~*addr2 & GENMASK(size - 1, offset);

include/linux/find.h

160

val = (*addr1 | *addr2) & GENMASK(size - 1, offset);

include/linux/find.h

188

val = *addr | ~GENMASK(size - 1, offset);

include/linux/find.h

209

unsigned long val = *addr & GENMASK(size - 1, 0);

include/linux/find.h

238

unsigned long val = *addr & GENMASK(size - 1, 0);

include/linux/find.h

264

unsigned long val = *addr1 & *addr2 & GENMASK(size - 1, 0);

include/linux/find.h

294

unsigned long val = *addr1 & *addr2 & (~*addr3) & GENMASK(size - 1, 0);

include/linux/find.h

318

unsigned long val = *addr1 & *addr2 & GENMASK(size - 1, 0);

include/linux/find.h

342

unsigned long val = *addr1 & (~*addr2) & GENMASK(size - 1, 0);

include/linux/find.h

367

unsigned long val = *addr1 & *addr2 & *addr3 & GENMASK(size - 1, 0);

include/linux/find.h

388

unsigned long val = *addr | ~GENMASK(size - 1, 0);

include/linux/find.h

409

unsigned long val = *addr & GENMASK(size - 1, 0);

include/linux/find.h

540

val = swab(val) | ~GENMASK(size - 1, offset);

include/linux/find.h

553

unsigned long val = swab(*(const unsigned long *)addr) | ~GENMASK(size - 1, 0);

include/linux/find.h

573

val = swab(val) & GENMASK(size - 1, offset);

include/linux/find.h

69

val = *addr & GENMASK(size - 1, offset);

include/linux/find.h

99

val = *addr1 & *addr2 & GENMASK(size - 1, offset);

include/linux/firmware/xlnx-zynqmp.h

48

#define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0)

include/linux/firmware/xlnx-zynqmp.h

61

#define API_ID_MASK GENMASK(7, 0)

include/linux/firmware/xlnx-zynqmp.h

62

#define MODULE_ID_MASK GENMASK(11, 8)

include/linux/firmware/xlnx-zynqmp.h

63

#define PLM_MODULE_ID_MASK GENMASK(15, 8)

include/linux/fsl/enetc_mdio.h

17

#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))

include/linux/generic_pt/common.h

80

PT_TOP_LEVEL_MASK = GENMASK(PT_TOP_LEVEL_BITS - 1, 0),

include/linux/hid-over-i2c.h

70

#define HIDI2C_CMD_REPORT_ID GENMASK(3, 0)

include/linux/hid-over-i2c.h

71

#define HIDI2C_CMD_REPORT_TYPE GENMASK(5, 4)

include/linux/hid-over-i2c.h

72

#define HIDI2C_CMD_OPCODE GENMASK(11, 8)

include/linux/hid-over-i2c.h

73

#define HIDI2C_CMD_OPCODE GENMASK(11, 8)

include/linux/hid-over-i2c.h

74

#define HIDI2C_CMD_3RD_BYTE GENMASK(23, 16)

include/linux/hid-over-spi.h

62

#define HIDSPI_INPUT_HEADER_VER GENMASK(3, 0)

include/linux/hid-over-spi.h

63

#define HIDSPI_INPUT_HEADER_REPORT_LEN GENMASK(21, 8)

include/linux/hid-over-spi.h

65

#define HIDSPI_INPUT_HEADER_SYNC GENMASK(31, 24)

include/linux/hisi_acc_qm.h

19

#define AXUSER_CMD_TYPE GENMASK(14, 12)

include/linux/hisi_acc_qm.h

78

#define SQC_CACHE_WB_THRD GENMASK(10, 5)

include/linux/hisi_acc_qm.h

80

#define CQC_CACHE_WB_THRD GENMASK(17, 12)

include/linux/i2c.h

960

return 0xf0 | ((msg->addr & GENMASK(9, 8)) >> 7) | (msg->flags & I2C_M_RD);

include/linux/i2c.h

965

return msg->addr & GENMASK(7, 0);

include/linux/i3c/ccc.h

200

#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))

include/linux/i3c/ccc.h

203

(((status) & GENMASK(7, 6)) >> 6)

include/linux/i3c/ccc.h

268

#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)

include/linux/i3c/device.h

97

#define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6))

include/linux/i3c/master.h

23

#define I3C_MAX_ADDR GENMASK(6, 0)

include/linux/i3c/master.h

55

#define I3C_LVR_I2C_INDEX_MASK GENMASK(7, 5)

include/linux/i3c/master.h

59

#define I2C_MAX_ADDR GENMASK(6, 0)

include/linux/ieee80211-he.h

28

#define IEEE80211_TWT_REQTYPE_SETUP_CMD GENMASK(3, 1)

include/linux/ieee80211-he.h

32

#define IEEE80211_TWT_REQTYPE_FLOWID GENMASK(9, 7)

include/linux/ieee80211-he.h

33

#define IEEE80211_TWT_REQTYPE_WAKE_INT_EXP GENMASK(14, 10)

include/linux/ieee80211-s1g.h

207

#define S1G_CAP0_SUPP_CH_WIDTH GENMASK(7, 6)

include/linux/ieee80211-s1g.h

221

#define S1G_CAP1_BFEE_STS GENMASK(7, 5)

include/linux/ieee80211-s1g.h

223

#define S1G_CAP2_SOUNDING_DIMENSIONS GENMASK(2, 0)

include/linux/ieee80211-s1g.h

227

#define S1G_CAP2_TRAVELING_PILOT GENMASK(7, 6)

include/linux/ieee80211-s1g.h

232

#define S1G_CAP3_MAX_AMPDU_LEN_EXP GENMASK(4, 3)

include/linux/ieee80211-s1g.h

233

#define S1G_CAP3_MIN_MPDU_START GENMASK(7, 5)

include/linux/ieee80211-s1g.h

241

#define S1G_CAP4_STA_TYPE GENMASK(7, 6)

include/linux/ieee80211-s1g.h

249

#define S1G_CAP5_SECTORIZED_BEAM GENMASK(7, 6)

include/linux/ieee80211-s1g.h

257

#define S1G_CAP6_VHT_LINK_ADAPT GENMASK(7, 6)

include/linux/ieee80211-s1g.h

270

#define S1G_CAP8_COLOR GENMASK(4, 2)

include/linux/ieee80211-s1g.h

278

#define S1G_OPER_CH_WIDTH_OPER GENMASK(4, 1)

include/linux/ieee80211-s1g.h

284

#define LISTEN_INT_USF GENMASK(15, 14)

include/linux/ieee80211-s1g.h

285

#define LISTEN_INT_UI GENMASK(13, 0)

include/linux/ieee80211-s1g.h

488

ptr += hweight8(blkmap & GENMASK(aid->target_subblk - 1, 0));

include/linux/ieee80211.h

940

#define IEEE80211_ADDBA_EXT_FRAG_LEVEL_MASK GENMASK(2, 1)

include/linux/ieee80211.h

943

#define IEEE80211_ADDBA_EXT_BUF_SIZE_MASK GENMASK(7, 5)

include/linux/if_rmnet.h

21

#define MAP_PAD_LEN_MASK GENMASK(5, 0)

include/linux/if_rmnet.h

48

#define MAP_CSUM_UL_OFFSET_MASK GENMASK(13, 0)

include/linux/if_rmnet.h

70

#define MAPV5_HDRINFO_HDR_TYPE_FMASK GENMASK(7, 1)

include/linux/intel_pmt_features.h

22

#define PMT_CAP_PMT_SP_POLICY GENMASK(17, 12)

include/linux/intel_tpmi.h

14

#define TPMI_MINOR_VERSION(val) FIELD_GET(GENMASK(4, 0), val)

include/linux/intel_tpmi.h

15

#define TPMI_MAJOR_VERSION(val) FIELD_GET(GENMASK(7, 5), val)

include/linux/intel_vsec.h

28

#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0))

include/linux/intel_vsec.h

29

#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3))

include/linux/irqchip/arm-gic-v3.h

352

#define GICR_VSGIR_VPEID GENMASK(15, 0)

include/linux/irqchip/arm-gic-v3.h

357

#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)

include/linux/irqchip/arm-gic-v3.h

95

#define GICD_TYPER2_VID GENMASK(4, 0)

include/linux/irqchip/arm-gic-v5.h

107

#define GICV5_IRS_CR1_IC GENMASK(5, 4)

include/linux/irqchip/arm-gic-v5.h

108

#define GICV5_IRS_CR1_OC GENMASK(3, 2)

include/linux/irqchip/arm-gic-v5.h

109

#define GICV5_IRS_CR1_SH GENMASK(1, 0)

include/linux/irqchip/arm-gic-v5.h

118

#define GICV5_IRS_SPI_SELR_ID GENMASK(23, 0)

include/linux/irqchip/arm-gic-v5.h

122

#define GICV5_IRS_PE_SELR_IAFFID GENMASK(15, 0)

include/linux/irqchip/arm-gic-v5.h

132

#define GICV5_IRS_IST_CFGR_ISTSZ GENMASK(8, 7)

include/linux/irqchip/arm-gic-v5.h

133

#define GICV5_IRS_IST_CFGR_L2SZ GENMASK(6, 5)

include/linux/irqchip/arm-gic-v5.h

134

#define GICV5_IRS_IST_CFGR_LPI_ID_BITS GENMASK(4, 0)

include/linux/irqchip/arm-gic-v5.h

150

#define GICV5_IRS_MAP_L2_ISTR_ID GENMASK(23, 0)

include/linux/irqchip/arm-gic-v5.h

173

#define GICV5_ITS_IDR1_L2SZ GENMASK(10, 8)

include/linux/irqchip/arm-gic-v5.h

176

#define GICV5_ITS_IDR1_DEVICEID_BITS GENMASK(5, 0)

include/linux/irqchip/arm-gic-v5.h

182

#define GICV5_ITS_IDR2_XDMN_EVENTs GENMASK(6, 5)

include/linux/irqchip/arm-gic-v5.h

183

#define GICV5_ITS_IDR2_EVENTID_BITS GENMASK(4, 0)

include/linux/irqchip/arm-gic-v5.h

19

#define GICV5_HWIRQ_ID GENMASK(23, 0)

include/linux/irqchip/arm-gic-v5.h

190

#define GICV5_ITS_CR1_IC GENMASK(5, 4)

include/linux/irqchip/arm-gic-v5.h

191

#define GICV5_ITS_CR1_OC GENMASK(3, 2)

include/linux/irqchip/arm-gic-v5.h

192

#define GICV5_ITS_CR1_SH GENMASK(1, 0)

include/linux/irqchip/arm-gic-v5.h

195

#define GICV5_ITS_DT_CFGR_L2SZ GENMASK(7, 6)

include/linux/irqchip/arm-gic-v5.h

196

#define GICV5_ITS_DT_CFGR_DEVICEID_BITS GENMASK(5, 0)

include/linux/irqchip/arm-gic-v5.h

20

#define GICV5_HWIRQ_TYPE GENMASK(31, 29)

include/linux/irqchip/arm-gic-v5.h

201

#define GICV5_ITS_INV_DEVICER_EVENTID_BITS GENMASK(5, 1)

include/linux/irqchip/arm-gic-v5.h

206

#define GICV5_ITS_EIDR_EVENTID GENMASK(15, 0)

include/linux/irqchip/arm-gic-v5.h

209

#define GICV5_ITS_INV_EVENTR_ITT_L2SZ GENMASK(2, 1)

include/linux/irqchip/arm-gic-v5.h

263

#define GICV5_IWB_IDR0_INT_DOMS GENMASK(14, 11)

include/linux/irqchip/arm-gic-v5.h

264

#define GICV5_IWB_IDR0_IW_RANGE GENMASK(10, 0)

include/linux/irqchip/arm-gic-v5.h

271

#define GICV5_GSI_IC_TYPE GENMASK(31, 29)

include/linux/irqchip/arm-gic-v5.h

274

#define GICV5_GSI_IWB_FRAME_ID GENMASK(28, 16)

include/linux/irqchip/arm-gic-v5.h

275

#define GICV5_GSI_IWB_WIRE GENMASK(15, 0)

include/linux/irqchip/arm-gic-v5.h

69

#define GICV5_IRS_IDR1_PRIORITY_BITS GENMASK(22, 20)

include/linux/irqchip/arm-gic-v5.h

70

#define GICV5_IRS_IDR1_IAFFID_BITS GENMASK(19, 16)

include/linux/irqchip/arm-gic-v5.h

78

#define GICV5_IRS_IDR2_ISTMD_SZ GENMASK(19, 15)

include/linux/irqchip/arm-gic-v5.h

80

#define GICV5_IRS_IDR2_IST_L2SZ GENMASK(13, 11)

include/linux/irqchip/arm-gic-v5.h

82

#define GICV5_IRS_IDR2_MIN_LPI_ID_BITS GENMASK(9, 6)

include/linux/irqchip/arm-gic-v5.h

84

#define GICV5_IRS_IDR2_ID_BITS GENMASK(4, 0)

include/linux/irqchip/arm-gic-v5.h

86

#define GICV5_IRS_IDR5_SPI_RANGE GENMASK(24, 0)

include/linux/irqchip/arm-gic-v5.h

87

#define GICV5_IRS_IDR6_SPI_IRS_RANGE GENMASK(24, 0)

include/linux/irqchip/arm-gic-v5.h

88

#define GICV5_IRS_IDR7_SPI_BASE GENMASK(23, 0)

include/linux/irqchip/arm-gic.h

95

#define GICH_HCR_EOICOUNT GENMASK(31, 27)

include/linux/kvm_host.h

158

#define KVM_REQUEST_MASK GENMASK(7,0)

include/linux/mfd/adp5585.h

102

#define ADP5585_R3_EXTEND_CFG_MASK GENMASK(3, 2)

include/linux/mfd/adp5585.h

105

#define ADP5585_R0_EXTEND_CFG_MASK GENMASK(0, 0)

include/linux/mfd/adp5585.h

112

#define ADP5585_OSC_FREQ_MASK GENMASK(6, 5)

include/linux/mfd/adp5585.h

148

#define ADP5589_UNLOCK_TIMER GENMASK(2, 0)

include/linux/mfd/adp5585.h

157

#define ADP5585_RESET_TRIG_TIME GENMASK(4, 2)

include/linux/mfd/adp5585.h

158

#define ADP5585_PULSE_WIDTH GENMASK(1, 0)

include/linux/mfd/adp5585.h

17

#define ADP5585_MAN_ID_MASK GENMASK(7, 4)

include/linux/mfd/adp5585.h

18

#define ADP5585_REV_ID_MASK GENMASK(3, 0)

include/linux/mfd/adp5585.h

23

#define ADP5585_EC_MASK GENMASK(4, 0)

include/linux/mfd/adp5585.h

26

#define ADP5585_KEY_EVENT_MASK GENMASK(6, 0)

include/linux/mfd/adp5585.h

95

#define ADP5585_C4_EXTEND_CFG_MASK GENMASK(6, 6)

include/linux/mfd/adp5585.h

98

#define ADP5585_R4_EXTEND_CFG_MASK GENMASK(5, 5)

include/linux/mfd/atc260x/atc2603c.h

213

#define ATC2603C_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))

include/linux/mfd/atc260x/atc2603c.h

218

#define ATC2603C_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3)

include/linux/mfd/atc260x/atc2603c.h

236

#define ATC2603C_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3)

include/linux/mfd/atc260x/atc2603c.h

238

#define ATC2603C_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7)

include/linux/mfd/atc260x/atc2603c.h

240

#define ATC2603C_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)

include/linux/mfd/atc260x/atc2603c.h

247

#define ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7)

include/linux/mfd/atc260x/atc2603c.h

249

#define ATC2603C_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)

include/linux/mfd/atc260x/atc2609a.h

240

#define ATC2609A_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10)))

include/linux/mfd/atc260x/atc2609a.h

245

#define ATC2609A_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3)

include/linux/mfd/atc260x/atc2609a.h

263

#define ATC2609A_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3)

include/linux/mfd/atc260x/atc2609a.h

265

#define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7)

include/linux/mfd/atc260x/atc2609a.h

267

#define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10)

include/linux/mfd/atc260x/atc2609a.h

274

#define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7)

include/linux/mfd/atc260x/atc2609a.h

276

#define ATC2609A_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10)

include/linux/mfd/atmel-hlcdc.h

24

#define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8)

include/linux/mfd/atmel-hlcdc.h

25

#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8)

include/linux/mfd/atmel-hlcdc.h

30

#define ATMEL_HLCDC_GUARDTIME_MASK GENMASK(20, 16)

include/linux/mfd/atmel-hlcdc.h

51

#define ATMEL_HLCDC_CLKDIV_MASK GENMASK(23, 16)

include/linux/mfd/bd9571mwv.h

30

#define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK GENMASK(3, 0)

include/linux/mfd/bq257xx.h

28

#define BQ25703_WDTMR_ADJ_MASK GENMASK(14, 13)

include/linux/mfd/bq257xx.h

34

#define BQ25703_ICHG_MASK GENMASK(12, 6)

include/linux/mfd/bq257xx.h

39

#define BQ25703_MAX_CHARGE_VOLT_MASK GENMASK(15, 4)

include/linux/mfd/bq257xx.h

44

#define BQ25703_OTG_VOLT_MASK GENMASK(13, 6)

include/linux/mfd/bq257xx.h

50

#define BQ25703_OTG_CUR_MASK GENMASK(14, 8)

include/linux/mfd/bq257xx.h

54

#define BQ25703_MINVSYS_MASK GENMASK(13, 8)

include/linux/mfd/bq257xx.h

66

#define BQ25703_IINDPM_MASK GENMASK(14, 8)

include/linux/mfd/bq257xx.h

73

#define BQ25703_ADCIBAT_DISCHG_MASK GENMASK(6, 0)

include/linux/mfd/bq257xx.h

74

#define BQ25703_ADCIBAT_CHG_MASK GENMASK(14, 8)

include/linux/mfd/bq257xx.h

78

#define BQ25703_ADCIIN GENMASK(15, 8)

include/linux/mfd/bq257xx.h

81

#define BQ25703_ADCVSYS_MASK GENMASK(15, 8)

include/linux/mfd/bq257xx.h

82

#define BQ25703_ADCVBAT_MASK GENMASK(7, 0)

include/linux/mfd/bq257xx.h

86

#define BQ25703_ADC_CH_MASK GENMASK(7, 0)

include/linux/mfd/idtRC38xxx_reg.h

113

#define TIME_REF_DIV_MASK GENMASK(29, 24)

include/linux/mfd/idtRC38xxx_reg.h

122

#define FINE_MEAS_MASK GENMASK(12, 0)

include/linux/mfd/idtRC38xxx_reg.h

38

#define TDC_FB_DIV_INT_MASK GENMASK(7, 0)

include/linux/mfd/idtRC38xxx_reg.h

41

#define TDC_REF_DIV_CONFIG_MASK GENMASK(2, 0)

include/linux/mfd/idtRC38xxx_reg.h

46

#define TIME_CLOCK_COUNT_MASK GENMASK(5, 0)

include/linux/mfd/idtRC38xxx_reg.h

55

#define SUB_SYNC_COUNTER_MASK GENMASK(30, 0)

include/linux/mfd/idtRC38xxx_reg.h

76

#define LPF_BW_SHIFT GENMASK(7, 3)

include/linux/mfd/idtRC38xxx_reg.h

77

#define LPF_BW_MULT GENMASK(2, 0)

include/linux/mfd/idtRC38xxx_reg.h

89

#define SIG1_MUX_SEL_MASK GENMASK(7, 4)

include/linux/mfd/idtRC38xxx_reg.h

90

#define SIG2_MUX_SEL_MASK GENMASK(11, 8)

include/linux/mfd/imx25-tsadc.h

106

#define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)

include/linux/mfd/imx25-tsadc.h

123

#define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)

include/linux/mfd/imx25-tsadc.h

138

#define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)

include/linux/mfd/imx25-tsadc.h

31

#define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)

include/linux/mfd/imx25-tsadc.h

37

#define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)

include/linux/mfd/imx25-tsadc.h

65

#define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)

include/linux/mfd/imx25-tsadc.h

67

#define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)

include/linux/mfd/imx25-tsadc.h

73

#define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)

include/linux/mfd/intel-m10-bmc.h

136

#define AUTH_RESULT_RSU_STATUS GENMASK(23, 16)

include/linux/mfd/intel-m10-bmc.h

159

#define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0)

include/linux/mfd/intel-m10-bmc.h

173

#define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4)

include/linux/mfd/intel-m10-bmc.h

174

#define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16)

include/linux/mfd/intel-m10-bmc.h

29

#define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)

include/linux/mfd/intel-m10-bmc.h

30

#define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)

include/linux/mfd/intel-m10-bmc.h

31

#define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)

include/linux/mfd/intel-m10-bmc.h

32

#define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)

include/linux/mfd/intel-m10-bmc.h

34

#define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)

include/linux/mfd/intel-m10-bmc.h

35

#define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)

include/linux/mfd/intel-m10-bmc.h

36

#define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)

include/linux/mfd/intel-m10-bmc.h

39

#define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)

include/linux/mfd/intel-m10-bmc.h

40

#define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)

include/linux/mfd/intel-m10-bmc.h

56

#define DRBL_RSU_PROGRESS GENMASK(7, 4)

include/linux/mfd/intel-m10-bmc.h

57

#define DRBL_HOST_STATUS GENMASK(11, 8)

include/linux/mfd/intel-m10-bmc.h

58

#define DRBL_RSU_STATUS GENMASK(23, 16)

include/linux/mfd/intel_soc_pmic_mrfld.h

15

#define BCOVE_ID_MINREV0 GENMASK(2, 0)

include/linux/mfd/intel_soc_pmic_mrfld.h

16

#define BCOVE_ID_MAJREV0 GENMASK(5, 3)

include/linux/mfd/intel_soc_pmic_mrfld.h

17

#define BCOVE_ID_VENDID0 GENMASK(7, 6)

include/linux/mfd/max7360.h

59

#define MAX7360_FIFO_COL GENMASK(5, 3)

include/linux/mfd/max7360.h

60

#define MAX7360_FIFO_ROW GENMASK(2, 0)

include/linux/mfd/max7360.h

68

#define MAX7360_DEBOUNCE GENMASK(4, 0)

include/linux/mfd/max7360.h

71

#define MAX7360_PORTS GENMASK(8, 5)

include/linux/mfd/max7360.h

73

#define MAX7360_INTERRUPT_TIME_MASK GENMASK(4, 0)

include/linux/mfd/max7360.h

74

#define MAX7360_INTERRUPT_FIFO_MASK GENMASK(7, 5)

include/linux/mfd/max7360.h

94

#define MAX7360_ROT_DEBOUNCE GENMASK(3, 0)

include/linux/mfd/max7360.h

97

#define MAX7360_ROT_INTCNT GENMASK(6, 4)

include/linux/mfd/max77541.h

43

#define MAX77541_BITS_MX_VOUT GENMASK(7, 0)

include/linux/mfd/max77541.h

48

#define MAX77541_BITS_MX_CFG1_RNG GENMASK(7, 6)

include/linux/mfd/max77650.h

51

#define MAX77650_CID_MASK GENMASK(3, 0)

include/linux/mfd/max77705-private.h

21

#define MAX77705_REVISION_MASK GENMASK(2, 0)

include/linux/mfd/max77705-private.h

22

#define MAX77705_VERSION_MASK GENMASK(7, MAX77705_VERSION_SHIFT)

include/linux/mfd/pf1550.h

170

#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK GENMASK(7, 6)

include/linux/mfd/pf1550.h

172

#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK GENMASK(3, 2)

include/linux/mfd/rk808.h

933

#define RK806_RST_FUN_MSK GENMASK(7, 6)

include/linux/mfd/rohm-bd72720.h

483

#define BD72720_MASK_RAMP_UP_DELAY GENMASK(7, 6)

include/linux/mfd/rohm-bd72720.h

484

#define BD72720_MASK_BUCK_VSEL GENMASK(7, 0)

include/linux/mfd/rohm-bd72720.h

485

#define BD72720_MASK_LDO12346_VSEL GENMASK(6, 0)

include/linux/mfd/rohm-bd72720.h

486

#define BD72720_MASK_LDO_VSEL GENMASK(7, 0)

include/linux/mfd/rz-mtu3.h

101

#define RZ_MTU3_TIOR_IOB GENMASK(7, 4)

include/linux/mfd/rz-mtu3.h

102

#define RZ_MTU3_TIOR_IOA GENMASK(3, 0)

include/linux/mfd/rz-mtu3.h

40

#define RZ_MTU3_TMDR1_MD GENMASK(3, 0)

include/linux/mfd/rz-mtu3.h

94

#define RZ_MTU3_TCR_CCLR GENMASK(7, 5)

include/linux/mfd/rz-mtu3.h

95

#define RZ_MTU3_TCR_CKEG GENMASK(4, 3)

include/linux/mfd/rz-mtu3.h

96

#define RZ_MTU3_TCR_TPCS GENMASK(2, 0)

include/linux/mfd/samsung/rtc.h

165

#define S2MPG10_WTSR_COLDTIMER GENMASK(6, 5)

include/linux/mfd/samsung/rtc.h

167

#define S2MPG10_WTSR_WTSRT GENMASK(3, 1)

include/linux/mfd/samsung/s2mpg10.h

39

#define S2MPG10_COMMON_INT_SRC GENMASK(7, 0)

include/linux/mfd/samsung/s2mpg11.h

36

#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0)

include/linux/mfd/stm32-lptimer.h

33

#define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3)

include/linux/mfd/stm32-lptimer.h

40

#define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)

include/linux/mfd/stm32-lptimer.h

55

#define STM32_LPTIM_PRESC GENMASK(11, 9)

include/linux/mfd/stm32-lptimer.h

56

#define STM32_LPTIM_CKPOL GENMASK(2, 1)

include/linux/mfd/stm32-lptimer.h

67

#define STM32_LPTIM_CC2P GENMASK(19, 18)

include/linux/mfd/stm32-lptimer.h

70

#define STM32_LPTIM_CC1P GENMASK(3, 2)

include/linux/mfd/stm32-lptimer.h

78

#define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0)

include/linux/mfd/stm32-timers.h

104

#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */

include/linux/mfd/stm32-timers.h

105

#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */

include/linux/mfd/stm32-timers.h

106

#define TIM_HWCFGR1_NB_OF_CC GENMASK(3, 0) /* Capture/compare channels */

include/linux/mfd/stm32-timers.h

107

#define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */

include/linux/mfd/stm32-timers.h

108

#define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */

include/linux/mfd/stm32-timers.h

44

#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */

include/linux/mfd/stm32-timers.h

67

#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */

include/linux/mfd/stm32-timers.h

69

#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */

include/linux/mfd/stmfx.h

63

#define STMFX_REG_CHIP_ID_MASK GENMASK(7, 0)

include/linux/mfd/stpmic1.h

101

#define LDO_VOLTAGE_MASK GENMASK(6, 2)

include/linux/mfd/stpmic1.h

102

#define BUCK_VOLTAGE_MASK GENMASK(7, 2)

include/linux/mfd/stpmic1.h

113

#define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)

include/linux/mfd/stpmic1.h

114

#define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)

include/linux/mfd/stpmic1.h

115

#define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)

include/linux/mfd/stpmic1.h

116

#define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)

include/linux/mfd/stpmic1.h

117

#define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)

include/linux/mfd/stpmic1.h

118

#define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)

include/linux/mfd/stpmic1.h

119

#define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)

include/linux/mfd/stpmic1.h

145

#define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)

include/linux/mfd/stpmic1.h

146

#define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)

include/linux/mfd/stpmic1.h

177

#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)

include/linux/mfd/stpmic1.h

196

#define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)

include/linux/mfd/stpmic1.h

197

#define PONKEY_TURNOFF_MASK GENMASK(7, 0)

include/linux/mfd/sun4i-gpadc.h

12

#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)

include/linux/mfd/sun4i-gpadc.h

15

#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)

include/linux/mfd/sun4i-gpadc.h

16

#define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)

include/linux/mfd/sun4i-gpadc.h

17

#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))

include/linux/mfd/sun4i-gpadc.h

21

#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)

include/linux/mfd/sun4i-gpadc.h

27

#define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))

include/linux/mfd/sun4i-gpadc.h

28

#define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)

include/linux/mfd/sun4i-gpadc.h

35

#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))

include/linux/mfd/sun4i-gpadc.h

36

#define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)

include/linux/mfd/sun4i-gpadc.h

44

#define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)

include/linux/mfd/sun4i-gpadc.h

45

#define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26)

include/linux/mfd/sun4i-gpadc.h

47

#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))

include/linux/mfd/sun4i-gpadc.h

52

#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))

include/linux/mfd/sun4i-gpadc.h

57

#define SUN4I_GPADC_TPR_TEMP_PERIOD(x) (GENMASK(15, 0) & (x))

include/linux/mfd/sun4i-gpadc.h

65

#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)

include/linux/mfd/syscon/atmel-matrix.h

64

#define AT91_MATRIX_ULBT GENMASK(2, 0)

include/linux/mfd/syscon/atmel-matrix.h

72

#define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0)

include/linux/mfd/syscon/atmel-matrix.h

73

#define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16)

include/linux/mfd/syscon/atmel-matrix.h

77

#define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18)

include/linux/mfd/syscon/atmel-matrix.h

78

#define AT91_MATRIX_ARBT GENMASK(25, 24)

include/linux/mfd/syscon/atmel-matrix.h

82

#define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0)

include/linux/mfd/syscon/atmel-matrix.h

87

#define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4)

include/linux/mfd/syscon/atmel-matrix.h

95

#define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4))

include/linux/mfd/syscon/atmel-mc.h

100

#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)

include/linux/mfd/syscon/atmel-mc.h

116

#define AT91_MC_BFC_BFCOM GENMASK(1, 0)

include/linux/mfd/syscon/atmel-mc.h

120

#define AT91_MC_BFC_BFCC GENMASK(3, 2)

include/linux/mfd/syscon/atmel-mc.h

124

#define AT91_MC_BFC_AVL GENMASK(7, 4)

include/linux/mfd/syscon/atmel-mc.h

125

#define AT91_MC_BFC_PAGES GENMASK(10, 8)

include/linux/mfd/syscon/atmel-mc.h

134

#define AT91_MC_BFC_OEL GENMASK(13, 12)

include/linux/mfd/syscon/atmel-mc.h

21

#define AT91_MC_ABTSZ GENMASK(9, 8)

include/linux/mfd/syscon/atmel-mc.h

25

#define AT91_MC_ABTTYP GENMASK(11, 10)

include/linux/mfd/syscon/atmel-mc.h

35

#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))

include/linux/mfd/syscon/atmel-mc.h

47

#define AT91_MC_SMC_NWS GENMASK(6, 0)

include/linux/mfd/syscon/atmel-mc.h

50

#define AT91_MC_SMC_TDF GENMASK(11, 8)

include/linux/mfd/syscon/atmel-mc.h

54

#define AT91_MC_SMC_DBW GENMASK(14, 13)

include/linux/mfd/syscon/atmel-mc.h

58

#define AT91_MC_SMC_ACSS GENMASK(17, 16)

include/linux/mfd/syscon/atmel-mc.h

61

#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)

include/linux/mfd/syscon/atmel-mc.h

63

#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)

include/linux/mfd/syscon/atmel-mc.h

69

#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)

include/linux/mfd/syscon/atmel-mc.h

78

#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)

include/linux/mfd/syscon/atmel-mc.h

81

#define AT91_MC_SDRAMC_NC GENMASK(1, 0)

include/linux/mfd/syscon/atmel-mc.h

86

#define AT91_MC_SDRAMC_NR GENMASK(3, 2)

include/linux/mfd/syscon/atmel-mc.h

93

#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)

include/linux/mfd/syscon/atmel-mc.h

95

#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)

include/linux/mfd/syscon/atmel-mc.h

96

#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)

include/linux/mfd/syscon/atmel-mc.h

97

#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)

include/linux/mfd/syscon/atmel-mc.h

98

#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)

include/linux/mfd/syscon/atmel-mc.h

99

#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)

include/linux/mfd/syscon/atmel-smc.h

43

#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)

include/linux/mfd/syscon/atmel-smc.h

50

#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)

include/linux/mfd/syscon/atmel-smc.h

54

#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)

include/linux/mfd/syscon/atmel-smc.h

60

#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)

include/linux/mfd/ti_am335x_tscadc.h

103

#define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val))

include/linux/mfd/ti_am335x_tscadc.h

114

#define FIFOREAD_DATA_MASK GENMASK(11, 0)

include/linux/mfd/ti_am335x_tscadc.h

115

#define FIFOREAD_CHNLID_MASK GENMASK(19, 16)

include/linux/mfd/ti_am335x_tscadc.h

55

#define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val))

include/linux/mfd/ti_am335x_tscadc.h

58

#define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))

include/linux/mfd/ti_am335x_tscadc.h

66

#define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))

include/linux/mfd/ti_am335x_tscadc.h

68

#define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))

include/linux/mfd/ti_am335x_tscadc.h

70

#define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))

include/linux/mfd/ti_am335x_tscadc.h

74

#define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))

include/linux/mfd/ti_am335x_tscadc.h

78

#define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))

include/linux/mfd/ti_am335x_tscadc.h

80

#define STEPCONFIG_MAX_OPENDLY GENMASK(17, 0)

include/linux/mfd/ti_am335x_tscadc.h

81

#define STEPDELAY_SAMPLE(val) FIELD_PREP(GENMASK(31, 24), (val))

include/linux/mfd/ti_am335x_tscadc.h

83

#define STEPCONFIG_MAX_SAMPLE GENMASK(7, 0)

include/linux/mfd/ti_am335x_tscadc.h

86

#define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val))

include/linux/mfd/ti_am335x_tscadc.h

88

#define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val))

include/linux/mfd/ti_am335x_tscadc.h

90

#define STEPCHARGE_INP(val) FIELD_PREP(GENMASK(22, 19), (val))

include/linux/mfd/ti_am335x_tscadc.h

91

#define STEPCHARGE_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))

include/linux/mfd/ti_am335x_tscadc.h

95

#define CHARGEDLY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))

include/linux/mfd/tps65086.h

86

#define TPS65086_DEVICEID2_PART_MASK GENMASK(3, 0)

include/linux/mfd/tps65086.h

87

#define TPS65086_DEVICEID2_OTP_MASK GENMASK(5, 4)

include/linux/mfd/tps65086.h

88

#define TPS65086_DEVICEID2_REV_MASK GENMASK(7, 6)

include/linux/mfd/tps65086.h

91

#define BUCK_VID_MASK GENMASK(7, 1)

include/linux/mfd/tps65086.h

92

#define VDOA1_VID_MASK GENMASK(4, 1)

include/linux/mfd/tps65086.h

93

#define VDOA23_VID_MASK GENMASK(3, 0)

include/linux/mfd/tps65219.h

135

#define TPS65219_DEVID_REV_MASK GENMASK(7, 0)

include/linux/mfd/tps65219.h

136

#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)

include/linux/mfd/tps65219.h

155

#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)

include/linux/mfd/tps65219.h

156

#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4)

include/linux/mfd/tps65219.h

180

#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0)

include/linux/mfd/tps65219.h

183

#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4)

include/linux/mfd/tps65219.h

201

#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)

include/linux/mfd/tps6594.h

1007

#define TPS6594_MASK_WD_RST_TH GENMASK(2, 0)

include/linux/mfd/tps6594.h

1008

#define TPS6594_MASK_WD_FAIL_TH GENMASK(5, 3)

include/linux/mfd/tps6594.h

1013

#define TPS6594_MASK_WD_FAIL_CNT GENMASK(3, 0)

include/linux/mfd/tps6594.h

258

#define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)

include/linux/mfd/tps6594.h

259

#define TPS6594_MASK_BUCK_ILIM GENMASK(5, 3)

include/linux/mfd/tps6594.h

262

#define TPS65224_MASK_BUCK_SLEW_RATE GENMASK(1, 0)

include/linux/mfd/tps6594.h

265

#define TPS6594_MASK_BUCK_OV_THR GENMASK(2, 0)

include/linux/mfd/tps6594.h

266

#define TPS6594_MASK_BUCK_UV_THR GENMASK(5, 3)

include/linux/mfd/tps6594.h

269

#define TPS65224_MASK_BUCK_VMON_THR GENMASK(1, 0)

include/linux/mfd/tps6594.h

272

#define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)

include/linux/mfd/tps6594.h

275

#define TPS65224_MASK_BUCK1_VSET GENMASK(7, 0)

include/linux/mfd/tps6594.h

276

#define TPS65224_MASK_BUCKS_VSET GENMASK(6, 0)

include/linux/mfd/tps6594.h

282

#define TPS6594_MASK_LDO_PLDN GENMASK(6, 5)

include/linux/mfd/tps6594.h

290

#define TPS6594_MASK_LDO123_VSET GENMASK(6, 1)

include/linux/mfd/tps6594.h

291

#define TPS6594_MASK_LDO4_VSET GENMASK(6, 0)

include/linux/mfd/tps6594.h

295

#define TPS6594_MASK_LDO_OV_THR GENMASK(2, 0)

include/linux/mfd/tps6594.h

296

#define TPS6594_MASK_LDO_UV_THR GENMASK(5, 3)

include/linux/mfd/tps6594.h

299

#define TPS65224_MASK_LDO_VMON_THR GENMASK(1, 0)

include/linux/mfd/tps6594.h

308

#define TPS65224_BIT_VMON_DEGLITCH_SEL GENMASK(7, 5)

include/linux/mfd/tps6594.h

311

#define TPS6594_MASK_VCCA_OV_THR GENMASK(2, 0)

include/linux/mfd/tps6594.h

312

#define TPS6594_MASK_VCCA_UV_THR GENMASK(5, 3)

include/linux/mfd/tps6594.h

313

#define TPS65224_MASK_VCCA_VMON_THR GENMASK(1, 0)

include/linux/mfd/tps6594.h

317

#define TPS6594_MASK_VMONX_OV_THR GENMASK(2, 0)

include/linux/mfd/tps6594.h

318

#define TPS6594_MASK_VMONX_UV_THR GENMASK(5, 3)

include/linux/mfd/tps6594.h

322

#define TPS65224_MASK_VMONX_THR GENMASK(1, 0)

include/linux/mfd/tps6594.h

330

#define TPS6594_MASK_GPIO_SEL GENMASK(7, 5)

include/linux/mfd/tps6594.h

331

#define TPS65224_MASK_GPIO_SEL GENMASK(6, 5)

include/linux/mfd/tps6594.h

332

#define TPS65224_MASK_GPIO_SEL_GPIO6 GENMASK(7, 5)

include/linux/mfd/tps6594.h

340

#define TPS6594_MASK_NPWRON_SEL GENMASK(7, 6)

include/linux/mfd/tps6594.h

346

#define TPS65224_MASK_EN_PB_VSENSE_CONFIG GENMASK(7, 6)

include/linux/mfd/tps6594.h

362

#define TPS6594_MASK_BUCK1_GRP_SEL GENMASK(1, 0)

include/linux/mfd/tps6594.h

363

#define TPS6594_MASK_BUCK2_GRP_SEL GENMASK(3, 2)

include/linux/mfd/tps6594.h

364

#define TPS6594_MASK_BUCK3_GRP_SEL GENMASK(5, 4)

include/linux/mfd/tps6594.h

365

#define TPS6594_MASK_BUCK4_GRP_SEL GENMASK(7, 6)

include/linux/mfd/tps6594.h

368

#define TPS6594_MASK_BUCK5_GRP_SEL GENMASK(1, 0)

include/linux/mfd/tps6594.h

369

#define TPS6594_MASK_LDO1_GRP_SEL GENMASK(3, 2)

include/linux/mfd/tps6594.h

370

#define TPS6594_MASK_LDO2_GRP_SEL GENMASK(5, 4)

include/linux/mfd/tps6594.h

371

#define TPS6594_MASK_LDO3_GRP_SEL GENMASK(7, 6)

include/linux/mfd/tps6594.h

374

#define TPS6594_MASK_LDO4_GRP_SEL GENMASK(1, 0)

include/linux/mfd/tps6594.h

375

#define TPS6594_MASK_VCCA_GRP_SEL GENMASK(3, 2)

include/linux/mfd/tps6594.h

376

#define TPS6594_MASK_VMON1_GRP_SEL GENMASK(5, 4)

include/linux/mfd/tps6594.h

377

#define TPS6594_MASK_VMON2_GRP_SEL GENMASK(7, 6)

include/linux/mfd/tps6594.h

380

#define TPS6594_MASK_MCU_RAIL_TRIG GENMASK(1, 0)

include/linux/mfd/tps6594.h

381

#define TPS6594_MASK_SOC_RAIL_TRIG GENMASK(3, 2)

include/linux/mfd/tps6594.h

382

#define TPS6594_MASK_OTHER_RAIL_TRIG GENMASK(5, 4)

include/linux/mfd/tps6594.h

383

#define TPS6594_MASK_SEVERE_ERR_TRIG GENMASK(7, 6)

include/linux/mfd/tps6594.h

386

#define TPS6594_MASK_MODERATE_ERR_TRIG GENMASK(1, 0)

include/linux/mfd/tps6594.h

677

#define TPS6594_MASK_PGOOD_SEL_BUCK1 GENMASK(1, 0)

include/linux/mfd/tps6594.h

678

#define TPS6594_MASK_PGOOD_SEL_BUCK2 GENMASK(3, 2)

include/linux/mfd/tps6594.h

679

#define TPS6594_MASK_PGOOD_SEL_BUCK3 GENMASK(5, 4)

include/linux/mfd/tps6594.h

680

#define TPS6594_MASK_PGOOD_SEL_BUCK4 GENMASK(7, 6)

include/linux/mfd/tps6594.h

683

#define TPS6594_MASK_PGOOD_SEL_BUCK5 GENMASK(1, 0)

include/linux/mfd/tps6594.h

686

#define TPS6594_MASK_PGOOD_SEL_LDO1 GENMASK(1, 0)

include/linux/mfd/tps6594.h

687

#define TPS6594_MASK_PGOOD_SEL_LDO2 GENMASK(3, 2)

include/linux/mfd/tps6594.h

688

#define TPS6594_MASK_PGOOD_SEL_LDO3 GENMASK(5, 4)

include/linux/mfd/tps6594.h

689

#define TPS6594_MASK_PGOOD_SEL_LDO4 GENMASK(7, 6)

include/linux/mfd/tps6594.h

702

#define TPS6594_MASK_EXT_CLK_FREQ GENMASK(1, 0)

include/linux/mfd/tps6594.h

716

#define TPS6594_MASK_BB_VEOC GENMASK(3, 2)

include/linux/mfd/tps6594.h

731

#define TPS6594_MASK_SYNCCLKOUT_FREQ_SEL GENMASK(7, 6)

include/linux/mfd/tps6594.h

742

#define TPS6594_MASK_RECOV_CNT GENMASK(3, 0)

include/linux/mfd/tps6594.h

745

#define TPS6594_MASK_RECOV_CNT_THR GENMASK(3, 0)

include/linux/mfd/tps6594.h

759

#define TPS6594_MASK_SS_DEPTH GENMASK(1, 0)

include/linux/mfd/tps6594.h

766

#define TPS6594_MASK_PFSM_DELAY_STEP GENMASK(4, 0)

include/linux/mfd/tps6594.h

769

#define TPS6594_MASK_LDO1_RV_TIMEOUT GENMASK(3, 0)

include/linux/mfd/tps6594.h

770

#define TPS6594_MASK_LDO2_RV_TIMEOUT GENMASK(7, 4)

include/linux/mfd/tps6594.h

773

#define TPS6594_MASK_LDO3_RV_TIMEOUT GENMASK(3, 0)

include/linux/mfd/tps6594.h

774

#define TPS6594_MASK_LDO4_RV_TIMEOUT GENMASK(7, 4)

include/linux/mfd/tps6594.h

783

#define TPS6594_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)

include/linux/mfd/tps6594.h

789

#define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)

include/linux/mfd/tps6594.h

798

#define TPS6594_MASK_ESM_SOC_ERR_CNT_TH GENMASK(3, 0)

include/linux/mfd/tps6594.h

804

#define TPS65224_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)

include/linux/mfd/tps6594.h

810

#define TPS6594_MASK_ESM_SOC_ERR_CNT GENMASK(4, 0)

include/linux/mfd/tps6594.h

813

#define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)

include/linux/mfd/tps6594.h

819

#define TPS6594_MASK_VMON1_SLEW_RATE GENMASK(2, 0)

include/linux/mfd/tps6594.h

820

#define TPS6594_MASK_VMON2_SLEW_RATE GENMASK(5, 3)

include/linux/mfd/tps6594.h

823

#define TPS65224_MASk_SRAM_UNLOCK_SEQ GENMASK(7, 0)

include/linux/mfd/tps6594.h

834

#define TPS65224_MASk_SRAM_SEL GENMASK(1, 0)

include/linux/mfd/tps6594.h

840

#define TPS65224_MASK_SILICON_REV GENMASK(7, 0)

include/linux/mfd/tps6594.h

843

#define TPS65224_MASK_CUSTOMER_NVM_ID GENMASK(7, 0)

include/linux/mfd/tps6594.h

849

#define TPS6594_MASK_SECOND_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

850

#define TPS6594_MASK_SECOND_1 GENMASK(6, 4)

include/linux/mfd/tps6594.h

853

#define TPS6594_MASK_MINUTE_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

854

#define TPS6594_MASK_MINUTE_1 GENMASK(6, 4)

include/linux/mfd/tps6594.h

857

#define TPS6594_MASK_HOUR_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

858

#define TPS6594_MASK_HOUR_1 GENMASK(5, 4)

include/linux/mfd/tps6594.h

862

#define TPS6594_MASK_DAY_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

863

#define TPS6594_MASK_DAY_1 GENMASK(5, 4)

include/linux/mfd/tps6594.h

866

#define TPS6594_MASK_MONTH_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

870

#define TPS6594_MASK_YEAR_0 GENMASK(3, 0)

include/linux/mfd/tps6594.h

871

#define TPS6594_MASK_YEAR_1 GENMASK(7, 4)

include/linux/mfd/tps6594.h

874

#define TPS6594_MASK_WEEK GENMASK(2, 0)

include/linux/mfd/tps6594.h

887

#define TPS6594_MASK_XTAL_SEL GENMASK(2, 1)

include/linux/mfd/tps6594.h

890

#define TPS6594_MASK_STARTUP_DEST GENMASK(6, 5)

include/linux/mfd/tps6594.h

900

#define TPS6594_MASK_EVERY GENMASK(1, 0)

include/linux/mfd/tps6594.h

911

#define TPS6594_MASK_T_CRC GENMASK(7, 3)

include/linux/mfd/tps6594.h

921

#define TPS65224_MASK_ADC_RESULT_11_4 GENMASK(7, 0)

include/linux/mfd/tps6594.h

924

#define TPS65224_MASK_ADC_RESULT_3_0 GENMASK(7, 4)

include/linux/mfd/tps6594.h

927

#define TPS65224_MASK_STARTUP_DEST GENMASK(6, 5)

include/linux/mfd/tps6594.h

931

#define TPS6594_MASK_SCRATCH_PAD_1 GENMASK(7, 0)

include/linux/mfd/tps6594.h

934

#define TPS6594_MASK_SCRATCH_PAD_2 GENMASK(7, 0)

include/linux/mfd/tps6594.h

937

#define TPS6594_MASK_SCRATCH_PAD_3 GENMASK(7, 0)

include/linux/mfd/tps6594.h

940

#define TPS6594_MASK_SCRATCH_PAD_4 GENMASK(7, 0)

include/linux/mfd/tps6594.h

943

#define TPS6594_MASK_PFSM_DELAY1 GENMASK(7, 0)

include/linux/mfd/tps6594.h

946

#define TPS6594_MASK_PFSM_DELAY2 GENMASK(7, 0)

include/linux/mfd/tps6594.h

949

#define TPS6594_MASK_PFSM_DELAY3 GENMASK(7, 0)

include/linux/mfd/tps6594.h

952

#define TPS6594_MASK_PFSM_DELAY4 GENMASK(7, 0)

include/linux/mfd/tps6594.h

959

#define TPS65224_MASK_ADC_GAIN_COMP GENMASK(7, 0)

include/linux/mfd/tps6594.h

962

#define TPS65224_MASK_REGMAP_USER_CRC16_LOW GENMASK(7, 0)

include/linux/mfd/tps6594.h

965

#define TPS65224_MASK_REGMAP_USER_CRC16_HIGH GENMASK(7, 0)

include/linux/mfd/tps6594.h

968

#define TPS6594_MASK_WD_ANSWER GENMASK(7, 0)

include/linux/mfd/tps6594.h

971

#define TPS6594_MASK_WD_QUESTION GENMASK(3, 0)

include/linux/mfd/tps6594.h

972

#define TPS6594_MASK_WD_ANSW_CNT GENMASK(5, 4)

include/linux/mfd/tps6594.h

976

#define TPS6594_MASK_WD_WIN1_CFG GENMASK(6, 0)

include/linux/mfd/tps6594.h

979

#define TPS6594_MASK_WD_WIN2_CFG GENMASK(6, 0)

include/linux/mfd/tps6594.h

982

#define TPS6594_MASK_WD_LONGWIN_CFG GENMASK(7, 0)

include/linux/mfd/tps6594.h

992

#define TPS6594_MASK_WD_QUESTION_SEED GENMASK(3, 0)

include/linux/mfd/tps6594.h

993

#define TPS6594_MASK_WD_QA_LFSR GENMASK(5, 4)

include/linux/mfd/tps6594.h

994

#define TPS6594_MASK_WD_QA_FDBK GENMASK(7, 6)

include/linux/mfd/tps68470.h

57

#define TPS68470_REG_RESET_MASK GENMASK(7, 0)

include/linux/mfd/tps68470.h

58

#define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

60

#define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)

include/linux/mfd/tps68470.h

61

#define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

62

#define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

63

#define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

64

#define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

65

#define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)

include/linux/mfd/tps68470.h

67

#define TPS68470_VACTL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

68

#define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

69

#define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

70

#define TPS68470_S_I2C_CTL_EN_MASK GENMASK(1, 0)

include/linux/mfd/tps68470.h

71

#define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

72

#define TPS68470_VAUX2CTL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

73

#define TPS68470_PLL_EN_MASK GENMASK(0, 0)

include/linux/mfd/tps68470.h

75

#define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0)

include/linux/mfd/tps68470.h

76

#define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2)

include/linux/mfd/tps68470.h

81

#define TPS68470_PLLSWR_DEFAULT GENMASK(1, 0)

include/linux/mfd/tps68470.h

86

#define TPS68470_CLK_SRC_SHIFT GENMASK(2, 0)

include/linux/mfd/tps68470.h

91

#define TPS68470_GPIO_MODE_MASK GENMASK(1, 0)

include/linux/mfd/wcd934x/registers.h

11

#define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)

include/linux/mfd/wcd934x/registers.h

128

#define WCD934X_VTH_MASK GENMASK(7, 2)

include/linux/mfd/wcd934x/registers.h

136

#define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2)

include/linux/mfd/wcd934x/registers.h

138

#define WCD934X_MICB_VAL_MASK GENMASK(5, 0)

include/linux/mfd/wcd934x/registers.h

139

#define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6)

include/linux/mfd/wcd934x/registers.h

149

#define WCD934X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)

include/linux/mfd/wcd934x/registers.h

150

#define WCD934X_ANA_MICB2_VOUT_MASK GENMASK(5, 0)

include/linux/mfd/wcd934x/registers.h

153

#define WCD934X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)

include/linux/mfd/wcd934x/registers.h

17

#define WCD934X_EFUSE_SENSE_STATE_MASK GENMASK(4, 1)

include/linux/mfd/wcd934x/registers.h

205

#define WCD934X_EXT_CLK_DIV_RATIO_MASK GENMASK(5, 4)

include/linux/mfd/wcd934x/registers.h

224

#define WCD934X_M_RTH_CTL_MASK GENMASK(3, 2)

include/linux/mfd/wcd934x/registers.h

226

#define WCD934X_HSDET_PULLUP_C_MASK GENMASK(7, 6)

include/linux/mfd/wcd934x/registers.h

228

#define WCD934X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)

include/linux/mfd/wcd934x/registers.h

229

#define WCD934X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)

include/linux/mfd/wcd934x/registers.h

241

#define WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0)

include/linux/mfd/wcd934x/registers.h

323

#define WCD934X_RX_PCM_RATE_MASK GENMASK(3, 0)

include/linux/mfd/wcd934x/registers.h

326

#define WCD934X_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0)

include/linux/mfd/wcd934x/registers.h

34

#define WCD934X_DMIC_RATE_MASK GENMASK(3, 1)

include/linux/mfd/wcd934x/registers.h

360

#define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2)

include/linux/mfd/wcd934x/registers.h

444

#define WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0)

include/linux/mfd/wcd934x/registers.h

7

#define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0)

include/linux/mfd/wcd934x/registers.h

92

#define WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK GENMASK(1, 0)

include/linux/mlx5/device.h

1021

CQE_RSS_HTYPE_IP = GENMASK(3, 2),

include/linux/mlx5/device.h

1030

CQE_RSS_HTYPE_L4 = GENMASK(7, 6),

include/linux/mlx5/eswitch.h

102

return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS);

include/linux/mlx5/eswitch.h

129

#define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)

include/linux/mlx5/eswitch.h

130

#define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET)

include/linux/mlx5/eswitch.h

131

#define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET)

include/linux/mlx5/eswitch.h

135

#define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0)

include/linux/mlx5/eswitch.h

145

GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \

include/linux/mlx5/eswitch.h

149

#define ESW_IPSEC_RX_MAPPED_ID_MASK GENMASK(ESW_TUN_OPTS_BITS - 1, 0)

include/linux/mlx5/eswitch.h

151

GENMASK(31 - ESW_RESERVED_BITS, ESW_ZONE_ID_BITS)

include/linux/mlx5/eswitch.h

98

#define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0)

include/linux/mlx5/qp.h

262

GENMASK(5, 2) << MLX5_ETH_WQE_FT_META_SHIFT,

include/linux/mm.h

4855

#define PP_DMA_INDEX_MASK GENMASK(PP_DMA_INDEX_BITS + PP_DMA_INDEX_SHIFT - 1, \

include/linux/mmc/mmc.h

423

#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0)

include/linux/msi.h

572

MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0),

include/linux/msi.h

575

MSI_DOMAIN_FLAGS_MASK = GENMASK(31, 16),

include/linux/mtd/nand-qpic-common.h

103

#define READ_ADDR_MASK GENMASK(7, 0)

include/linux/mtd/nand-qpic-common.h

113

#define NUM_STEPS_MASK GENMASK(9, 0)

include/linux/mtd/nand-qpic-common.h

133

#define READ_LOCATION_OFFSET_MASK GENMASK(9, 0)

include/linux/mtd/nand-qpic-common.h

134

#define READ_LOCATION_SIZE_MASK GENMASK(25, 16)

include/linux/mtd/nand-qpic-common.h

74

#define CW_PER_PAGE_MASK GENMASK(8, 6)

include/linux/mtd/nand-qpic-common.h

75

#define UD_SIZE_BYTES_MASK GENMASK(18, 9)

include/linux/mtd/nand-qpic-common.h

76

#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)

include/linux/mtd/nand-qpic-common.h

77

#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)

include/linux/mtd/nand-qpic-common.h

78

#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)

include/linux/mtd/nand-qpic-common.h

85

#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)

include/linux/mtd/nand-qpic-common.h

87

#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)

include/linux/mtd/nand-qpic-common.h

89

#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)

include/linux/mtd/nand-qpic-common.h

95

#define ECC_MODE_MASK GENMASK(5, 4)

include/linux/mtd/nand-qpic-common.h

98

#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)

include/linux/mtd/nand-qpic-common.h

99

#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)

include/linux/mtd/onfi.h

43

#define ONFI_TIMING_MODE_PARAM(x) FIELD_GET(GENMASK(3, 0), (x))

include/linux/mtd/spi-nor.h

131

#define SNOR_PROTO_INST_MASK GENMASK(23, 16)

include/linux/mtd/spi-nor.h

137

#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)

include/linux/mtd/spi-nor.h

143

#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)

include/linux/mtd/spi-nor.h

222

#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)

include/linux/mtd/spi-nor.h

227

#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)

include/linux/mtd/spi-nor.h

233

#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)

include/linux/mtd/spi-nor.h

239

#define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)

include/linux/mtd/spi-nor.h

255

#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)

include/linux/mtd/spi-nor.h

258

#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)

include/linux/mtd/spi-nor.h

263

#define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)

include/linux/mtd/spinand.h

327

#define STATUS_ECC_MASK GENMASK(5, 4)

include/linux/nvme.h

772

NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14),

include/linux/nvme.h

773

NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),

include/linux/nvme.h

775

NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),

include/linux/olpc-ec.h

31

#define EC_SCI_SRC_ALL GENMASK(8, 0)

include/linux/page_frag_cache.h

15

#define PAGE_FRAG_CACHE_ORDER_MASK GENMASK(7, 0)

include/linux/pds/pds_adminq.h

1268

#define PDS_FWCTL_RPC_OPCODE_CMD_MASK GENMASK(15, PDS_FWCTL_RPC_OPCODE_CMD_SHIFT)

include/linux/pds/pds_adminq.h

1270

#define PDS_FWCTL_RPC_OPCODE_VER_MASK GENMASK(23, PDS_FWCTL_RPC_OPCODE_VER_SHIFT)

include/linux/peci-cpu.h

18

#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT)

include/linux/peci-cpu.h

19

#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT)

include/linux/peci-cpu.h

20

#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT)

include/linux/perf/arm_pmuv3.h

219

#define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */

include/linux/perf/arm_pmuv3.h

229

#define ARMV8_PMU_OVSR_P GENMASK(30, 0)

include/linux/perf/arm_pmuv3.h

239

#define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */

include/linux/perf/arm_pmuv3.h

266

#define ARMV8_PMU_SLOTS GENMASK(7, 0)

include/linux/perf/arm_pmuv3.h

267

#define ARMV8_PMU_BUS_SLOTS GENMASK(15, 8)

include/linux/perf/arm_pmuv3.h

268

#define ARMV8_PMU_BUS_WIDTH GENMASK(19, 16)

include/linux/perf/arm_pmuv3.h

269

#define ARMV8_PMU_THWIDTH GENMASK(23, 20)

include/linux/phy.h

1569

#define PHY_ID_MATCH_EXTACT_MASK GENMASK(31, 0)

include/linux/phy.h

1570

#define PHY_ID_MATCH_MODEL_MASK GENMASK(31, 4)

include/linux/phy.h

1571

#define PHY_ID_MATCH_VENDOR_MASK GENMASK(31, 10)

include/linux/platform_data/cros_ec_commands.h

4631

(((events) & GENMASK(27, 0)) | (((port) & 0xf) << 28))

include/linux/platform_data/cros_ec_commands.h

4632

#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event) & GENMASK(27, 0))

include/linux/platform_data/cros_ec_commands.h

5811

& GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))

include/linux/platform_data/dma-dw.h

73

#define CHAN_PROTCTL_MASK GENMASK(2, 0)

include/linux/platform_data/x86/amd-fch.h

9

#define FCH_PM_DECODEEN_SMBUS0SEL GENMASK(20, 19)

include/linux/platform_data/x86/pmc_atom.h

157

#define SLEEP_TYPE_MASK GENMASK(12, 10)

include/linux/platform_data/x86/pmc_atom.h

54

#define PMC_MASK_CLK_CTL GENMASK(1, 0)

include/linux/power/max77705_charger.h

36

#define MAX77705_WCIN_DTLS GENMASK(4, 3)

include/linux/power/max77705_charger.h

38

#define MAX77705_CHGIN_DTLS GENMASK(6, 5)

include/linux/power/max77705_charger.h

42

#define MAX77705_CHG_DTLS GENMASK(3, 0)

include/linux/power/max77705_charger.h

44

#define MAX77705_BAT_DTLS GENMASK(6, 4)

include/linux/power/max77705_charger.h

48

#define MAX77705_BYP_DTLS GENMASK(3, 0)

include/linux/power/max77705_charger.h

88

#define MAX77705_CHG_MINVSYS_MASK GENMASK(7, 6)

include/linux/power/max77705_charger.h

98

#define MAX77705_WDTCLR_MASK GENMASK(1, 0)

include/linux/psp-sev.h

24

#define SEV_POLICY_MASK_API_MAJOR GENMASK(23, 16)

include/linux/psp-sev.h

25

#define SEV_POLICY_MASK_API_MINOR GENMASK(31, 24)

include/linux/psp.h

20

#define PSP_CMDRESP_STS GENMASK(15, 0)

include/linux/psp.h

22

#define PSP_CMDRESP_CMD GENMASK(23, 16)

include/linux/psp.h

23

#define PSP_CMDRESP_RESERVED GENMASK(29, 24)

include/linux/pxa2xx_ssp.h

100

#define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */

include/linux/pxa2xx_ssp.h

102

#define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

104

#define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

111

#define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */

include/linux/pxa2xx_ssp.h

113

#define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */

include/linux/pxa2xx_ssp.h

119

#define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */

include/linux/pxa2xx_ssp.h

120

#define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */

include/linux/pxa2xx_ssp.h

122

#define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

124

#define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

193

#define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */

include/linux/pxa2xx_ssp.h

194

#define SFIFOL_RFL_MASK GENMASK(31, 16) /* Receive FIFO Level mask */

include/linux/pxa2xx_ssp.h

196

#define SFIFOTT_TFT GENMASK(15, 0) /* Transmit FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

198

#define SFIFOTT_RFT GENMASK(31, 16) /* Receive FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

49

#define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */

include/linux/pxa2xx_ssp.h

51

#define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */

include/linux/pxa2xx_ssp.h

64

#define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */

include/linux/pxa2xx_ssp.h

77

#define SSSR_ALT_FRM_MASK GENMASK(1, 0) /* Masks the SFRM signal number */

include/linux/pxa2xx_ssp.h

88

#define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */

include/linux/pxa2xx_ssp.h

89

#define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */

include/linux/pxa2xx_ssp.h

91

#define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

93

#define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */

include/linux/pxa2xx_ssp.h

99

#define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */

include/linux/regmap.h

46

#define REGMAP_MDIO_C45_DEVAD_MASK GENMASK(20, 16)

include/linux/regmap.h

47

#define REGMAP_MDIO_C45_REGNUM_MASK GENMASK(15, 0)

include/linux/regulator/mt6363-regulator.h

102

#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

128

#define MT6363_RG_VCN13_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

130

#define MT6363_RG_VEMC_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

131

#define MT6363_RG_VEMC_VOSEL_1_MASK GENMASK(7, 4)

include/linux/regulator/mt6363-regulator.h

133

#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

135

#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

137

#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

139

#define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

141

#define MT6363_RG_VEMC_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

259

#define MT6363_RG_VTREF18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

261

#define MT6363_RG_VTREF18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

263

#define MT6363_RG_VAUX18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

265

#define MT6363_RG_VAUX18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

267

#define MT6363_RG_VCN15_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

269

#define MT6363_RG_VCN15_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

271

#define MT6363_RG_VUFS18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

273

#define MT6363_RG_VUFS18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

275

#define MT6363_RG_VIO18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

277

#define MT6363_RG_VIO18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

279

#define MT6363_RG_VM18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

281

#define MT6363_RG_VM18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

283

#define MT6363_RG_VA15_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

285

#define MT6363_RG_VA15_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

287

#define MT6363_RG_VRF18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

289

#define MT6363_RG_VRF18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

291

#define MT6363_RG_VRFIO18_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

293

#define MT6363_RG_VRFIO18_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

296

#define MT6363_RG_VIO075_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

298

#define MT6363_RG_VIO075_VOSEL_MASK GENMASK(6, 4)

include/linux/regulator/mt6363-regulator.h

300

#define MT6363_RG_VCN13_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

302

#define MT6363_RG_VUFS12_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

304

#define MT6363_RG_VUFS12_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

306

#define MT6363_RG_VA12_1_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

308

#define MT6363_RG_VA12_1_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

310

#define MT6363_RG_VA12_2_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

312

#define MT6363_RG_VA12_2_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

314

#define MT6363_RG_VRF12_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

316

#define MT6363_RG_VRF12_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

318

#define MT6363_RG_VRF13_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

320

#define MT6363_RG_VRF13_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

322

#define MT6363_RG_VRF09_VOCAL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

324

#define MT6363_RG_VRF09_VOSEL_MASK GENMASK(3, 0)

include/linux/regulator/mt6363-regulator.h

326

#define MT6363_ISINK_CTRL0_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

328

#define MT6363_ISINK_CTRL1_MASK GENMASK(7, 4)

include/linux/regulator/mt6363-regulator.h

46

#define MT6363_RG_BUCK_VS2_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

48

#define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

50

#define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

52

#define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

54

#define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

56

#define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

58

#define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

60

#define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

62

#define MT6363_RG_BUCK_VS1_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

64

#define MT6363_RG_BUCK_VS3_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

66

#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

68

#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

70

#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK GENMASK(6, 0)

include/linux/regulator/mt6363-regulator.h

83

#define MT6363_RG_BUCK_EFUSE_RSV1_MASK GENMASK(7, 4)

include/linux/regulator/mt6363-regulator.h

90

#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK GENMASK(7, 0)

include/linux/regulator/mt6363-regulator.h

95

#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK GENMASK(7, 0)

include/linux/resctrl_types.h

35

#define MAX_EVT_CONFIG_BITS GENMASK(6, 0)

include/linux/scmi_protocol.h

290

#define SCMI_SENS_INTVL_GET_SECS(x) FIELD_GET(GENMASK(20, 5), (x))

include/linux/scmi_protocol.h

293

int __signed_exp = FIELD_GET(GENMASK(4, 0), (x)); \

include/linux/scmi_protocol.h

296

__signed_exp |= GENMASK(31, 5); \

include/linux/scmi_protocol.h

354

#define SCMI_SENS_CFG_UPDATE_SECS_MASK GENMASK(31, 16)

include/linux/scmi_protocol.h

358

#define SCMI_SENS_CFG_UPDATE_EXP_MASK GENMASK(15, 11)

include/linux/scmi_protocol.h

365

__signed_exp |= GENMASK(31, 5); \

include/linux/scmi_protocol.h

369

#define SCMI_SENS_CFG_ROUND_MASK GENMASK(10, 9)

include/linux/serial_s3c.h

270

#define APPLE_S5L_UTRSTAT_ALL_FLAGS GENMASK(9, 3)

include/linux/soc/airoha/airoha_offload.h

102

#define NPU_TX_DMA_DESC_LEN_MASK GENMASK(30, 18)

include/linux/soc/airoha/airoha_offload.h

103

#define NPU_TX_DMA_DESC_VEND_LEN_MASK GENMASK(17, 1)

include/linux/soc/airoha/airoha_offload.h

75

#define NPU_RX_DMA_DESC_LEN_MASK GENMASK(26, 14)

include/linux/soc/airoha/airoha_offload.h

76

#define NPU_RX_DMA_DESC_CUR_LEN_MASK GENMASK(13, 1)

include/linux/soc/airoha/airoha_offload.h

79

#define NPU_RX_DMA_PKT_COUNT_MASK GENMASK(31, 29)

include/linux/soc/airoha/airoha_offload.h

80

#define NPU_RX_DMA_PKT_ID_MASK GENMASK(28, 26)

include/linux/soc/airoha/airoha_offload.h

81

#define NPU_RX_DMA_SRC_PORT_MASK GENMASK(25, 21)

include/linux/soc/airoha/airoha_offload.h

82

#define NPU_RX_DMA_CRSN_MASK GENMASK(20, 16)

include/linux/soc/airoha/airoha_offload.h

83

#define NPU_RX_DMA_FOE_ID_MASK GENMASK(15, 0)

include/linux/soc/airoha/airoha_offload.h

85

#define NPU_RX_DMA_SID_MASK GENMASK(31, 16)

include/linux/soc/airoha/airoha_offload.h

86

#define NPU_RX_DMA_FRAG_TYPE_MASK GENMASK(15, 14)

include/linux/soc/airoha/airoha_offload.h

87

#define NPU_RX_DMA_PRIORITY_MASK GENMASK(13, 10)

include/linux/soc/airoha/airoha_offload.h

88

#define NPU_RX_DMA_RADIO_ID_MASK GENMASK(9, 6)

include/linux/soc/airoha/airoha_offload.h

89

#define NPU_RX_DMA_VAP_ID_MASK GENMASK(5, 2)

include/linux/soc/airoha/airoha_offload.h

90

#define NPU_RX_DMA_FRAME_TYPE_MASK GENMASK(1, 0)

include/linux/soc/mediatek/infracfg.h

103

#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)

include/linux/soc/mediatek/infracfg.h

104

#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))

include/linux/soc/mediatek/infracfg.h

108

#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))

include/linux/soc/mediatek/infracfg.h

109

#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)

include/linux/soc/mediatek/infracfg.h

117

#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)

include/linux/soc/mediatek/infracfg.h

150

#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)

include/linux/soc/mediatek/infracfg.h

157

#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)

include/linux/soc/mediatek/infracfg.h

212

#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21)

include/linux/soc/mediatek/infracfg.h

219

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29)

include/linux/soc/mediatek/infracfg.h

220

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))

include/linux/soc/mediatek/infracfg.h

221

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \

include/linux/soc/mediatek/infracfg.h

223

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))

include/linux/soc/mediatek/infracfg.h

224

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8)

include/linux/soc/mediatek/infracfg.h

225

#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21)

include/linux/soc/mediatek/infracfg.h

232

#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8)

include/linux/soc/mediatek/infracfg.h

236

#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))

include/linux/soc/mediatek/infracfg.h

239

#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30)

include/linux/soc/mediatek/infracfg.h

245

#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5)

include/linux/soc/mediatek/infracfg.h

260

#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26)

include/linux/soc/mediatek/infracfg.h

261

#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24)

include/linux/soc/mediatek/infracfg.h

267

#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30)

include/linux/soc/mediatek/infracfg.h

269

#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28)

include/linux/soc/mediatek/infracfg.h

276

#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1)

include/linux/soc/mediatek/infracfg.h

277

#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1)

include/linux/soc/mediatek/infracfg.h

280

#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2)

include/linux/soc/mediatek/infracfg.h

281

#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2)

include/linux/soc/mediatek/infracfg.h

319

#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))

include/linux/soc/mediatek/infracfg.h

320

#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))

include/linux/soc/mediatek/infracfg.h

324

#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))

include/linux/soc/mediatek/infracfg.h

325

#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))

include/linux/soc/mediatek/infracfg.h

333

#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))

include/linux/soc/mediatek/infracfg.h

334

#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))

include/linux/soc/mediatek/infracfg.h

350

#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))

include/linux/soc/mediatek/infracfg.h

351

#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))

include/linux/soc/mediatek/infracfg.h

372

#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)

include/linux/soc/mediatek/infracfg.h

377

#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \

include/linux/soc/mediatek/infracfg.h

392

#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)

include/linux/soc/mediatek/infracfg.h

77

#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)

include/linux/soc/mediatek/infracfg.h

79

#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)

include/linux/soc/mediatek/infracfg.h

82

#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)

include/linux/soc/mediatek/infracfg.h

85

#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))

include/linux/soc/mediatek/infracfg.h

89

#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)

include/linux/soc/mediatek/infracfg.h

90

#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)

include/linux/soc/mediatek/mtk-cmdq.h

14

#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))

include/linux/soc/qcom/geni-se.h

134

#define CLK_DIV_MSK GENMASK(15, 4)

include/linux/soc/qcom/geni-se.h

141

#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)

include/linux/soc/qcom/geni-se.h

145

#define CLK_SEL_MSK GENMASK(2, 0)

include/linux/soc/qcom/geni-se.h

154

#define M_OPCODE_MSK GENMASK(31, 27)

include/linux/soc/qcom/geni-se.h

156

#define M_PARAMS_MSK GENMASK(26, 0)

include/linux/soc/qcom/geni-se.h

164

#define S_OPCODE_MSK GENMASK(31, 27)

include/linux/soc/qcom/geni-se.h

166

#define S_PARAMS_MSK GENMASK(26, 0)

include/linux/soc/qcom/geni-se.h

200

#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \

include/linux/soc/qcom/geni-se.h

226

#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \

include/linux/soc/qcom/geni-se.h

230

#define WATERMARK_MSK GENMASK(5, 0)

include/linux/soc/qcom/geni-se.h

233

#define TX_FIFO_WC GENMASK(27, 0)

include/linux/soc/qcom/geni-se.h

237

#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)

include/linux/soc/qcom/geni-se.h

239

#define RX_FIFO_WC_MSK GENMASK(24, 0)

include/linux/soc/qcom/geni-se.h

246

#define GP_LENGTH GENMASK(31, 0)

include/linux/soc/qcom/geni-se.h

261

#define RX_DMA_BREAK GENMASK(8, 7)

include/linux/soc/qcom/geni-se.h

262

#define RX_GENI_GP_IRQ GENMASK(10, 5)

include/linux/soc/qcom/geni-se.h

263

#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)

include/linux/soc/qcom/geni-se.h

267

#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)

include/linux/soc/qcom/geni-se.h

273

#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)

include/linux/soc/qcom/geni-se.h

274

#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)

include/linux/soc/qcom/geni-se.h

278

#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)

include/linux/soc/qcom/geni-se.h

284

#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16)

include/linux/soc/qcom/geni-se.h

285

#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)

include/linux/soc/qcom/geni-se.h

288

#define HW_VER_MAJOR_MASK GENMASK(31, 28)

include/linux/soc/qcom/geni-se.h

290

#define HW_VER_MINOR_MASK GENMASK(27, 16)

include/linux/soc/qcom/geni-se.h

292

#define HW_VER_STEP_MASK GENMASK(15, 0)

include/linux/soundwire/sdw.h

81

#define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)

include/linux/soundwire/sdw_intel.h

106

#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)

include/linux/soundwire/sdw_intel.h

113

#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)

include/linux/soundwire/sdw_intel.h

114

#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)

include/linux/soundwire/sdw_intel.h

129

#define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */

include/linux/soundwire/sdw_intel.h

133

#define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */

include/linux/soundwire/sdw_intel.h

134

#define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */

include/linux/soundwire/sdw_intel.h

135

#define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */

include/linux/soundwire/sdw_intel.h

139

#define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */

include/linux/soundwire/sdw_intel.h

143

#define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */

include/linux/soundwire/sdw_intel.h

144

#define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */

include/linux/soundwire/sdw_intel.h

145

#define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */

include/linux/soundwire/sdw_intel.h

151

#define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27)

include/linux/soundwire/sdw_intel.h

184

#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)

include/linux/soundwire/sdw_intel.h

187

#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7)

include/linux/soundwire/sdw_intel.h

188

#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12)

include/linux/soundwire/sdw_intel.h

25

#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)

include/linux/soundwire/sdw_intel.h

32

#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)

include/linux/soundwire/sdw_intel.h

34

#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)

include/linux/soundwire/sdw_intel.h

35

#define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27)

include/linux/soundwire/sdw_intel.h

47

#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)

include/linux/soundwire/sdw_intel.h

49

#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)

include/linux/soundwire/sdw_intel.h

63

#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)

include/linux/soundwire/sdw_intel.h

64

#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)

include/linux/soundwire/sdw_intel.h

65

#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)

include/linux/soundwire/sdw_intel.h

73

#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)

include/linux/soundwire/sdw_intel.h

74

#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)

include/linux/soundwire/sdw_intel.h

75

#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)

include/linux/soundwire/sdw_registers.h

116

#define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0)

include/linux/soundwire/sdw_registers.h

13

#define SDW_REGADDR GENMASK(14, 0)

include/linux/soundwire/sdw_registers.h

14

#define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)

include/linux/soundwire/sdw_registers.h

15

#define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)

include/linux/soundwire/sdw_registers.h

224

#define SDW_SCP_CLOCK_SCALE GENMASK(3, 0)

include/linux/soundwire/sdw_registers.h

236

#define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0)

include/linux/soundwire/sdw_registers.h

237

#define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3)

include/linux/soundwire/sdw_registers.h

238

#define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6)

include/linux/soundwire/sdw_registers.h

259

#define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0)

include/linux/soundwire/sdw_registers.h

260

#define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2)

include/linux/soundwire/sdw_registers.h

263

#define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0)

include/linux/soundwire/sdw_registers.h

265

#define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0)

include/linux/soundwire/sdw_registers.h

294

#define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0)

include/linux/soundwire/sdw_registers.h

295

#define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8)

include/linux/soundwire/sdw_registers.h

297

#define SDW_DPN_HCTRL_HSTART GENMASK(7, 4)

include/linux/soundwire/sdw_registers.h

298

#define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0)

include/linux/soundwire/sdw_registers.h

336

(((fun) & GENMASK(2, 0)) << 22) | \

include/linux/soundwire/sdw_registers.h

338

(((ent) & GENMASK(5, 0)) << 7) | \

include/linux/soundwire/sdw_registers.h

339

(((ctl) & GENMASK(5, 4)) << 15) | \

include/linux/soundwire/sdw_registers.h

340

(((ctl) & GENMASK(3, 0)) << 3) | \

include/linux/soundwire/sdw_registers.h

341

(((ch) & GENMASK(5, 3)) << 12) | \

include/linux/soundwire/sdw_registers.h

342

((ch) & GENMASK(2, 0)))

include/linux/soundwire/sdw_registers.h

344

#define SDW_SDCA_CTL_FUNC(reg) FIELD_GET(GENMASK(24, 22), (reg))

include/linux/soundwire/sdw_registers.h

346

FIELD_GET(GENMASK(12, 7), (reg)))

include/linux/soundwire/sdw_registers.h

347

#define SDW_SDCA_CTL_CSEL(reg) ((FIELD_GET(GENMASK(20, 19), (reg)) << 4) | \

include/linux/soundwire/sdw_registers.h

348

FIELD_GET(GENMASK(6, 3), (reg)))

include/linux/soundwire/sdw_registers.h

349

#define SDW_SDCA_CTL_CNUM(reg) ((FIELD_GET(GENMASK(17, 15), (reg)) << 3) | \

include/linux/soundwire/sdw_registers.h

350

FIELD_GET(GENMASK(2, 0), (reg)))

include/linux/soundwire/sdw_registers.h

356

#define SDW_SDCA_VALID_CTL(reg) (((reg) & (GENMASK(31, 25) | BIT(18) | BIT(13))) == BIT(30))

include/linux/soundwire/sdw_registers.h

54

#define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)

include/linux/soundwire/sdw_registers.h

56

#define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)

include/linux/soundwire/sdw_registers.h

74

#define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)

include/linux/soundwire/sdw_registers.h

78

#define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)

include/linux/soundwire/sdw_registers.h

81

#define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)

include/linux/spi/sh_msiof.h

29

#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */

include/linux/spi/sh_msiof.h

35

#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */

include/linux/spi/sh_msiof.h

36

#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */

include/linux/spi/sh_msiof.h

37

#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */

include/linux/spi/sh_msiof.h

41

#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */

include/linux/spi/sh_msiof.h

45

#define SIMDR2_GRP GENMASK(31, 30) /* Group Count */

include/linux/spi/sh_msiof.h

46

#define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */

include/linux/spi/sh_msiof.h

47

#define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */

include/linux/spi/sh_msiof.h

48

#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */

include/linux/spi/sh_msiof.h

51

#define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */

include/linux/spi/sh_msiof.h

52

#define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */

include/linux/spi/sh_msiof.h

55

#define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */

include/linux/spi/sh_msiof.h

56

#define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */

include/linux/spi/sh_msiof.h

59

#define SICTR_TSCKIZ GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */

include/linux/spi/sh_msiof.h

62

#define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */

include/linux/spi/sh_msiof.h

67

#define SICTR_TXDIZ GENMASK(23, 22) /* Pin Output When TX is Disabled */

include/linux/spi/sh_msiof.h

79

#define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */

include/linux/spi/sh_msiof.h

88

#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */

include/linux/spi/sh_msiof.h

89

#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */

include/linux/spi/sh_msiof.h

98

#define SIFCTR_RFUA GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */

include/linux/spi/spi.h

610

#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)

include/linux/string_helpers.h

44

#define UNESCAPE_ALL_MASK GENMASK(3, 0)

include/linux/string_helpers.h

76

#define ESCAPE_ALL_MASK GENMASK(8, 0)

include/linux/turris-omnia-mcu-interface.h

101

OMNIA_STS_MCU_TYPE_MASK = GENMASK(1, 0),

include/linux/turris-omnia-mcu-interface.h

116

OMNIA_STS_BUTTON_COUNTER_MASK = GENMASK(15, 13),

include/linux/turris-omnia-mcu-interface.h

134

OMNIA_FEAT_LED_STATE_EXT_MASK = GENMASK(4, 3),

include/linux/turris-omnia-mcu-interface.h

157

OMNIA_FEAT_MCU_TYPE_MASK = GENMASK(17, 16),

include/linux/turris-omnia-mcu-interface.h

173

OMNIA_EXT_STS_LED_STATES_MASK = GENMASK(31, 12),

include/linux/turris-omnia-mcu-interface.h

219

OMNIA_INT_LED_STATES_MASK = GENMASK(31, 12),

include/linux/turris-omnia-mcu-interface.h

243

OMNIA_CMD_LED_MODE_LED_MASK = GENMASK(3, 0),

include/linux/turris-omnia-mcu-interface.h

250

OMNIA_CMD_LED_STATE_LED_MASK = GENMASK(3, 0),

include/linux/turris-omnia-mcu-interface.h

262

OMNIA_CMD_xET_USB_OVC_PROT_PORT_MASK = GENMASK(3, 0),

include/linux/usb/pd.h

307

#define PDO_EPR_AVS_APDO_PEAK_CURRENT GENMASK(27, 26)

include/linux/usb/pd.h

314

#define PDO_EPR_AVS_APDO_MAX_VOLT GENMASK(25, 17) /* 100mV unit */

include/linux/usb/pd.h

315

#define PDO_EPR_AVS_APDO_MIN_VOLT GENMASK(15, 8) /* 100mV unit */

include/linux/usb/pd.h

316

#define PDO_EPR_AVS_APDO_PDP GENMASK(7, 0) /* 1W unit */

include/linux/usb/pd.h

322

#define PDO_SPR_AVS_APDO_PEAK_CURRENT GENMASK(27, 26)

include/linux/usb/pd.h

329

#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR GENMASK(19, 10) /* 10mA unit */

include/linux/usb/pd.h

330

#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR GENMASK(9, 0) /* 10mA unit */

include/linux/usb/pd.h

498

#define EUDO_USB_MODE_MASK GENMASK(30, 28)

include/linux/usb/pd.h

505

#define EUDO_CABLE_SPEED_MASK GENMASK(23, 21)

include/linux/usb/pd.h

511

#define EUDO_CABLE_TYPE_MASK GENMASK(20, 19)

include/linux/usb/pd.h

517

#define EUDO_CABLE_CURRENT_MASK GENMASK(18, 17)

include/linux/usb/pd_vdo.h

146

#define IDH_DFP_MASK GENMASK(25, 23)

include/linux/usb/pd_vdo.h

147

#define IDH_CONN_MASK GENMASK(22, 21)

include/linux/usb/pd_vdo.h

192

#define PD_VDO_UFP_DEVCAP(vdo) FIELD_GET(GENMASK(27, 24), vdo)

include/linux/usb/pd_vdo.h

251

#define PD_VDO_DFP_HOSTCAP(vdo) FIELD_GET(GENMASK(26, 24), vdo)

include/linux/usb/tcpci.h

132

#define TCPC_MSG_HDR_INFO_REV GENMASK(2, 1)

include/linux/usb/tcpci.h

151

#define TCPC_TRANSMIT_RETRY GENMASK(5, 4)

include/linux/usb/tcpci.h

152

#define TCPC_TRANSMIT_TYPE GENMASK(2, 0)

include/linux/usb/tcpci.h

66

#define TCPC_ROLE_CTRL_RP_VAL GENMASK(5, 4)

include/linux/usb/tcpci.h

70

#define TCPC_ROLE_CTRL_CC2 GENMASK(3, 2)

include/linux/usb/tcpci.h

71

#define TCPC_ROLE_CTRL_CC1 GENMASK(1, 0)

include/linux/usb/tcpci.h

92

#define TCPC_CC_STATUS_CC2 GENMASK(3, 2)

include/linux/usb/tcpci.h

93

#define TCPC_CC_STATUS_CC1 GENMASK(1, 0)

include/linux/usb/typec_dp.h

111

#define DP_CONF_SIGNALLING_MASK GENMASK(5, 2)

include/linux/usb/typec_dp.h

117

#define DP_CONF_PIN_ASSIGNEMENT_MASK GENMASK(15, 8)

include/linux/usb/typec_dp.h

121

#define DP_CONF_GET_PIN_ASSIGN(_conf_) FIELD_GET(GENMASK(15, 8), _conf_)

include/linux/usb/typec_dp.h

123

#define DP_CONF_CABLE_TYPE_MASK GENMASK(29, 28)

include/linux/usb/typec_dp.h

72

#define DP_CAP_DP_SIGNALLING(_cap_) FIELD_GET(GENMASK(5, 2), _cap_)

include/linux/usb/typec_dp.h

78

#define DP_CAP_DFP_D_PIN_ASSIGN(_cap_) FIELD_GET(GENMASK(15, 8), _cap_)

include/linux/usb/typec_dp.h

79

#define DP_CAP_UFP_D_PIN_ASSIGN(_cap_) FIELD_GET(GENMASK(23, 16), _cap_)

include/linux/usb/typec_dp.h

86

#define DP_CAP_CABLE_TYPE(_cap_) FIELD_GET(GENMASK(29, 28), _cap_)

include/linux/usb/typec_tbt.h

39

#define TBT_CABLE_SPEED(_vdo_) FIELD_GET(GENMASK(18, 16), _vdo_)

include/linux/usb/typec_tbt.h

43

#define TBT_CABLE_ROUNDED_SUPPORT(_vdo_) FIELD_GET(GENMASK(20, 19), _vdo_)

include/linux/usb/typec_tbt.h

53

#define TBT_SET_CABLE_SPEED(_s_) (((_s_) & GENMASK(2, 0)) << 16)

include/linux/usb/typec_tbt.h

54

#define TBT_SET_CABLE_ROUNDED(_g_) (((_g_) & GENMASK(1, 0)) << 19)

include/media/drv-intf/cx25840.h

100

#define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)

include/media/drv-intf/cx25840.h

103

#define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)

include/media/drv-intf/cx25840.h

107

#define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)

include/media/drv-intf/cx25840.h

112

#define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)

include/media/drv-intf/cx25840.h

117

#define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)

include/media/drv-intf/cx25840.h

122

#define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)

include/media/drv-intf/cx25840.h

127

#define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)

include/media/drv-intf/cx25840.h

132

#define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)

include/media/drv-intf/cx25840.h

137

#define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)

include/media/drv-intf/cx25840.h

142

#define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)

include/media/drv-intf/cx25840.h

145

#define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)

include/media/drv-intf/cx25840.h

148

#define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)

include/media/drv-intf/cx25840.h

153

#define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)

include/media/drv-intf/cx25840.h

158

#define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)

include/media/v4l2-cci.h

34

#define CCI_REG_ADDR_MASK GENMASK(15, 0)

include/media/v4l2-cci.h

36

#define CCI_REG_WIDTH_MASK GENMASK(19, 16)

include/media/v4l2-cci.h

41

#define CCI_REG_PRIVATE_MASK GENMASK(31U, CCI_REG_PRIVATE_SHIFT)

include/net/flow_dissector.h

342

#define FLOW_DIS_CFM_MDL_MASK GENMASK(7, 5)

include/net/ip_tunnels.h

103

GENMASK((sizeof_field(struct ip_tunnel_info, \

include/net/libeth/xdp.h

304

LIBETH_XDP_TX_LEN = GENMASK(15, 0),

include/net/libeth/xdp.h

313

LIBETH_XDP_TX_FLAGS = GENMASK(31, 16),

include/net/mctp.h

33

#define MCTP_HDR_FLAGS GENMASK(5, 3)

include/net/mctp.h

35

#define MCTP_HDR_SEQ_MASK GENMASK(1, 0)

include/net/mctp.h

37

#define MCTP_HDR_TAG_MASK GENMASK(2, 0)

include/net/pfcp.h

29

#define PFCP_VERSION_MASK GENMASK(4, 0)

include/net/psp/types.h

25

#define PSP_SPI_KEY_ID GENMASK(30, 0)

include/net/psp/types.h

28

#define PSPHDR_CRYPT_OFFSET GENMASK(5, 0)

include/net/psp/types.h

32

#define PSPHDR_VERFL_VERSION GENMASK(5, 2)

include/rdma/ib_verbs.h

1299

IB_QP_ATTR_STANDARD_BITS = GENMASK(20, 0),

include/rdma/iba.h

120

GENMASK(7 - (bit_offset), 7 - (bit_offset) - (num_bits - 1)), \

include/rdma/iba.h

127

GENMASK(15 - (((byte_offset) % 2) * 8), \

include/rdma/iba.h

133

GENMASK(31 - (((byte_offset) % 4) * 8), \

include/rdma/uverbs_ioctl.h

131

UVERBS_API_ATTR_KEY_MASK = GENMASK(UVERBS_API_ATTR_KEY_BITS - 1, 0),

include/rdma/uverbs_ioctl.h

143

UVERBS_API_METHOD_KEY_MASK = GENMASK(

include/rdma/uverbs_ioctl.h

153

UVERBS_API_OBJ_KEY_MASK = GENMASK(31, UVERBS_API_OBJ_KEY_SHIFT),

include/soc/at91/atmel-sfr.h

37

#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)

include/soc/at91/atmel-sfr.h

41

#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)

include/soc/at91/atmel-sfr.h

49

#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)

include/soc/fsl/qman.h

197

#define QM_SG_LEN_MASK GENMASK(29, 0)

include/soc/fsl/qman.h

198

#define QM_SG_OFF_MASK GENMASK(12, 0)

include/soc/fsl/qman.h

271

#define QM_FQID_MASK GENMASK(23, 0)

include/soc/fsl/qman.h

388

#define QM_FQD_WQ_MASK GENMASK(2, 0)

include/soc/fsl/qman.h

389

#define QM_FQD_TD_EXP_MASK GENMASK(4, 0)

include/soc/fsl/qman.h

391

#define QM_FQD_TD_MANT_MASK GENMASK(12, 5)

include/soc/fsl/qman.h

93

#define QM_FD_FORMAT_MASK GENMASK(31, 29)

include/soc/fsl/qman.h

95

#define QM_FD_OFF_MASK GENMASK(28, 20)

include/soc/fsl/qman.h

96

#define QM_FD_LEN_MASK GENMASK(19, 0)

include/soc/fsl/qman.h

97

#define QM_FD_LEN_BIG_MASK GENMASK(28, 0)

include/soc/mscc/ocelot.h

104

#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)

include/soc/mscc/ocelot_ana.h

100

#define ANA_PGID_PGID_PGID_M GENMASK(11, 0)

include/soc/mscc/ocelot_ana.h

101

#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))

include/soc/mscc/ocelot_ana.h

102

#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)

include/soc/mscc/ocelot_ana.h

103

#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)

include/soc/mscc/ocelot_ana.h

105

#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))

include/soc/mscc/ocelot_ana.h

106

#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)

include/soc/mscc/ocelot_ana.h

107

#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

108

#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

109

#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

112

#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))

include/soc/mscc/ocelot_ana.h

113

#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)

include/soc/mscc/ocelot_ana.h

114

#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)

include/soc/mscc/ocelot_ana.h

116

#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

117

#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

124

#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))

include/soc/mscc/ocelot_ana.h

125

#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)

include/soc/mscc/ocelot_ana.h

126

#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)

include/soc/mscc/ocelot_ana.h

127

#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))

include/soc/mscc/ocelot_ana.h

128

#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)

include/soc/mscc/ocelot_ana.h

129

#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)

include/soc/mscc/ocelot_ana.h

130

#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_ana.h

131

#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)

include/soc/mscc/ocelot_ana.h

141

#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))

include/soc/mscc/ocelot_ana.h

142

#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)

include/soc/mscc/ocelot_ana.h

143

#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

144

#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

145

#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

15

#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))

include/soc/mscc/ocelot_ana.h

156

#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))

include/soc/mscc/ocelot_ana.h

157

#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)

include/soc/mscc/ocelot_ana.h

159

#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))

include/soc/mscc/ocelot_ana.h

16

#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)

include/soc/mscc/ocelot_ana.h

160

#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)

include/soc/mscc/ocelot_ana.h

161

#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

162

#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

163

#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

165

#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))

include/soc/mscc/ocelot_ana.h

166

#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)

include/soc/mscc/ocelot_ana.h

167

#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)

include/soc/mscc/ocelot_ana.h

168

#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))

include/soc/mscc/ocelot_ana.h

169

#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)

include/soc/mscc/ocelot_ana.h

17

#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)

include/soc/mscc/ocelot_ana.h

170

#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)

include/soc/mscc/ocelot_ana.h

173

#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

174

#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

178

#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))

include/soc/mscc/ocelot_ana.h

179

#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)

include/soc/mscc/ocelot_ana.h

180

#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)

include/soc/mscc/ocelot_ana.h

181

#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))

include/soc/mscc/ocelot_ana.h

182

#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)

include/soc/mscc/ocelot_ana.h

184

#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))

include/soc/mscc/ocelot_ana.h

185

#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)

include/soc/mscc/ocelot_ana.h

186

#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)

include/soc/mscc/ocelot_ana.h

189

#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

19

#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))

include/soc/mscc/ocelot_ana.h

190

#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

192

#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))

include/soc/mscc/ocelot_ana.h

193

#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)

include/soc/mscc/ocelot_ana.h

194

#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)

include/soc/mscc/ocelot_ana.h

195

#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))

include/soc/mscc/ocelot_ana.h

196

#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)

include/soc/mscc/ocelot_ana.h

197

#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

199

#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))

include/soc/mscc/ocelot_ana.h

20

#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)

include/soc/mscc/ocelot_ana.h

200

#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)

include/soc/mscc/ocelot_ana.h

201

#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)

include/soc/mscc/ocelot_ana.h

205

#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))

include/soc/mscc/ocelot_ana.h

206

#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)

include/soc/mscc/ocelot_ana.h

208

#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))

include/soc/mscc/ocelot_ana.h

209

#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)

include/soc/mscc/ocelot_ana.h

210

#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

211

#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))

include/soc/mscc/ocelot_ana.h

212

#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)

include/soc/mscc/ocelot_ana.h

214

#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))

include/soc/mscc/ocelot_ana.h

215

#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)

include/soc/mscc/ocelot_ana.h

216

#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)

include/soc/mscc/ocelot_ana.h

220

#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))

include/soc/mscc/ocelot_ana.h

221

#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)

include/soc/mscc/ocelot_ana.h

222

#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)

include/soc/mscc/ocelot_ana.h

224

#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))

include/soc/mscc/ocelot_ana.h

225

#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)

include/soc/mscc/ocelot_ana.h

226

#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

227

#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

228

#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

236

#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))

include/soc/mscc/ocelot_ana.h

237

#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)

include/soc/mscc/ocelot_ana.h

238

#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)

include/soc/mscc/ocelot_ana.h

24

#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))

include/soc/mscc/ocelot_ana.h

240

#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))

include/soc/mscc/ocelot_ana.h

241

#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)

include/soc/mscc/ocelot_ana.h

242

#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)

include/soc/mscc/ocelot_ana.h

243

#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

244

#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

25

#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)

include/soc/mscc/ocelot_ana.h

250

#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

251

#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

254

#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

255

#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

256

#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))

include/soc/mscc/ocelot_ana.h

257

#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)

include/soc/mscc/ocelot_ana.h

258

#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

26

#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)

include/soc/mscc/ocelot_ana.h

260

#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))

include/soc/mscc/ocelot_ana.h

261

#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)

include/soc/mscc/ocelot_ana.h

262

#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)

include/soc/mscc/ocelot_ana.h

264

#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24))

include/soc/mscc/ocelot_ana.h

265

#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21))

include/soc/mscc/ocelot_ana.h

266

#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21)

include/soc/mscc/ocelot_ana.h

267

#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21)

include/soc/mscc/ocelot_ana.h

272

#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_ana.h

273

#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)

include/soc/mscc/ocelot_ana.h

278

#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

279

#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

28

#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

281

#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))

include/soc/mscc/ocelot_ana.h

282

#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)

include/soc/mscc/ocelot_ana.h

283

#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)

include/soc/mscc/ocelot_ana.h

29

#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

290

#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))

include/soc/mscc/ocelot_ana.h

291

#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)

include/soc/mscc/ocelot_ana.h

292

#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)

include/soc/mscc/ocelot_ana.h

296

#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))

include/soc/mscc/ocelot_ana.h

297

#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)

include/soc/mscc/ocelot_ana.h

298

#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

299

#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))

include/soc/mscc/ocelot_ana.h

300

#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)

include/soc/mscc/ocelot_ana.h

315

#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))

include/soc/mscc/ocelot_ana.h

316

#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)

include/soc/mscc/ocelot_ana.h

317

#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)

include/soc/mscc/ocelot_ana.h

32

#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))

include/soc/mscc/ocelot_ana.h

321

#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

322

#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

327

#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))

include/soc/mscc/ocelot_ana.h

328

#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)

include/soc/mscc/ocelot_ana.h

329

#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)

include/soc/mscc/ocelot_ana.h

33

#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)

include/soc/mscc/ocelot_ana.h

330

#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))

include/soc/mscc/ocelot_ana.h

331

#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)

include/soc/mscc/ocelot_ana.h

332

#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)

include/soc/mscc/ocelot_ana.h

333

#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

334

#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

339

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))

include/soc/mscc/ocelot_ana.h

34

#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)

include/soc/mscc/ocelot_ana.h

340

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)

include/soc/mscc/ocelot_ana.h

341

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)

include/soc/mscc/ocelot_ana.h

342

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))

include/soc/mscc/ocelot_ana.h

343

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)

include/soc/mscc/ocelot_ana.h

344

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

345

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

346

#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

350

#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))

include/soc/mscc/ocelot_ana.h

351

#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)

include/soc/mscc/ocelot_ana.h

352

#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)

include/soc/mscc/ocelot_ana.h

353

#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))

include/soc/mscc/ocelot_ana.h

354

#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)

include/soc/mscc/ocelot_ana.h

355

#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)

include/soc/mscc/ocelot_ana.h

357

#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))

include/soc/mscc/ocelot_ana.h

358

#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)

include/soc/mscc/ocelot_ana.h

359

#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

360

#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))

include/soc/mscc/ocelot_ana.h

361

#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)

include/soc/mscc/ocelot_ana.h

362

#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)

include/soc/mscc/ocelot_ana.h

363

#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))

include/soc/mscc/ocelot_ana.h

364

#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)

include/soc/mscc/ocelot_ana.h

365

#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)

include/soc/mscc/ocelot_ana.h

366

#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))

include/soc/mscc/ocelot_ana.h

367

#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)

include/soc/mscc/ocelot_ana.h

368

#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

369

#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))

include/soc/mscc/ocelot_ana.h

370

#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)

include/soc/mscc/ocelot_ana.h

371

#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

372

#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

373

#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

379

#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_ana.h

380

#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)

include/soc/mscc/ocelot_ana.h

395

#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_ana.h

396

#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)

include/soc/mscc/ocelot_ana.h

397

#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

398

#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

399

#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

40

#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))

include/soc/mscc/ocelot_ana.h

403

#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_ana.h

404

#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)

include/soc/mscc/ocelot_ana.h

405

#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

406

#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

407

#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

41

#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)

include/soc/mscc/ocelot_ana.h

411

#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_ana.h

412

#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)

include/soc/mscc/ocelot_ana.h

413

#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

414

#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

415

#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

42

#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

429

#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))

include/soc/mscc/ocelot_ana.h

430

#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)

include/soc/mscc/ocelot_ana.h

431

#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

440

#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))

include/soc/mscc/ocelot_ana.h

441

#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)

include/soc/mscc/ocelot_ana.h

442

#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)

include/soc/mscc/ocelot_ana.h

443

#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))

include/soc/mscc/ocelot_ana.h

444

#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)

include/soc/mscc/ocelot_ana.h

458

#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_ana.h

459

#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)

include/soc/mscc/ocelot_ana.h

463

#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))

include/soc/mscc/ocelot_ana.h

464

#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)

include/soc/mscc/ocelot_ana.h

465

#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

466

#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_ana.h

467

#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)

include/soc/mscc/ocelot_ana.h

474

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))

include/soc/mscc/ocelot_ana.h

475

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)

include/soc/mscc/ocelot_ana.h

476

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

477

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))

include/soc/mscc/ocelot_ana.h

478

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)

include/soc/mscc/ocelot_ana.h

479

#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)

include/soc/mscc/ocelot_ana.h

484

#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))

include/soc/mscc/ocelot_ana.h

485

#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)

include/soc/mscc/ocelot_ana.h

486

#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)

include/soc/mscc/ocelot_ana.h

487

#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))

include/soc/mscc/ocelot_ana.h

488

#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)

include/soc/mscc/ocelot_ana.h

489

#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)

include/soc/mscc/ocelot_ana.h

490

#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))

include/soc/mscc/ocelot_ana.h

491

#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)

include/soc/mscc/ocelot_ana.h

497

#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_ana.h

498

#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)

include/soc/mscc/ocelot_ana.h

499

#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

500

#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_ana.h

501

#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)

include/soc/mscc/ocelot_ana.h

512

#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))

include/soc/mscc/ocelot_ana.h

513

#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)

include/soc/mscc/ocelot_ana.h

514

#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)

include/soc/mscc/ocelot_ana.h

515

#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))

include/soc/mscc/ocelot_ana.h

516

#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)

include/soc/mscc/ocelot_ana.h

517

#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)

include/soc/mscc/ocelot_ana.h

518

#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))

include/soc/mscc/ocelot_ana.h

519

#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)

include/soc/mscc/ocelot_ana.h

520

#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)

include/soc/mscc/ocelot_ana.h

521

#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))

include/soc/mscc/ocelot_ana.h

522

#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)

include/soc/mscc/ocelot_ana.h

523

#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)

include/soc/mscc/ocelot_ana.h

524

#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))

include/soc/mscc/ocelot_ana.h

525

#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)

include/soc/mscc/ocelot_ana.h

526

#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)

include/soc/mscc/ocelot_ana.h

527

#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))

include/soc/mscc/ocelot_ana.h

528

#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)

include/soc/mscc/ocelot_ana.h

529

#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

530

#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))

include/soc/mscc/ocelot_ana.h

531

#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)

include/soc/mscc/ocelot_ana.h

532

#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)

include/soc/mscc/ocelot_ana.h

533

#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_ana.h

534

#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)

include/soc/mscc/ocelot_ana.h

535

#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

536

#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))

include/soc/mscc/ocelot_ana.h

537

#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)

include/soc/mscc/ocelot_ana.h

538

#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)

include/soc/mscc/ocelot_ana.h

539

#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_ana.h

540

#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)

include/soc/mscc/ocelot_ana.h

544

#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_ana.h

545

#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)

include/soc/mscc/ocelot_ana.h

546

#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

547

#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))

include/soc/mscc/ocelot_ana.h

548

#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)

include/soc/mscc/ocelot_ana.h

549

#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)

include/soc/mscc/ocelot_ana.h

550

#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_ana.h

551

#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)

include/soc/mscc/ocelot_ana.h

556

#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))

include/soc/mscc/ocelot_ana.h

557

#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)

include/soc/mscc/ocelot_ana.h

558

#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)

include/soc/mscc/ocelot_ana.h

559

#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))

include/soc/mscc/ocelot_ana.h

560

#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)

include/soc/mscc/ocelot_ana.h

561

#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

571

#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_ana.h

572

#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)

include/soc/mscc/ocelot_ana.h

573

#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_ana.h

574

#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_ana.h

575

#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)

include/soc/mscc/ocelot_ana.h

578

#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))

include/soc/mscc/ocelot_ana.h

579

#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)

include/soc/mscc/ocelot_ana.h

58

#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_ana.h

59

#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)

include/soc/mscc/ocelot_ana.h

590

#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))

include/soc/mscc/ocelot_ana.h

591

#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)

include/soc/mscc/ocelot_ana.h

592

#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

593

#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_ana.h

594

#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)

include/soc/mscc/ocelot_ana.h

598

#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))

include/soc/mscc/ocelot_ana.h

599

#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)

include/soc/mscc/ocelot_ana.h

60

#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

600

#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

601

#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_ana.h

602

#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)

include/soc/mscc/ocelot_ana.h

606

#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))

include/soc/mscc/ocelot_ana.h

607

#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)

include/soc/mscc/ocelot_ana.h

608

#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)

include/soc/mscc/ocelot_ana.h

609

#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))

include/soc/mscc/ocelot_ana.h

61

#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_ana.h

610

#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)

include/soc/mscc/ocelot_ana.h

611

#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)

include/soc/mscc/ocelot_ana.h

62

#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)

include/soc/mscc/ocelot_ana.h

626

#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))

include/soc/mscc/ocelot_ana.h

627

#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)

include/soc/mscc/ocelot_ana.h

628

#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)

include/soc/mscc/ocelot_ana.h

629

#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_ana.h

63

#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

630

#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)

include/soc/mscc/ocelot_ana.h

64

#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_ana.h

65

#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)

include/soc/mscc/ocelot_ana.h

67

#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))

include/soc/mscc/ocelot_ana.h

68

#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)

include/soc/mscc/ocelot_ana.h

69

#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)

include/soc/mscc/ocelot_ana.h

70

#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_ana.h

71

#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)

include/soc/mscc/ocelot_ana.h

72

#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_ana.h

73

#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_ana.h

74

#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)

include/soc/mscc/ocelot_ana.h

75

#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_ana.h

76

#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_ana.h

77

#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)

include/soc/mscc/ocelot_ana.h

81

#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))

include/soc/mscc/ocelot_ana.h

82

#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)

include/soc/mscc/ocelot_ana.h

83

#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)

include/soc/mscc/ocelot_ana.h

90

#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))

include/soc/mscc/ocelot_ana.h

91

#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)

include/soc/mscc/ocelot_ana.h

92

#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)

include/soc/mscc/ocelot_ana.h

99

#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))

include/soc/mscc/ocelot_dev.h

101

#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x) (((x) << 4) & GENMASK(11, 4))

include/soc/mscc/ocelot_dev.h

102

#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M GENMASK(11, 4)

include/soc/mscc/ocelot_dev.h

103

#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x) (((x) & GENMASK(11, 4)) >> 4)

include/soc/mscc/ocelot_dev.h

104

#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x) (((x) << 12) & GENMASK(13, 12))

include/soc/mscc/ocelot_dev.h

105

#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M GENMASK(13, 12)

include/soc/mscc/ocelot_dev.h

106

#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12)

include/soc/mscc/ocelot_dev.h

110

#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8))

include/soc/mscc/ocelot_dev.h

111

#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8)

include/soc/mscc/ocelot_dev.h

112

#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8)

include/soc/mscc/ocelot_dev.h

130

#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_dev.h

131

#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)

include/soc/mscc/ocelot_dev.h

132

#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_dev.h

137

#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_dev.h

138

#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)

include/soc/mscc/ocelot_dev.h

139

#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_dev.h

150

#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_dev.h

151

#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)

include/soc/mscc/ocelot_dev.h

152

#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_dev.h

157

#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))

include/soc/mscc/ocelot_dev.h

158

#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)

include/soc/mscc/ocelot_dev.h

159

#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)

include/soc/mscc/ocelot_dev.h

17

#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_dev.h

170

#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))

include/soc/mscc/ocelot_dev.h

171

#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)

include/soc/mscc/ocelot_dev.h

172

#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)

include/soc/mscc/ocelot_dev.h

18

#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)

include/soc/mscc/ocelot_dev.h

183

#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_dev.h

184

#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)

include/soc/mscc/ocelot_dev.h

185

#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_dev.h

194

#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))

include/soc/mscc/ocelot_dev.h

195

#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)

include/soc/mscc/ocelot_dev.h

196

#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)

include/soc/mscc/ocelot_dev.h

197

#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))

include/soc/mscc/ocelot_dev.h

198

#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)

include/soc/mscc/ocelot_dev.h

199

#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)

include/soc/mscc/ocelot_dev.h

201

#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_dev.h

202

#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)

include/soc/mscc/ocelot_dev.h

203

#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_dev.h

209

#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))

include/soc/mscc/ocelot_dev.h

210

#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)

include/soc/mscc/ocelot_dev.h

211

#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)

include/soc/mscc/ocelot_dev.h

27

#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))

include/soc/mscc/ocelot_dev.h

28

#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)

include/soc/mscc/ocelot_dev.h

29

#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)

include/soc/mscc/ocelot_dev.h

30

#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))

include/soc/mscc/ocelot_dev.h

31

#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)

include/soc/mscc/ocelot_dev.h

32

#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)

include/soc/mscc/ocelot_dev.h

33

#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))

include/soc/mscc/ocelot_dev.h

34

#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)

include/soc/mscc/ocelot_dev.h

35

#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)

include/soc/mscc/ocelot_dev.h

38

#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))

include/soc/mscc/ocelot_dev.h

39

#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)

include/soc/mscc/ocelot_dev.h

40

#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)

include/soc/mscc/ocelot_dev.h

41

#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_dev.h

42

#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)

include/soc/mscc/ocelot_dev.h

51

#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_dev.h

52

#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)

include/soc/mscc/ocelot_dev.h

53

#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_dev.h

62

#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))

include/soc/mscc/ocelot_dev.h

63

#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)

include/soc/mscc/ocelot_dev.h

64

#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)

include/soc/mscc/ocelot_dev.h

65

#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_dev.h

66

#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)

include/soc/mscc/ocelot_dev.h

67

#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_dev.h

68

#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_dev.h

69

#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)

include/soc/mscc/ocelot_dev.h

74

#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_dev.h

75

#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)

include/soc/mscc/ocelot_dev.h

76

#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_dev.h

79

#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))

include/soc/mscc/ocelot_dev.h

80

#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)

include/soc/mscc/ocelot_hsio.h

103

#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_hsio.h

104

#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)

include/soc/mscc/ocelot_hsio.h

105

#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

106

#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

107

#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

114

#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))

include/soc/mscc/ocelot_hsio.h

115

#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)

include/soc/mscc/ocelot_hsio.h

116

#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

131

#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_hsio.h

132

#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)

include/soc/mscc/ocelot_hsio.h

133

#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

140

#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))

include/soc/mscc/ocelot_hsio.h

141

#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)

include/soc/mscc/ocelot_hsio.h

142

#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)

include/soc/mscc/ocelot_hsio.h

149

#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))

include/soc/mscc/ocelot_hsio.h

150

#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)

include/soc/mscc/ocelot_hsio.h

151

#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)

include/soc/mscc/ocelot_hsio.h

152

#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))

include/soc/mscc/ocelot_hsio.h

153

#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)

include/soc/mscc/ocelot_hsio.h

154

#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)

include/soc/mscc/ocelot_hsio.h

166

#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

167

#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

169

#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_hsio.h

170

#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)

include/soc/mscc/ocelot_hsio.h

171

#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

172

#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_hsio.h

173

#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)

include/soc/mscc/ocelot_hsio.h

175

#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_hsio.h

176

#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)

include/soc/mscc/ocelot_hsio.h

177

#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

178

#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_hsio.h

179

#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)

include/soc/mscc/ocelot_hsio.h

182

#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))

include/soc/mscc/ocelot_hsio.h

183

#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)

include/soc/mscc/ocelot_hsio.h

184

#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)

include/soc/mscc/ocelot_hsio.h

186

#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))

include/soc/mscc/ocelot_hsio.h

187

#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)

include/soc/mscc/ocelot_hsio.h

188

#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

189

#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_hsio.h

190

#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)

include/soc/mscc/ocelot_hsio.h

191

#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

194

#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

195

#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

201

#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))

include/soc/mscc/ocelot_hsio.h

202

#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)

include/soc/mscc/ocelot_hsio.h

203

#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

206

#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))

include/soc/mscc/ocelot_hsio.h

207

#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)

include/soc/mscc/ocelot_hsio.h

208

#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)

include/soc/mscc/ocelot_hsio.h

209

#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))

include/soc/mscc/ocelot_hsio.h

210

#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)

include/soc/mscc/ocelot_hsio.h

211

#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

212

#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))

include/soc/mscc/ocelot_hsio.h

213

#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)

include/soc/mscc/ocelot_hsio.h

214

#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

215

#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))

include/soc/mscc/ocelot_hsio.h

216

#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)

include/soc/mscc/ocelot_hsio.h

217

#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

222

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))

include/soc/mscc/ocelot_hsio.h

223

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)

include/soc/mscc/ocelot_hsio.h

224

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)

include/soc/mscc/ocelot_hsio.h

225

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))

include/soc/mscc/ocelot_hsio.h

226

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)

include/soc/mscc/ocelot_hsio.h

227

#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

228

#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_hsio.h

229

#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)

include/soc/mscc/ocelot_hsio.h

231

#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

232

#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

233

#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

238

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_hsio.h

239

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)

include/soc/mscc/ocelot_hsio.h

240

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

241

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_hsio.h

242

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)

include/soc/mscc/ocelot_hsio.h

246

#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))

include/soc/mscc/ocelot_hsio.h

247

#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)

include/soc/mscc/ocelot_hsio.h

248

#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)

include/soc/mscc/ocelot_hsio.h

249

#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))

include/soc/mscc/ocelot_hsio.h

250

#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)

include/soc/mscc/ocelot_hsio.h

251

#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

253

#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_hsio.h

254

#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)

include/soc/mscc/ocelot_hsio.h

258

#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_hsio.h

259

#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)

include/soc/mscc/ocelot_hsio.h

263

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

264

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

265

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

266

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))

include/soc/mscc/ocelot_hsio.h

267

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)

include/soc/mscc/ocelot_hsio.h

268

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

273

#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))

include/soc/mscc/ocelot_hsio.h

274

#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)

include/soc/mscc/ocelot_hsio.h

275

#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

276

#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))

include/soc/mscc/ocelot_hsio.h

277

#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)

include/soc/mscc/ocelot_hsio.h

278

#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)

include/soc/mscc/ocelot_hsio.h

279

#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))

include/soc/mscc/ocelot_hsio.h

280

#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)

include/soc/mscc/ocelot_hsio.h

281

#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

282

#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))

include/soc/mscc/ocelot_hsio.h

283

#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)

include/soc/mscc/ocelot_hsio.h

284

#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)

include/soc/mscc/ocelot_hsio.h

286

#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))

include/soc/mscc/ocelot_hsio.h

287

#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)

include/soc/mscc/ocelot_hsio.h

288

#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

292

#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))

include/soc/mscc/ocelot_hsio.h

293

#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)

include/soc/mscc/ocelot_hsio.h

294

#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)

include/soc/mscc/ocelot_hsio.h

295

#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))

include/soc/mscc/ocelot_hsio.h

296

#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)

include/soc/mscc/ocelot_hsio.h

297

#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)

include/soc/mscc/ocelot_hsio.h

304

#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_hsio.h

305

#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)

include/soc/mscc/ocelot_hsio.h

306

#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

307

#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))

include/soc/mscc/ocelot_hsio.h

308

#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)

include/soc/mscc/ocelot_hsio.h

309

#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

310

#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_hsio.h

311

#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)

include/soc/mscc/ocelot_hsio.h

313

#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))

include/soc/mscc/ocelot_hsio.h

314

#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)

include/soc/mscc/ocelot_hsio.h

315

#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)

include/soc/mscc/ocelot_hsio.h

316

#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))

include/soc/mscc/ocelot_hsio.h

317

#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)

include/soc/mscc/ocelot_hsio.h

318

#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

319

#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))

include/soc/mscc/ocelot_hsio.h

320

#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)

include/soc/mscc/ocelot_hsio.h

321

#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)

include/soc/mscc/ocelot_hsio.h

324

#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

325

#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

326

#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

327

#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_hsio.h

328

#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)

include/soc/mscc/ocelot_hsio.h

334

#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))

include/soc/mscc/ocelot_hsio.h

335

#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)

include/soc/mscc/ocelot_hsio.h

336

#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

347

#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))

include/soc/mscc/ocelot_hsio.h

348

#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)

include/soc/mscc/ocelot_hsio.h

349

#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

360

#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_hsio.h

361

#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)

include/soc/mscc/ocelot_hsio.h

362

#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

371

#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

372

#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

376

#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))

include/soc/mscc/ocelot_hsio.h

377

#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)

include/soc/mscc/ocelot_hsio.h

378

#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)

include/soc/mscc/ocelot_hsio.h

379

#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))

include/soc/mscc/ocelot_hsio.h

380

#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)

include/soc/mscc/ocelot_hsio.h

381

#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

387

#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))

include/soc/mscc/ocelot_hsio.h

388

#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)

include/soc/mscc/ocelot_hsio.h

389

#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

390

#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

391

#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

392

#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

398

#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))

include/soc/mscc/ocelot_hsio.h

399

#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)

include/soc/mscc/ocelot_hsio.h

400

#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

401

#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

402

#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

403

#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

410

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))

include/soc/mscc/ocelot_hsio.h

411

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)

include/soc/mscc/ocelot_hsio.h

412

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

413

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_hsio.h

414

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)

include/soc/mscc/ocelot_hsio.h

415

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

416

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

417

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

419

#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))

include/soc/mscc/ocelot_hsio.h

420

#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)

include/soc/mscc/ocelot_hsio.h

421

#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)

include/soc/mscc/ocelot_hsio.h

443

#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))

include/soc/mscc/ocelot_hsio.h

444

#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)

include/soc/mscc/ocelot_hsio.h

446

#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))

include/soc/mscc/ocelot_hsio.h

447

#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)

include/soc/mscc/ocelot_hsio.h

448

#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

451

#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))

include/soc/mscc/ocelot_hsio.h

452

#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)

include/soc/mscc/ocelot_hsio.h

453

#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)

include/soc/mscc/ocelot_hsio.h

454

#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_hsio.h

455

#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)

include/soc/mscc/ocelot_hsio.h

459

#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))

include/soc/mscc/ocelot_hsio.h

460

#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)

include/soc/mscc/ocelot_hsio.h

461

#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)

include/soc/mscc/ocelot_hsio.h

462

#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))

include/soc/mscc/ocelot_hsio.h

463

#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)

include/soc/mscc/ocelot_hsio.h

464

#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

470

#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))

include/soc/mscc/ocelot_hsio.h

471

#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)

include/soc/mscc/ocelot_hsio.h

472

#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

473

#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

474

#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

475

#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

481

#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))

include/soc/mscc/ocelot_hsio.h

482

#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)

include/soc/mscc/ocelot_hsio.h

483

#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

484

#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

485

#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

486

#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

493

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))

include/soc/mscc/ocelot_hsio.h

494

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)

include/soc/mscc/ocelot_hsio.h

495

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

496

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_hsio.h

497

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)

include/soc/mscc/ocelot_hsio.h

498

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

499

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

500

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

502

#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))

include/soc/mscc/ocelot_hsio.h

503

#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)

include/soc/mscc/ocelot_hsio.h

504

#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

505

#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))

include/soc/mscc/ocelot_hsio.h

506

#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)

include/soc/mscc/ocelot_hsio.h

507

#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)

include/soc/mscc/ocelot_hsio.h

519

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))

include/soc/mscc/ocelot_hsio.h

520

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)

include/soc/mscc/ocelot_hsio.h

521

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)

include/soc/mscc/ocelot_hsio.h

522

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))

include/soc/mscc/ocelot_hsio.h

523

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)

include/soc/mscc/ocelot_hsio.h

524

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

525

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))

include/soc/mscc/ocelot_hsio.h

526

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)

include/soc/mscc/ocelot_hsio.h

527

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

528

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_hsio.h

529

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)

include/soc/mscc/ocelot_hsio.h

530

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

531

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

532

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

545

#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))

include/soc/mscc/ocelot_hsio.h

546

#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)

include/soc/mscc/ocelot_hsio.h

547

#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

548

#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))

include/soc/mscc/ocelot_hsio.h

549

#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)

include/soc/mscc/ocelot_hsio.h

550

#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)

include/soc/mscc/ocelot_hsio.h

551

#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))

include/soc/mscc/ocelot_hsio.h

552

#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)

include/soc/mscc/ocelot_hsio.h

553

#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

554

#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))

include/soc/mscc/ocelot_hsio.h

555

#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)

include/soc/mscc/ocelot_hsio.h

556

#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)

include/soc/mscc/ocelot_hsio.h

558

#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))

include/soc/mscc/ocelot_hsio.h

559

#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)

include/soc/mscc/ocelot_hsio.h

560

#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

563

#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))

include/soc/mscc/ocelot_hsio.h

564

#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)

include/soc/mscc/ocelot_hsio.h

565

#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)

include/soc/mscc/ocelot_hsio.h

567

#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))

include/soc/mscc/ocelot_hsio.h

568

#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)

include/soc/mscc/ocelot_hsio.h

569

#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)

include/soc/mscc/ocelot_hsio.h

570

#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))

include/soc/mscc/ocelot_hsio.h

571

#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)

include/soc/mscc/ocelot_hsio.h

572

#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)

include/soc/mscc/ocelot_hsio.h

573

#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))

include/soc/mscc/ocelot_hsio.h

574

#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)

include/soc/mscc/ocelot_hsio.h

575

#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

576

#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))

include/soc/mscc/ocelot_hsio.h

577

#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)

include/soc/mscc/ocelot_hsio.h

578

#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)

include/soc/mscc/ocelot_hsio.h

579

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))

include/soc/mscc/ocelot_hsio.h

580

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)

include/soc/mscc/ocelot_hsio.h

581

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)

include/soc/mscc/ocelot_hsio.h

582

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))

include/soc/mscc/ocelot_hsio.h

583

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)

include/soc/mscc/ocelot_hsio.h

584

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)

include/soc/mscc/ocelot_hsio.h

585

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))

include/soc/mscc/ocelot_hsio.h

586

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)

include/soc/mscc/ocelot_hsio.h

587

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)

include/soc/mscc/ocelot_hsio.h

588

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))

include/soc/mscc/ocelot_hsio.h

589

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)

include/soc/mscc/ocelot_hsio.h

590

#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)

include/soc/mscc/ocelot_hsio.h

599

#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))

include/soc/mscc/ocelot_hsio.h

600

#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)

include/soc/mscc/ocelot_hsio.h

601

#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)

include/soc/mscc/ocelot_hsio.h

602

#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))

include/soc/mscc/ocelot_hsio.h

603

#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)

include/soc/mscc/ocelot_hsio.h

604

#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)

include/soc/mscc/ocelot_hsio.h

605

#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))

include/soc/mscc/ocelot_hsio.h

606

#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)

include/soc/mscc/ocelot_hsio.h

607

#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

617

#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))

include/soc/mscc/ocelot_hsio.h

618

#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)

include/soc/mscc/ocelot_hsio.h

619

#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)

include/soc/mscc/ocelot_hsio.h

620

#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))

include/soc/mscc/ocelot_hsio.h

621

#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)

include/soc/mscc/ocelot_hsio.h

622

#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)

include/soc/mscc/ocelot_hsio.h

623

#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))

include/soc/mscc/ocelot_hsio.h

624

#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)

include/soc/mscc/ocelot_hsio.h

625

#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)

include/soc/mscc/ocelot_hsio.h

626

#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))

include/soc/mscc/ocelot_hsio.h

627

#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)

include/soc/mscc/ocelot_hsio.h

628

#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

629

#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))

include/soc/mscc/ocelot_hsio.h

630

#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)

include/soc/mscc/ocelot_hsio.h

631

#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)

include/soc/mscc/ocelot_hsio.h

632

#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))

include/soc/mscc/ocelot_hsio.h

633

#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)

include/soc/mscc/ocelot_hsio.h

634

#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)

include/soc/mscc/ocelot_hsio.h

635

#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))

include/soc/mscc/ocelot_hsio.h

636

#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)

include/soc/mscc/ocelot_hsio.h

637

#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)

include/soc/mscc/ocelot_hsio.h

638

#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))

include/soc/mscc/ocelot_hsio.h

639

#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)

include/soc/mscc/ocelot_hsio.h

641

#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))

include/soc/mscc/ocelot_hsio.h

642

#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)

include/soc/mscc/ocelot_hsio.h

643

#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

644

#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_hsio.h

645

#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)

include/soc/mscc/ocelot_hsio.h

646

#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_hsio.h

647

#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_hsio.h

648

#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)

include/soc/mscc/ocelot_hsio.h

649

#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

650

#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

651

#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

653

#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))

include/soc/mscc/ocelot_hsio.h

654

#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)

include/soc/mscc/ocelot_hsio.h

655

#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

656

#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_hsio.h

657

#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)

include/soc/mscc/ocelot_hsio.h

658

#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_hsio.h

659

#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_hsio.h

660

#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)

include/soc/mscc/ocelot_hsio.h

661

#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

662

#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

663

#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

665

#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))

include/soc/mscc/ocelot_hsio.h

666

#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)

include/soc/mscc/ocelot_hsio.h

667

#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

668

#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_hsio.h

669

#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)

include/soc/mscc/ocelot_hsio.h

670

#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_hsio.h

671

#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_hsio.h

672

#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)

include/soc/mscc/ocelot_hsio.h

673

#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

674

#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

675

#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

680

#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))

include/soc/mscc/ocelot_hsio.h

681

#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)

include/soc/mscc/ocelot_hsio.h

682

#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)

include/soc/mscc/ocelot_hsio.h

683

#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))

include/soc/mscc/ocelot_hsio.h

684

#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)

include/soc/mscc/ocelot_hsio.h

685

#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

688

#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))

include/soc/mscc/ocelot_hsio.h

689

#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)

include/soc/mscc/ocelot_hsio.h

690

#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)

include/soc/mscc/ocelot_hsio.h

694

#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_hsio.h

695

#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)

include/soc/mscc/ocelot_hsio.h

696

#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

697

#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_hsio.h

698

#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)

include/soc/mscc/ocelot_hsio.h

700

#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_hsio.h

701

#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)

include/soc/mscc/ocelot_hsio.h

702

#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

703

#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

704

#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

709

#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))

include/soc/mscc/ocelot_hsio.h

710

#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)

include/soc/mscc/ocelot_hsio.h

711

#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)

include/soc/mscc/ocelot_hsio.h

723

#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))

include/soc/mscc/ocelot_hsio.h

724

#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)

include/soc/mscc/ocelot_hsio.h

725

#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)

include/soc/mscc/ocelot_hsio.h

733

#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_hsio.h

734

#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)

include/soc/mscc/ocelot_hsio.h

736

#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))

include/soc/mscc/ocelot_hsio.h

737

#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)

include/soc/mscc/ocelot_hsio.h

738

#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

741

#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))

include/soc/mscc/ocelot_hsio.h

742

#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)

include/soc/mscc/ocelot_hsio.h

743

#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

758

#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_hsio.h

759

#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)

include/soc/mscc/ocelot_hsio.h

760

#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

761

#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_hsio.h

762

#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_hsio.h

774

#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))

include/soc/mscc/ocelot_hsio.h

775

#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)

include/soc/mscc/ocelot_hsio.h

776

#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

777

#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))

include/soc/mscc/ocelot_hsio.h

778

#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)

include/soc/mscc/ocelot_hsio.h

779

#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)

include/soc/mscc/ocelot_hsio.h

780

#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))

include/soc/mscc/ocelot_hsio.h

781

#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)

include/soc/mscc/ocelot_hsio.h

782

#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)

include/soc/mscc/ocelot_hsio.h

783

#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_hsio.h

784

#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)

include/soc/mscc/ocelot_hsio.h

793

#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

794

#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

796

#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))

include/soc/mscc/ocelot_hsio.h

797

#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)

include/soc/mscc/ocelot_hsio.h

798

#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)

include/soc/mscc/ocelot_hsio.h

799

#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))

include/soc/mscc/ocelot_hsio.h

800

#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)

include/soc/mscc/ocelot_hsio.h

801

#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)

include/soc/mscc/ocelot_hsio.h

802

#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))

include/soc/mscc/ocelot_hsio.h

803

#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)

include/soc/mscc/ocelot_hsio.h

804

#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)

include/soc/mscc/ocelot_hsio.h

805

#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))

include/soc/mscc/ocelot_hsio.h

806

#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)

include/soc/mscc/ocelot_hsio.h

807

#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)

include/soc/mscc/ocelot_hsio.h

808

#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))

include/soc/mscc/ocelot_hsio.h

809

#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)

include/soc/mscc/ocelot_hsio.h

810

#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)

include/soc/mscc/ocelot_hsio.h

811

#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))

include/soc/mscc/ocelot_hsio.h

812

#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)

include/soc/mscc/ocelot_hsio.h

816

#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))

include/soc/mscc/ocelot_hsio.h

817

#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)

include/soc/mscc/ocelot_hsio.h

832

#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))

include/soc/mscc/ocelot_hsio.h

833

#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)

include/soc/mscc/ocelot_hsio.h

834

#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

837

#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))

include/soc/mscc/ocelot_hsio.h

838

#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)

include/soc/mscc/ocelot_hsio.h

839

#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)

include/soc/mscc/ocelot_hsio.h

849

#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_hsio.h

850

#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)

include/soc/mscc/ocelot_hsio.h

851

#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_hsio.h

852

#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

853

#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

856

#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_hsio.h

857

#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)

include/soc/mscc/ocelot_hsio.h

90

#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))

include/soc/mscc/ocelot_hsio.h

91

#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)

include/soc/mscc/ocelot_hsio.h

92

#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)

include/soc/mscc/ocelot_hsio.h

93

#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))

include/soc/mscc/ocelot_hsio.h

94

#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)

include/soc/mscc/ocelot_hsio.h

95

#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)

include/soc/mscc/ocelot_hsio.h

96

#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))

include/soc/mscc/ocelot_hsio.h

97

#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)

include/soc/mscc/ocelot_hsio.h

98

#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

101

#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_qsys.h

102

#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)

include/soc/mscc/ocelot_qsys.h

103

#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))

include/soc/mscc/ocelot_qsys.h

104

#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)

include/soc/mscc/ocelot_qsys.h

105

#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

106

#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))

include/soc/mscc/ocelot_qsys.h

107

#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)

include/soc/mscc/ocelot_qsys.h

108

#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)

include/soc/mscc/ocelot_qsys.h

109

#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_qsys.h

110

#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)

include/soc/mscc/ocelot_qsys.h

111

#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

115

#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))

include/soc/mscc/ocelot_qsys.h

116

#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)

include/soc/mscc/ocelot_qsys.h

117

#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)

include/soc/mscc/ocelot_qsys.h

118

#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_qsys.h

119

#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)

include/soc/mscc/ocelot_qsys.h

123

#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))

include/soc/mscc/ocelot_qsys.h

124

#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)

include/soc/mscc/ocelot_qsys.h

125

#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)

include/soc/mscc/ocelot_qsys.h

126

#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))

include/soc/mscc/ocelot_qsys.h

127

#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)

include/soc/mscc/ocelot_qsys.h

128

#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)

include/soc/mscc/ocelot_qsys.h

133

#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))

include/soc/mscc/ocelot_qsys.h

134

#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)

include/soc/mscc/ocelot_qsys.h

135

#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)

include/soc/mscc/ocelot_qsys.h

138

#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))

include/soc/mscc/ocelot_qsys.h

139

#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)

include/soc/mscc/ocelot_qsys.h

140

#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)

include/soc/mscc/ocelot_qsys.h

149

#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))

include/soc/mscc/ocelot_qsys.h

150

#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)

include/soc/mscc/ocelot_qsys.h

151

#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)

include/soc/mscc/ocelot_qsys.h

152

#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))

include/soc/mscc/ocelot_qsys.h

153

#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)

include/soc/mscc/ocelot_qsys.h

154

#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)

include/soc/mscc/ocelot_qsys.h

155

#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))

include/soc/mscc/ocelot_qsys.h

156

#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)

include/soc/mscc/ocelot_qsys.h

157

#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)

include/soc/mscc/ocelot_qsys.h

158

#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))

include/soc/mscc/ocelot_qsys.h

159

#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)

include/soc/mscc/ocelot_qsys.h

160

#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)

include/soc/mscc/ocelot_qsys.h

165

#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))

include/soc/mscc/ocelot_qsys.h

166

#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)

include/soc/mscc/ocelot_qsys.h

167

#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)

include/soc/mscc/ocelot_qsys.h

168

#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))

include/soc/mscc/ocelot_qsys.h

169

#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)

include/soc/mscc/ocelot_qsys.h

170

#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)

include/soc/mscc/ocelot_qsys.h

171

#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))

include/soc/mscc/ocelot_qsys.h

172

#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)

include/soc/mscc/ocelot_qsys.h

173

#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)

include/soc/mscc/ocelot_qsys.h

180

#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))

include/soc/mscc/ocelot_qsys.h

181

#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)

include/soc/mscc/ocelot_qsys.h

182

#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)

include/soc/mscc/ocelot_qsys.h

183

#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_qsys.h

184

#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)

include/soc/mscc/ocelot_qsys.h

190

#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))

include/soc/mscc/ocelot_qsys.h

191

#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)

include/soc/mscc/ocelot_qsys.h

192

#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)

include/soc/mscc/ocelot_qsys.h

196

#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))

include/soc/mscc/ocelot_qsys.h

197

#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)

include/soc/mscc/ocelot_qsys.h

198

#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)

include/soc/mscc/ocelot_qsys.h

206

#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))

include/soc/mscc/ocelot_qsys.h

207

#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)

include/soc/mscc/ocelot_qsys.h

208

#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)

include/soc/mscc/ocelot_qsys.h

209

#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_qsys.h

210

#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)

include/soc/mscc/ocelot_qsys.h

211

#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

212

#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_qsys.h

213

#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)

include/soc/mscc/ocelot_qsys.h

214

#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

216

#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_qsys.h

217

#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)

include/soc/mscc/ocelot_qsys.h

223

#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_qsys.h

224

#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_qsys.h

225

#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_qsys.h

226

#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)

include/soc/mscc/ocelot_qsys.h

227

#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

229

#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_qsys.h

230

#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)

include/soc/mscc/ocelot_qsys.h

231

#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_qsys.h

232

#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)

include/soc/mscc/ocelot_qsys.h

233

#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

235

#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_qsys.h

236

#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_qsys.h

237

#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_qsys.h

238

#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)

include/soc/mscc/ocelot_qsys.h

239

#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

241

#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_qsys.h

242

#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)

include/soc/mscc/ocelot_qsys.h

243

#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))

include/soc/mscc/ocelot_qsys.h

244

#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)

include/soc/mscc/ocelot_qsys.h

245

#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)

include/soc/mscc/ocelot_qsys.h

248

#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_qsys.h

249

#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)

include/soc/mscc/ocelot_qsys.h

25

#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_qsys.h

250

#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_qsys.h

251

#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)

include/soc/mscc/ocelot_qsys.h

252

#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

26

#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)

include/soc/mscc/ocelot_qsys.h

27

#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

28

#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_qsys.h

29

#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)

include/soc/mscc/ocelot_qsys.h

33

#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))

include/soc/mscc/ocelot_qsys.h

34

#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)

include/soc/mscc/ocelot_qsys.h

35

#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

36

#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_qsys.h

37

#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)

include/soc/mscc/ocelot_qsys.h

41

#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))

include/soc/mscc/ocelot_qsys.h

42

#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)

include/soc/mscc/ocelot_qsys.h

43

#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)

include/soc/mscc/ocelot_qsys.h

44

#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))

include/soc/mscc/ocelot_qsys.h

45

#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)

include/soc/mscc/ocelot_qsys.h

46

#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)

include/soc/mscc/ocelot_qsys.h

47

#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_qsys.h

48

#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)

include/soc/mscc/ocelot_qsys.h

54

#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))

include/soc/mscc/ocelot_qsys.h

55

#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)

include/soc/mscc/ocelot_qsys.h

56

#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)

include/soc/mscc/ocelot_qsys.h

59

#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))

include/soc/mscc/ocelot_qsys.h

60

#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)

include/soc/mscc/ocelot_qsys.h

64

#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))

include/soc/mscc/ocelot_qsys.h

65

#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)

include/soc/mscc/ocelot_qsys.h

66

#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)

include/soc/mscc/ocelot_qsys.h

67

#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))

include/soc/mscc/ocelot_qsys.h

68

#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)

include/soc/mscc/ocelot_qsys.h

74

#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_qsys.h

75

#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT_M GENMASK(15, 0)

include/soc/mscc/ocelot_qsys.h

77

#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))

include/soc/mscc/ocelot_qsys.h

78

#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)

include/soc/mscc/ocelot_qsys.h

79

#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)

include/soc/mscc/ocelot_qsys.h

80

#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_qsys.h

81

#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)

include/soc/mscc/ocelot_sys.h

100

#define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16))

include/soc/mscc/ocelot_sys.h

101

#define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16)

include/soc/mscc/ocelot_sys.h

102

#define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16)

include/soc/mscc/ocelot_sys.h

103

#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_sys.h

104

#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0)

include/soc/mscc/ocelot_sys.h

106

#define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0))

include/soc/mscc/ocelot_sys.h

107

#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0)

include/soc/mscc/ocelot_sys.h

112

#define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2))

include/soc/mscc/ocelot_sys.h

113

#define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2)

include/soc/mscc/ocelot_sys.h

114

#define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2)

include/soc/mscc/ocelot_sys.h

115

#define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_sys.h

116

#define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0)

include/soc/mscc/ocelot_sys.h

20

#define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))

include/soc/mscc/ocelot_sys.h

21

#define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)

include/soc/mscc/ocelot_sys.h

23

#define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))

include/soc/mscc/ocelot_sys.h

24

#define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)

include/soc/mscc/ocelot_sys.h

25

#define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)

include/soc/mscc/ocelot_sys.h

26

#define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))

include/soc/mscc/ocelot_sys.h

27

#define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)

include/soc/mscc/ocelot_sys.h

40

#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))

include/soc/mscc/ocelot_sys.h

41

#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)

include/soc/mscc/ocelot_sys.h

42

#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)

include/soc/mscc/ocelot_sys.h

43

#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_sys.h

44

#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)

include/soc/mscc/ocelot_sys.h

46

#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9))

include/soc/mscc/ocelot_sys.h

47

#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)

include/soc/mscc/ocelot_sys.h

48

#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9)

include/soc/mscc/ocelot_sys.h

49

#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0))

include/soc/mscc/ocelot_sys.h

50

#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)

include/soc/mscc/ocelot_sys.h

56

#define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26))

include/soc/mscc/ocelot_sys.h

57

#define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26)

include/soc/mscc/ocelot_sys.h

58

#define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26)

include/soc/mscc/ocelot_sys.h

59

#define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))

include/soc/mscc/ocelot_sys.h

60

#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)

include/soc/mscc/ocelot_sys.h

61

#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)

include/soc/mscc/ocelot_sys.h

65

#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_sys.h

66

#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0)

include/soc/mscc/ocelot_sys.h

68

#define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_sys.h

69

#define SYS_MMGT_RELCNT_M GENMASK(31, 16)

include/soc/mscc/ocelot_sys.h

70

#define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_sys.h

71

#define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_sys.h

72

#define SYS_MMGT_FREECNT_M GENMASK(15, 0)

include/soc/mscc/ocelot_sys.h

74

#define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4))

include/soc/mscc/ocelot_sys.h

75

#define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)

include/soc/mscc/ocelot_sys.h

76

#define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4)

include/soc/mscc/ocelot_sys.h

77

#define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0))

include/soc/mscc/ocelot_sys.h

78

#define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)

include/soc/mscc/ocelot_sys.h

82

#define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6))

include/soc/mscc/ocelot_sys.h

83

#define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)

include/soc/mscc/ocelot_sys.h

84

#define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6)

include/soc/mscc/ocelot_sys.h

85

#define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_sys.h

86

#define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0)

include/soc/mscc/ocelot_sys.h

89

#define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0))

include/soc/mscc/ocelot_sys.h

90

#define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0)

include/soc/mscc/ocelot_sys.h

97

#define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))

include/soc/mscc/ocelot_sys.h

98

#define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)

include/soc/mscc/ocelot_sys.h

99

#define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)

include/soc/mscc/ocelot_vcap.h

104

#define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))

include/soc/mscc/ocelot_vcap.h

105

#define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)

include/soc/mscc/ocelot_vcap.h

69

#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))

include/soc/mscc/ocelot_vcap.h

70

#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)

include/soc/mscc/ocelot_vcap.h

71

#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)

include/soc/mscc/ocelot_vcap.h

75

#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))

include/soc/mscc/ocelot_vcap.h

76

#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)

include/soc/mscc/ocelot_vcap.h

77

#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)

include/soc/mscc/ocelot_vcap.h

82

#define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))

include/soc/mscc/ocelot_vcap.h

83

#define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)

include/soc/mscc/ocelot_vcap.h

84

#define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)

include/soc/mscc/ocelot_vcap.h

85

#define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))

include/soc/mscc/ocelot_vcap.h

86

#define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)

include/soc/qcom/tcs.h

68

#define BCM_TCS_CMD_VOTE_MASK GENMASK(13, 0)

include/soc/qcom/tcs.h

69

#define BCM_TCS_CMD_VOTE_Y_MASK GENMASK(13, 0)

include/soc/qcom/tcs.h

70

#define BCM_TCS_CMD_VOTE_X_MASK GENMASK(27, 14)

include/soc/rockchip/rk3399_grf.h

14

#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)

include/soc/rockchip/rk3399_grf.h

15

#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)

include/soc/rockchip/rk3399_grf.h

16

#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)

include/soc/rockchip/rk3568_grf.h

10

#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)

include/soc/rockchip/rk3568_grf.h

11

#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)

include/soc/rockchip/rk3568_grf.h

6

#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)

include/soc/rockchip/rk3568_grf.h

7

#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)

include/soc/rockchip/rk3588_grf.h

12

#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)

include/soc/rockchip/rk3588_grf.h

13

#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)

include/soc/rockchip/rk3588_grf.h

18

#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1)

include/soc/rockchip/rk3588_grf.h

6

#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)

include/soc/rockchip/rk3588_grf.h

7

#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)

include/soc/rockchip/rk3588_grf.h

8

#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)

include/soc/rockchip/rk3588_grf.h

9

#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)

include/sound/cs35l56.h

141

#define CS35L56_PAD_GPIO_PULL_MASK GENMASK(3, 2)

include/sound/cs35l56.h

208

#define CS35L56_GPIO_FN_MASK GENMASK(2, 0)

include/sound/cs42l42.h

66

#define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4)

include/sound/hda_register.h

134

#define AZX_REG_VS_LTRP_GB_MASK GENMASK(6, 0)

include/sound/hda_register.h

275

#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */

include/sound/hda_register.h

285

#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */

include/sound/hda_register.h

309

#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0)

include/sound/hda_register.h

313

#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24)

include/sound/hda_register.h

319

#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20)

include/sound/hda_register.h

320

#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0)

include/sound/hda_register.h

94

#define AZX_SD_FIFOSIZE_MASK GENMASK(15, 0)

include/sound/sdw.h

46

port_config->ch_mask = GENMASK(stream_config->ch_count - 1, 0);

include/sound/soc_sdw_utils.h

18

#define SOC_SDW_JACK_JDSRC(quirk) ((quirk) & GENMASK(3, 0))

include/sound/sof/ext_manifest.h

35

((host_ver) & GENMASK(31, 24)) != \

include/sound/sof/ext_manifest.h

36

((cli_ver) & GENMASK(31, 24)))

include/sound/sof/ipc4/header.h

161

#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24)

include/sound/sof/ipc4/header.h

171

#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

175

#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11)

include/sound/sof/ipc4/header.h

179

#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0)

include/sound/sof/ipc4/header.h

187

#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20)

include/sound/sof/ipc4/header.h

192

#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

196

#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0)

include/sound/sof/ipc4/header.h

208

#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0)

include/sound/sof/ipc4/header.h

213

#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8)

include/sound/sof/ipc4/header.h

230

#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0)

include/sound/sof/ipc4/header.h

284

#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0)

include/sound/sof/ipc4/header.h

288

#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8)

include/sound/sof/ipc4/header.h

293

#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

327

#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

333

#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0)

include/sound/sof/ipc4/header.h

340

#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0)

include/sound/sof/ipc4/header.h

344

#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

348

#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24)

include/sound/sof/ipc4/header.h

361

#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0)

include/sound/sof/ipc4/header.h

365

#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

369

#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24)

include/sound/sof/ipc4/header.h

373

#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27)

include/sound/sof/ipc4/header.h

381

#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0)

include/sound/sof/ipc4/header.h

385

#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20)

include/sound/sof/ipc4/header.h

482

#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0)

include/sound/sof/ipc4/header.h

500

#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16)

include/sound/sof/ipc4/header.h

505

#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12)

include/sound/sof/ipc4/header.h

589

#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK GENMASK(31, 16)

include/sound/sof/ipc4/header.h

591

#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_PARAMID_MASK GENMASK(15, 0)

include/sound/sof/ipc4/header.h

639

#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_MASK GENMASK(15, 1)

include/sound/sof/ipc4/header.h

643

#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_MASK GENMASK(31, 16)

include/sound/tas2781.h

70

#define TAS2781_AMP_LEVEL_MASK GENMASK(5, 1)

include/uapi/cxl/features.h

176

#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0)

include/uapi/cxl/features.h

54

#define CXL_CMD_EFFECTS_RESERVED GENMASK(15, 12)

include/uapi/linux/cxl_mem.h

137

#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0)

include/uapi/linux/mdio.h

260

#define MDIO_AN_C73_0_S_MASK GENMASK(4, 0)

include/uapi/linux/mdio.h

261

#define MDIO_AN_C73_0_E_MASK GENMASK(9, 5)

include/uapi/linux/mdio.h

268

#define MDIO_AN_C73_1_T_MASK GENMASK(4, 0)

include/uapi/linux/mptcp.h

43

#define MPTCP_PM_ADDR_FLAGS_MASK GENMASK(5, 0)

include/uapi/linux/v4l2-controls.h

1750

#define V4L2_FWHT_FL_COMPONENTS_NUM_MSK GENMASK(18, 16)

include/uapi/linux/v4l2-controls.h

1754

#define V4L2_FWHT_FL_PIXENC_MSK GENMASK(20, 19)

include/ufs/ufshci.h

131

#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)

include/ufs/ufshci.h

166

#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)

include/ufs/ufshci.h

167

#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)

io_uring/poll.c

46

#define IO_POLL_REF_MASK GENMASK(29, 0)

io_uring/waitid.c

22

#define IO_WAITID_REF_MASK GENMASK(30, 0)

kernel/bpf/verifier.c

18490

clobbered_regs_mask = GENMASK(cs.num_params, cs.is_void ? 1 : 0);

kernel/bpf/verifier.c

25660

use = GENMASK(cs.num_params, 1);

kernel/kcsan/encoding.h

47

#define WATCHPOINT_SIZE_MASK GENMASK(BITS_PER_LONG-2, WATCHPOINT_ADDR_BITS)

kernel/kcsan/encoding.h

48

#define WATCHPOINT_ADDR_MASK GENMASK(WATCHPOINT_ADDR_BITS-1, 0)

kernel/trace/fgraph.c

109

#define FGRAPH_FRAME_OFFSET_MASK GENMASK(FGRAPH_FRAME_OFFSET_BITS - 1, 0)

kernel/trace/fgraph.c

112

#define FGRAPH_TYPE_MASK GENMASK(FGRAPH_TYPE_BITS - 1, 0)

kernel/trace/fgraph.c

126

#define FGRAPH_INDEX_MASK GENMASK(FGRAPH_INDEX_BITS - 1, 0)

kernel/trace/fgraph.c

138

#define FGRAPH_DATA_MASK GENMASK(FGRAPH_DATA_BITS - 1, 0)

kernel/trace/fgraph.c

143

#define FGRAPH_DATA_INDEX_MASK GENMASK(FGRAPH_DATA_INDEX_BITS - 1, 0)

kernel/trace/trace_probe.h

404

#define TPARG_FL_LOC_MASK GENMASK(4, 0)

lib/packing.c

136

box_mask = GENMASK(box_start_bit, box_end_bit);

lib/packing.c

247

box_mask = GENMASK(box_start_bit, box_end_bit);

lib/test_bitmap.c

1232

var ^= GENMASK(9, 6);

lib/test_bitmap.c

1245

res = initvar & GENMASK(14, 8);

lib/tests/scanf_kunit.c

260

return prandom_u32_state(&rnd_state) & GENMASK(n_bits, 0);

lib/tests/test_bits.c

22

static_assert(assert_type(unsigned long, GENMASK(31, 0)) == U32_MAX);

lib/tests/test_bits.c

49

KUNIT_EXPECT_EQ(test, 1ul, GENMASK(0, 0));

lib/tests/test_bits.c

50

KUNIT_EXPECT_EQ(test, 3ul, GENMASK(1, 0));

lib/tests/test_bits.c

51

KUNIT_EXPECT_EQ(test, 6ul, GENMASK(2, 1));

lib/tests/test_bits.c

52

KUNIT_EXPECT_EQ(test, 0xFFFFFFFFul, GENMASK(31, 0));

lib/tests/test_bits.c

60

GENMASK(0, 1);

lib/tests/test_bits.c

61

GENMASK(0, 10);

lib/tests/test_bits.c

62

GENMASK(9, 10);

mm/debug_vm_pgtable.c

43

#define RANDOM_NZVALUE GENMASK(7, 0)

net/bridge/br.c

385

bm->optmask = GENMASK((BR_BOOLOPT_MAX - 1), 0);

net/dsa/tag_8021q.c

40

#define DSA_8021Q_RSV_MASK GENMASK(11, 10)

net/dsa/tag_8021q.c

45

#define DSA_8021Q_SWITCH_ID_MASK GENMASK(8, 6)

net/dsa/tag_8021q.c

50

#define DSA_8021Q_VBID_HI_MASK GENMASK(9, 9)

net/dsa/tag_8021q.c

52

#define DSA_8021Q_VBID_LO_MASK GENMASK(5, 4)

net/dsa/tag_8021q.c

53

#define DSA_8021Q_VBID_HI(x) (((x) & GENMASK(2, 2)) >> 2)

net/dsa/tag_8021q.c

54

#define DSA_8021Q_VBID_LO(x) ((x) & GENMASK(1, 0))

net/dsa/tag_8021q.c

62

#define DSA_8021Q_PORT_MASK GENMASK(3, 0)

net/dsa/tag_ar9331.c

17

#define AR9331_HDR_VERSION_MASK GENMASK(15, 14)

net/dsa/tag_ar9331.c

18

#define AR9331_HDR_PRIORITY_MASK GENMASK(13, 12)

net/dsa/tag_ar9331.c

19

#define AR9331_HDR_TYPE_MASK GENMASK(10, 8)

net/dsa/tag_ar9331.c

26

#define AR9331_HDR_RESERVED_MASK GENMASK(5, 4)

net/dsa/tag_ar9331.c

27

#define AR9331_HDR_PORT_NUM_MASK GENMASK(3, 0)

net/dsa/tag_gswip.c

47

#define GSWIP_TX_CLASS_MASK GENMASK(3, 0)

net/dsa/tag_gswip.c

51

#define GSWIP_TX_PORT_MAP GENMASK(6, 1)

net/dsa/tag_gswip.c

58

#define GSWIP_RX_SPPID_MASK GENMASK(6, 4)

net/dsa/tag_ksz.c

117

#define KSZ8795_TAIL_TAG_EG_PORT_M GENMASK(1, 0)

net/dsa/tag_ksz.c

187

#define KSZ9477_TAIL_TAG_EG_PORT_M GENMASK(2, 0)

net/dsa/tag_ksz.c

188

#define KSZ9477_TAIL_TAG_PRIO GENMASK(8, 7)

net/dsa/tag_ksz.c

342

#define KSZ9893_TAIL_TAG_PRIO GENMASK(4, 3)

net/dsa/tag_ksz.c

408

#define LAN937X_TAIL_TAG_PRIO GENMASK(10, 8)

net/dsa/tag_mtk.c

19

#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)

net/dsa/tag_mtk.c

20

#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)

net/dsa/tag_mxl-gsw1xx.c

32

#define GSW1XX_TX_PORT_MAP GENMASK(7, 0)

net/dsa/tag_mxl-gsw1xx.c

37

#define GSW1XX_TX_CLASS GENMASK(11, 8)

net/dsa/tag_mxl-gsw1xx.c

41

#define GSW1XX_RX_PORT_MAP GENMASK(15, 8)

net/dsa/tag_mxl862xx.c

22

#define MXL862_SUBIF_ID GENMASK(4, 0)

net/dsa/tag_mxl862xx.c

25

#define MXL862_IGP_EGP GENMASK(3, 0)

net/dsa/tag_rtl8_4.c

100

#define RTL8_4_TX GENMASK(3, 0)

net/dsa/tag_rtl8_4.c

101

#define RTL8_4_RX GENMASK(10, 0)

net/dsa/tag_rtl8_4.c

92

#define RTL8_4_PROTOCOL GENMASK(15, 8)

net/dsa/tag_rtl8_4.c

94

#define RTL8_4_REASON GENMASK(7, 0)

net/dsa/tag_rzn1_a5psw.c

31

#define A5PSW_CTRL_DATA_PORT GENMASK(3, 0)

net/dsa/tag_sja1105.c

24

#define SJA1110_RX_HEADER_SRC_PORT(x) (((x) & GENMASK(7, 4)) >> 4)

net/dsa/tag_sja1105.c

25

#define SJA1110_RX_HEADER_SWITCH_ID(x) ((x) & GENMASK(3, 0))

net/dsa/tag_sja1105.c

28

#define SJA1110_RX_HEADER_TRAILER_POS(x) ((x) & GENMASK(11, 0))

net/dsa/tag_sja1105.c

30

#define SJA1110_RX_TRAILER_SWITCH_ID(x) (((x) & GENMASK(7, 4)) >> 4)

net/dsa/tag_sja1105.c

31

#define SJA1110_RX_TRAILER_SRC_PORT(x) ((x) & GENMASK(3, 0))

net/dsa/tag_sja1105.c

34

#define SJA1110_RX_HEADER_N_TS(x) (((x) & GENMASK(8, 4)) >> 4)

net/dsa/tag_sja1105.c

43

#define SJA1110_TX_HEADER_PRIO(x) (((x) << 7) & GENMASK(10, 7))

net/dsa/tag_sja1105.c

44

#define SJA1110_TX_HEADER_TSTAMP_ID(x) ((x) & GENMASK(7, 0))

net/dsa/tag_sja1105.c

47

#define SJA1110_TX_HEADER_TRAILER_POS(x) ((x) & GENMASK(10, 0))

net/dsa/tag_sja1105.c

49

#define SJA1110_TX_TRAILER_TSTAMP_ID(x) (((x) << 24) & GENMASK(31, 24))

net/dsa/tag_sja1105.c

50

#define SJA1110_TX_TRAILER_PRIO(x) (((x) << 21) & GENMASK(23, 21))

net/dsa/tag_sja1105.c

51

#define SJA1110_TX_TRAILER_SWITCHID(x) (((x) << 12) & GENMASK(15, 12))

net/dsa/tag_sja1105.c

52

#define SJA1110_TX_TRAILER_DESTPORTS(x) (((x) << 1) & GENMASK(11, 1))

net/dsa/tag_sja1105.c

554

source_port = (buf[1] & GENMASK(7, 4)) >> 4;

net/dsa/tag_yt921x.c

38

#define YT921X_TAG_RX_PORT_M GENMASK(14, 11)

net/dsa/tag_yt921x.c

39

#define YT921X_TAG_PRIO_M GENMASK(10, 8)

net/dsa/tag_yt921x.c

42

#define YT921X_TAG_CODE_M GENMASK(6, 1)

net/dsa/tag_yt921x.c

44

#define YT921X_TAG_TX_PORTS_M GENMASK(10, 0)

net/ieee802154/nl802154.c

227

NLA_POLICY_MASK(NLA_U32, GENMASK(IEEE802154_MAX_CHANNEL, 0)),

net/mac80211/rc80211_minstrel_ht.h

62

#define MI_RATE_IDX_MASK GENMASK(3, 0)

net/mac80211/rc80211_minstrel_ht.h

63

#define MI_RATE_GROUP_MASK GENMASK(15, 4)

net/mac80211/tests/s1g_tim.c

150

tim_push(p, single6 & GENMASK(5, 0));

net/netfilter/nft_set_pipapo.c

1006

v &= GENMASK(BITS_PER_BYTE - bit_offset - 1, 0);

net/netfilter/nft_set_pipapo.c

1021

mask = GENMASK(f->bb - 1, 0);

net/netfilter/nft_set_pipapo_avx2.c

113

*data |= GENMASK(len - 1 + offset, offset);

net/openvswitch/flow.c

815

key->mpls.num_labels_mask = GENMASK(label_count - 1, 0);

net/openvswitch/flow_netlink.c

1644

label_count_mask = GENMASK(label_count - 1, 0);

net/sched/sch_taprio.c

1451

queue_mask |= GENMASK(offset + count - 1, offset);

net/shaper/shaper.c

19

#define NET_SHAPER_ID_MASK GENMASK(NET_SHAPER_SCOPE_SHIFT - 1, 0)

net/shaper/shaper.c

20

#define NET_SHAPER_SCOPE_MASK GENMASK(31, NET_SHAPER_SCOPE_SHIFT)

scripts/dtc/include-prefixes/dt-bindings/pinctrl/k210-fpioa.h

13

#define K210_PCF_MASK GENMASK(7, 0)

security/landlock/domain.c

149

GENMASK(access_bit, 0));

sound/core/pcm_drm_eld.c

15

#define SAD0_CHANNELS_MASK GENMASK(2, 0) /* max number of channels - 1 */

sound/core/pcm_drm_eld.c

16

#define SAD0_FORMAT_MASK GENMASK(6, 3) /* audio format */

sound/core/pcm_drm_eld.c

18

#define SAD1_RATE_MASK GENMASK(6, 0) /* bitfield of supported rates */

sound/hda/codecs/cirrus/cs8409.h

241

#define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */

sound/hda/codecs/cirrus/cs8409.h

242

#define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */

sound/hda/codecs/cirrus/cs8409.h

243

#define CS8409_CYBORG_SPEAKER_PDN GENMASK(2, 2) /* CS8409_GPIO2 */

sound/hda/codecs/cirrus/cs8409.h

244

#define CS8409_WARLOCK_SPEAKER_PDN GENMASK(1, 1) /* CS8409_GPIO1 */

sound/hda/codecs/cirrus/cs8409.h

259

#define DOLPHIN_C0_INT GENMASK(4, 4)

sound/hda/codecs/cirrus/cs8409.h

260

#define DOLPHIN_C1_INT GENMASK(0, 0)

sound/hda/codecs/cirrus/cs8409.h

261

#define DOLPHIN_C0_RESET GENMASK(5, 5)

sound/hda/codecs/cirrus/cs8409.h

262

#define DOLPHIN_C1_RESET GENMASK(1, 1)

sound/hda/codecs/side-codecs/tas2781_hda_spi.c

58

.selector_mask = GENMASK(7, 0),

sound/hda/core/intel-nhlt.c

223

mclk_mask |= blob[mdivc_offset] & GENMASK(1, 0);

sound/hda/core/intel-sdw-acpi.c

157

if (FIELD_GET(GENMASK(31, 28), adr) != SDW_LINK_TYPE)

sound/hda/core/intel-sdw-acpi.c

93

list = GENMASK(count - 1, 0);

sound/soc/amd/acp/acp-i2s.c

29

#define LRCLK_DIV_FIELD GENMASK(10, 2)

sound/soc/amd/acp/acp-i2s.c

30

#define BCLK_DIV_FIELD GENMASK(23, 11)

sound/soc/amd/acp/acp-i2s.c

31

#define ACP63_LRCLK_DIV_FIELD GENMASK(12, 2)

sound/soc/amd/acp/acp-i2s.c

32

#define ACP63_BCLK_DIV_FIELD GENMASK(23, 13)

sound/soc/amd/acp/soc_amd_sdw_common.h

26

#define SOC_JACK_JDSRC(quirk) ((quirk) & GENMASK(3, 0))

sound/soc/amd/ps/acp63.h

36

#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)

sound/soc/amd/renoir/rn_acp3x.h

37

#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)

sound/soc/amd/yc/acp6x.h

34

#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)

sound/soc/apple/mca.c

103

#define SERDES_CONF_SYNC_SEL GENMASK(18, 16)

sound/soc/apple/mca.c

113

#define DMA_ADAPTER_TX_LSB_PAD GENMASK(4, 0)

sound/soc/apple/mca.c

114

#define DMA_ADAPTER_TX_NCHANS GENMASK(6, 5)

sound/soc/apple/mca.c

115

#define DMA_ADAPTER_RX_MSB_PAD GENMASK(12, 8)

sound/soc/apple/mca.c

116

#define DMA_ADAPTER_RX_NCHANS GENMASK(14, 13)

sound/soc/apple/mca.c

117

#define DMA_ADAPTER_NCHANS GENMASK(22, 20)

sound/soc/apple/mca.c

50

#define MCLK_CONF_DIV GENMASK(11, 8)

sound/soc/apple/mca.c

55

#define SYNCGEN_MCLK_SEL GENMASK(3, 0)

sound/soc/apple/mca.c

60

#define PORT_ENABLES_CLOCKS GENMASK(2, 1)

sound/soc/apple/mca.c

63

#define PORT_CLOCK_SEL GENMASK(11, 8)

sound/soc/apple/mca.c

91

#define SERDES_CONF_NCHANS GENMASK(3, 0)

sound/soc/apple/mca.c

92

#define SERDES_CONF_WIDTH_MASK GENMASK(8, 4)

sound/soc/atmel/atmel-i2s.c

102

#define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16)

sound/soc/atmel/atmel-i2s.c

107

#define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24)

sound/soc/atmel/atmel-i2s.c

112

#define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)

sound/soc/atmel/atmel-i2s.c

135

#define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8)

sound/soc/atmel/atmel-i2s.c

139

#define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20)

sound/soc/atmel/atmel-i2s.c

57

#define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0)

sound/soc/atmel/atmel-i2s.c

61

#define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2)

sound/soc/atmel/atmel-i2s.c

71

#define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6)

sound/soc/atmel/atmel-i2s.c

81

#define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9)

sound/soc/atmel/atmel-i2s.c

92

#define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13)

sound/soc/atmel/atmel-i2s.c

97

#define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14)

sound/soc/atmel/atmel-pdmic.h

25

#define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8)

sound/soc/atmel/atmel-pdmic.h

60

#define PDMIC_DSPR0_OSR_MASK GENMASK(6, 4)

sound/soc/atmel/atmel-pdmic.h

63

#define PDMIC_DSPR0_SCALE_MASK GENMASK(11, 8)

sound/soc/atmel/atmel-pdmic.h

66

#define PDMIC_DSPR0_SHIFT_MASK GENMASK(15, 12)

sound/soc/atmel/atmel-pdmic.h

71

#define PDMIC_DSPR1_DGAIN_MASK GENMASK(14, 0)

sound/soc/atmel/atmel-pdmic.h

74

#define PDMIC_DSPR1_OFFSET_MASK GENMASK(31, 16)

sound/soc/atmel/mchp-i2s-mcc.c

102

#define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4)

sound/soc/atmel/mchp-i2s-mcc.c

110

#define MCHP_I2SMCC_MRA_FORMAT_MASK GENMASK(7, 6)

sound/soc/atmel/mchp-i2s-mcc.c

136

#define MCHP_I2SMCC_MRA_NBCHAN_MASK GENMASK(15, 13)

sound/soc/atmel/mchp-i2s-mcc.c

141

#define MCHP_I2SMCC_MRA_IMCKDIV_MASK GENMASK(21, 16)

sound/soc/atmel/mchp-i2s-mcc.c

146

#define MCHP_I2SMCC_MRA_TDMFS_MASK GENMASK(23, 22)

sound/soc/atmel/mchp-i2s-mcc.c

152

#define MCHP_I2SMCC_MRA_ISCKDIV_MASK GENMASK(29, 24)

sound/soc/atmel/mchp-i2s-mcc.c

157

#define MCHP_I2SMCC_MRA_IMCKMODE_MASK GENMASK(30, 30)

sound/soc/atmel/mchp-i2s-mcc.c

181

#define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8)

sound/soc/atmel/mchp-i2s-mcc.c

185

#define MCHP_I2SMCC_MRB_CLKSEL_MASK GENMASK(16, 16)

sound/soc/atmel/mchp-i2s-mcc.c

198

#define MCHP_I2SMCC_INT_TXRDY_MASK(ch) GENMASK((ch) - 1, 0)

sound/soc/atmel/mchp-i2s-mcc.c

200

#define MCHP_I2SMCC_INT_TXUNF_MASK(ch) GENMASK((ch) + 7, 8)

sound/soc/atmel/mchp-i2s-mcc.c

202

#define MCHP_I2SMCC_INT_RXRDY_MASK(ch) GENMASK((ch) + 15, 16)

sound/soc/atmel/mchp-i2s-mcc.c

204

#define MCHP_I2SMCC_INT_RXOVF_MASK(ch) GENMASK((ch) + 23, 24)

sound/soc/atmel/mchp-i2s-mcc.c

219

#define MCHP_I2SMCC_VERSION_MASK GENMASK(11, 0)

sound/soc/atmel/mchp-i2s-mcc.c

391

if (rx_mask != GENMASK(slots - 1, 0) ||

sound/soc/atmel/mchp-i2s-mcc.c

453

(clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&

sound/soc/atmel/mchp-i2s-mcc.c

454

(clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));

sound/soc/atmel/mchp-i2s-mcc.c

88

#define MCHP_I2SMCC_MRA_MODE_MASK GENMASK(0, 0)

sound/soc/atmel/mchp-i2s-mcc.c

92

#define MCHP_I2SMCC_MRA_DATALENGTH_MASK GENMASK(3, 1)

sound/soc/atmel/mchp-pdmc.c

44

#define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0)

sound/soc/atmel/mchp-pdmc.c

47

#define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16)

sound/soc/atmel/mchp-pdmc.c

52

#define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20)

sound/soc/atmel/mchp-pdmc.c

54

#define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24)

sound/soc/atmel/mchp-pdmc.c

63

#define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28)

sound/soc/atmel/mchp-pdmc.c

87

#define MCHP_PDMC_VER_VERSION GENMASK(11, 0)

sound/soc/atmel/mchp-spdifrx.c

120

#define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16)

sound/soc/atmel/mchp-spdifrx.c

127

#define SPDIFRX_VERSION_MASK GENMASK(11, 0)

sound/soc/atmel/mchp-spdifrx.c

128

#define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16)

sound/soc/atmel/mchp-spdifrx.c

53

#define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0)

sound/soc/atmel/mchp-spdifrx.c

65

#define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2)

sound/soc/atmel/mchp-spdifrx.c

70

#define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3)

sound/soc/atmel/mchp-spdifrx.c

75

#define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4)

sound/soc/atmel/mchp-spdifrx.c

80

#define SPDIFRX_MR_PACK_MASK GENMASK(7, 7)

sound/soc/atmel/mchp-spdifrx.c

85

#define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8)

sound/soc/atmel/mchp-spdifrx.c

90

#define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24)

sound/soc/atmel/mchp-spdifrx.c

996

regmap_write(dev->regmap, SPDIFRX_IDR, GENMASK(14, 0));

sound/soc/atmel/mchp-spdiftx.c

48

#define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0)

sound/soc/atmel/mchp-spdiftx.c

58

#define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2)

sound/soc/atmel/mchp-spdiftx.c

63

#define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3)

sound/soc/atmel/mchp-spdiftx.c

68

#define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4)

sound/soc/atmel/mchp-spdiftx.c

74

#define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8)

sound/soc/atmel/mchp-spdiftx.c

77

#define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16)

sound/soc/atmel/mchp-spdiftx.c

84

#define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)

sound/soc/atmel/mchp-spdiftx.c

89

#define SPDIFTX_MR_BPS_MASK GENMASK(29, 28)

sound/soc/bcm/bcm2835-i2s.c

260

rx_mask &= GENMASK(slots - 1, 0);

sound/soc/bcm/bcm2835-i2s.c

261

tx_mask &= GENMASK(slots - 1, 0);

sound/soc/codecs/adau7118.c

16

#define ADAU7118_DEC_RATIO_MASK GENMASK(1, 0)

sound/soc/codecs/adau7118.c

18

#define ADAU7118_CLK_MAP_MASK GENMASK(7, 4)

sound/soc/codecs/adau7118.c

19

#define ADAU7118_SLOT_WIDTH_MASK GENMASK(5, 4)

sound/soc/codecs/adau7118.c

23

#define ADAU7118_DATA_FMT_MASK GENMASK(3, 1)

sound/soc/codecs/adau7118.c

27

#define ADAU7118_LRCLK_BCLK_POL_MASK GENMASK(1, 0)

sound/soc/codecs/adau7118.c

30

#define ADAU7118_SPT_SLOT_MASK GENMASK(7, 4)

sound/soc/codecs/ak4375.c

31

#define FS_MASK GENMASK(4, 0)

sound/soc/codecs/ak4375.c

43

#define CM_MASK GENMASK(6, 5) /* For SRC Bypass mode */

sound/soc/codecs/ak4375.c

53

#define DACMUTE_MASK (GENMASK(5, 4) | GENMASK(1, 0)) /* Clear to mute */

sound/soc/codecs/ak4375.c

74

#define DEVICEID_MASK GENMASK(7, 5)

sound/soc/codecs/ak4458.h

46

#define AK4458_SD_MASK GENMASK(5, 5)

sound/soc/codecs/ak4458.h

47

#define AK4458_SLOW_MASK GENMASK(0, 0)

sound/soc/codecs/ak4458.h

48

#define AK4458_SSLOW_MASK GENMASK(0, 0)

sound/soc/codecs/ak4458.h

55

#define AK4458_DIF_MASK GENMASK(3, 1)

sound/soc/codecs/ak4458.h

64

#define AK4458_RSTN_MASK GENMASK(0, 0)

sound/soc/codecs/ak4458.h

69

#define AK4458_MODE_MASK GENMASK(7, 6)

sound/soc/codecs/ak4458.h

84

#define AK4458_ATS_MASK GENMASK(7, 6)

sound/soc/codecs/ak5558.h

20

#define AK5558_DIF GENMASK(1, 1)

sound/soc/codecs/ak5558.h

24

#define AK5558_BITS GENMASK(2, 2)

sound/soc/codecs/ak5558.h

28

#define AK5558_CKS GENMASK(6, 3)

sound/soc/codecs/ak5558.h

46

#define AK5558_MODE_BITS GENMASK(6, 5)

sound/soc/codecs/cs35l41-lib.c

858

GENMASK(31, bit_offset)) >> bit_offset;

sound/soc/codecs/cs35l41-lib.c

860

GENMASK(bit_offset + otp_map[i].size - 33, 0)) <<

sound/soc/codecs/cs35l41-lib.c

865

GENMASK(bit_offset + otp_map[i].size - 1, bit_offset)

sound/soc/codecs/cs35l41-lib.c

880

GENMASK(otp_map[i].shift + otp_map[i].size - 1,

sound/soc/codecs/cs35l45.h

172

#define CS35L45_BST_EN_MASK GENMASK(5, 4)

sound/soc/codecs/cs35l45.h

206

#define CS35L45_PLL_REFCLK_FREQ_MASK GENMASK(10, 5)

sound/soc/codecs/cs35l45.h

210

#define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/cs35l45.h

216

#define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0)

sound/soc/codecs/cs35l45.h

234

#define CS35L45_ASP_WIDTH_RX_MASK GENMASK(31, 24)

sound/soc/codecs/cs35l45.h

236

#define CS35L45_ASP_WIDTH_TX_MASK GENMASK(23, 16)

sound/soc/codecs/cs35l45.h

238

#define CS35L45_ASP_FMT_MASK GENMASK(10, 8)

sound/soc/codecs/cs35l45.h

249

#define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0)

sound/soc/codecs/cs35l45.h

253

#define CS35L45_ASP_TX4_SLOT_MASK GENMASK(29, 24)

sound/soc/codecs/cs35l45.h

255

#define CS35L45_ASP_TX3_SLOT_MASK GENMASK(21, 16)

sound/soc/codecs/cs35l45.h

257

#define CS35L45_ASP_TX2_SLOT_MASK GENMASK(13, 8)

sound/soc/codecs/cs35l45.h

259

#define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0)

sound/soc/codecs/cs35l45.h

267

#define CS35L45_ASP_RX2_SLOT_MASK GENMASK(13, 8)

sound/soc/codecs/cs35l45.h

269

#define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0)

sound/soc/codecs/cs35l45.h

277

#define CS35L45_ASP_WL_MASK GENMASK(5, 0)

sound/soc/codecs/cs35l45.h

284

#define CS35L45_HVLV_MODE_MASK GENMASK(1, 0)

sound/soc/codecs/cs35l45.h

302

#define CS35L45_AMP_GAIN_PCM_MASK GENMASK(9, 8)

sound/soc/codecs/cs35l45.h

320

#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20)

sound/soc/codecs/cs35l45.h

389

#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8)

sound/soc/codecs/cs35l45.h

391

#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0)

sound/soc/codecs/cs35l45.h

397

#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0)

sound/soc/codecs/cs35l56-shared-test.c

546

{ .spkid_gpios = { -1 }, .gpio_status = GENMASK(12, 0) },

sound/soc/codecs/cs35l56.c

623

pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0);

sound/soc/codecs/cs40l50-codec.c

27

#define CS40L50_PLL_REFCLK_FREQ_MASK GENMASK(10, 5)

sound/soc/codecs/cs40l50-codec.c

29

#define CS40L50_PLL_REFCLK_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/cs40l50-codec.c

34

#define CS40L50_ASP_RX_WIDTH_MASK GENMASK(31, 24)

sound/soc/codecs/cs40l50-codec.c

35

#define CS40L50_ASP_RX_WL_MASK GENMASK(5, 0)

sound/soc/codecs/cs40l50-codec.c

38

#define CS40L50_ASP_FMT_MASK GENMASK(10, 8)

sound/soc/codecs/cs42l84.h

103

#define CS42L84_MIC_DET_CTL1_HS_DET_LEVEL GENMASK(5, 0)

sound/soc/codecs/cs42l84.h

120

#define CS42L84_HS_DET_CTL2_CTL GENMASK(7, 6)

sound/soc/codecs/cs42l84.h

121

#define CS42L84_HS_DET_CTL2_SET GENMASK(5, 4)

sound/soc/codecs/cs42l84.h

123

#define CS42L84_HS_DET_CTL2_AUTO_TIME GENMASK(1, 0)

sound/soc/codecs/cs42l84.h

173

#define CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO GENMASK(7, 1)

sound/soc/codecs/cs42l84.h

175

#define CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI GENMASK(4, 0)

sound/soc/codecs/cs42l84.h

192

#define CS42L84_ASP_RX_CHx_CTL1_SLOT_START_LSB GENMASK(7, 1)

sound/soc/codecs/cs42l84.h

193

#define CS42L84_ASP_RX_CHx_CTL2_SLOT_START_MSB GENMASK(2, 0)

sound/soc/codecs/cs42l84.h

31

#define CS42L84_TSRS_PLUG_VAL_MASK GENMASK(3, 0)

sound/soc/codecs/cs42l84.h

41

#define CS42L84_CCM_CTL1_MCLK_SRC GENMASK(1, 0)

sound/soc/codecs/cs42l84.h

46

#define CS42L84_CCM_CTL1_MCLK_FREQ GENMASK(3, 2)

sound/soc/codecs/cs42l84.h

63

#define CS42L84_CCM_CTL3_REFCLK_DIV GENMASK(2, 1)

sound/soc/codecs/cs42l84.h

71

#define CS42L84_PLL_CTL1_MODE GENMASK(2, 1)

sound/soc/codecs/cs42l84.h

81

#define CS42L84_RING_SENSE_CTL_FALLTIME GENMASK(5, 3)

sound/soc/codecs/cs42l84.h

82

#define CS42L84_RING_SENSE_CTL_RISETIME GENMASK(2, 0)

sound/soc/codecs/cs42l84.h

85

#define CS42L84_TIP_SENSE_CTL_FALLTIME GENMASK(5, 3)

sound/soc/codecs/cs42l84.h

86

#define CS42L84_TIP_SENSE_CTL_RISETIME GENMASK(2, 0)

sound/soc/codecs/cs42l84.h

91

#define CS42L84_TIP_SENSE_CTL2_MODE GENMASK(7, 6)

sound/soc/codecs/cs42l84.h

98

#define CS42L84_MISC_DET_CTL_DETECT_MODE GENMASK(4, 3)

sound/soc/codecs/cs42l84.h

99

#define CS42L84_MISC_DET_CTL_HSBIAS_CTL GENMASK(2, 1)

sound/soc/codecs/cs530x.h

105

#define CS530X_ASP_BCLK_FREQ_MASK GENMASK(1, 0)

sound/soc/codecs/cs530x.h

114

#define CS530X_ASP_FMT_MASK GENMASK(2, 0)

sound/soc/codecs/cs530x.h

115

#define CS530X_ASP_TDM_SLOT_MASK GENMASK(5, 3)

sound/soc/codecs/cs530x.h

124

#define CS530X_0_1_TDM_SLOT_MASK GENMASK(1, 0)

sound/soc/codecs/cs530x.h

125

#define CS530X_0_3_TDM_SLOT_MASK GENMASK(3, 0)

sound/soc/codecs/cs530x.h

126

#define CS530X_0_7_TDM_SLOT_MASK GENMASK(7, 0)

sound/soc/codecs/cs530x.h

129

#define CS530X_2_3_TDM_SLOT_MASK GENMASK(3, 2)

sound/soc/codecs/cs530x.h

132

#define CS530X_4_5_TDM_SLOT_MASK GENMASK(5, 4)

sound/soc/codecs/cs530x.h

133

#define CS530X_4_7_TDM_SLOT_MASK GENMASK(7, 4)

sound/soc/codecs/cs530x.h

136

#define CS530X_6_7_TDM_SLOT_MASK GENMASK(7, 6)

sound/soc/codecs/cs530x.h

139

#define CS530X_8_9_TDM_SLOT_MASK GENMASK(9, 8)

sound/soc/codecs/cs530x.h

140

#define CS530X_8_11_TDM_SLOT_MASK GENMASK(11, 8)

sound/soc/codecs/cs530x.h

141

#define CS530X_8_15_TDM_SLOT_MASK GENMASK(15, 8)

sound/soc/codecs/cs530x.h

144

#define CS530X_10_11_TDM_SLOT_MASK GENMASK(11, 10)

sound/soc/codecs/cs530x.h

147

#define CS530X_12_13_TDM_SLOT_MASK GENMASK(13, 12)

sound/soc/codecs/cs530x.h

148

#define CS530X_12_15_TDM_SLOT_MASK GENMASK(15, 12)

sound/soc/codecs/cs530x.h

151

#define CS530X_14_15_TDM_SLOT_MASK GENMASK(15, 14)

sound/soc/codecs/cs530x.h

75

#define CS530X_MTLREVID GENMASK(3, 0)

sound/soc/codecs/cs530x.h

76

#define CS530X_AREVID GENMASK(7, 4)

sound/soc/codecs/cs530x.h

84

#define CS530X_PLL_REFCLK_FREQ_MASK GENMASK(5, 4)

sound/soc/codecs/cs530x.h

93

#define CS530X_SAMPLE_RATE_MASK GENMASK(2, 0)

sound/soc/codecs/es8311.h

18

#define ES8311_RESET_RST_MASK GENMASK(4, 0)

sound/soc/codecs/es8311.h

30

#define ES8311_CLKMGR2_DIV_PRE_MASK GENMASK(7, 5)

sound/soc/codecs/es8311.h

33

#define ES8311_CLKMGR2_MULT_PRE_MASK GENMASK(4, 3)

sound/soc/codecs/es8311.h

38

#define ES8311_CLKMGR5_ADC_DIV_MASK GENMASK(7, 4)

sound/soc/codecs/es8311.h

40

#define ES8311_CLKMGR5_DAC_DIV_MASK GENMASK(3, 0)

sound/soc/codecs/es8311.h

44

#define ES8311_CLKMGR6_DIV_BCLK_MASK GENMASK(4, 0)

sound/soc/codecs/es8311.h

46

#define ES8311_CLKMGR7_LRCLK_DIV_H_MASK GENMASK(3, 0)

sound/soc/codecs/es8311.h

57

#define ES8311_SDP_WL_MASK GENMASK(4, 2)

sound/soc/codecs/es8311.h

64

#define ES8311_SDP_FMT_MASK GENMASK(1, 0)

sound/soc/codecs/es8311.h

79

#define ES8311_SYS3_PDN_VMIDSEL_MASK GENMASK(1, 0)

sound/soc/codecs/es8323.h

121

#define ES8323_DACCONTROL1_DACFORMAT GENMASK(1, 0)

sound/soc/codecs/es8323.h

122

#define ES8323_DACCONTROL1_DACWL GENMASK(5, 3)

sound/soc/codecs/es8323.h

128

#define ES8323_DACCONTROL2_DACFSRATIO GENMASK(4, 0)

sound/soc/codecs/es8323.h

57

#define ES8323_MASTERMODE_BCLKDIV GENMASK(4, 0)

sound/soc/codecs/es8323.h

72

#define ES8323_ADCCONTROL4_ADCFORMAT GENMASK(1, 0)

sound/soc/codecs/es8323.h

77

#define ES8323_ADCCONTROL4_ADCWL GENMASK(4, 2)

sound/soc/codecs/es8323.h

84

#define ES8323_ADCCONTROL4_DATSEL GENMASK(7, 6)

sound/soc/codecs/es8323.h

88

#define ES8323_ADCCONTROL5_ADCFSRATIO GENMASK(4, 0)

sound/soc/codecs/fs210x.h

60

#define FS210X_17H_I2SSR_MASK GENMASK(15, 12)

sound/soc/codecs/jz4725b.c

32

#define ICDC_RGADW_RGADDR_MASK GENMASK(14, ICDC_RGADW_RGADDR_OFFSET)

sound/soc/codecs/jz4725b.c

35

#define ICDC_RGADW_RGDIN_MASK GENMASK(7, ICDC_RGADW_RGDIN_OFFSET)

sound/soc/codecs/jz4725b.c

41

#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET)

sound/soc/codecs/jz4760.c

115

#define REG_ICR_INT_FORM_MASK GENMASK(7, 6)

sound/soc/codecs/jz4760.c

116

#define REG_ICR_ALL_MASK GENMASK(5, 0)

sound/soc/codecs/jz4760.c

124

#define REG_IFR_ALL_MASK GENMASK(5, 0)

sound/soc/codecs/jz4760.c

138

#define REG_GCR_GIM1_MASK GENMASK(5, 3)

sound/soc/codecs/jz4760.c

139

#define REG_GCR_GIM2_MASK GENMASK(2, 0)

sound/soc/codecs/jz4760.c

143

#define REG_AGC1_TARGET_MASK GENMASK(5, 2)

sound/soc/codecs/jz4760.c

145

#define REG_AGC2_NG_THR_MASK GENMASK(6, 4)

sound/soc/codecs/jz4760.c

146

#define REG_AGC2_HOLD_MASK GENMASK(3, 0)

sound/soc/codecs/jz4760.c

148

#define REG_AGC3_ATK_MASK GENMASK(7, 4)

sound/soc/codecs/jz4760.c

149

#define REG_AGC3_DCY_MASK GENMASK(3, 0)

sound/soc/codecs/jz4760.c

151

#define REG_AGC4_AGC_MAX_MASK GENMASK(4, 0)

sound/soc/codecs/jz4760.c

153

#define REG_AGC5_AGC_MIN_MASK GENMASK(4, 0)

sound/soc/codecs/jz4760.c

155

#define REG_MIX1_MIX_REC_MASK GENMASK(7, 6)

sound/soc/codecs/jz4760.c

156

#define REG_MIX1_GIMIX_MASK GENMASK(4, 0)

sound/soc/codecs/jz4760.c

158

#define REG_MIX2_DAC_MIX_MASK GENMASK(7, 6)

sound/soc/codecs/jz4760.c

159

#define REG_MIX2_GOMIX_MASK GENMASK(4, 0)

sound/soc/codecs/jz4760.c

27

#define ICDC_RGADW_RGADDR_MASK GENMASK(14, 8)

sound/soc/codecs/jz4760.c

28

#define ICDC_RGADW_RGDIN_MASK GENMASK(7, 0)

sound/soc/codecs/jz4760.c

32

#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, 0)

sound/soc/codecs/jz4760.c

66

#define REG_AICR_DAC_ADWL_MASK GENMASK(7, 6)

sound/soc/codecs/jz4760.c

70

#define REG_AICR_ADC_ADWL_MASK GENMASK(5, 4)

sound/soc/codecs/jz4760.c

80

#define REG_CR1_OUTSEL_MASK GENMASK(1, REG_CR1_OUTSEL_OFFSET)

sound/soc/codecs/jz4760.c

88

#define REG_CR3_ADC_INSEL_MASK GENMASK(3, REG_CR3_ADC_INSEL_OFFSET)

sound/soc/codecs/jz4760.c

95

#define REG_CCR1_CRYSTAL_MASK GENMASK(3, 0)

sound/soc/codecs/jz4760.c

97

#define REG_CCR2_DAC_FREQ_MASK GENMASK(7, 4)

sound/soc/codecs/jz4760.c

98

#define REG_CCR2_ADC_FREQ_MASK GENMASK(3, 0)

sound/soc/codecs/jz4770.c

28

#define ICDC_RGADW_RGADDR_MASK GENMASK(14, ICDC_RGADW_RGADDR_OFFSET)

sound/soc/codecs/jz4770.c

31

#define ICDC_RGADW_RGDIN_MASK GENMASK(7, ICDC_RGADW_RGDIN_OFFSET)

sound/soc/codecs/jz4770.c

37

#define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET)

sound/soc/codecs/lpass-rx-macro.c

169

#define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-rx-macro.c

182

#define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)

sound/soc/codecs/lpass-rx-macro.c

186

#define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)

sound/soc/codecs/lpass-rx-macro.c

191

#define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-rx-macro.c

207

#define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/lpass-rx-macro.c

234

#define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2)

sound/soc/codecs/lpass-rx-macro.c

73

#define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-rx-macro.c

74

#define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)

sound/soc/codecs/lpass-rx-macro.c

76

#define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-rx-macro.c

77

#define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)

sound/soc/codecs/lpass-rx-macro.c

89

#define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0)

sound/soc/codecs/lpass-rx-macro.c

91

#define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0)

sound/soc/codecs/lpass-rx-macro.c

96

#define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-tx-macro.c

43

#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)

sound/soc/codecs/lpass-tx-macro.c

50

#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-tx-macro.c

51

#define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4)

sound/soc/codecs/lpass-tx-macro.c

86

#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/lpass-tx-macro.c

93

#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)

sound/soc/codecs/lpass-tx-macro.c

94

#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)

sound/soc/codecs/lpass-va-macro.c

100

#define CDC_VA_ADC_MODE_MASK GENMASK(2, 1)

sound/soc/codecs/lpass-va-macro.c

102

#define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5)

sound/soc/codecs/lpass-va-macro.c

41

#define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)

sound/soc/codecs/lpass-va-macro.c

68

#define CORE_ID_0_REV_MAJ GENMASK(7, 0)

sound/soc/codecs/lpass-va-macro.c

75

#define CORE_ID_2_REV_MIN GENMASK(7, 4)

sound/soc/codecs/lpass-va-macro.c

76

#define CORE_ID_2_REV_STEP GENMASK(3, 0)

sound/soc/codecs/lpass-wsa-macro.c

108

#define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0)

sound/soc/codecs/lpass-wsa-macro.c

123

#define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0)

sound/soc/codecs/lpass-wsa-macro.c

124

#define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2)

sound/soc/codecs/lpass-wsa-macro.c

182

#define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1)

sound/soc/codecs/lpass-wsa-macro.c

427

.rx_intx_1_mix_inp0_sel_mask = GENMASK(2, 0),

sound/soc/codecs/lpass-wsa-macro.c

428

.rx_intx_1_mix_inp1_sel_mask = GENMASK(5, 3),

sound/soc/codecs/lpass-wsa-macro.c

429

.rx_intx_1_mix_inp2_sel_mask = GENMASK(5, 3),

sound/soc/codecs/lpass-wsa-macro.c

430

.rx_intx_2_sel_mask = GENMASK(2, 0),

sound/soc/codecs/lpass-wsa-macro.c

437

.rx_intx_1_mix_inp0_sel_mask = GENMASK(3, 0),

sound/soc/codecs/lpass-wsa-macro.c

438

.rx_intx_1_mix_inp1_sel_mask = GENMASK(7, 4),

sound/soc/codecs/lpass-wsa-macro.c

439

.rx_intx_1_mix_inp2_sel_mask = GENMASK(7, 4),

sound/soc/codecs/lpass-wsa-macro.c

440

.rx_intx_2_sel_mask = GENMASK(3, 0),

sound/soc/codecs/lpass-wsa-macro.c

52

#define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3)

sound/soc/codecs/lpass-wsa-macro.c

54

#define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/lpass-wsa-macro.c

64

#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/max98363.c

239

port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);

sound/soc/codecs/max98373-sdw.c

548

port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);

sound/soc/codecs/msm8916-wcd-analog.c

100

#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)

sound/soc/codecs/msm8916-wcd-analog.c

110

#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)

sound/soc/codecs/msm8916-wcd-analog.c

160

#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)

sound/soc/codecs/msm8916-wcd-analog.c

165

#define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)

sound/soc/codecs/msm8916-wcd-analog.c

174

#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)

sound/soc/codecs/msm8916-wcd-analog.c

184

#define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)

sound/soc/codecs/msm8916-wcd-analog.c

185

#define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)

sound/soc/codecs/msm8916-wcd-analog.c

190

#define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)

sound/soc/codecs/msm8916-wcd-analog.c

58

#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)

sound/soc/codecs/msm8916-wcd-analog.c

64

#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)

sound/soc/codecs/msm8916-wcd-digital.c

162

#define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)

sound/soc/codecs/msm8916-wcd-digital.c

176

#define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/msm8916-wcd-digital.c

24

#define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)

sound/soc/codecs/msm8916-wcd-digital.c

37

#define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)

sound/soc/codecs/msm8916-wcd-digital.c

48

#define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

119

#define MT6357_DIVCKS_PWD_NCP_ST_SEL_MASK GENMASK(1, 0)

sound/soc/codecs/mt6357.h

212

#define MT6357_DCCLK_DIV_MASK GENMASK(15, 5)

sound/soc/codecs/mt6357.h

228

#define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK GENMASK(15, 8)

sound/soc/codecs/mt6357.h

231

#define MT6357_AUD_PAD_TX_FIFO_LPBK_MASK GENMASK(7, 0)

sound/soc/codecs/mt6357.h

236

#define MT6357_AUDADCLINPUTSEL_MASK GENMASK(14, 13)

sound/soc/codecs/mt6357.h

244

#define MT6357_AUDPREAMPLGAIN_MASK GENMASK(10, 8)

sound/soc/codecs/mt6357.h

247

#define MT6357_AUDPREAMPLINPUTSEL_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

259

#define MT6357_AUDADCRINPUTSEL_MASK GENMASK(14, 13)

sound/soc/codecs/mt6357.h

267

#define MT6357_AUDPREAMPRGAIN_MASK GENMASK(10, 8)

sound/soc/codecs/mt6357.h

270

#define MT6357_AUDPREAMPRINPUTSEL_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

285

#define MT6357_AUDDIGMICBIAS_MASK GENMASK(2, 1)

sound/soc/codecs/mt6357.h

311

#define MT6357_AUD_MICBIAS0_VREF_MASK GENMASK(6, 4)

sound/soc/codecs/mt6357.h

338

#define MT6357_AUD_MICBIAS1_VREF_MASK GENMASK(6, 4)

sound/soc/codecs/mt6357.h

349

#define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

351

#define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

379

#define MT6357_HPROUT_STG_CTRL_VAUDP15_MASK GENMASK(14, 12)

sound/soc/codecs/mt6357.h

381

#define MT6357_HPLOUT_STG_CTRL_VAUDP15_MASK GENMASK(10, 8)

sound/soc/codecs/mt6357.h

416

#define MT6357_HPROUT_STB_ENH_VAUDP15_MASK GENMASK(6, 4)

sound/soc/codecs/mt6357.h

42

#define MT6357_GPIO8_MODE_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

423

#define MT6357_HPLOUT_STB_ENH_VAUDP15_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

438

#define MT6357_AUD_HS_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

45

#define MT6357_GPIO9_MODE_MASK GENMASK(5, 3)

sound/soc/codecs/mt6357.h

454

#define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)

sound/soc/codecs/mt6357.h

464

#define MT6357_HP_AUX_LOOP_GAIN_MASK GENMASK(15, 12)

sound/soc/codecs/mt6357.h

48

#define MT6357_GPIO10_MODE_MASK GENMASK(8, 6)

sound/soc/codecs/mt6357.h

51

#define MT6357_GPIO11_MODE_MASK GENMASK(11, 9)

sound/soc/codecs/mt6357.h

538

#define MT6357_AUD_LOL_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/mt6357.h

540

#define MT6357_AUD_LOR_GAIN_MASK GENMASK(11, 7)

sound/soc/codecs/mt6357.h

545

#define MT6357_AUD_HPL_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/mt6357.h

547

#define MT6357_AUD_HPR_GAIN_MASK GENMASK(11, 7)

sound/soc/codecs/mt6357.h

552

#define MT6357_AUD_HS_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/mt6357.h

56

#define MT6357_GPIO8_MODE_SET_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

58

#define MT6357_GPIO9_MODE_SET_MASK GENMASK(5, 3)

sound/soc/codecs/mt6357.h

60

#define MT6357_GPIO10_MODE_SET_MASK GENMASK(8, 6)

sound/soc/codecs/mt6357.h

62

#define MT6357_GPIO11_MODE_SET_MASK GENMASK(11, 9)

sound/soc/codecs/mt6357.h

66

#define MT6357_GPIO_MODE2_CLEAR_ALL GENMASK(15, 0)

sound/soc/codecs/mt6357.h

69

#define MT6357_GPIO12_MODE_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

72

#define MT6357_GPIO13_MODE_MASK GENMASK(5, 3)

sound/soc/codecs/mt6357.h

75

#define MT6357_GPIO14_MODE_MASK GENMASK(8, 6)

sound/soc/codecs/mt6357.h

78

#define MT6357_GPIO15_MODE_MASK GENMASK(11, 9)

sound/soc/codecs/mt6357.h

83

#define MT6357_GPIO12_MODE_SET_MASK GENMASK(2, 0)

sound/soc/codecs/mt6357.h

85

#define MT6357_GPIO13_MODE_SET_MASK GENMASK(5, 3)

sound/soc/codecs/mt6357.h

87

#define MT6357_GPIO14_MODE_SET_MASK GENMASK(8, 6)

sound/soc/codecs/mt6357.h

89

#define MT6357_GPIO15_MODE_SET_MASK GENMASK(11, 9)

sound/soc/codecs/mt6357.h

93

#define MT6357_GPIO_MODE3_CLEAR_ALL GENMASK(15, 0)

sound/soc/codecs/ntp8835.c

37

#define NTP8835_GSA_BS_MASK GENMASK(3, 2)

sound/soc/codecs/ntp8835.c

42

#define NTP8835_MCLK_FREQ_MCF GENMASK(1, 0)

sound/soc/codecs/ntp8918.c

39

#define NTP8918_GSA_BS_MASK GENMASK(3, 2)

sound/soc/codecs/ntp8918.c

44

#define NTP8918_MCLK_FREQ_MCF GENMASK(1, 0)

sound/soc/codecs/pcm186x.h

146

#define PCM186X_ADC_INPUT_SEL_MASK GENMASK(5, 0)

sound/soc/codecs/pcm186x.h

149

#define PCM186X_PCM_CFG_RX_WLEN_MASK GENMASK(7, 6)

sound/soc/codecs/pcm186x.h

156

#define PCM186X_PCM_CFG_TX_WLEN_MASK GENMASK(3, 2)

sound/soc/codecs/pcm186x.h

162

#define PCM186X_PCM_CFG_FMT_MASK GENMASK(1, 0)

sound/soc/codecs/pm4125-sdw.c

405

pdev->prop.source_ports = GENMASK(PM4125_MAX_TX_SWR_PORTS, 0);

sound/soc/codecs/pm4125-sdw.c

421

pdev->prop.sink_ports = GENMASK(PM4125_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/pm4125.h

120

#define PM4125_DIG_SWR_TX_ANA_TXD1_MODE_MASK GENMASK(7, 4)

sound/soc/codecs/pm4125.h

121

#define PM4125_DIG_SWR_TX_ANA_TXD0_MODE_MASK GENMASK(3, 0)

sound/soc/codecs/pm4125.h

154

#define PM4125_WDT_ENABLE_MASK GENMASK(1, 0)

sound/soc/codecs/pm4125.h

23

#define PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK GENMASK(7, 3)

sound/soc/codecs/pm4125.h

37

#define PM4125_ANA_MBHC_BTN0_THRESHOLD_MASK GENMASK(7, 2)

sound/soc/codecs/pm4125.h

70

#define PM4125_ANA_HPHPA_FSM_DIV_RATIO_MASK GENMASK(6, 0)

sound/soc/codecs/pm4125.h

76

#define PM4125_SWR_HPHPA_HD2_LEFT_MASK GENMASK(5, 3)

sound/soc/codecs/pm4125.h

77

#define PM4125_SWR_HPHPA_HD2_RIGHT_MASK GENMASK(2, 0)

sound/soc/codecs/rk3328_codec.h

189

#define HPOUTL_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/rk3328_codec.h

192

#define HPOUTR_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/rk3328_codec.h

195

#define HPOUTR_POP_MASK GENMASK(5, 4)

sound/soc/codecs/rk3328_codec.h

198

#define HPOUTL_POP_MASK GENMASK(1, 0)

sound/soc/codecs/rk3328_codec.h

48

#define DAC_VDL_MASK GENMASK(6, 5)

sound/soc/codecs/rk3328_codec.h

53

#define DAC_MODE_MASK GENMASK(4, 3)

sound/soc/codecs/rk3328_codec.h

63

#define DAC_WL_MASK GENMASK(3, 2)

sound/soc/codecs/rk3328_codec.h

93

#define DAC_CHARGE_CURRENT_ALL_MASK GENMASK(6, 0)

sound/soc/codecs/rt1320-sdw.c

2665

dmic_port_config[0].ch_mask = GENMASK(num_channels - 1, 0);

sound/soc/codecs/rt712-sdca-dmic.c

657

port_config.ch_mask = GENMASK(num_channels - 1, 0);

sound/soc/codecs/rt712-sdca.c

1498

port_config.ch_mask = GENMASK(num_channels - 1, 0);

sound/soc/codecs/rt721-sdca.c

1317

port_config.ch_mask = GENMASK(num_channels - 1, 0);

sound/soc/codecs/rt722-sdca.c

1167

port_config.ch_mask = GENMASK(num_channels - 1, 0);

sound/soc/codecs/rt9120.c

34

#define RT9120_VID_MASK GENMASK(15, 8)

sound/soc/codecs/rt9120.c

36

#define RT9120_MUTE_MASK GENMASK(5, 4)

sound/soc/codecs/rt9120.c

37

#define RT9120_I2SFMT_MASK GENMASK(4, 2)

sound/soc/codecs/rt9120.c

44

#define RT9120_AUDBIT_MASK GENMASK(1, 0)

sound/soc/codecs/rt9120.c

48

#define RT9120_AUDWL_MASK GENMASK(5, 0)

sound/soc/codecs/rt9120.c

52

#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)

sound/soc/codecs/rt9123.c

40

#define RT9123_MASK_AUDBIT GENMASK(14, 12)

sound/soc/codecs/rt9123.c

41

#define RT9123_MASK_AUDFMT GENMASK(11, 8)

sound/soc/codecs/rt9123.c

42

#define RT9123_MASK_TDMRXLOC GENMASK(4, 0)

sound/soc/codecs/rt9123.c

43

#define RT9123_MASK_VENID GENMASK(15, 4)

sound/soc/codecs/rtq9124.c

48

#define RTQ9124_MASK_AUD_BITS GENMASK(5, 4)

sound/soc/codecs/rtq9124.c

49

#define RTQ9124_MASK_AUD_FMT GENMASK(3, 0)

sound/soc/codecs/rtq9124.c

50

#define RTQ9124_MASK_CH_STATE GENMASK(1, 0)

sound/soc/codecs/rtq9128.c

49

#define RTQ9128_CHSTAT_VAL_MASK GENMASK(1, 0)

sound/soc/codecs/rtq9128.c

50

#define RTQ9128_DOLEN_MASK GENMASK(7, 6)

sound/soc/codecs/rtq9128.c

51

#define RTQ9128_TDMSRCIN_MASK GENMASK(5, 4)

sound/soc/codecs/rtq9128.c

52

#define RTQ9128_AUDBIT_MASK GENMASK(5, 4)

sound/soc/codecs/rtq9128.c

53

#define RTQ9128_AUDFMT_MASK GENMASK(3, 0)

sound/soc/codecs/rtq9128.c

55

#define RTQ9128_DIE_CHECK_MASK GENMASK(4, 0)

sound/soc/codecs/rtq9128.c

56

#define RTQ9128_VENDOR_ID_MASK GENMASK(19, 8)

sound/soc/codecs/rtq9128.c

57

#define RTQ9128_MODEL_ID_MASK GENMASK(7, 4)

sound/soc/codecs/ssm3515.c

30

#define SSM3515_GEC_ANA_GAIN GENMASK(1, 0)

sound/soc/codecs/ssm3515.c

37

#define SSM3515_DAC_FS GENMASK(2, 0)

sound/soc/codecs/ssm3515.c

44

#define SSM3515_SAI1_TDM_BCLKS GENMASK(5, 3)

sound/soc/codecs/ssm3515.c

52

#define SSM3515_SAI2_TDM_SLOT GENMASK(3, 0)

sound/soc/codecs/tas2562.h

37

#define TAS2562_RX_OFF_MASK GENMASK(5, 1)

sound/soc/codecs/tas2562.h

38

#define TAS2562_TX_OFF_MASK GENMASK(3, 1)

sound/soc/codecs/tas2562.h

49

#define TAS2562_MODE_MASK GENMASK(1,0)

sound/soc/codecs/tas2562.h

59

#define TAS2562_TDM_CFG0_SAMPRATE_MASK GENMASK(3, 1)

sound/soc/codecs/tas2562.h

70

#define TAS2562_TDM_CFG2_RXLEN_MASK GENMASK(1, 0)

sound/soc/codecs/tas2562.h

75

#define TAS2562_TDM_CFG2_RXWLEN_MASK GENMASK(3, 2)

sound/soc/codecs/tas2562.h

85

#define TAS2562_TDM_CFG5_VSNS_SLOT_MASK GENMASK(5, 0)

sound/soc/codecs/tas2562.h

88

#define TAS2562_TDM_CFG6_ISNS_SLOT_MASK GENMASK(5, 0)

sound/soc/codecs/tas2764.h

103

#define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2764.h

28

#define TAS2764_PWR_CTRL_MASK GENMASK(2, 0)

sound/soc/codecs/tas2764.h

56

#define TAS2764_TDM_CFG0_MASK GENMASK(3, 1)

sound/soc/codecs/tas2764.h

63

#define TAS2764_TDM_CFG1_MASK GENMASK(5, 1)

sound/soc/codecs/tas2764.h

71

#define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2)

sound/soc/codecs/tas2764.h

75

#define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0)

sound/soc/codecs/tas2764.h

83

#define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4)

sound/soc/codecs/tas2764.h

85

#define TAS2764_TDM_CFG3_MASK GENMASK(3, 0)

sound/soc/codecs/tas2764.h

97

#define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2770.h

22

#define TAS2770_PWR_CTRL_MASK GENMASK(1, 0)

sound/soc/codecs/tas2770.h

40

#define TAS2770_TDM_CFG_REG0_31_MASK GENMASK(3, 1)

sound/soc/codecs/tas2770.h

49

#define TAS2770_TDM_CFG_REG1_MASK GENMASK(5, 1)

sound/soc/codecs/tas2770.h

56

#define TAS2770_TDM_CFG_REG2_RXW_MASK GENMASK(3, 2)

sound/soc/codecs/tas2770.h

60

#define TAS2770_TDM_CFG_REG2_RXS_MASK GENMASK(1, 0)

sound/soc/codecs/tas2770.h

66

#define TAS2770_TDM_CFG_REG3_RXS_MASK GENMASK(7, 4)

sound/soc/codecs/tas2770.h

68

#define TAS2770_TDM_CFG_REG3_30_MASK GENMASK(3, 0)

sound/soc/codecs/tas2770.h

74

#define TAS2770_TDM_CFG_REG5_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2770.h

79

#define TAS2770_TDM_CFG_REG6_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2770.h

84

#define TAS2770_TDM_CFG_REG7_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2780.h

28

#define TAS2780_PWR_CTRL_MASK GENMASK(1, 0)

sound/soc/codecs/tas2780.h

47

#define TAS2780_TDM_CFG0_MASK GENMASK(3, 1)

sound/soc/codecs/tas2780.h

53

#define TAS2780_TDM_CFG1_MASK GENMASK(5, 1)

sound/soc/codecs/tas2780.h

61

#define TAS2780_TDM_CFG2_RXW_MASK GENMASK(3, 2)

sound/soc/codecs/tas2780.h

65

#define TAS2780_TDM_CFG2_RXS_MASK GENMASK(1, 0)

sound/soc/codecs/tas2780.h

69

#define TAS2780_TDM_CFG2_SCFG_MASK GENMASK(5, 4)

sound/soc/codecs/tas2780.h

76

#define TAS2780_TDM_CFG3_RXS_MASK GENMASK(7, 4)

sound/soc/codecs/tas2780.h

78

#define TAS2780_TDM_CFG3_MASK GENMASK(3, 0)

sound/soc/codecs/tas2780.h

82

#define TAS2780_TDM_CFG4_TX_OFFSET_MASK GENMASK(3, 1)

sound/soc/codecs/tas2780.h

88

#define TAS2780_TDM_CFG5_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2780.h

94

#define TAS2780_TDM_CFG6_50_MASK GENMASK(5, 0)

sound/soc/codecs/tas2780.h

98

#define TAS2780_IC_CFG_MASK GENMASK(7, 6)

sound/soc/codecs/tas2783.h

35

#define TAS2783_AMP_LEVEL_MASK GENMASK(5, 1)

sound/soc/codecs/tas5720.h

100

#define TAS5720_CLIP1_MASK GENMASK(7, 2)

sound/soc/codecs/tas5720.h

112

#define TAS5722_HPF_MASK GENMASK(7, 5)

sound/soc/codecs/tas5720.h

117

#define TAS5722_AUTO_SLEEP_MASK GENMASK(4, 3)

sound/soc/codecs/tas5720.h

41

#define TAS5720_DIG_CLIP_MASK GENMASK(7, 2)

sound/soc/codecs/tas5720.h

55

#define TAS5720_SAIF_FORMAT_MASK GENMASK(2, 0)

sound/soc/codecs/tas5720.h

60

#define TAS5720_TDM_SLOT_SEL_MASK GENMASK(2, 0)

sound/soc/codecs/tas5720.h

64

#define TAS5720_Q1_MUTE GENMASK(1, 0)

sound/soc/codecs/tas5720.h

75

#define TAS5720_PWM_RATE_MASK GENMASK(6, 4)

sound/soc/codecs/tas5720.h

80

#define TAS5720_ANALOG_GAIN_MASK GENMASK(3, 2)

sound/soc/codecs/tas5720.h

92

#define TAS5720_OC_THRESH_MASK GENMASK(5, 4)

sound/soc/codecs/tas5720.h

97

#define TAS5720_FAULT_MASK GENMASK(3, 0)

sound/soc/codecs/tas6424.h

60

#define TAS6424_SAP_RATE_MASK GENMASK(7, 6)

sound/soc/codecs/tas6424.h

67

#define TAS6424_SAP_FMT_MASK GENMASK(2, 0)

sound/soc/codecs/tas6424.h

77

#define TAS6424_CH1_STATE_MASK GENMASK(7, 6)

sound/soc/codecs/tas6424.h

82

#define TAS6424_CH2_STATE_MASK GENMASK(5, 4)

sound/soc/codecs/tas6424.h

87

#define TAS6424_CH3_STATE_MASK GENMASK(3, 2)

sound/soc/codecs/tas6424.h

92

#define TAS6424_CH4_STATE_MASK GENMASK(1, 0)

sound/soc/codecs/tfa989x.c

21

#define TFA989X_REVISIONNUMBER_REV_MSK GENMASK(7, 0) /* device revision */

sound/soc/codecs/tfa989x.c

25

#define TFA989X_I2SREG_CHSA_MSK GENMASK(7, 6)

sound/soc/codecs/tfa989x.c

27

#define TFA989X_I2SREG_I2SSR_MSK GENMASK(15, 12)

sound/soc/codecs/tfa989x.c

41

#define TFA989X_I2S_SEL_REG_SPKR_MSK GENMASK(10, 9) /* speaker impedance */

sound/soc/codecs/tfa989x.c

42

#define TFA989X_I2S_SEL_REG_DCFG_MSK GENMASK(14, 11) /* DCDC compensation */

sound/soc/codecs/tlv320adcx140.c

898

if (tx_mask != GENMASK(__fls(tx_mask), 0)) {

sound/soc/codecs/tlv320adcx140.h

121

#define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4)

sound/soc/codecs/tlv320adcx140.h

127

#define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0)

sound/soc/codecs/tlv320adcx140.h

129

#define ADCX140_PWR_CTRL_MSK GENMASK(7, 5)

sound/soc/codecs/tlv320adcx140.h

134

#define ADCX140_TX_OFFSET_MASK GENMASK(4, 0)

sound/soc/codecs/tlv320aic31xx.h

118

#define AIC31XX_PLL_CLKIN_MASK GENMASK(3, 2)

sound/soc/codecs/tlv320aic31xx.h

124

#define AIC31XX_CODEC_CLKIN_MASK GENMASK(1, 0)

sound/soc/codecs/tlv320aic31xx.h

137

#define AIC31XX_PLL_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic31xx.h

141

#define AIC31XX_IFACE1_DATATYPE_MASK GENMASK(7, 6)

sound/soc/codecs/tlv320aic31xx.h

147

#define AIC31XX_IFACE1_DATALEN_MASK GENMASK(5, 4)

sound/soc/codecs/tlv320aic31xx.h

153

#define AIC31XX_IFACE1_MASTER_MASK GENMASK(3, 2)

sound/soc/codecs/tlv320aic31xx.h

158

#define AIC31XX_DATA_OFFSET_MASK GENMASK(7, 0)

sound/soc/codecs/tlv320aic31xx.h

162

#define AIC31XX_BDIVCLK_MASK GENMASK(1, 0)

sound/soc/codecs/tlv320aic31xx.h

206

#define AIC31XX_GPIO1_FUNC_MASK GENMASK(5, 2)

sound/soc/codecs/tlv320aic31xx.h

222

#define AIC31XX_DACMUTE_MASK GENMASK(3, 2)

sound/soc/codecs/tlv320aic31xx.h

226

#define AIC31XX_HSD_TYPE_MASK GENMASK(6, 5)

sound/soc/codecs/tlv320aic31xx.h

233

#define AIC31XX_HPD_OCMV_MASK GENMASK(4, 3)

sound/soc/codecs/tlv320aic31xx.h

241

#define AIC31XX_MICBIAS_MASK GENMASK(1, 0)

sound/soc/codecs/tlv320aic32x4.h

115

#define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2)

sound/soc/codecs/tlv320aic32x4.h

121

#define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0)

sound/soc/codecs/tlv320aic32x4.h

130

#define AIC32X4_PLL_P_MASK GENMASK(6, 4)

sound/soc/codecs/tlv320aic32x4.h

132

#define AIC32X4_PLL_R_MASK GENMASK(3, 0)

sound/soc/codecs/tlv320aic32x4.h

136

#define AIC32X4_NDAC_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic32x4.h

140

#define AIC32X4_MDAC_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic32x4.h

144

#define AIC32X4_NADC_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic32x4.h

148

#define AIC32X4_MADC_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic32x4.h

152

#define AIC32X4_BCLK_MASK GENMASK(6, 0)

sound/soc/codecs/tlv320aic32x4.h

155

#define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6)

sound/soc/codecs/tlv320aic32x4.h

161

#define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4)

sound/soc/codecs/tlv320aic32x4.h

167

#define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2)

sound/soc/codecs/tlv320aic32x4.h

172

#define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0)

sound/soc/codecs/tlv320aic32x4.h

176

#define AIC32X4_BDIVCLK_MASK GENMASK(1, 0)

sound/soc/codecs/tlv320aic32x4.h

184

#define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2)

sound/soc/codecs/tlv320aic32x4.h

210

#define AIC32x4_MICBIAS_MASK GENMASK(6, 3)

sound/soc/codecs/tlv320aic32x4.h

228

#define AIC32X4_DIV_MASK GENMASK(6, 0)

sound/soc/codecs/wcd-clsh-v2.c

30

#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0)

sound/soc/codecs/wcd-clsh-v2.c

32

#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0)

sound/soc/codecs/wcd-clsh-v2.c

52

#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2)

sound/soc/codecs/wcd-clsh-v2.c

61

#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5)

sound/soc/codecs/wcd-clsh-v2.c

67

#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)

sound/soc/codecs/wcd-clsh-v2.c

68

#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)

sound/soc/codecs/wcd-clsh-v2.c

70

#define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3)

sound/soc/codecs/wcd-clsh-v2.c

76

#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0)

sound/soc/codecs/wcd-clsh-v2.c

78

#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4)

sound/soc/codecs/wcd-clsh-v2.c

87

#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4)

sound/soc/codecs/wcd9335.h

18

#define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

219

#define WCD9335_ANA_BUCK_VOUT_MASK GENMASK(7, 0)

sound/soc/codecs/wcd9335.h

22

#define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

258

#define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd9335.h

259

#define WCD9335_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4)

sound/soc/codecs/wcd9335.h

267

#define WCD9335_MBHC_BTN_RESULT_MASK GENMASK(2, 0)

sound/soc/codecs/wcd9335.h

27

#define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1)

sound/soc/codecs/wcd9335.h

294

#define WCD9335_MBHC_BTN_DBNC_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

300

#define WCD9335_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

303

#define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK GENMASK(7, 6)

sound/soc/codecs/wcd9335.h

312

#define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK GENMASK(3, 0)

sound/soc/codecs/wcd9335.h

316

#define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)

sound/soc/codecs/wcd9335.h

318

#define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)

sound/soc/codecs/wcd9335.h

321

#define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK GENMASK(2, 0)

sound/soc/codecs/wcd9335.h

330

#define WCD9335_HPH_PA_GM3_IB_SCALE_MASK GENMASK(3, 1)

sound/soc/codecs/wcd9335.h

342

#define WCD9335_HPH_CONST_SEL_L_MASK GENMASK(7, 6)

sound/soc/codecs/wcd9335.h

346

#define WCD9335_HPH_PA_GAIN_MASK GENMASK(4, 0)

sound/soc/codecs/wcd9335.h

355

#define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK GENMASK(2, 0)

sound/soc/codecs/wcd9335.h

357

#define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd9335.h

379

#define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd9335.h

449

#define WCD9335_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd9335.h

475

#define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

478

#define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2)

sound/soc/codecs/wcd9335.h

489

#define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK GENMASK(1, 0)

sound/soc/codecs/wcd9335.h

552

#define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0)

sound/soc/codecs/wcd937x-sdw.c

1023

pdev->prop.source_ports = GENMASK(WCD937X_MAX_TX_SWR_PORTS, 0);

sound/soc/codecs/wcd937x-sdw.c

1040

pdev->prop.sink_ports = GENMASK(WCD937X_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/wcd937x.h

18

#define WCD937X_EAR_GAIN_MASK GENMASK(6, 2)

sound/soc/codecs/wcd937x.h

229

#define WCD937X_MBHC_BTN_DBNC_MASK GENMASK(1, 0)

sound/soc/codecs/wcd937x.h

234

#define WCD937X_M_RTH_CTL_MASK GENMASK(3, 2)

sound/soc/codecs/wcd937x.h

235

#define WCD937X_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0)

sound/soc/codecs/wcd937x.h

238

#define WCD937X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)

sound/soc/codecs/wcd937x.h

239

#define WCD937X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd937x.h

271

#define WCD937X_HSDET_PULLUP_C_MASK GENMASK(4, 0)

sound/soc/codecs/wcd937x.h

39

#define WCD937X_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd937x.h

398

#define WCD937X_DIGITAL_PDM_WD_CTL2_MASK GENMASK(2, 0)

sound/soc/codecs/wcd937x.h

40

#define WCD937X_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4)

sound/soc/codecs/wcd937x.h

48

#define WCD937X_MBHC_BTN_RESULT_MASK GENMASK(2, 0)

sound/soc/codecs/wcd937x.h

50

#define WCD937X_MBHC_BTN_VTH_MASK GENMASK(7, 2)

sound/soc/codecs/wcd937x.h

56

#define WCD937X_VTH_MASK GENMASK(7, 2)

sound/soc/codecs/wcd937x.h

60

#define WCD937X_MICB_VOUT_MASK GENMASK(5, 0)

sound/soc/codecs/wcd937x.h

61

#define WCD937X_MICB_EN_MASK GENMASK(7, 6)

sound/soc/codecs/wcd937x.h

68

#define WCD937X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)

sound/soc/codecs/wcd937x.h

69

#define WCD937X_ANA_MICB2_VOUT_MASK GENMASK(5, 0)

sound/soc/codecs/wcd937x.h

72

#define WCD937X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)

sound/soc/codecs/wcd937x.h

74

#define WCD937X_ANA_MICB_EN GENMASK(7, 6)

sound/soc/codecs/wcd937x.h

78

#define WCD937X_ANA_MICB_VOUT GENMASK(5, 0)

sound/soc/codecs/wcd938x-sdw.c

1190

pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/wcd938x-sdw.c

1195

pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/wcd938x.h

24

#define WCD938X_EAR_GAIN_MASK GENMASK(6, 2)

sound/soc/codecs/wcd938x.h

245

#define WCD938X_MBHC_BTN_DBNC_MASK GENMASK(1, 0)

sound/soc/codecs/wcd938x.h

248

#define WCD938X_M_RTH_CTL_MASK GENMASK(3, 2)

sound/soc/codecs/wcd938x.h

249

#define WCD938X_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0)

sound/soc/codecs/wcd938x.h

255

#define WCD938X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)

sound/soc/codecs/wcd938x.h

256

#define WCD938X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd938x.h

272

#define WCD938X_HPH_RES_DIV_MASK GENMASK(4, 0)

sound/soc/codecs/wcd938x.h

292

#define WCD938X_HSDET_PULLUP_C_MASK GENMASK(4, 0)

sound/soc/codecs/wcd938x.h

355

#define WCD938X_TX_CLK_EN_MASK GENMASK(7, 4)

sound/soc/codecs/wcd938x.h

367

#define WCD938X_TXD0_MODE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd938x.h

368

#define WCD938X_TXD1_MODE_MASK GENMASK(7, 4)

sound/soc/codecs/wcd938x.h

370

#define WCD938X_TXD2_MODE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd938x.h

371

#define WCD938X_TXD3_MODE_MASK GENMASK(7, 4)

sound/soc/codecs/wcd938x.h

455

#define WCD938X_DMIC_CLK_SCALING_EN_MASK GENMASK(2, 1)

sound/soc/codecs/wcd938x.h

465

#define WCD938X_DMIC1_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd938x.h

466

#define WCD938X_DMIC2_RATE_MASK GENMASK(7, 4)

sound/soc/codecs/wcd938x.h

467

#define WCD938X_DMIC3_RATE_MASK GENMASK(3, 0)

sound/soc/codecs/wcd938x.h

468

#define WCD938X_DMIC4_RATE_MASK GENMASK(7, 4)

sound/soc/codecs/wcd938x.h

472

#define WCD938X_PDM_WD_EN_MASK GENMASK(2, 0)

sound/soc/codecs/wcd938x.h

475

#define WCD938X_AUX_PDM_WD_EN_MASK GENMASK(2, 0)

sound/soc/codecs/wcd938x.h

50

#define WCD938X_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4)

sound/soc/codecs/wcd938x.h

51

#define WCD938X_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4)

sound/soc/codecs/wcd938x.h

545

#define WCD938X_ID_MASK GENMASK(4, 1)

sound/soc/codecs/wcd938x.h

59

#define WCD938X_MBHC_BTN_RESULT_MASK GENMASK(2, 0)

sound/soc/codecs/wcd938x.h

61

#define WCD938X_MBHC_BTN_VTH_MASK GENMASK(7, 2)

sound/soc/codecs/wcd938x.h

67

#define WCD938X_VTH_MASK GENMASK(7, 2)

sound/soc/codecs/wcd938x.h

71

#define WCD938X_MICB_VOUT_MASK GENMASK(5, 0)

sound/soc/codecs/wcd938x.h

72

#define WCD938X_MICB_EN_MASK GENMASK(7, 6)

sound/soc/codecs/wcd938x.h

80

#define WCD938X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)

sound/soc/codecs/wcd939x-sdw.c

1376

pdev->prop.source_ports = GENMASK(WCD939X_MAX_TX_SWR_PORTS - 1, 0);

sound/soc/codecs/wcd939x-sdw.c

1381

pdev->prop.sink_ports = GENMASK(WCD939X_MAX_RX_SWR_PORTS - 1, 0);

sound/soc/codecs/wcd939x.c

2156

q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10));

sound/soc/codecs/wcd939x.h

101

#define WCD939X_MICB2_RAMP_SHIFT_CTL GENMASK(4, 2)

sound/soc/codecs/wcd939x.h

102

#define WCD939X_MICB2_RAMP_USB_MGDET_MICB2_RAMP GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

120

#define WCD939X_MODE_VOUT_ADJUST GENMASK(4, 3)

sound/soc/codecs/wcd939x.h

121

#define WCD939X_MODE_VOUT_COARSE_ADJ GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

126

#define WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL GENMASK(7, 5)

sound/soc/codecs/wcd939x.h

129

#define WCD939X_TEST_CTL_1_LDO_BLEEDER_I_CTRL GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

131

#define WCD939X_TEST_CTL_2_IBIAS_VREFGEN GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

133

#define WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

136

#define WCD939X_TEST_CTL_3_RZ_LDO_VAL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

137

#define WCD939X_TEST_CTL_3_IBIAS_LDO_STG3 GENMASK(3, 2)

sound/soc/codecs/wcd939x.h

138

#define WCD939X_TEST_CTL_3_ATEST_CTRL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

178

#define WCD939X_TEST_BLK_EN2_ADC12_VREF_NONL2 GENMASK(2, 1)

sound/soc/codecs/wcd939x.h

203

#define WCD939X_VNEG_CTRL_4_ILIM_SEL GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

204

#define WCD939X_VNEG_CTRL_4_PW_BUF_POS GENMASK(3, 2)

sound/soc/codecs/wcd939x.h

205

#define WCD939X_VNEG_CTRL_4_PW_BUF_NEG GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

244

#define WCD939X_OCP_CTL_OCP_CURR_LIMIT GENMASK(7, 5)

sound/soc/codecs/wcd939x.h

254

#define WCD939X_PA_CTL2_GM3_CASCODE_CTL_NORMAL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

256

#define WCD939X_L_EN_CONST_SEL_L GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

258

#define WCD939X_L_EN_SPARE_BITS GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

262

#define WCD939X_R_EN_CONST_SEL_R GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

264

#define WCD939X_R_EN_SPARE_BITS GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

275

#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

276

#define WCD939X_RDAC_CLK_CTL1_SPARE_BITS GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

281

#define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

284

#define WCD939X_REFBUFF_UHQA_CTL_REFBUFP_IOUT_CTL GENMASK(3, 2)

sound/soc/codecs/wcd939x.h

285

#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_IOUT_CTL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

287

#define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

288

#define WCD939X_REFBUFF_LP_CTL_SPARE_BITS GENMASK(5, 4)

sound/soc/codecs/wcd939x.h

290

#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL GENMASK(2, 1)

sound/soc/codecs/wcd939x.h

298

#define WCD939X_EN_SEL_SURGE_COMP_IQ GENMASK(5, 4)

sound/soc/codecs/wcd939x.h

30

#define WCD939X_HPH_PWR_LEVEL GENMASK(3, 2)

sound/soc/codecs/wcd939x.h

311

#define WCD939X_DAC_CON_REF_DBG_GAIN GENMASK(5, 3)

sound/soc/codecs/wcd939x.h

312

#define WCD939X_DAC_CON_GAIN_DAC GENMASK(2, 1)

sound/soc/codecs/wcd939x.h

332

#define WCD939X_CTL_1_BTN_DBNC_CTL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

334

#define WCD939X_CTL_2_MUX_CTL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

335

#define WCD939X_CTL_2_M_RTH_CTL GENMASK(3, 2)

sound/soc/codecs/wcd939x.h

336

#define WCD939X_CTL_2_HS_VREF_CTL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

34

#define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN GENMASK(6, 2)

sound/soc/codecs/wcd939x.h

340

#define WCD939X_ZDET_ANA_CTL_MAXV_CTL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

341

#define WCD939X_ZDET_ANA_CTL_RANGE_CTL GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

343

#define WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

344

#define WCD939X_ZDET_RAMP_CTL_TIME_CTL GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

355

#define WCD939X_ADC_RESULT_VALUE GENMASK(7, 0)

sound/soc/codecs/wcd939x.h

365

#define WCD939X_PA_GAIN_CTL_L_VALUE GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

370

#define WCD939X_PA_GAIN_CTL_R_SPARE_BITS GENMASK(6, 5)

sound/soc/codecs/wcd939x.h

371

#define WCD939X_PA_GAIN_CTL_R_VALUE GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

376

#define WCD939X_TIMER1_CURR_IDIV_CTL_CMPDR_OFF GENMASK(7, 5)

sound/soc/codecs/wcd939x.h

377

#define WCD939X_TIMER1_CURR_IDIV_CTL_AUTOCHOP GENMASK(4, 2)

sound/soc/codecs/wcd939x.h

387

#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L GENMASK(5, 0)

sound/soc/codecs/wcd939x.h

391

#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R GENMASK(5, 0)

sound/soc/codecs/wcd939x.h

396

#define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT GENMASK(6, 5)

sound/soc/codecs/wcd939x.h

397

#define WCD939X_MOISTURE_DET_DC_CTRL_OFFCOUNT GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

400

#define WCD939X_MOISTURE_DET_POLLING_CTRL_DTEST_EN GENMASK(5, 4)

sound/soc/codecs/wcd939x.h

403

#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_DBNC_TIME GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

405

#define WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

42

#define WCD939X_TX_CH2_GAIN GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

426

#define WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

429

#define WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

430

#define WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

468

#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

469

#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

471

#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

472

#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

48

#define WCD939X_TX_CH4_GAIN GENMASK(4, 0)

sound/soc/codecs/wcd939x.h

547

#define WCD939X_CDC_SWR_CLH_CLH_CTL GENMASK(7, 0)

sound/soc/codecs/wcd939x.h

572

#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

574

#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SEL GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

577

#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

579

#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SEL GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

581

#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

583

#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SEL GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

585

#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

587

#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SEL GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

591

#define WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

592

#define WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

594

#define WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE GENMASK(7, 4)

sound/soc/codecs/wcd939x.h

595

#define WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE GENMASK(3, 0)

sound/soc/codecs/wcd939x.h

599

#define WCD939X_PDM_WD_CTL0_PDM_WD_EN GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

603

#define WCD939X_PDM_WD_CTL1_PDM_WD_EN GENMASK(2, 0)

sound/soc/codecs/wcd939x.h

62

#define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL GENMASK(6, 4)

sound/soc/codecs/wcd939x.h

64

#define WCD939X_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL GENMASK(2, 1)

sound/soc/codecs/wcd939x.h

674

#define WCD939X_EFUSE_REG_0_WCD939X_ID GENMASK(4, 1)

sound/soc/codecs/wcd939x.h

73

#define WCD939X_MBHC_RESULT_1_Z_RESULT_LSB GENMASK(7, 0)

sound/soc/codecs/wcd939x.h

75

#define WCD939X_MBHC_RESULT_2_Z_RESULT_MSB GENMASK(7, 0)

sound/soc/codecs/wcd939x.h

760

#define WCD939X_HPHL_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

769

#define WCD939X_HPHR_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0)

sound/soc/codecs/wcd939x.h

78

#define WCD939X_MBHC_BTN0_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

80

#define WCD939X_MBHC_BTN1_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

82

#define WCD939X_MBHC_BTN2_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

84

#define WCD939X_MBHC_BTN3_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

86

#define WCD939X_MBHC_BTN4_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

88

#define WCD939X_MBHC_BTN5_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

90

#define WCD939X_MBHC_BTN6_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

92

#define WCD939X_MBHC_BTN7_VTH GENMASK(7, 2)

sound/soc/codecs/wcd939x.h

94

#define WCD939X_MICB_ENABLE GENMASK(7, 6)

sound/soc/codecs/wcd939x.h

95

#define WCD939X_MICB_VOUT_CTL GENMASK(5, 0)

sound/soc/codecs/wsa881x.c

1157

pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/wsa881x.c

136

#define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4)

sound/soc/codecs/wsa881x.c

141

#define WSA881X_SPKR_OCP_MASK GENMASK(7, 6)

sound/soc/codecs/wsa883x.c

1639

pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS - 1, 0);

sound/soc/codecs/wsa883x.c

190

#define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)

sound/soc/codecs/wsa883x.c

261

#define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)

sound/soc/codecs/wsa883x.c

262

#define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)

sound/soc/codecs/wsa883x.c

329

#define WSA883X_ID_MASK GENMASK(3, 0)

sound/soc/codecs/wsa884x.c

2095

pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS - 1, 0);

sound/soc/dwc/local.h

82

#define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)

sound/soc/dwc/local.h

83

#define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)

sound/soc/dwc/local.h

84

#define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)

sound/soc/dwc/local.h

85

#define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)

sound/soc/dwc/local.h

86

#define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)

sound/soc/dwc/local.h

87

#define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)

sound/soc/dwc/local.h

91

#define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)

sound/soc/dwc/local.h

92

#define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)

sound/soc/dwc/local.h

94

#define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)

sound/soc/dwc/local.h

95

#define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)

sound/soc/dwc/local.h

96

#define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)

sound/soc/dwc/local.h

97

#define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)

sound/soc/fsl/fsl_easrc.c

105

GENMASK(31, 0), regval, &changed);

sound/soc/fsl/fsl_micfil.h

101

#define MICFIL_PARAM_NUM_HWVAD_MASK GENMASK(27, 24)

sound/soc/fsl/fsl_micfil.h

110

#define MICFIL_PARAM_FIFO_PTRWID_MASK GENMASK(7, 4)

sound/soc/fsl/fsl_micfil.h

112

#define MICFIL_PARAM_NPAIR_MASK GENMASK(3, 0)

sound/soc/fsl/fsl_micfil.h

115

#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)

sound/soc/fsl/fsl_micfil.h

116

#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)

sound/soc/fsl/fsl_micfil.h

117

#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)

sound/soc/fsl/fsl_micfil.h

128

#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)

sound/soc/fsl/fsl_micfil.h

129

#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)

sound/soc/fsl/fsl_micfil.h

130

#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)

sound/soc/fsl/fsl_micfil.h

135

#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)

sound/soc/fsl/fsl_micfil.h

142

#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)

sound/soc/fsl/fsl_micfil.h

143

#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)

sound/soc/fsl/fsl_micfil.h

146

#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)

sound/soc/fsl/fsl_micfil.h

147

#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)

sound/soc/fsl/fsl_micfil.h

51

#define MICFIL_CTRL1_DISEL GENMASK(25, 24)

sound/soc/fsl/fsl_micfil.h

58

#define MICFIL_CTRL2_QSEL GENMASK(27, 25)

sound/soc/fsl/fsl_micfil.h

66

#define MICFIL_CTRL2_CICOSR GENMASK(20, 16)

sound/soc/fsl/fsl_micfil.h

67

#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)

sound/soc/fsl/fsl_micfil.h

76

#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(4, 0)

sound/soc/fsl/fsl_micfil.h

83

#define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0)

sound/soc/fsl/fsl_micfil.h

85

#define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) << 1))

sound/soc/fsl/fsl_micfil.h

93

#define MICFIL_VERID_MAJOR_MASK GENMASK(31, 24)

sound/soc/fsl/fsl_micfil.h

95

#define MICFIL_VERID_MINOR_MASK GENMASK(23, 16)

sound/soc/fsl/fsl_micfil.h

97

#define MICFIL_VERID_FEATURE_MASK GENMASK(15, 0)

sound/soc/fsl/fsl_mqs.c

385

.div_mask = GENMASK(15, 8),

sound/soc/fsl/fsl_mqs.c

399

.div_mask = GENMASK(15, 8),

sound/soc/fsl/fsl_mqs.c

412

.div_mask = GENMASK(16, 9),

sound/soc/fsl/fsl_mqs.c

426

.div_mask = GENMASK(15, 8),

sound/soc/fsl/fsl_mqs.c

440

.div_mask = GENMASK(15, 8),

sound/soc/fsl/fsl_sai.h

135

#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)

sound/soc/fsl/fsl_sai.h

180

#define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)

sound/soc/fsl/fsl_sai.h

182

#define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16)

sound/soc/fsl/fsl_sai.h

184

#define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0)

sound/soc/fsl/fsl_sai.h

190

#define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16)

sound/soc/fsl/fsl_sai.h

192

#define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8)

sound/soc/fsl/fsl_sai.h

193

#define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0)

sound/soc/fsl/fsl_xcvr.h

113

#define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0)

sound/soc/fsl/fsl_xcvr.h

117

#define FSL_XCVR_EXT_CTRL_RX_FWM_MASK GENMASK(14, 8)

sound/soc/fsl/fsl_xcvr.h

121

#define FSL_XCVR_EXT_CTRL_PAGE_MASK GENMASK(19, 16)

sound/soc/fsl/fsl_xcvr.h

125

#define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0)

sound/soc/fsl/fsl_xcvr.h

126

#define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8)

sound/soc/fsl/fsl_xcvr.h

184

#define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0)

sound/soc/fsl/fsl_xcvr.h

217

#define FSL_XCVR_RX_DPTH_CTRL_FSM GENMASK(31, 30)

sound/soc/fsl/fsl_xcvr.h

234

#define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30)

sound/soc/fsl/fsl_xcvr.h

279

#define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25)

sound/soc/fsl/fsl_xcvr.h

284

#define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31, 24)

sound/soc/fsl/fsl_xcvr.h

392

#define FSL_XCVR_GP_PLL_NUMERATOR_MFN GENMASK(31, 2)

sound/soc/fsl/fsl_xcvr.h

395

#define FSL_XCVR_GP_PLL_DENOMINATOR_MFD GENMASK(29, 0)

sound/soc/fsl/fsl_xcvr.h

399

#define FSL_XCVR_GP_PLL_DIV_MFI GENMASK(24, 16)

sound/soc/fsl/fsl_xcvr.h

400

#define FSL_XCVR_GP_PLL_DIV_RDIV GENMASK(15, 13)

sound/soc/fsl/fsl_xcvr.h

401

#define FSL_XCVR_GP_PLL_DIV_ODIV GENMASK(7, 0)

sound/soc/intel/avs/board_selection.c

71

#define AVS_SSP_RANGE(a, b) (GENMASK(b, a))

sound/soc/intel/avs/boards/rt5682.c

26

#define AVS_RT5682_SSP_CODEC(quirk) ((quirk) & GENMASK(2, 0))

sound/soc/intel/avs/boards/rt5682.c

27

#define AVS_RT5682_SSP_CODEC_MASK (GENMASK(2, 0))

sound/soc/intel/avs/cldma.c

16

#define AZX_SD_CTL_STRM_MASK GENMASK(23, 20)

sound/soc/intel/avs/cldma.c

18

#define AZX_SD_BDLPL_BDLPLBA_MASK GENMASK(31, 7)

sound/soc/intel/avs/core.c

577

avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0));

sound/soc/intel/avs/ipc.c

137

core_mask = GENMASK(adev->hw_cfg.dsp_cores - 1, 0);

sound/soc/intel/avs/mtl.c

24

#define MTL_DSPCCTL_OSEL GENMASK(25, 24)

sound/soc/intel/avs/mtl.c

30

#define MTL_HfINTIPPTR_PTR GENMASK(20, 0)

sound/soc/intel/avs/ptl.c

22

#define MTL_DSPCCTL_OSEL GENMASK(25, 24)

sound/soc/intel/boards/bytcht_es8316.c

50

#define BYT_CHT_ES8316_MAP_MASK GENMASK(3, 0)

sound/soc/intel/boards/bytcr_rt5640.c

71

#define BYT_RT5640_MAP_MASK GENMASK(3, 0)

sound/soc/intel/boards/bytcr_rt5640.c

73

#define BYT_RT5640_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4)

sound/soc/intel/boards/bytcr_rt5640.c

74

#define BYT_RT5640_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8)

sound/soc/intel/boards/bytcr_rt5640.c

75

#define BYT_RT5640_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13)

sound/soc/intel/boards/bytcr_rt5651.c

61

#define BYT_RT5651_MAP_MASK GENMASK(3, 0)

sound/soc/intel/boards/bytcr_rt5651.c

63

#define BYT_RT5651_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4)

sound/soc/intel/boards/bytcr_rt5651.c

64

#define BYT_RT5651_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8)

sound/soc/intel/boards/bytcr_rt5651.c

65

#define BYT_RT5651_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13)

sound/soc/intel/boards/bytcr_wm5102.c

41

#define BYT_WM5102_IN_MAP GENMASK(3, 0)

sound/soc/intel/boards/bytcr_wm5102.c

42

#define BYT_WM5102_OUT_MAP GENMASK(7, 4)

sound/soc/intel/boards/cht_bsw_rt5645.c

46

#define CHT_RT5645_MAP(quirk) ((quirk) & GENMASK(7, 0))

sound/soc/intel/boards/sof_board_helpers.h

20

#define SOF_SSP_PORT_CODEC_MASK (GENMASK(10, 8))

sound/soc/intel/boards/sof_board_helpers.h

26

#define SOF_SSP_PORT_AMP_MASK (GENMASK(13, 11))

sound/soc/intel/boards/sof_board_helpers.h

32

#define SOF_SSP_PORT_BT_OFFLOAD_MASK (GENMASK(16, 14))

sound/soc/intel/boards/sof_board_helpers.h

38

#define SOF_SSP_MASK_HDMI_CAPTURE_MASK (GENMASK(22, 17))

sound/soc/intel/boards/sof_board_helpers.h

44

#define SOF_NUM_IDISP_HDMI_MASK (GENMASK(25, 23))

sound/soc/intel/boards/sof_es8336.c

27

#define SOF_ES8336_SSP_CODEC(quirk) ((quirk) & GENMASK(3, 0))

sound/soc/intel/boards/sof_es8336.c

28

#define SOF_ES8336_SSP_CODEC_MASK (GENMASK(3, 0))

sound/soc/intel/boards/sof_es8336.c

35

#define SOF_NO_OF_HDMI_CAPTURE_SSP_MASK (GENMASK(16, 15))

sound/soc/intel/boards/sof_es8336.c

40

#define SOF_HDMI_CAPTURE_1_SSP_MASK (GENMASK(9, 7))

sound/soc/intel/boards/sof_es8336.c

45

#define SOF_HDMI_CAPTURE_2_SSP_MASK (GENMASK(12, 10))

sound/soc/intel/boards/sof_pcm512x.c

27

#define SOF_PCM512X_SSP_CODEC(quirk) ((quirk) & GENMASK(3, 0))

sound/soc/intel/boards/sof_pcm512x.c

28

#define SOF_PCM512X_SSP_CODEC_MASK (GENMASK(3, 0))

sound/soc/intel/boards/sof_sdw_common.h

43

#define SOF_SSP_PORT(x) (((x) & GENMASK(5, 0)) << 7)

sound/soc/intel/boards/sof_sdw_common.h

44

#define SOF_SSP_GET_PORT(quirk) (((quirk) >> 7) & GENMASK(5, 0))

sound/soc/intel/boards/sof_sdw_common.h

50

#define SOF_BT_OFFLOAD_SSP_MASK (GENMASK(20, 18))

sound/soc/intel/catpt/dsp.c

198

new |= GENMASK(h, l);

sound/soc/intel/catpt/dsp.c

27

#define CATPT_DMA_DSP_ADDR_MASK GENMASK(31, 20)

sound/soc/intel/catpt/pcm.c

178

return GENMASK(31, 4) | CATPT_CHANNEL_CENTER;

sound/soc/intel/catpt/pcm.c

181

return GENMASK(31, 8) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

185

return GENMASK(31, 12) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

190

return GENMASK(31, 12) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

195

return GENMASK(31, 16) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

201

return GENMASK(31, 16) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

207

return GENMASK(31, 16) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

213

return GENMASK(31, 20) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/pcm.c

220

return GENMASK(31, 24) | CATPT_CHANNEL_CENTER

sound/soc/intel/catpt/pcm.c

228

return GENMASK(31, 8) | CATPT_CHANNEL_LEFT

sound/soc/intel/catpt/registers.h

105

#define WPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 12)

sound/soc/intel/catpt/registers.h

107

#define WPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(11, 2)

sound/soc/intel/catpt/registers.h

41

#define CATPT_CS_DCS GENMASK(6, 4)

sound/soc/intel/catpt/registers.h

64

#define CATPT_CLKCTL_SMOS GENMASK(25, 24)

sound/soc/intel/catpt/registers.h

95

#define LPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 16)

sound/soc/intel/catpt/registers.h

97

#define LPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(15, 6)

sound/soc/intel/common/soc-acpi-intel-cnl-match.c

71

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-lnl-match.c

692

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-lnl-match.c

704

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-lnl-match.c

716

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-lnl-match.c

766

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-lnl-match.c

772

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1194

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1206

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1218

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1224

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1236

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1263

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1283

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-mtl-match.c

1322

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-nvl-match.c

22

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-nvl-match.c

34

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-ptl-match.c

621

.link_mask = GENMASK(3, 0),

sound/soc/intel/common/soc-acpi-intel-ptl-match.c

633

.link_mask = GENMASK(2, 0),

sound/soc/intel/common/soc-acpi-intel-tgl-match.c

731

.link_mask = GENMASK(3, 0),

sound/soc/intel/keembay/kmb_platform.h

65

#define TX_INT_FLAG GENMASK(5, 4)

sound/soc/intel/keembay/kmb_platform.h

66

#define RX_INT_FLAG GENMASK(1, 0)

sound/soc/intel/keembay/kmb_platform.h

71

#define COMP1_TX_WORDSIZE_3(r) FIELD_GET(GENMASK(27, 25), (r))

sound/soc/intel/keembay/kmb_platform.h

72

#define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r))

sound/soc/intel/keembay/kmb_platform.h

73

#define COMP1_TX_WORDSIZE_1(r) FIELD_GET(GENMASK(21, 19), (r))

sound/soc/intel/keembay/kmb_platform.h

74

#define COMP1_TX_WORDSIZE_0(r) FIELD_GET(GENMASK(18, 16), (r))

sound/soc/intel/keembay/kmb_platform.h

78

#define COMP1_APB_DATA_WIDTH(r) FIELD_GET(GENMASK(1, 0), (r))

sound/soc/intel/keembay/kmb_platform.h

79

#define COMP2_RX_WORDSIZE_3(r) FIELD_GET(GENMASK(12, 10), (r))

sound/soc/intel/keembay/kmb_platform.h

80

#define COMP2_RX_WORDSIZE_2(r) FIELD_GET(GENMASK(9, 7), (r))

sound/soc/intel/keembay/kmb_platform.h

81

#define COMP2_RX_WORDSIZE_1(r) FIELD_GET(GENMASK(5, 3), (r))

sound/soc/intel/keembay/kmb_platform.h

82

#define COMP2_RX_WORDSIZE_0(r) FIELD_GET(GENMASK(2, 0), (r))

sound/soc/intel/keembay/kmb_platform.h

85

#define COMP1_TX_CHANNELS(r) (FIELD_GET(GENMASK(10, 9), (r)) + 1)

sound/soc/intel/keembay/kmb_platform.h

86

#define COMP1_RX_CHANNELS(r) (FIELD_GET(GENMASK(8, 7), (r)) + 1)

sound/soc/intel/keembay/kmb_platform.h

87

#define COMP1_FIFO_DEPTH(r) (FIELD_GET(GENMASK(3, 2), (r)) + 1)

sound/soc/jz4740/jz4740-i2s.c

291

i2sdiv_max = GENMASK(i2s->soc_info->field_i2sdiv_playback.msb,

sound/soc/jz4740/jz4740-i2s.c

298

i2sdiv_max = GENMASK(i2s->soc_info->field_i2sdiv_capture.msb,

sound/soc/jz4740/jz4740-i2s.c

42

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19)

sound/soc/jz4740/jz4740-i2s.c

43

#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16)

sound/soc/loongson/loongson1_ac97.c

36

#define M_FIFO_THRES GENMASK(21, 20)

sound/soc/loongson/loongson1_ac97.c

40

#define M_SW GENMASK(19, 18)

sound/soc/loongson/loongson1_ac97.c

47

#define R_FIFO_THRES GENMASK(13, 12)

sound/soc/loongson/loongson1_ac97.c

51

#define R_SW GENMASK(11, 10)

sound/soc/loongson/loongson1_ac97.c

58

#define L_FIFO_THRES GENMASK(5, 4)

sound/soc/loongson/loongson1_ac97.c

62

#define L_SW GENMASK(3, 2)

sound/soc/loongson/loongson1_ac97.c

70

#define CODEC_ADR GENMASK(22, 16)

sound/soc/loongson/loongson1_ac97.c

71

#define CODEC_DAT GENMASK(15, 0)

sound/soc/loongson/loongson1_ac97.c

79

#define LS1X_AC97_DMA_TX_BYTES GENMASK(29, 28)

sound/soc/loongson/loongson1_ac97.c

83

#define LS1X_AC97_DMA_DADDR_MASK GENMASK(27, 0)

sound/soc/mediatek/mt7986/mt7986-reg.h

150

#define IN_CLK_SRC_MASK GENMASK(12, 10)

sound/soc/mediatek/mt7986/mt7986-reg.h

155

#define IN_SEL_FS_MASK GENMASK(30, 26)

sound/soc/mediatek/mt7986/mt7986-reg.h

160

#define IN_RELATCH_MASK GENMASK(24, 20)

sound/soc/mediatek/mt7986/mt7986-reg.h

165

#define RELATCH_SRC_MASK GENMASK(30, 28)

sound/soc/mediatek/mt7986/mt7986-reg.h

166

#define ETDM_CH_NUM_MASK GENMASK(27, 23)

sound/soc/mediatek/mt7986/mt7986-reg.h

167

#define ETDM_WRD_LEN_MASK GENMASK(20, 16)

sound/soc/mediatek/mt7986/mt7986-reg.h

168

#define ETDM_BIT_LEN_MASK GENMASK(15, 11)

sound/soc/mediatek/mt7986/mt7986-reg.h

169

#define ETDM_FMT_MASK GENMASK(8, 6)

sound/soc/mediatek/mt7986/mt7986-reg.h

178

#define OUT_RELATCH_MASK GENMASK(28, 24)

sound/soc/mediatek/mt7986/mt7986-reg.h

181

#define OUT_CLK_SRC_MASK GENMASK(8, 6)

sound/soc/mediatek/mt7986/mt7986-reg.h

184

#define OUT_SEL_FS_MASK GENMASK(4, 0)

sound/soc/mediatek/mt7986/mt7986-reg.h

195

#define OUT_SEL_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1005

#define DL8_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1010

#define DL12_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1013

#define DL12_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1016

#define DL12_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1022

#define DL12_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1037

#define DL12_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1042

#define AWB_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1063

#define AWB_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1068

#define AWB2_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1089

#define AWB2_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1094

#define VUL_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1115

#define VUL_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1120

#define VUL12_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1144

#define VUL12_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1149

#define VUL2_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1170

#define VUL2_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1175

#define VUL3_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1196

#define VUL3_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1201

#define VUL4_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1222

#define VUL4_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1227

#define VUL5_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1248

#define VUL5_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1253

#define VUL6_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1274

#define VUL6_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1279

#define DAI_MODE_MASK_SFT GENMASK(25, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1300

#define DAI_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1305

#define MOD_DAI_MODE_MASK_SFT GENMASK(25, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1326

#define MOD_DAI_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1331

#define DAI2_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1352

#define DAI2_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1451

#define IRQ7_MCU_MODE_MASK_SFT GENMASK(31, 28)

sound/soc/mediatek/mt8186/mt8186-reg.h

1454

#define IRQ6_MCU_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1457

#define IRQ5_MCU_MODE_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1460

#define IRQ4_MCU_MODE_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1463

#define IRQ3_MCU_MODE_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1466

#define IRQ2_MCU_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1469

#define IRQ1_MCU_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1472

#define IRQ0_MCU_MODE_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1477

#define IRQ15_MCU_MODE_MASK_SFT GENMASK(31, 28)

sound/soc/mediatek/mt8186/mt8186-reg.h

1480

#define IRQ14_MCU_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1483

#define IRQ13_MCU_MODE_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1486

#define IRQ12_MCU_MODE_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1489

#define IRQ11_MCU_MODE_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1492

#define IRQ10_MCU_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1495

#define IRQ9_MCU_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1498

#define IRQ8_MCU_MODE_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1503

#define IRQ23_MCU_MODE_MASK_SFT GENMASK(31, 28)

sound/soc/mediatek/mt8186/mt8186-reg.h

1506

#define IRQ22_MCU_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

1509

#define IRQ21_MCU_MODE_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1512

#define IRQ20_MCU_MODE_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1515

#define IRQ19_MCU_MODE_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1518

#define IRQ18_MCU_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1521

#define IRQ17_MCU_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1524

#define IRQ16_MCU_MODE_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1529

#define IRQ26_MCU_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1532

#define IRQ25_MCU_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1535

#define IRQ24_MCU_MODE_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1699

#define AUD_PAD_TOP_MON_MASK_SFT GENMASK(31, 15)

sound/soc/mediatek/mt8186/mt8186-reg.h

1701

#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1705

#define RESERVDED_01_MASK_SFT GENMASK(2, 1)

sound/soc/mediatek/mt8186/mt8186-reg.h

1715

#define MTKAIF_RXIF_VOICE_MODE_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1719

#define MTKAIF_RXIF_DATA_BIT_MASK_SFT GENMASK(10, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1721

#define MTKAIF_RXIF_FIFO_RSP_MASK_SFT GENMASK(6, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1728

#define GENERAL2_ASRCOUT_MODE_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

1731

#define GENERAL2_ASRCIN_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1734

#define GENERAL1_ASRCOUT_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

1737

#define GENERAL1_ASRCIN_MODE_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

174

#define I2S_OUT_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1757

#define G_SRC_ASM_FREQ_4_MASK_SFT GENMASK(23, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1761

#define G_SRC_ASM_FREQ_5_MASK_SFT GENMASK(23, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1765

#define G_SRC_COEFF_SRAM_ADR_MASK_SFT GENMASK(5, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1777

#define G_SRC_CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

1793

#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT GENMASK(7, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1801

#define SDM_AUTO_RESET_COUNT_TH_MASK_SFT GENMASK(23, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1815

#define IRQ_COUNTER_MASK_SFT GENMASK(31, 3)

sound/soc/mediatek/mt8186/mt8186-reg.h

1825

#define WR_MSTR_ON_MASK_SFT GENMASK(28, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1827

#define WR_AG_SEL_MASK_SFT GENMASK(12, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1831

#define WR_MSTR_REQ_REAL_MASK_SFT GENMASK(28, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1833

#define WR_MSTR_REQ_IN_MASK_SFT GENMASK(12, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1837

#define MEM1_WDATA_MON0_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1841

#define MEM1_WDATA_MON1_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1851

#define WR_AG_REG_MON_MASK_SFT GENMASK(28, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1857

#define RD_AG_REQ_MON_MASK_SFT GENMASK(13, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1861

#define MEM_BYTE_0_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1865

#define MEM_BYTE_1_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1869

#define RDATA_CNT_MASK_SFT GENMASK(31, 30)

sound/soc/mediatek/mt8186/mt8186-reg.h

1875

#define AG_SEL_MASK_SFT GENMASK(25, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1879

#define AFE_ST_MASK_SFT GENMASK(31, 27)

sound/soc/mediatek/mt8186/mt8186-reg.h

1881

#define AG_IN_SERVICE_MASK_SFT GENMASK(25, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1895

#define ETDM_IN1_CON0_REG_FMT_MASK_SFT GENMASK(8, 6)

sound/soc/mediatek/mt8186/mt8186-reg.h

1899

#define ETDM_IN1_CON0_REG_BIT_LENGTH_MASK_SFT GENMASK(15, 11)

sound/soc/mediatek/mt8186/mt8186-reg.h

1901

#define ETDM_IN1_CON0_REG_WORD_LENGTH_MASK_SFT GENMASK(20, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

1903

#define ETDM_IN1_CON0_REG_CH_NUM_MASK_SFT GENMASK(27, 23)

sound/soc/mediatek/mt8186/mt8186-reg.h

1905

#define ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_MASK_SFT GENMASK(31, 28)

sound/soc/mediatek/mt8186/mt8186-reg.h

1912

#define ETDM_IN1_CON1_REG_INITIAL_COUNT_MASK_SFT GENMASK(4, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1914

#define ETDM_IN1_CON1_REG_INITIAL_POINT_MASK_SFT GENMASK(9, 5)

sound/soc/mediatek/mt8186/mt8186-reg.h

1930

#define ETDM_IN1_CON1_REG_LRCK_WIDTH_MASK_SFT GENMASK(29, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

1939

#define ETDM_IN1_CON2_REG_UPDATE_POINT_MASK_SFT GENMASK(4, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

1941

#define ETDM_IN1_CON2_REG_UPDATE_GAP_MASK_SFT GENMASK(9, 5)

sound/soc/mediatek/mt8186/mt8186-reg.h

1943

#define ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_MASK_SFT GENMASK(12, 10)

sound/soc/mediatek/mt8186/mt8186-reg.h

1949

#define ETDM_IN1_CON2_REG_MULTI_IP_ONE_DATA_CH_NUM_MASK_SFT GENMASK(19, 15)

sound/soc/mediatek/mt8186/mt8186-reg.h

1953

#define ETDM_IN1_CON2_REG_MASK_NUM_MASK_SFT GENMASK(25, 21)

sound/soc/mediatek/mt8186/mt8186-reg.h

2006

#define ETDM_IN1_CON3_REG_MONITOR_SEL_MASK_SFT GENMASK(18, 17)

sound/soc/mediatek/mt8186/mt8186-reg.h

2008

#define ETDM_IN1_CON3_REG_CNT_UPPER_LIMIT_MASK_SFT GENMASK(24, 19)

sound/soc/mediatek/mt8186/mt8186-reg.h

2012

#define ETDM_IN1_CON3_REG_FS_TIMING_SEL_MASK_SFT GENMASK(30, 26)

sound/soc/mediatek/mt8186/mt8186-reg.h

202

#define I2S2_OUT_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

2020

#define ETDM_IN1_CON4_REG_DSD_MODE_MASK_SFT GENMASK(5, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

2024

#define ETDM_IN1_CON4_REG_REPACK_WORD_LENGTH_MASK_SFT GENMASK(10, 9)

sound/soc/mediatek/mt8186/mt8186-reg.h

2028

#define ETDM_IN1_CON4_REG_DSD_CHNUM_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

2038

#define ETDM_IN1_CON4_REG_RELATCH_1X_EN_SEL_MASK_SFT GENMASK(24, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

2040

#define ETDM_IN1_CON4_REG_SAMPLE_END_POINT_MASK_SFT GENMASK(29, 25)

sound/soc/mediatek/mt8186/mt8186-reg.h

2120

#define ETDM_IN1_CON6_LCH_DATA_REG_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

2124

#define ETDM_IN1_CON7_RCH_DATA_REG_MASK_SFT GENMASK(31, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

2128

#define ETDM_IN1_CON8_REG_AFIFO_THRESHOLD_MASK_SFT GENMASK(30, 29)

sound/soc/mediatek/mt8186/mt8186-reg.h

2130

#define ETDM_IN1_CON8_REG_CK_EN_SEL_MANUAL_MASK_SFT GENMASK(25, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

2140

#define ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT GENMASK(7, 5)

sound/soc/mediatek/mt8186/mt8186-reg.h

2142

#define ETDM_IN1_CON8_REG_AFIFO_MODE_MASK_SFT GENMASK(4, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

216

#define I2S3_UPDATE_WORD_MASK_SFT GENMASK(28, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

230

#define I2S3_OUT_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

246

#define I2S4_OUT_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

279

#define I2S_MODE_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

305

#define CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

317

#define GAIN1_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

319

#define GAIN1_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

326

#define GAIN1_TARGET_MASK_SFT GENMASK(27, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

330

#define GAIN2_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

332

#define GAIN2_MODE_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

339

#define GAIN2_TARGET_MASK_SFT GENMASK(27, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

343

#define AFE_GAIN1_CUR_MASK_SFT GENMASK(27, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

347

#define AFE_GAIN2_CUR_MASK_SFT GENMASK(27, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

383

#define PCM_WLEN_MASK_SFT GENMASK(15, 14)

sound/soc/mediatek/mt8186/mt8186-reg.h

385

#define PCM_SYNC_LENGTH_MASK_SFT GENMASK(13, 9)

sound/soc/mediatek/mt8186/mt8186-reg.h

395

#define PCM_MODE_MASK_SFT GENMASK(4, 3)

sound/soc/mediatek/mt8186/mt8186-reg.h

397

#define PCM_FMT_MASK_SFT GENMASK(2, 1)

sound/soc/mediatek/mt8186/mt8186-reg.h

419

#define DAI_PCM_LOOPBACK_CH_MASK_SFT GENMASK(15, 14)

sound/soc/mediatek/mt8186/mt8186-reg.h

421

#define I2S_PCM_LOOPBACK_CH_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

423

#define TX_FIX_VALUE_MASK_SFT GENMASK(7, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

427

#define PCM2_TX_FIX_VALUE_MASK_SFT GENMASK(31, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

453

#define PCM2_LOOPBACK_CH_SEL_MASK_SFT GENMASK(11, 10)

sound/soc/mediatek/mt8186/mt8186-reg.h

463

#define PCM2_MODE_MASK_SFT GENMASK(4, 3)

sound/soc/mediatek/mt8186/mt8186-reg.h

465

#define PCM2_FMT_MASK_SFT GENMASK(2, 1)

sound/soc/mediatek/mt8186/mt8186-reg.h

478

#define CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT GENMASK(28, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

480

#define CM1_FS_SELECT_MASK_SFT GENMASK(12, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

482

#define CHANNEL_MERGE0_CHNUM_MASK_SFT GENMASK(7, 3)

sound/soc/mediatek/mt8186/mt8186-reg.h

510

#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

515

#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT GENMASK(6, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

519

#define DL_2_INPUT_MODE_CTL_MASK_SFT GENMASK(31, 28)

sound/soc/mediatek/mt8186/mt8186-reg.h

525

#define DL_2_OUTPUT_SEL_CTL_MASK_SFT GENMASK(25, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

527

#define DL_2_FADEIN_0START_EN_MASK_SFT GENMASK(17, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

539

#define DL2_ARAMPSP_CTL_PRE_MASK_SFT GENMASK(10, 9)

sound/soc/mediatek/mt8186/mt8186-reg.h

541

#define DL_2_IIRMODE_CTL_PRE_MASK_SFT GENMASK(8, 6)

sound/soc/mediatek/mt8186/mt8186-reg.h

558

#define DL_2_GAIN_CTL_PRE_MASK_SFT GENMASK(31, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

566

#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT GENMASK(29, 27)

sound/soc/mediatek/mt8186/mt8186-reg.h

568

#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT GENMASK(26, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

574

#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT GENMASK(19, 17)

sound/soc/mediatek/mt8186/mt8186-reg.h

578

#define DMIC_LOW_POWER_CTL_MASK_SFT GENMASK(15, 14)

sound/soc/mediatek/mt8186/mt8186-reg.h

584

#define UL_IIRMODE_CTL_MASK_SFT GENMASK(9, 7)

sound/soc/mediatek/mt8186/mt8186-reg.h

604

#define C_AMP_DIV_CH2_CTL_MASK_SFT GENMASK(23, 21)

sound/soc/mediatek/mt8186/mt8186-reg.h

606

#define C_FREQ_DIV_CH2_CTL_MASK_SFT GENMASK(20, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

608

#define C_SINE_MODE_CH2_CTL_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

610

#define C_AMP_DIV_CH1_CTL_MASK_SFT GENMASK(11, 9)

sound/soc/mediatek/mt8186/mt8186-reg.h

612

#define C_FREQ_DIV_CH1_CTL_MASK_SFT GENMASK(8, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

614

#define C_SINE_MODE_CH1_CTL_MASK_SFT GENMASK(3, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

618

#define C_LOOP_BACK_MODE_CTL_MASK_SFT GENMASK(15, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

620

#define ADDA_UL_GAIN_MODE_MASK_SFT GENMASK(9, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

632

#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(22, 21)

sound/soc/mediatek/mt8186/mt8186-reg.h

642

#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(6, 5)

sound/soc/mediatek/mt8186/mt8186-reg.h

660

#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT GENMASK(20, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

662

#define SIDE_TONE_COEFFICIENT_MASK_SFT GENMASK(15, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

666

#define SIDE_TONE_COEFF_MASK_SFT GENMASK(15, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

688

#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT GENMASK(5, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

692

#define POSITIVE_GAIN_MASK_SFT GENMASK(18, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

694

#define SIDE_TONE_GAIN_MASK_SFT GENMASK(15, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

700

#define DL_FIFO_START_POINT_MASK_SFT GENMASK(26, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

720

#define ATTGAIN_CTL_MASK_SFT GENMASK(5, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

734

#define SINE_MODE_CH2_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

737

#define AMP_DIV_CH2_MASK_SFT GENMASK(19, 17)

sound/soc/mediatek/mt8186/mt8186-reg.h

740

#define FREQ_DIV_CH2_MASK_SFT GENMASK(16, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

743

#define SINE_MODE_CH1_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

746

#define AMP_DIV_CH1_MASK_SFT GENMASK(7, 5)

sound/soc/mediatek/mt8186/mt8186-reg.h

749

#define FREQ_DIV_CH1_MASK_SFT GENMASK(4, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

753

#define INNER_LOOP_BACK_MODE_MASK_SFT GENMASK(7, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

763

#define DL_NLE_FIFO_WBIN_MASK_SFT GENMASK(11, 8)

sound/soc/mediatek/mt8186/mt8186-reg.h

765

#define DL_NLE_FIFO_RBIN_MASK_SFT GENMASK(7, 4)

sound/soc/mediatek/mt8186/mt8186-reg.h

778

#define DL1_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

781

#define DL1_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

784

#define DL1_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

790

#define DL1_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

802

#define DL1_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

807

#define DL2_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

810

#define DL2_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

813

#define DL2_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

819

#define DL2_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

831

#define DL2_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

836

#define DL3_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

839

#define DL3_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

842

#define DL3_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

848

#define DL3_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

860

#define DL3_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

865

#define DL4_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

868

#define DL4_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

871

#define DL4_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

877

#define DL4_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

889

#define DL4_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

894

#define DL5_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

897

#define DL5_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

900

#define DL5_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

906

#define DL5_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

918

#define DL5_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

923

#define DL6_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

926

#define DL6_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

929

#define DL6_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

935

#define DL6_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

947

#define DL6_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

952

#define DL7_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

955

#define DL7_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

958

#define DL7_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

964

#define DL7_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8186/mt8186-reg.h

976

#define DL7_HD_MODE_MASK_SFT GENMASK(1, 0)

sound/soc/mediatek/mt8186/mt8186-reg.h

981

#define DL8_MODE_MASK_SFT GENMASK(27, 24)

sound/soc/mediatek/mt8186/mt8186-reg.h

984

#define DL8_MINLEN_MASK_SFT GENMASK(23, 20)

sound/soc/mediatek/mt8186/mt8186-reg.h

987

#define DL8_MAXLEN_MASK_SFT GENMASK(19, 16)

sound/soc/mediatek/mt8186/mt8186-reg.h

993

#define DL8_PBUF_SIZE_MASK_SFT GENMASK(13, 12)

sound/soc/mediatek/mt8188/mt8188-dai-dmic.c

20

#define DMIC_GAIN_MAX_STEP GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-dai-dmic.c

21

#define DMIC_GAIN_MAX_PER_STEP GENMASK(7, 0)

sound/soc/mediatek/mt8188/mt8188-dai-dmic.c

22

#define DMIC_GAIN_MAX_TARGET GENMASK(27, 0)

sound/soc/mediatek/mt8188/mt8188-dai-dmic.c

23

#define DMIC_GAIN_MAX_CURRENT GENMASK(27, 0)

sound/soc/mediatek/mt8188/mt8188-mt6359.c

31

#define TEST_MISO_COUNT_1 GENMASK(3, 0)

sound/soc/mediatek/mt8188/mt8188-mt6359.c

32

#define TEST_MISO_COUNT_2 GENMASK(7, 4)

sound/soc/mediatek/mt8188/mt8188-reg.h

2808

#define AFE_GAIN_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

2809

#define AFE_GAIN_CON0_GAIN_MODE_MASK GENMASK(7, 3)

sound/soc/mediatek/mt8188/mt8188-reg.h

2813

#define AFE_GAIN_CON1_TARGET_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2816

#define AFE_GAIN_CON2_DOWN_STEP_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2819

#define AFE_GAIN_CON3_UP_STEP_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2822

#define AFE_GAIN_CUR_GAIN_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2832

#define PWR2_TOP_CON_DMIC8_SRC_SEL_MASK GENMASK(31, 29)

sound/soc/mediatek/mt8188/mt8188-reg.h

2833

#define PWR2_TOP_CON_DMIC7_SRC_SEL_MASK GENMASK(28, 26)

sound/soc/mediatek/mt8188/mt8188-reg.h

2834

#define PWR2_TOP_CON_DMIC6_SRC_SEL_MASK GENMASK(25, 23)

sound/soc/mediatek/mt8188/mt8188-reg.h

2835

#define PWR2_TOP_CON_DMIC5_SRC_SEL_MASK GENMASK(22, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

2836

#define PWR2_TOP_CON_DMIC4_SRC_SEL_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8188/mt8188-reg.h

2837

#define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK GENMASK(16, 14)

sound/soc/mediatek/mt8188/mt8188-reg.h

2838

#define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK GENMASK(13, 11)

sound/soc/mediatek/mt8188/mt8188-reg.h

2839

#define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK GENMASK(10, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

2858

#define PCM_INTF_CON1_CLK_OUT_INV_MASK GENMASK(23, 22)

sound/soc/mediatek/mt8188/mt8188-reg.h

2861

#define PCM_INTF_CON1_CLK_IN_INV_MASK GENMASK(21, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

2868

#define PCM_INTF_CON1_SYNC_LENGTH_MASK GENMASK(13, 9)

sound/soc/mediatek/mt8188/mt8188-reg.h

2872

#define PCM_INTF_CON1_PCM_MODE_MASK GENMASK(4, 3)

sound/soc/mediatek/mt8188/mt8188-reg.h

2873

#define PCM_INTF_CON1_PCM_FMT_MASK GENMASK(2, 1)

sound/soc/mediatek/mt8188/mt8188-reg.h

2877

#define PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK GENMASK(24, 23)

sound/soc/mediatek/mt8188/mt8188-reg.h

2878

#define PCM_INTF_CON2_SYNC_FREQ_MODE_MASK GENMASK(16, 12)

sound/soc/mediatek/mt8188/mt8188-reg.h

2899

#define AFE_MPHONE_MULTI_CON1_LRCK_CYCLE_SEL_MASK GENMASK(17, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

2903

#define AFE_MPHONE_MULTI_CON1_BIT_NUM_MASK GENMASK(12, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

2905

#define AFE_MPHONE_MULTI_CON1_CH_NUM_MASK GENMASK(1, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2922

#define MTKAIF_RXIF_DELAY_CYCLE_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8188/mt8188-reg.h

2931

#define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK GENMASK(29, 24)

sound/soc/mediatek/mt8188/mt8188-reg.h

2935

#define AFE_DMIC_UL_VOICE_MODE(x) (((x) & GENMASK(2, 0)) << 17)

sound/soc/mediatek/mt8188/mt8188-reg.h

2936

#define AFE_DMIC_UL_VOICE_MODE_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8188/mt8188-reg.h

2942

#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x) (((x) & GENMASK(2, 0)) << 7)

sound/soc/mediatek/mt8188/mt8188-reg.h

2943

#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK GENMASK(9, 7)

sound/soc/mediatek/mt8188/mt8188-reg.h

2960

#define DMIC_GAIN_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

2963

#define DMIC_GAIN_CON1_TARGET_MASK GENMASK(27, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2966

#define DMIC_GAIN_CON2_DOWN_STEP GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2969

#define DMIC_GAIN_CON3_UP_STEP GENMASK(19, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2972

#define DMIC_GAIN_CUR_GAIN_MASK GENMASK(27, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2976

#define ETDM_IN_AFIFO_CLOCK_MASK GENMASK(7, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

2977

#define ETDM_IN_AFIFO_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

2980

#define ETDM_OUT1_SLAVE_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

2982

#define ETDM_OUT1_SYNC_SEL_MASK GENMASK(19, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

2986

#define ETDM_IN1_SDATA_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

2988

#define ETDM_IN1_SDATA0_SEL_MASK GENMASK(19, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

2990

#define ETDM_IN1_SYNC_SEL_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8188/mt8188-reg.h

2992

#define ETDM_IN1_SLAVE_SEL_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

2996

#define ETDM_IN2_SYNC_SEL_MASK GENMASK(31, 28)

sound/soc/mediatek/mt8188/mt8188-reg.h

2998

#define ETDM_IN2_SLAVE_SEL_MASK GENMASK(27, 24)

sound/soc/mediatek/mt8188/mt8188-reg.h

3000

#define ETDM_OUT3_SLAVE_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3002

#define ETDM_OUT3_SYNC_SEL_MASK GENMASK(19, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

3004

#define ETDM_OUT2_SLAVE_SEL_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3006

#define ETDM_OUT2_SYNC_SEL_MASK GENMASK(7, 4)

sound/soc/mediatek/mt8188/mt8188-reg.h

3010

#define ETDM_IN2_SDATA_SEL_MASK GENMASK(7, 4)

sound/soc/mediatek/mt8188/mt8188-reg.h

3012

#define ETDM_IN2_SDATA0_SEL_MASK GENMASK(3, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3016

#define ETDM_CON0_CH_NUM_MASK GENMASK(27, 23)

sound/soc/mediatek/mt8188/mt8188-reg.h

3017

#define ETDM_CON0_WORD_LEN_MASK GENMASK(20, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

3018

#define ETDM_CON0_BIT_LEN_MASK GENMASK(15, 11)

sound/soc/mediatek/mt8188/mt8188-reg.h

3019

#define ETDM_CON0_FORMAT_MASK GENMASK(8, 6)

sound/soc/mediatek/mt8188/mt8188-reg.h

3025

#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28)

sound/soc/mediatek/mt8188/mt8188-reg.h

3030

#define ETDM_IN_CON1_LRCK_WIDTH_MASK GENMASK(29, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3033

#define ETDM_OUT_CON1_LRCK_WIDTH_MASK GENMASK(28, 19)

sound/soc/mediatek/mt8188/mt8188-reg.h

3036

#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3037

#define ETDM_IN_CON2_CLOCK_MASK GENMASK(12, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3039

#define ETDM_IN_CON2_UPDATE_GAP_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3044

#define ETDM_IN_CON3_FS_MASK GENMASK(30, 26)

sound/soc/mediatek/mt8188/mt8188-reg.h

3046

#define ETDM_IN_CON3_DISABLE_OUT_MASK GENMASK(15, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3053

#define ETDM_OUT_CON4_RELATCH_EN_MASK GENMASK(28, 24)

sound/soc/mediatek/mt8188/mt8188-reg.h

3054

#define ETDM_OUT_CON4_CLOCK_MASK GENMASK(8, 6)

sound/soc/mediatek/mt8188/mt8188-reg.h

3056

#define ETDM_OUT_CON4_FS_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3059

#define ETDM_IN_CON5_LR_SWAP_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

3061

#define ETDM_IN_CON5_ENABLE_ODD_MASK GENMASK(15, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3069

#define GASRC_TIMING_CON0_GASRC0_IN_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3070

#define GASRC_TIMING_CON0_GASRC1_IN_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3071

#define GASRC_TIMING_CON0_GASRC2_IN_MODE_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3072

#define GASRC_TIMING_CON0_GASRC3_IN_MODE_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3073

#define GASRC_TIMING_CON0_GASRC4_IN_MODE_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3074

#define GASRC_TIMING_CON0_GASRC5_IN_MODE_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8188/mt8188-reg.h

3077

#define GASRC_TIMING_CON1_GASRC6_IN_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3078

#define GASRC_TIMING_CON1_GASRC7_IN_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3079

#define GASRC_TIMING_CON1_GASRC8_IN_MODE_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3080

#define GASRC_TIMING_CON1_GASRC9_IN_MODE_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3081

#define GASRC_TIMING_CON1_GASRC10_IN_MODE_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3082

#define GASRC_TIMING_CON1_GASRC11_IN_MODE_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8188/mt8188-reg.h

3085

#define GASRC_TIMING_CON2_GASRC12_IN_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3086

#define GASRC_TIMING_CON2_GASRC13_IN_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3087

#define GASRC_TIMING_CON2_GASRC14_IN_MODE_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3088

#define GASRC_TIMING_CON2_GASRC15_IN_MODE_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3089

#define GASRC_TIMING_CON2_GASRC16_IN_MODE_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3090

#define GASRC_TIMING_CON2_GASRC17_IN_MODE_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8188/mt8188-reg.h

3093

#define GASRC_TIMING_CON3_GASRC18_IN_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3094

#define GASRC_TIMING_CON3_GASRC19_IN_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3097

#define GASRC_TIMING_CON4_GASRC0_OUT_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3098

#define GASRC_TIMING_CON4_GASRC1_OUT_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3099

#define GASRC_TIMING_CON4_GASRC2_OUT_MODE_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3100

#define GASRC_TIMING_CON4_GASRC3_OUT_MODE_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3101

#define GASRC_TIMING_CON4_GASRC4_OUT_MODE_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3102

#define GASRC_TIMING_CON4_GASRC5_OUT_MODE_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8188/mt8188-reg.h

3105

#define GASRC_TIMING_CON5_GASRC6_OUT_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3106

#define GASRC_TIMING_CON5_GASRC7_OUT_MODE_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8188/mt8188-reg.h

3107

#define GASRC_TIMING_CON5_GASRC8_OUT_MODE_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8188/mt8188-reg.h

3108

#define GASRC_TIMING_CON5_GASRC9_OUT_MODE_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8188/mt8188-reg.h

3109

#define GASRC_TIMING_CON5_GASRC10_OUT_MODE_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8188/mt8188-reg.h

3110

#define GASRC_TIMING_CON5_GASRC11_OUT_MODE_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8188/mt8188-reg.h

3113

#define AFE_DPTX_CON_CH_EN_2CH GENMASK(9, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3114

#define AFE_DPTX_CON_CH_EN_4CH GENMASK(11, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3115

#define AFE_DPTX_CON_CH_EN_6CH GENMASK(13, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3116

#define AFE_DPTX_CON_CH_EN_8CH GENMASK(15, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3117

#define AFE_DPTX_CON_CH_EN_MASK GENMASK(15, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3128

#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)

sound/soc/mediatek/mt8188/mt8188-reg.h

3138

#define DL_2_GAIN_CTL_PRE_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

3142

#define C_LOOPBACK_MODE_CTL_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8188/mt8188-reg.h

3150

#define ATTGAIN_CTL_MASK GENMASK(5, 0)

sound/soc/mediatek/mt8188/mt8188-reg.h

3155

#define UL_VOICE_MODE_CTL_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8188/mt8188-reg.h

3163

#define AFE_GASRC_NEW_CON0_CHSET0_OFS_SEL_MASK GENMASK(15, 14)

sound/soc/mediatek/mt8188/mt8188-reg.h

3166

#define AFE_GASRC_NEW_CON0_CHSET0_IFS_SEL_MASK GENMASK(13, 12)

sound/soc/mediatek/mt8188/mt8188-reg.h

3170

#define AFE_GASRC_NEW_CON0_CHSET0_IIR_STAGE_MASK GENMASK(10, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3176

#define AFE_GASRC_NEW_CON5_CALI_LRCK_SEL_MASK GENMASK(3, 1)

sound/soc/mediatek/mt8188/mt8188-reg.h

3180

#define AFE_GASRC_NEW_CON6_FREQ_CALI_CYCLE_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8188/mt8188-reg.h

3183

#define AFE_GASRC_NEW_CON6_CALI_SIG_MUX_SEL_MASK GENMASK(9, 8)

sound/soc/mediatek/mt8188/mt8188-reg.h

3191

#define AFE_GASRC_NEW_CON7_FREQ_CALC_DENOMINATOR_MASK GENMASK(23, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2510

#define PWR2_TOP_CON_DMIC8_SRC_SEL_MASK GENMASK(31, 29)

sound/soc/mediatek/mt8195/mt8195-reg.h

2511

#define PWR2_TOP_CON_DMIC7_SRC_SEL_MASK GENMASK(28, 26)

sound/soc/mediatek/mt8195/mt8195-reg.h

2512

#define PWR2_TOP_CON_DMIC6_SRC_SEL_MASK GENMASK(25, 23)

sound/soc/mediatek/mt8195/mt8195-reg.h

2513

#define PWR2_TOP_CON_DMIC5_SRC_SEL_MASK GENMASK(22, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2514

#define PWR2_TOP_CON_DMIC4_SRC_SEL_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8195/mt8195-reg.h

2515

#define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK GENMASK(16, 14)

sound/soc/mediatek/mt8195/mt8195-reg.h

2516

#define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK GENMASK(13, 11)

sound/soc/mediatek/mt8195/mt8195-reg.h

2517

#define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK GENMASK(10, 8)

sound/soc/mediatek/mt8195/mt8195-reg.h

2533

#define PCM_INTF_CON1_CLK_OUT_INV_MASK GENMASK(23, 22)

sound/soc/mediatek/mt8195/mt8195-reg.h

2536

#define PCM_INTF_CON1_CLK_IN_INV_MASK GENMASK(21, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2584

#define AFE_MPHONE_MULTI_CON1_LRCK_CYCLE_SEL_MASK GENMASK(17, 16)

sound/soc/mediatek/mt8195/mt8195-reg.h

2592

#define AFE_MPHONE_MULTI_CON1_BIT_NUM_MASK GENMASK(12, 8)

sound/soc/mediatek/mt8195/mt8195-reg.h

2596

#define AFE_MPHONE_MULTI_CON1_CH_NUM_MASK GENMASK(1, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2616

#define MTKAIF_RXIF_DELAY_CYCLE_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8195/mt8195-reg.h

2642

#define ETDM_IN_AFIFO_CLOCK_MASK GENMASK(7, 5)

sound/soc/mediatek/mt8195/mt8195-reg.h

2644

#define ETDM_IN_AFIFO_MODE_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2648

#define ETDM_OUT1_SLAVE_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2653

#define ETDM_IN1_SDATA_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2656

#define ETDM_IN1_SDATA0_SEL_MASK GENMASK(19, 16)

sound/soc/mediatek/mt8195/mt8195-reg.h

2659

#define ETDM_IN1_SLAVE_SEL_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8195/mt8195-reg.h

2664

#define ETDM_IN2_SLAVE_SEL_MASK GENMASK(27, 24)

sound/soc/mediatek/mt8195/mt8195-reg.h

2667

#define ETDM_OUT3_SLAVE_SEL_MASK GENMASK(23, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2670

#define ETDM_OUT2_SLAVE_SEL_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8195/mt8195-reg.h

2675

#define ETDM_IN2_SDATA_SEL_MASK GENMASK(7, 4)

sound/soc/mediatek/mt8195/mt8195-reg.h

2678

#define ETDM_IN2_SDATA0_SEL_MASK GENMASK(3, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2683

#define ETDM_CON0_CH_NUM_MASK GENMASK(27, 23)

sound/soc/mediatek/mt8195/mt8195-reg.h

2685

#define ETDM_CON0_WORD_LEN_MASK GENMASK(20, 16)

sound/soc/mediatek/mt8195/mt8195-reg.h

2687

#define ETDM_CON0_BIT_LEN_MASK GENMASK(15, 11)

sound/soc/mediatek/mt8195/mt8195-reg.h

2689

#define ETDM_CON0_FORMAT_MASK GENMASK(8, 6)

sound/soc/mediatek/mt8195/mt8195-reg.h

2694

#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28)

sound/soc/mediatek/mt8195/mt8195-reg.h

2699

#define ETDM_IN_CON1_LRCK_WIDTH_MASK GENMASK(29, 20)

sound/soc/mediatek/mt8195/mt8195-reg.h

2702

#define ETDM_OUT_CON1_LRCK_WIDTH_MASK GENMASK(28, 19)

sound/soc/mediatek/mt8195/mt8195-reg.h

2706

#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8195/mt8195-reg.h

2708

#define ETDM_IN_CON2_CLOCK_MASK GENMASK(12, 10)

sound/soc/mediatek/mt8195/mt8195-reg.h

2711

#define ETDM_IN_CON2_UPDATE_GAP_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8195/mt8195-reg.h

2717

#define ETDM_IN_CON3_FS_MASK GENMASK(30, 26)

sound/soc/mediatek/mt8195/mt8195-reg.h

2719

#define ETDM_IN_CON3_DISABLE_OUT_MASK GENMASK(15, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2727

#define ETDM_OUT_CON4_RELATCH_EN_MASK GENMASK(28, 24)

sound/soc/mediatek/mt8195/mt8195-reg.h

2729

#define ETDM_OUT_CON4_CLOCK_MASK GENMASK(8, 6)

sound/soc/mediatek/mt8195/mt8195-reg.h

2732

#define ETDM_OUT_CON4_FS_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2735

#define ETDM_IN_CON5_LR_SWAP_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8195/mt8195-reg.h

2737

#define ETDM_IN_CON5_ENABLE_ODD_MASK GENMASK(15, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2746

#define AFE_DPTX_CON_CH_EN_2CH (AFE_DPTX_CON_CH_EN(GENMASK(1, 0)))

sound/soc/mediatek/mt8195/mt8195-reg.h

2747

#define AFE_DPTX_CON_CH_EN_4CH (AFE_DPTX_CON_CH_EN(GENMASK(3, 0)))

sound/soc/mediatek/mt8195/mt8195-reg.h

2748

#define AFE_DPTX_CON_CH_EN_6CH (AFE_DPTX_CON_CH_EN(GENMASK(5, 0)))

sound/soc/mediatek/mt8195/mt8195-reg.h

2749

#define AFE_DPTX_CON_CH_EN_8CH (AFE_DPTX_CON_CH_EN(GENMASK(7, 0)))

sound/soc/mediatek/mt8195/mt8195-reg.h

2750

#define AFE_DPTX_CON_CH_EN_MASK GENMASK(15, 8)

sound/soc/mediatek/mt8195/mt8195-reg.h

2766

#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)

sound/soc/mediatek/mt8195/mt8195-reg.h

2777

#define DL_2_GAIN_CTL_PRE_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8195/mt8195-reg.h

2781

#define C_LOOPBACK_MODE_CTL_MASK GENMASK(15, 12)

sound/soc/mediatek/mt8195/mt8195-reg.h

2786

#define ATTGAIN_CTL_MASK GENMASK(5, 0)

sound/soc/mediatek/mt8195/mt8195-reg.h

2792

#define UL_VOICE_MODE_CTL_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

2044

{ AFE_CONN_24BIT, GENMASK(31, 0), GENMASK(31, 0) },

sound/soc/mediatek/mt8365/mt8365-afe-pcm.c

2045

{ AFE_CONN_24BIT_1, GENMASK(21, 0), GENMASK(21, 0) },

sound/soc/mediatek/mt8365/mt8365-reg.h

775

#define AFE_I2S_CON_RATE_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

790

#define IIR_STAGE_MASK GENMASK(10, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

793

#define CALI_CYCLE_MASK GENMASK(31, 16)

sound/soc/mediatek/mt8365/mt8365-reg.h

802

#define CALI_SEL_MASK GENMASK(9, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

822

#define AFE_I2S_CON1_RATE GENMASK(11, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

829

#define AFE_I2S_CON2_RATE GENMASK(11, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

836

#define AFE_I2S_CON3_RATE GENMASK(11, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

842

#define AFE_ADDA_DL_SAMPLING_RATE GENMASK(31, 28)

sound/soc/mediatek/mt8365/mt8365-reg.h

843

#define AFE_ADDA_DL_8X_UPSAMPLE GENMASK(25, 24)

sound/soc/mediatek/mt8365/mt8365-reg.h

850

#define AFE_ADDA_UL_SAMPLING_RATE GENMASK(19, 17)

sound/soc/mediatek/mt8365/mt8365-reg.h

857

#define AFE_APLL_TUNER_CFG_MASK GENMASK(15, 1)

sound/soc/mediatek/mt8365/mt8365-reg.h

861

#define AFE_APLL_TUNER_CFG1_MASK GENMASK(15, 1)

sound/soc/mediatek/mt8365/mt8365-reg.h

872

#define PCM_INTF_CON1_FS_MASK GENMASK(4, 3)

sound/soc/mediatek/mt8365/mt8365-reg.h

877

#define PCM_INTF_CON1_SYNC_LEN_MASK GENMASK(13, 9)

sound/soc/mediatek/mt8365/mt8365-reg.h

879

#define PCM_INTF_CON1_FORMAT_MASK GENMASK(2, 1)

sound/soc/mediatek/mt8365/mt8365-reg.h

893

#define DMIC_TOP_CON_CK_PHASE_SEL_CH1 GENMASK(29, 27)

sound/soc/mediatek/mt8365/mt8365-reg.h

894

#define DMIC_TOP_CON_CK_PHASE_SEL_CH2 GENMASK(26, 24)

sound/soc/mediatek/mt8365/mt8365-reg.h

898

#define DMIC_TOP_CON_VOICE_MODE_MASK GENMASK(19, 17)

sound/soc/mediatek/mt8365/mt8365-reg.h

903

#define DMIC_TOP_CON_LOW_POWER_MODE_MASK GENMASK(15, 14)

sound/soc/mediatek/mt8365/mt8365-reg.h

906

#define DMIC_TOP_CON_IIR_MODE GENMASK(9, 7)

sound/soc/mediatek/mt8365/mt8365-reg.h

929

#define AFE_GAIN1_CON0_EN_MASK GENMASK(0, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

930

#define AFE_GAIN1_CON0_MODE_MASK GENMASK(7, 4)

sound/soc/mediatek/mt8365/mt8365-reg.h

931

#define AFE_GAIN1_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

934

#define AFE_GAIN1_CON1_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

937

#define AFE_GAIN1_CUR_MASK GENMASK(19, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

941

#define CM_AFE_CM_CH_NUM_MASK GENMASK(3, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

944

#define CM_AFE_CM_START_DATA_MASK GENMASK(11, 8)

sound/soc/mediatek/mt8365/mt8365-reg.h

947

#define CM_AFE_CM1_IN_MODE_MASK GENMASK(19, 16)

sound/soc/mediatek/mt8365/mt8365-reg.h

955

#define CM2_AFE_CM2_CONN_CFG1_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

957

#define CM2_AFE_CM2_CONN_CFG2_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8365/mt8365-reg.h

959

#define CM2_AFE_CM2_CONN_CFG3_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8365/mt8365-reg.h

961

#define CM2_AFE_CM2_CONN_CFG4_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8365/mt8365-reg.h

963

#define CM2_AFE_CM2_CONN_CFG5_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8365/mt8365-reg.h

965

#define CM2_AFE_CM2_CONN_CFG6_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8365/mt8365-reg.h

967

#define CM2_AFE_CM2_CONN_CFG7_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

969

#define CM2_AFE_CM2_CONN_CFG8_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8365/mt8365-reg.h

971

#define CM2_AFE_CM2_CONN_CFG9_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8365/mt8365-reg.h

973

#define CM2_AFE_CM2_CONN_CFG10_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8365/mt8365-reg.h

975

#define CM2_AFE_CM2_CONN_CFG11_MASK GENMASK(24, 20)

sound/soc/mediatek/mt8365/mt8365-reg.h

977

#define CM2_AFE_CM2_CONN_CFG12_MASK GENMASK(29, 25)

sound/soc/mediatek/mt8365/mt8365-reg.h

979

#define CM2_AFE_CM2_CONN_CFG13_MASK GENMASK(4, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

981

#define CM2_AFE_CM2_CONN_CFG14_MASK GENMASK(9, 5)

sound/soc/mediatek/mt8365/mt8365-reg.h

983

#define CM2_AFE_CM2_CONN_CFG15_MASK GENMASK(14, 10)

sound/soc/mediatek/mt8365/mt8365-reg.h

985

#define CM2_AFE_CM2_CONN_CFG16_MASK GENMASK(19, 15)

sound/soc/mediatek/mt8365/mt8365-reg.h

988

#define CM_AFE_CM_UPDATE_CNT1_MASK GENMASK(15, 0)

sound/soc/mediatek/mt8365/mt8365-reg.h

990

#define CM_AFE_CM_UPDATE_CNT2_MASK GENMASK(31, 16)

sound/soc/meson/aiu-acodec-ctrl.c

21

#define CTRL_BCLK_MCLK_SRC GENMASK(5, 4)

sound/soc/meson/aiu-acodec-ctrl.c

22

#define CTRL_DIN_SKEW GENMASK(3, 2)

sound/soc/meson/aiu-codec-ctrl.c

15

#define CTRL_CLK_SEL GENMASK(1, 0)

sound/soc/meson/aiu-encoder-i2s.c

22

#define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2)

sound/soc/meson/aiu-encoder-i2s.c

25

#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)

sound/soc/meson/aiu-encoder-i2s.c

27

#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)

sound/soc/meson/aiu-encoder-i2s.c

28

#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)

sound/soc/meson/aiu-encoder-spdif.c

17

#define AIU_958_MISC_16BITS_ALIGN GENMASK(6, 5)

sound/soc/meson/aiu-encoder-spdif.c

23

#define AIU_CLK_CTRL_958_DIV GENMASK(5, 4)

sound/soc/meson/aiu-fifo-i2s.c

19

#define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)

sound/soc/meson/aiu-fifo-spdif.c

16

#define AIU_IEC958_DCU_FF_CTRL_IRQ_MODE GENMASK(3, 2)

sound/soc/meson/aiu-fifo-spdif.c

22

#define AIU_MEM_IEC958_CONTROL_ENDIAN GENMASK(5, 3)

sound/soc/meson/aiu-fifo.c

19

#define AIU_MEM_MASK_CH_RD GENMASK(7, 0)

sound/soc/meson/aiu-fifo.c

20

#define AIU_MEM_MASK_CH_MEM GENMASK(15, 8)

sound/soc/meson/axg-fifo.h

39

#define FIFO_INT_MASK GENMASK(7, 0)

sound/soc/meson/axg-fifo.h

43

#define CTRL0_INT_EN GENMASK(23, 16)

sound/soc/meson/axg-fifo.h

44

#define CTRL0_SEL_MASK GENMASK(2, 0)

sound/soc/meson/axg-fifo.h

47

#define CTRL1_INT_CLR GENMASK(7, 0)

sound/soc/meson/axg-fifo.h

48

#define CTRL1_STATUS2_SEL GENMASK(11, 8)

sound/soc/meson/axg-fifo.h

50

#define CTRL1_FRDDR_DEPTH GENMASK(31, 24)

sound/soc/meson/axg-fifo.h

55

#define STATUS1_INT_STS GENMASK(7, 0)

sound/soc/meson/axg-pdm.c

20

#define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8)

sound/soc/meson/axg-pdm.c

209

unsigned int mask = GENMASK(channels - 1, 0);

sound/soc/meson/axg-pdm.c

22

#define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0)

sound/soc/meson/axg-pdm.c

26

#define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24)

sound/soc/meson/axg-pdm.c

28

#define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16)

sound/soc/meson/axg-pdm.c

30

#define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4)

sound/soc/meson/axg-pdm.c

32

#define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0)

sound/soc/meson/axg-pdm.c

36

#define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16)

sound/soc/meson/axg-pdm.c

38

#define PDM_LPF_DSR_MASK GENMASK(15, 12)

sound/soc/meson/axg-pdm.c

40

#define PDM_LPF_STAGE_NUM_MASK GENMASK(8, 0)

sound/soc/meson/axg-pdm.c

47

#define PDM_HPF_SFT_STEPS_MASK GENMASK(20, 16)

sound/soc/meson/axg-pdm.c

49

#define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0)

sound/soc/meson/axg-spdifin.c

129

regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,

sound/soc/meson/axg-spdifin.c

21

#define SPDIFIN_CTRL0_STATUS_SEL GENMASK(10, 8)

sound/soc/meson/axg-spdifin.c

22

#define SPDIFIN_CTRL0_SRC_SEL GENMASK(5, 4)

sound/soc/meson/axg-spdifin.c

25

#define SPDIFIN_CTRL1_BASE_TIMER GENMASK(19, 0)

sound/soc/meson/axg-spdifin.c

26

#define SPDIFIN_CTRL1_IRQ_MASK GENMASK(27, 20)

sound/soc/meson/axg-spdifin.c

37

#define SPDIFIN_STAT0_MODE GENMASK(30, 28)

sound/soc/meson/axg-spdifin.c

38

#define SPDIFIN_STAT0_MAXW GENMASK(17, 8)

sound/soc/meson/axg-spdifin.c

39

#define SPDIFIN_STAT0_IRQ GENMASK(7, 0)

sound/soc/meson/axg-spdifout.c

36

#define SPDIFOUT_CTRL0_MASK_MASK GENMASK(11, 4)

sound/soc/meson/axg-spdifout.c

39

#define SPDIFOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)

sound/soc/meson/axg-spdifout.c

41

#define SPDIFOUT_CTRL1_TYPE_MASK GENMASK(6, 4)

sound/soc/meson/axg-tdmin.c

21

#define TDMIN_CTRL_IN_BIT_SKEW_MASK GENMASK(18, 16)

sound/soc/meson/axg-tdmin.c

24

#define TDMIN_CTRL_BITNUM_MASK GENMASK(4, 0)

sound/soc/meson/axg-tdmout.c

15

#define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)

sound/soc/meson/axg-tdmout.c

17

#define TDMOUT_CTRL0_SLOTNUM_MASK GENMASK(9, 5)

sound/soc/meson/axg-tdmout.c

19

#define TDMOUT_CTRL0_INIT_BITNUM_MASK GENMASK(19, 15)

sound/soc/meson/axg-tdmout.c

25

#define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)

sound/soc/meson/axg-tdmout.c

28

#define TDMOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)

sound/soc/meson/axg-toddr.c

23

#define CTRL0_TODDR_TYPE GENMASK(15, 13)

sound/soc/meson/axg-toddr.c

24

#define CTRL0_TODDR_MSB_POS GENMASK(12, 8)

sound/soc/meson/axg-toddr.c

25

#define CTRL0_TODDR_LSB_POS GENMASK(7, 3)

sound/soc/meson/g12a-toacodec.c

42

#define CTRL0_MCLK_SEL GENMASK(2, 0)

sound/soc/meson/g12a-tohdmitx.c

24

#define CTRL0_I2S_LRCLK_SEL GENMASK(9, 8)

sound/soc/meson/g12a-tohdmitx.c

27

#define CTRL0_I2S_BCLK_SEL GENMASK(5, 4)

sound/soc/qcom/apq8016_sbc.c

41

#define SPKR_CTL_TLMM_WS_OUT_SEL_MASK GENMASK(7, 6)

sound/soc/qcom/apq8016_sbc.c

43

#define SPKR_CTL_TLMM_WS_EN_SEL_MASK GENMASK(19, 18)

sound/soc/qcom/lpass-cpu.c

27

#define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)

sound/soc/qcom/lpass-cpu.c

28

#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)

sound/soc/qcom/lpass-cpu.c

29

#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)

sound/soc/qcom/lpass-cpu.c

30

#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)

sound/soc/qcom/lpass-hdmi.h

43

#define LPASS_DATA_FORMAT_MASK GENMASK(1, 1)

sound/soc/qcom/lpass-hdmi.h

44

#define LPASS_WORDLENGTH_MASK GENMASK(3, 0)

sound/soc/qcom/lpass-hdmi.h

45

#define LPASS_FREQ_BIT_MASK GENMASK(27, 24)

sound/soc/qcom/qdsp6/q6afe.c

64

#define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0)

sound/soc/qcom/qdsp6/q6afe.c

65

#define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2)

sound/soc/qcom/qdsp6/q6afe.c

66

#define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0)

sound/soc/qcom/qdsp6/q6afe.c

67

#define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0)

sound/soc/qcom/qdsp6/q6apm.h

43

#define APM_WRITE_TOKEN_MASK GENMASK(15, 0)

sound/soc/qcom/qdsp6/q6apm.h

44

#define APM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16)

sound/soc/qcom/qdsp6/q6asm.h

22

#define ASM_WRITE_TOKEN_MASK GENMASK(15, 0)

sound/soc/qcom/qdsp6/q6asm.h

23

#define ASM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16)

sound/soc/rockchip/rockchip_i2s_tdm.h

230

#define TDM_FSYNC_WIDTH_SEL1_MSK GENMASK(20, 18)

sound/soc/rockchip/rockchip_i2s_tdm.h

235

#define TDM_SHIFT_CTRL_MSK GENMASK(16, 14)

sound/soc/rockchip/rockchip_i2s_tdm.h

237

#define TDM_SLOT_BIT_WIDTH_MSK GENMASK(13, 9)

sound/soc/rockchip/rockchip_i2s_tdm.h

239

#define TDM_FRAME_WIDTH_MSK GENMASK(8, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

290

#define HIWORD_UPDATE(v, h, l) (FIELD_PREP_WM16_CONST(GENMASK((h), (l)), (v)))

sound/soc/rockchip/rockchip_pdm.c

222

GENMASK(16 - 1, 0),

sound/soc/rockchip/rockchip_pdm.c

223

GENMASK(16 - 1, 0),

sound/soc/rockchip/rockchip_pdm.h

44

#define PDM_SAMPLERATE_MSK GENMASK(7, 5)

sound/soc/rockchip/rockchip_pdm.h

51

#define PDM_FD_NUMERATOR_MSK GENMASK(31, 16)

sound/soc/rockchip/rockchip_pdm.h

53

#define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0)

sound/soc/rockchip/rockchip_sai.h

111

#define SAI_DMACR_RDL_MASK GENMASK(20, 16)

sound/soc/rockchip/rockchip_sai.h

116

#define SAI_DMACR_TDL_MASK GENMASK(4, 0)

sound/soc/rockchip/rockchip_sai.h

160

#define SAI_XSHIFT_LEFT_MASK GENMASK(25, 24)

sound/soc/rockchip/rockchip_sai.h

167

#define SAI_XSHIFT_RIGHT_MASK GENMASK(23, 0)

sound/soc/rockchip/rockchip_sai.h

172

#define SAI_FIFOLR_XFL3_MASK GENMASK(23, 18)

sound/soc/rockchip/rockchip_sai.h

174

#define SAI_FIFOLR_XFL2_MASK GENMASK(17, 12)

sound/soc/rockchip/rockchip_sai.h

176

#define SAI_FIFOLR_XFL1_MASK GENMASK(11, 6)

sound/soc/rockchip/rockchip_sai.h

178

#define SAI_FIFOLR_XFL0_MASK GENMASK(5, 0)

sound/soc/rockchip/rockchip_sai.h

18

#define SAI_XCR_CSR_MASK GENMASK(21, 20)

sound/soc/rockchip/rockchip_sai.h

212

#define SAI_FS_TIMEOUT_VAL_MASK GENMASK(31, 1)

sound/soc/rockchip/rockchip_sai.h

27

#define SAI_XCR_SNB_MASK GENMASK(17, 11)

sound/soc/rockchip/rockchip_sai.h

32

#define SAI_XCR_SBW_MASK GENMASK(9, 5)

sound/soc/rockchip/rockchip_sai.h

35

#define SAI_XCR_VDW_MASK GENMASK(4, 0)

sound/soc/rockchip/rockchip_sai.h

42

#define SAI_FSCR_FPW_MASK GENMASK(23, 12)

sound/soc/rockchip/rockchip_sai.h

44

#define SAI_FSCR_FW_MASK GENMASK(11, 0)

sound/soc/rockchip/rockchip_sai.h

49

#define SAI_MCR_RX_MONO_SLOT_MASK GENMASK(8, 2)

sound/soc/rockchip/rockchip_sai.h

96

#define SAI_CKR_MDIV_MASK GENMASK(14, 3)

sound/soc/rockchip/rockchip_spdif.h

16

#define SPDIF_CFGR_CLK_DIV_MASK GENMASK(23, 16)

sound/soc/rockchip/rockchip_spdif.h

35

#define SDPIF_CFGR_VDW_MASK GENMASK(1, 0)

sound/soc/rockchip/rockchip_spdif.h

50

#define SPDIF_DMACR_TDL_MASK GENMASK(4, 0)

sound/soc/sdca/sdca_asoc.c

420

(*widget)->mask = GENMASK(control->nbits - 1, 0);

sound/soc/sdw_utils/soc_sdw_cs_amp.c

97

mask = GENMASK(ch_per_amp - 1, 0) << ch_slot[ch_map->cpu];

sound/soc/sdw_utils/soc_sdw_utils.c

1106

ch_mask = GENMASK(ch - 1, 0);

sound/soc/sdw_utils/soc_sdw_utils.c

1117

ch_mask = GENMASK(ch / num_codecs - 1, 0);

sound/soc/soc-ops.c

198

return GENMASK(mc->sign_bit, 0);

sound/soc/soc-ops.c

200

return GENMASK(fls(mc->max) - 1, 0);

sound/soc/soc-ops.c

206

return GENMASK(fls(mc->min + mc->max) - 2, 0);

sound/soc/soc-ops.c

718

unsigned int regwmask = GENMASK(regwshift - 1, 0);

sound/soc/soc-ops.c

719

unsigned long mask = GENMASK(mc->nbits - 1, 0);

sound/soc/soc-ops.c

762

unsigned int regwmask = GENMASK(regwshift - 1, 0);

sound/soc/soc-ops.c

763

unsigned long mask = GENMASK(mc->nbits - 1, 0);

sound/soc/sof/intel/apl.c

104

.host_managed_cores_mask = GENMASK(1, 0),

sound/soc/sof/intel/cnl.c

452

.host_managed_cores_mask = GENMASK(3, 0),

sound/soc/sof/intel/cnl.c

489

.host_managed_cores_mask = GENMASK(1, 0),

sound/soc/sof/intel/hda-dai.c

574

ch_mask = GENMASK(params_channels(params) - 1, 0);

sound/soc/sof/intel/hda-ipc.h

34

#define HDA_IPC_TYPE_MASK GENMASK(28, 24)

sound/soc/sof/intel/hda-loader-skl.c

95

#define HDA_CL_SD_BDLPLBA_MASK GENMASK(31, 7)

sound/soc/sof/intel/hda-mlink.c

367

u16p_replace_bits(&val, lchan, GENMASK(3, 0));

sound/soc/sof/intel/hda-mlink.c

368

u16p_replace_bits(&val, hchan, GENMASK(7, 4));

sound/soc/sof/intel/hda-mlink.c

369

u16p_replace_bits(&val, stream_id, GENMASK(13, 8));

sound/soc/sof/intel/hda-mlink.c

665

cmdsync_mask = GENMASK(AZX_REG_ML_LSYNC_CMDSYNC_SHIFT + h2link->slcount - 1,

sound/soc/sof/intel/hda-sdw-bpt.c

304

GENMASK(num_channels_tx - 1, 0),

sound/soc/sof/intel/hda-sdw-bpt.c

315

GENMASK(num_channels_rx - 1, 0),

sound/soc/sof/intel/hda.h

140

#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)

sound/soc/sof/intel/hda.h

153

GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\

sound/soc/sof/intel/hda.h

195

#define FSR_STATE_MASK GENMASK(23, 0)

sound/soc/sof/intel/hda.h

196

#define FSR_WAIT_STATE_MASK GENMASK(27, 24)

sound/soc/sof/intel/hda.h

197

#define FSR_MODULE_MASK GENMASK(30, 28)

sound/soc/sof/intel/hda.h

380

#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)

sound/soc/sof/intel/hda.h

62

#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\

sound/soc/sof/intel/icl.c

173

.host_managed_cores_mask = GENMASK(3, 0),

sound/soc/sof/intel/lnl.c

160

return wake_sts & GENMASK(SDW_MAX_DEVICES, SDW_INTEL_DEV_NUM_IDA_MIN);

sound/soc/sof/intel/mtl.h

24

#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0)

sound/soc/sof/intel/mtl.h

32

#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)

sound/soc/sof/intel/mtl.h

38

#define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)

sound/soc/sof/intel/mtl.h

43

#define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)

sound/soc/sof/intel/mtl.h

46

#define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)

sound/soc/sof/intel/mtl.h

55

#define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0)

sound/soc/sof/intel/ptl.h

14

#define PTL_MICPVCP_DDZLS_SDW GENMASK(26, 20)

sound/soc/sof/intel/shim.h

154

#define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\

sound/soc/sof/intel/shim.h

157

#define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\

sound/soc/sof/intel/skl.c

104

.host_managed_cores_mask = GENMASK(1, 0),

sound/soc/sof/ipc4-fw-reg.h

82

#define SOF_IPC4_FW_FUSE_VALUE_MASK GENMASK(7, 0)

sound/soc/sof/ipc4-fw-reg.h

85

#define SOF_IPC4_FW_LOAD_METHOD_REV_MASK GENMASK(11, 10)

sound/soc/sof/ipc4-fw-reg.h

86

#define SOF_IPC4_FW_REVISION_MIN_MASK GENMASK(15, 12)

sound/soc/sof/ipc4-fw-reg.h

87

#define SOF_IPC4_FW_REVISION_MAJ_MASK GENMASK(19, 16)

sound/soc/sof/ipc4-fw-reg.h

88

#define SOF_IPC4_FW_VERSION_MIN_MASK GENMASK(23, 20)

sound/soc/sof/ipc4-fw-reg.h

89

#define SOF_IPC4_FW_VERSION_MAJ_MASK GENMASK(27, 24)

sound/soc/sof/ipc4-mtrace.c

52

#define SOF_MTRACE_SLOT_CORE_MASK GENMASK(7, 0)

sound/soc/sof/ipc4-mtrace.c

53

#define SOF_MTRACE_SLOT_TYPE_MASK GENMASK(31, 8)

sound/soc/sof/ipc4-topology.c

2332

mask = GENMASK(step - 1, 0);

sound/soc/sof/ipc4-topology.h

18

#define SOF_IPC4_MODULE_LOAD_TYPE GENMASK(3, 0)

sound/soc/sof/ipc4-topology.h

29

#define SOF_IPC4_MODULE_INIT_CONFIG_MASK GENMASK(11, 8)

sound/soc/sof/sof-client-probes-ipc4.c

39

#define SOF_IPC4_PROBE_NODE_ID_INDEX(x) ((x) & GENMASK(7, 0))

sound/soc/sof/sof-client-probes-ipc4.c

40

#define SOF_IPC4_PROBE_NODE_ID_TYPE(x) (((x) << 8) & GENMASK(12, 8))

sound/soc/sof/sof-client-probes-ipc4.c

54

#define SOF_IPC4_PROBE_TYPE_MASK GENMASK(25, 24)

sound/soc/sof/sof-client-probes-ipc4.c

58

#define SOF_IPC4_PROBE_IDX_MASK GENMASK(31, 26)

sound/soc/sophgo/cv1800b-sound-adc.c

32

#define REG_RXADC_EN GENMASK(0, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

33

#define REG_I2S_TX_EN GENMASK(1, 1)

sound/soc/sophgo/cv1800b-sound-adc.c

36

#define REG_RXADC_CIC_OPT GENMASK(1, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

37

#define REG_RXADC_IGR_INIT GENMASK(8, 8)

sound/soc/sophgo/cv1800b-sound-adc.c

40

#define REG_GSTEPL_RXPGA GENMASK(12, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

41

#define REG_G6DBL_RXPGA GENMASK(13, 13)

sound/soc/sophgo/cv1800b-sound-adc.c

42

#define REG_GAINL_RXADC GENMASK(15, 14)

sound/soc/sophgo/cv1800b-sound-adc.c

43

#define REG_GSTEPR_RXPGA GENMASK(28, 16)

sound/soc/sophgo/cv1800b-sound-adc.c

44

#define REG_G6DBR_RXPGA GENMASK(29, 29)

sound/soc/sophgo/cv1800b-sound-adc.c

45

#define REG_GAINR_RXADC GENMASK(31, 30)

sound/soc/sophgo/cv1800b-sound-adc.c

46

#define REG_COMB_LEFT_VOLUME GENMASK(15, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

47

#define REG_COMB_RIGHT_VOLUME GENMASK(31, 16)

sound/soc/sophgo/cv1800b-sound-adc.c

50

#define REG_MUTEL_RXPGA GENMASK(0, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

51

#define REG_MUTER_RXPGA GENMASK(1, 1)

sound/soc/sophgo/cv1800b-sound-adc.c

54

#define REG_RXADC_CLK_INV GENMASK(0, 0)

sound/soc/sophgo/cv1800b-sound-adc.c

55

#define REG_RXADC_SCK_DIV GENMASK(15, 8)

sound/soc/sophgo/cv1800b-sound-adc.c

56

#define REG_RXADC_DLYEN GENMASK(23, 16)

sound/soc/sophgo/cv1800b-sound-dac.c

23

#define REG_TXDAC_EN GENMASK(0, 0)

sound/soc/sophgo/cv1800b-sound-dac.c

24

#define REG_I2S_RX_EN GENMASK(1, 1)

sound/soc/sophgo/cv1800b-sound-dac.c

27

#define REG_TXDAC_CIC_OPT GENMASK(1, 0)

sound/soc/sophgo/cv1800b-sound-dac.c

30

#define REG_TXDAC_INIT_DLY_CNT GENMASK(5, 0)

sound/soc/sophgo/cv1800b-sound-dac.c

33

#define TXDAC_OW_VAL_L_MASK GENMASK(7, 0)

sound/soc/sophgo/cv1800b-sound-dac.c

34

#define TXDAC_OW_VAL_R_MASK GENMASK(15, 8)

sound/soc/sophgo/cv1800b-sound-dac.c

35

#define TXDAC_OW_EN_L_MASK GENMASK(16, 16)

sound/soc/sophgo/cv1800b-sound-dac.c

36

#define TXDAC_OW_EN_R_MASK GENMASK(17, 17)

sound/soc/sophgo/cv1800b-tdm.c

101

#define FIFO_RX_THRESHOLD_MASK GENMASK(4, 0)

sound/soc/sophgo/cv1800b-tdm.c

102

#define FIFO_TX_THRESHOLD_MASK GENMASK(20, 16)

sound/soc/sophgo/cv1800b-tdm.c

103

#define FIFO_TX_HIGH_THRESHOLD_MASK GENMASK(28, 24)

sound/soc/sophgo/cv1800b-tdm.c

106

#define SLOT_NUM_MASK GENMASK(3, 0)

sound/soc/sophgo/cv1800b-tdm.c

107

#define SLOT_SIZE_MASK GENMASK(13, 8)

sound/soc/sophgo/cv1800b-tdm.c

108

#define DATA_SIZE_MASK GENMASK(20, 16)

sound/soc/sophgo/cv1800b-tdm.c

109

#define FB_OFFSET_MASK GENMASK(28, 24)

sound/soc/sophgo/cv1800b-tdm.c

51

#define BLK_TX_MODE_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

52

#define BLK_MASTER_MODE_MASK GENMASK(1, 1)

sound/soc/sophgo/cv1800b-tdm.c

53

#define BLK_DMA_MODE_MASK GENMASK(7, 7)

sound/soc/sophgo/cv1800b-tdm.c

56

#define CLK_MCLK_DIV_MASK GENMASK(15, 0)

sound/soc/sophgo/cv1800b-tdm.c

57

#define CLK_BCLK_DIV_MASK GENMASK(31, 16)

sound/soc/sophgo/cv1800b-tdm.c

60

#define CLK_AUD_CLK_SEL_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

61

#define CLK_BCLK_OUT_CLK_FORCE_EN_MASK GENMASK(6, 6)

sound/soc/sophgo/cv1800b-tdm.c

62

#define CLK_MCLK_OUT_EN_MASK GENMASK(7, 7)

sound/soc/sophgo/cv1800b-tdm.c

63

#define CLK_AUD_EN_MASK GENMASK(8, 8)

sound/soc/sophgo/cv1800b-tdm.c

66

#define RST_I2S_RESET_RX_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

67

#define RST_I2S_RESET_TX_MASK GENMASK(1, 1)

sound/soc/sophgo/cv1800b-tdm.c

70

#define FIFO_RX_RESET_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

71

#define FIFO_TX_RESET_MASK GENMASK(16, 16)

sound/soc/sophgo/cv1800b-tdm.c

74

#define I2S_ENABLE_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

77

#define BLK_AUTO_DISABLE_WITH_CH_EN_MASK GENMASK(4, 4)

sound/soc/sophgo/cv1800b-tdm.c

78

#define BLK_RX_BLK_CLK_FORCE_EN_MASK GENMASK(8, 8)

sound/soc/sophgo/cv1800b-tdm.c

79

#define BLK_RX_FIFO_DMA_CLK_FORCE_EN_MASK GENMASK(9, 9)

sound/soc/sophgo/cv1800b-tdm.c

80

#define BLK_TX_BLK_CLK_FORCE_EN_MASK GENMASK(16, 16)

sound/soc/sophgo/cv1800b-tdm.c

81

#define BLK_TX_FIFO_DMA_CLK_FORCE_EN_MASK GENMASK(17, 17)

sound/soc/sophgo/cv1800b-tdm.c

84

#define FRAME_LENGTH_MASK GENMASK(8, 0)

sound/soc/sophgo/cv1800b-tdm.c

85

#define FS_ACTIVE_LENGTH_MASK GENMASK(23, 16)

sound/soc/sophgo/cv1800b-tdm.c

88

#define INT_I2S_INT_EN_MASK GENMASK(8, 8)

sound/soc/sophgo/cv1800b-tdm.c

91

#define SLOT_EN_MASK GENMASK(15, 0)

sound/soc/sophgo/cv1800b-tdm.c

94

#define LRCK_MASTER_ENABLE_MASK GENMASK(0, 0)

sound/soc/sophgo/cv1800b-tdm.c

97

#define DF_WORD_LENGTH_MASK GENMASK(2, 1)

sound/soc/sophgo/cv1800b-tdm.c

98

#define DF_TX_SOURCE_LEFT_ALIGN_MASK GENMASK(6, 6)

sound/soc/spacemit/k1_i2s.c

19

#define SSCR_FIELD_DSS GENMASK(9, 5)

sound/soc/spacemit/k1_i2s.c

26

#define SSCR_FRF_PSP GENMASK(2, 1) /* Frame Format*/

sound/soc/spacemit/k1_i2s.c

29

#define SSFCR_FIELD_TFT GENMASK(3, 0) /* TXFIFO Trigger Threshold */

sound/soc/spacemit/k1_i2s.c

30

#define SSFCR_FIELD_RFT GENMASK(8, 5) /* RXFIFO Trigger Threshold */

sound/soc/spacemit/k1_i2s.c

36

#define SSPSP_FIELD_SFRMWDTH GENMASK(17, 12) /* Serial Frame Width field */

sound/soc/sprd/sprd-mcdt.c

59

#define MCDT_CH_FIFO_AE_MASK GENMASK(24, 16)

sound/soc/sprd/sprd-mcdt.c

60

#define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)

sound/soc/sprd/sprd-mcdt.c

63

#define MCDT_DMA_CH0_SEL_MASK GENMASK(3, 0)

sound/soc/sprd/sprd-mcdt.c

65

#define MCDT_DMA_CH1_SEL_MASK GENMASK(7, 4)

sound/soc/sprd/sprd-mcdt.c

67

#define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)

sound/soc/sprd/sprd-mcdt.c

69

#define MCDT_DMA_CH3_SEL_MASK GENMASK(15, 12)

sound/soc/sprd/sprd-mcdt.c

71

#define MCDT_DMA_CH4_SEL_MASK GENMASK(19, 16)

sound/soc/sprd/sprd-mcdt.c

76

#define MCDT_DMA_ACK_SEL_MASK GENMASK(3, 0)

sound/soc/sprd/sprd-mcdt.c

80

#define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)

sound/soc/starfive/jh7110_pwmdac.c

33

#define JH7110_PWMDAC_DUTY_CYCLE_MASK GENMASK(3, 2)

sound/soc/starfive/jh7110_pwmdac.c

35

#define JH7110_PWMDAC_CNT_N_MASK GENMASK(12, 4)

sound/soc/starfive/jh7110_pwmdac.c

39

#define JH7110_PWMDAC_DATA_SHIFT_MASK GENMASK(17, 15)

sound/soc/stm/stm32_i2s.c

105

#define I2S_IFCR_MASK GENMASK(11, 3)

sound/soc/stm/stm32_i2s.c

111

#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)

sound/soc/stm/stm32_i2s.c

115

#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)

sound/soc/stm/stm32_i2s.c

121

#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)

sound/soc/stm/stm32_i2s.c

133

#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\

sound/soc/stm/stm32_i2s.c

146

#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)

sound/soc/stm/stm32_i2s.c

149

#define I2S_VERR_MIN_MASK GENMASK(3, 0)

sound/soc/stm/stm32_i2s.c

150

#define I2S_VERR_MAJ_MASK GENMASK(7, 4)

sound/soc/stm/stm32_i2s.c

153

#define I2S_IPIDR_ID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_i2s.c

156

#define I2S_SIDR_ID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_i2s.c

56

#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)

sound/soc/stm/stm32_i2s.c

89

#define I2S_SR_RXPLVL GENMASK(14, 13)

sound/soc/stm/stm32_i2s.c

92

#define I2S_SR_MASK GENMASK(15, 0)

sound/soc/stm/stm32_sai.h

108

#define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)

sound/soc/stm/stm32_sai.h

115

#define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT)

sound/soc/stm/stm32_sai.h

120

#define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT)

sound/soc/stm/stm32_sai.h

124

#define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT)

sound/soc/stm/stm32_sai.h

136

#define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)

sound/soc/stm/stm32_sai.h

140

#define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)

sound/soc/stm/stm32_sai.h

144

#define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)

sound/soc/stm/stm32_sai.h

149

#define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)

sound/soc/stm/stm32_sai.h

162

#define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT)

sound/soc/stm/stm32_sai.h

174

#define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT)

sound/soc/stm/stm32_sai.h

186

#define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT)

sound/soc/stm/stm32_sai.h

192

#define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)

sound/soc/stm/stm32_sai.h

202

#define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT)

sound/soc/stm/stm32_sai.h

206

#define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT)

sound/soc/stm/stm32_sai.h

210

#define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT)

sound/soc/stm/stm32_sai.h

214

#define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT)

sound/soc/stm/stm32_sai.h

218

#define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT)

sound/soc/stm/stm32_sai.h

222

#define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT)

sound/soc/stm/stm32_sai.h

226

#define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT)

sound/soc/stm/stm32_sai.h

230

#define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)

sound/soc/stm/stm32_sai.h

236

#define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0)

sound/soc/stm/stm32_sai.h

237

#define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8)

sound/soc/stm/stm32_sai.h

238

#define SAI_HWCFGR_REGOUT GENMASK(19, 12)

sound/soc/stm/stm32_sai.h

241

#define SAI_VERR_MIN_MASK GENMASK(3, 0)

sound/soc/stm/stm32_sai.h

242

#define SAI_VERR_MAJ_MASK GENMASK(7, 4)

sound/soc/stm/stm32_sai.h

245

#define SAI_IDR_ID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_sai.h

248

#define SAI_SIDR_ID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_sai.h

39

#define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)

sound/soc/stm/stm32_sai.h

44

#define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)

sound/soc/stm/stm32_sai.h

53

#define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)

sound/soc/stm/stm32_sai.h

57

#define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT)

sound/soc/stm/stm32_sai.h

66

#define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)

sound/soc/stm/stm32_sai.h

82

#define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\

sound/soc/stm/stm32_sai.h

95

#define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)

sound/soc/stm/stm32_spdifrx.c

100

#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)

sound/soc/stm/stm32_spdifrx.c

104

#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)

sound/soc/stm/stm32_spdifrx.c

114

#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)

sound/soc/stm/stm32_spdifrx.c

124

#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)

sound/soc/stm/stm32_spdifrx.c

128

#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)

sound/soc/stm/stm32_spdifrx.c

133

#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)

sound/soc/stm/stm32_spdifrx.c

137

#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)

sound/soc/stm/stm32_spdifrx.c

142

#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)

sound/soc/stm/stm32_spdifrx.c

147

#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)

sound/soc/stm/stm32_spdifrx.c

155

#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)

sound/soc/stm/stm32_spdifrx.c

159

#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)

sound/soc/stm/stm32_spdifrx.c

167

#define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)

sound/soc/stm/stm32_spdifrx.c

168

#define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)

sound/soc/stm/stm32_spdifrx.c

171

#define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_spdifrx.c

174

#define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)

sound/soc/stm/stm32_spdifrx.c

36

#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)

sound/soc/stm/stm32_spdifrx.c

43

#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)

sound/soc/stm/stm32_spdifrx.c

55

#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)

sound/soc/stm/stm32_spdifrx.c

61

#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)

sound/soc/stm/stm32_spdifrx.c

77

#define SPDIFRX_XIMR_MASK GENMASK(6, 0)

sound/soc/stm/stm32_spdifrx.c

91

#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)

sound/soc/sunxi/sun4i-i2s.c

105

#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)

sound/soc/sunxi/sun4i-i2s.c

111

#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4)

sound/soc/sunxi/sun4i-i2s.c

118

#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4)

sound/soc/sunxi/sun4i-i2s.c

120

#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0)

sound/soc/sunxi/sun4i-i2s.c

125

#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)

sound/soc/sunxi/sun4i-i2s.c

127

#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)

sound/soc/sunxi/sun4i-i2s.c

134

#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)

sound/soc/sunxi/sun4i-i2s.c

136

#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)

sound/soc/sunxi/sun4i-i2s.c

138

#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)

sound/soc/sunxi/sun4i-i2s.c

25

#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)

sound/soc/sunxi/sun4i-i2s.c

41

#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)

sound/soc/sunxi/sun4i-i2s.c

43

#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)

sound/soc/sunxi/sun4i-i2s.c

45

#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)

sound/soc/sunxi/sun4i-i2s.c

62

#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)

sound/soc/sunxi/sun4i-i2s.c

75

#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)

sound/soc/sunxi/sun4i-i2s.c

77

#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)

sound/soc/sunxi/sun4i-i2s.c

84

#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)

sound/soc/sunxi/sun4i-i2s.c

97

#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)

sound/soc/sunxi/sun4i-spdif.c

119

#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)

sound/soc/sunxi/sun4i-spdif.c

121

#define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)

sound/soc/sunxi/sun4i-spdif.c

133

#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)

sound/soc/sunxi/sun4i-spdif.c

40

#define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)

sound/soc/sunxi/sun4i-spdif.c

41

#define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)

sound/soc/sunxi/sun4i-spdif.c

470

GENMASK(31,0), reg, &chg0);

sound/soc/sunxi/sun4i-spdif.c

476

GENMASK(9,0), reg, &chg1);

sound/soc/sunxi/sun4i-spdif.c

63

#define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)

sound/soc/sunxi/sun4i-spdif.c

65

#define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)

sound/soc/sunxi/sun4i-spdif.c

68

#define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)

sound/soc/sunxi/sun4i-spdif.c

75

#define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)

sound/soc/sunxi/sun4i-spdif.c

77

#define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)

sound/soc/sunxi/sun4i-spdif.c

80

#define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)

sound/soc/sunxi/sun50i-dmic.c

22

#define SUN50I_DMIC_EN_CTL_CHAN_MASK GENMASK(7, 0)

sound/soc/sunxi/sun50i-dmic.c

25

#define SUN50I_DMIC_SR_SAMPLE_RATE_MASK GENMASK(2, 0)

sound/soc/sunxi/sun50i-dmic.c

44

#define SUN50I_DMIC_CH_NUM_N_MASK GENMASK(2, 0)

sound/soc/sunxi/sun8i-adda-pr-regmap.c

22

#define ADDA_PR_ADDR_MASK GENMASK(4, 0)

sound/soc/sunxi/sun8i-adda-pr-regmap.c

24

#define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)

sound/soc/sunxi/sun8i-adda-pr-regmap.c

26

#define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)

sound/soc/sunxi/sun8i-codec.c

157

#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8)

sound/soc/sunxi/sun8i-codec.c

158

#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)

sound/soc/sunxi/sun8i-codec.c

159

#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)

sound/soc/sunxi/sun8i-codec.c

160

#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)

sound/soc/sunxi/sun8i-codec.c

161

#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)

sound/soc/sunxi/sun8i-codec.c

162

#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)

sound/soc/sunxi/sun8i-codec.c

163

#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)

sound/soc/sunxi/sun8i-codec.c

164

#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)

sound/soc/sunxi/sun8i-codec.c

165

#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)

sound/soc/sunxi/sun8i-codec.c

166

#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK GENMASK(1, 0)

sound/soc/sunxi/sun8i-codec.c

167

#define SUN8I_HMIC_CTRL1_HMIC_M_MASK GENMASK(15, 12)

sound/soc/sunxi/sun8i-codec.c

168

#define SUN8I_HMIC_CTRL1_HMIC_N_MASK GENMASK(11, 8)

sound/soc/sunxi/sun8i-codec.c

169

#define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB_MASK GENMASK(6, 5)

sound/soc/sunxi/sun8i-codec.c

170

#define SUN8I_HMIC_CTRL2_HMIC_SAMPLE_MASK GENMASK(15, 14)

sound/soc/sunxi/sun8i-codec.c

171

#define SUN8I_HMIC_CTRL2_HMIC_SF_MASK GENMASK(7, 6)

sound/soc/sunxi/sun8i-codec.c

172

#define SUN8I_HMIC_STS_HMIC_DATA_MASK GENMASK(12, 8)

sound/soc/uniphier/aio-reg.h

112

#define IPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)

sound/soc/uniphier/aio-reg.h

124

#define IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

132

#define IPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)

sound/soc/uniphier/aio-reg.h

135

#define IPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)

sound/soc/uniphier/aio-reg.h

152

#define PBINMXCTR_ENDIAN_MASK GENMASK(5, 4)

sound/soc/uniphier/aio-reg.h

157

#define PBINMXCTR_MEMFMT_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

197

#define OPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

212

#define OPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)

sound/soc/uniphier/aio-reg.h

226

#define OPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)

sound/soc/uniphier/aio-reg.h

235

#define OPORTMXCTR3_SRCSEL_MASK GENMASK(18, 16)

sound/soc/uniphier/aio-reg.h

262

#define OPORTMXSRC1CTR_FSOCK_MASK GENMASK(11, 10)

sound/soc/uniphier/aio-reg.h

266

#define OPORTMXSRC1CTR_FSICK_MASK GENMASK(9, 8)

sound/soc/uniphier/aio-reg.h

270

#define OPORTMXSRC1CTR_FSIIPSEL_MASK GENMASK(5, 4)

sound/soc/uniphier/aio-reg.h

273

#define OPORTMXSRC1CTR_FSISEL_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

317

#define OPORTMXRATE_I_ACLKSRC_MASK GENMASK(15, 12)

sound/soc/uniphier/aio-reg.h

32

#define A2APLLCTR0_APLLXPOW_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

322

#define OPORTMXRATE_I_ACLKSEL_MASK GENMASK(11, 8)

sound/soc/uniphier/aio-reg.h

333

#define OPORTMXRATE_I_MCKSEL_MASK GENMASK(7, 4)

sound/soc/uniphier/aio-reg.h

337

#define OPORTMXRATE_I_FSSEL_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

353

#define OPORTMXMASK_IUDXMSK_MASK GENMASK(28, 24)

sound/soc/uniphier/aio-reg.h

356

#define OPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)

sound/soc/uniphier/aio-reg.h

359

#define OPORTMXMASK_DXMSK_MASK GENMASK(12, 8)

sound/soc/uniphier/aio-reg.h

362

#define OPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)

sound/soc/uniphier/aio-reg.h

367

#define OPORTMXTYVOLPARA1_SLOPEU_MASK GENMASK(31, 16)

sound/soc/uniphier/aio-reg.h

369

#define OPORTMXTYVOLPARA2_FADE_MASK GENMASK(17, 16)

sound/soc/uniphier/aio-reg.h

373

#define OPORTMXTYVOLPARA2_TARGET_MASK GENMASK(15, 0)

sound/soc/uniphier/aio-reg.h

375

#define OPORTMXTYVOLGAINSTATUS_CUR_MASK GENMASK(15, 0)

sound/soc/uniphier/aio-reg.h

378

#define OPORTMXTYSLOTCTR_SLOTSEL_MASK GENMASK(11, 8)

sound/soc/uniphier/aio-reg.h

396

#define PBOUTMXCTR0_ENDIAN_MASK GENMASK(5, 4)

sound/soc/uniphier/aio-reg.h

40

#define A2EXMCLKSEL0_EXMCLK_MASK GENMASK(2, 0)

sound/soc/uniphier/aio-reg.h

401

#define PBOUTMXCTR0_MEMFMT_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

419

#define CDA2D_TEST_DDR_MODE_MASK GENMASK(3, 2)

sound/soc/uniphier/aio-reg.h

431

#define CDA2D_CHMXAMODE_ENDIAN_MASK GENMASK(17, 16)

sound/soc/uniphier/aio-reg.h

437

#define CDA2D_CHMXAMODE_AUPDT_MASK GENMASK(5, 4)

sound/soc/uniphier/aio-reg.h

440

#define CDA2D_CHMXAMODE_TYPE_MASK GENMASK(3, 2)

sound/soc/uniphier/aio-reg.h

46

#define A2AIOINPUTSEL_RXSEL_PCMI1_MASK GENMASK(2, 0)

sound/soc/uniphier/aio-reg.h

468

#define CDA2D_RBMXPTRU_PTRU_MASK GENMASK(1, 0)

sound/soc/uniphier/aio-reg.h

48

#define A2AIOINPUTSEL_RXSEL_PCMI2_MASK GENMASK(6, 4)

sound/soc/uniphier/aio-reg.h

50

#define A2AIOINPUTSEL_RXSEL_PCMI3_MASK GENMASK(10, 8)

sound/soc/uniphier/aio-reg.h

52

#define A2AIOINPUTSEL_RXSEL_IECI1_MASK GENMASK(14, 12)

sound/soc/uniphier/aio-reg.h

67

#define IPORTMXCTR1_LRSEL_MASK GENMASK(11, 10)

sound/soc/uniphier/aio-reg.h

76

#define IPORTMXCTR1_CHSEL_MASK GENMASK(6, 4)

sound/soc/uniphier/aio-reg.h

83

#define IPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)

sound/soc/uniphier/aio-reg.h

98

#define IPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)

sound/soc/uniphier/evea.c

40

#define ADAC1ODC_HP_DIS_RES_MASK GENMASK(2, 1)

sound/soc/uniphier/evea.c

43

#define ADAC1ODC_ADAC_RAMPCLT_MASK GENMASK(8, 7)

sound/soc/xilinx/xlnx_formatter_pcm.c

48

#define CFG_MM2S_CH_MASK GENMASK(11, 8)

sound/soc/xilinx/xlnx_formatter_pcm.c

50

#define CFG_MM2S_XFER_MASK GENMASK(14, 13)

sound/soc/xilinx/xlnx_formatter_pcm.c

54

#define CFG_S2MM_CH_MASK GENMASK(27, 24)

sound/soc/xilinx/xlnx_formatter_pcm.c

56

#define CFG_S2MM_XFER_MASK GENMASK(30, 29)

sound/soc/xilinx/xlnx_i2s.c

25

#define I2S_I2STIM_VALID_MASK GENMASK(7, 0)

sound/soc/xilinx/xlnx_spdif.c

38

#define XSPDIF_CLOCK_CONFIG_BITS_MASK GENMASK(5, 2)

sound/usb/midi2.c

323

ep->urb_free = ep->urb_free_mask = GENMASK(ep->num_urbs - 1, 0);

sound/usb/mixer_quirks.c

3627

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG1L, GENMASK(3, 0)),

sound/usb/mixer_quirks.c

3652

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG1L, GENMASK(7, 4)),

sound/usb/mixer_quirks.c

3677

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG1L, GENMASK(11, 8)),

sound/usb/mixer_quirks.c

3693

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG0L, GENMASK(15, 12)) |

sound/usb/mixer_quirks.c

3702

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG1L, GENMASK(3, 0)),

sound/usb/mixer_quirks.c

3747

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_CTL_REG1, GENMASK(2, 0)),

sound/usb/mixer_quirks.c

3755

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG0L, GENMASK(12, 10)),

sound/usb/mixer_quirks.c

3769

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_CTL_REG1, GENMASK(6, 3)),

sound/usb/mixer_quirks.c

3777

.private_value = RME_DIGIFACE_REGISTER(RME_DIGIFACE_STATUS_REG1H, GENMASK(7, 4)),

tools/arch/arm64/include/asm/brk-imm.h

37

#define CFI_BRK_IMM_TARGET GENMASK(4, 0)

tools/arch/arm64/include/asm/brk-imm.h

38

#define CFI_BRK_IMM_TYPE GENMASK(9, 5)

tools/arch/arm64/include/asm/esr.h

77

#define ESR_ELx_ISS_MASK (GENMASK(24, 0))

tools/arch/arm64/include/asm/sysreg.h

1059

#define GCS_CAP_ADDR_MASK GENMASK(63, 12)

tools/arch/arm64/include/asm/sysreg.h

1064

#define GCS_CAP_TOKEN_MASK GENMASK(11, 0)

tools/arch/arm64/include/asm/sysreg.h

333

#define SYS_PAR_EL1_FST GENMASK(6, 1)

tools/arch/arm64/include/asm/sysreg.h

372

#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)

tools/arch/arm64/include/asm/sysreg.h

958

#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)

tools/arch/riscv/include/asm/csr.h

144

#define HGATP32_VMID GENMASK(28, 22)

tools/arch/riscv/include/asm/csr.h

145

#define HGATP32_PPN GENMASK(21, 0)

tools/arch/riscv/include/asm/csr.h

149

#define HGATP64_VMID GENMASK(57, 44)

tools/arch/riscv/include/asm/csr.h

150

#define HGATP64_PPN GENMASK(43, 0)

tools/arch/riscv/include/asm/csr.h

175

#define TOPI_IID_MASK GENMASK(11, 0)

tools/arch/riscv/include/asm/csr.h

176

#define TOPI_IPRIO_MASK GENMASK(7, 0)

tools/arch/riscv/include/asm/csr.h

180

#define TOPEI_ID_MASK GENMASK(10, 0)

tools/arch/riscv/include/asm/csr.h

181

#define TOPEI_PRIO_MASK GENMASK(10, 0)

tools/arch/riscv/include/asm/csr.h

185

#define ISELECT_MASK GENMASK(8, 0)

tools/arch/riscv/include/asm/csr.h

188

#define HVICTL_IID GENMASK(27, 16)

tools/arch/riscv/include/asm/csr.h

192

#define HVICTL_IPRIO GENMASK(7, 0)

tools/arch/riscv/include/asm/csr.h

87

#define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)

tools/arch/x86/include/asm/msr-index.h

770

#define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0)

tools/arch/x86/include/asm/msr-index.h

771

#define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8)

tools/arch/x86/include/asm/msr-index.h

772

#define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16)

tools/arch/x86/include/asm/msr-index.h

773

#define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24)

tools/arch/x86/include/asm/msr-index.h

776

#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0)

tools/arch/x86/include/asm/msr-index.h

777

#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8)

tools/arch/x86/include/asm/msr-index.h

778

#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16)

tools/arch/x86/include/asm/msr-index.h

779

#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24)

tools/include/linux/bitmap.h

187

*map |= GENMASK(start + nbits - 1, start);

tools/include/linux/bitmap.h

203

*map &= ~GENMASK(start + nbits - 1, start);

tools/include/linux/find.h

100

val = *addr | ~GENMASK(size - 1, offset);

tools/include/linux/find.h

121

unsigned long val = *addr & GENMASK(size - 1, 0);

tools/include/linux/find.h

146

unsigned long val = *addr1 & *addr2 & GENMASK(size - 1, 0);

tools/include/linux/find.h

168

unsigned long val = *addr | ~GENMASK(size - 1, 0);

tools/include/linux/find.h

42

val = *addr & GENMASK(size - 1, offset);

tools/include/linux/find.h

72

val = *addr1 & *addr2 & GENMASK(size - 1, offset);

tools/include/perf/arm_pmuv3.h

221

#define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */

tools/include/perf/arm_pmuv3.h

231

#define ARMV8_PMU_OVSR_P GENMASK(30, 0)

tools/include/perf/arm_pmuv3.h

239

#define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */

tools/include/perf/arm_pmuv3.h

240

#define ARMV8_PMU_EVTYPE_TH GENMASK(43, 32)

tools/include/perf/arm_pmuv3.h

241

#define ARMV8_PMU_EVTYPE_TC GENMASK(63, 61)

tools/include/perf/arm_pmuv3.h

265

#define ARMV8_PMU_SLOTS GENMASK(7, 0)

tools/include/perf/arm_pmuv3.h

266

#define ARMV8_PMU_BUS_SLOTS GENMASK(15, 8)

tools/include/perf/arm_pmuv3.h

267

#define ARMV8_PMU_BUS_WIDTH GENMASK(19, 16)

tools/include/perf/arm_pmuv3.h

268

#define ARMV8_PMU_THWIDTH GENMASK(23, 20)

tools/perf/arch/arm/util/cs-etm.c

176

trcidr0 &= GENMASK(28, 24);

tools/perf/arch/arm/util/cs-etm.c

630

#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0)

tools/perf/arch/arm/util/cs-etm.c

634

#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12)

tools/perf/arch/arm64/util/header.c

13

#define MIDR_REVISION_MASK GENMASK(3, 0)

tools/perf/arch/arm64/util/header.c

14

#define MIDR_VARIANT_MASK GENMASK(23, 20)

tools/perf/arch/x86/tests/intel-pt-test.c

335

#define INTEL_PT_ADDR_FILT_CNT_MASK GENMASK(2, 0)

tools/perf/arch/x86/tests/intel-pt-test.c

395

.ebx = GENMASK(8, 0),

tools/perf/arch/x86/tests/intel-pt-test.c

396

.ecx = GENMASK(3, 0),

tools/perf/arch/x86/tests/intel-pt-test.c

399

.eax = GENMASK(31, 16),

tools/perf/arch/x86/tests/intel-pt-test.c

400

.ebx = GENMASK(31, 0),

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

152

#define TRCIDR1_TRCARCHMIN_MASK GENMASK(7, 4)

tools/perf/util/cs-etm.h

216

#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)

tools/perf/util/cs-etm.h

231

#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0)

tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h

13

#define HISI_PTT_8DW_CHECK_MASK GENMASK(31, 11)

tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h

14

#define HISI_PTT_IS_8DW_PKT GENMASK(31, 11)

tools/power/x86/intel-speed-select/isst-core-mbox.c

316

ctdp_level->uncore_p0 = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

317

ctdp_level->uncore_p1 = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core-mbox.c

318

ctdp_level->uncore_pm = (resp & GENMASK(31, 24)) >> 24;

tools/power/x86/intel-speed-select/isst-core-mbox.c

337

ctdp_level->uncore_p0 = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

338

ctdp_level->uncore_p1 = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core-mbox.c

398

ctdp_level->sse_p1 = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

399

ctdp_level->avx2_p1 = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core-mbox.c

400

ctdp_level->avx512_p1 = (resp & GENMASK(23, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core-mbox.c

401

ctdp_level->amx_p1 = (resp & GENMASK(31, 24)) >> 24;

tools/power/x86/intel-speed-select/isst-core-mbox.c

421

ctdp_level->mem_freq = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

454

ctdp_level->pkg_tdp = resp & GENMASK(14, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

455

ctdp_level->tdp_ratio = (resp & GENMASK(23, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core-mbox.c

467

ctdp_level->t_proc_hot = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

491

ctdp_level->pkg_max_power = resp & GENMASK(14, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

492

ctdp_level->pkg_min_power = (resp & GENMASK(30, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core-mbox.c

552

trl[0] = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

553

trl[1] = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core-mbox.c

554

trl[2] = (resp & GENMASK(23, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core-mbox.c

555

trl[3] = (resp & GENMASK(31, 24)) >> 24;

tools/power/x86/intel-speed-select/isst-core-mbox.c

567

trl[4] = resp & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core-mbox.c

568

trl[5] = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core-mbox.c

569

trl[6] = (resp & GENMASK(23, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core-mbox.c

570

trl[7] = (resp & GENMASK(31, 24)) >> 24;

tools/power/x86/intel-speed-select/isst-core-mbox.c

669

pbf_info->p1_high = (resp & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core.c

156

trl[0] = msr_trl & GENMASK(7, 0);

tools/power/x86/intel-speed-select/isst-core.c

157

trl[1] = (msr_trl & GENMASK(15, 8)) >> 8;

tools/power/x86/intel-speed-select/isst-core.c

158

trl[2] = (msr_trl & GENMASK(23, 16)) >> 16;

tools/power/x86/intel-speed-select/isst-core.c

159

trl[3] = (msr_trl & GENMASK(31, 24)) >> 24;

tools/power/x86/intel-speed-select/isst-core.c

160

trl[4] = (msr_trl & GENMASK(39, 32)) >> 32;

tools/power/x86/intel-speed-select/isst-core.c

161

trl[5] = (msr_trl & GENMASK(47, 40)) >> 40;

tools/power/x86/intel-speed-select/isst-core.c

162

trl[6] = (msr_trl & GENMASK(55, 48)) >> 48;

tools/power/x86/intel-speed-select/isst-core.c

163

trl[7] = (msr_trl & GENMASK(63, 56)) >> 56;

tools/power/x86/turbostat/turbostat.c

19

#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT)

tools/power/x86/turbostat/turbostat.c

20

#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT)

tools/power/x86/turbostat/turbostat.c

21

#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT)

tools/power/x86/turbostat/turbostat.c

8214

tcc_offset = (msr >> 24) & GENMASK(bits - 1, 0);

tools/testing/selftests/arm64/fp/fp-ptrace.c

36

#define FPMR_LSCALE2_MASK GENMASK(37, 32)

tools/testing/selftests/arm64/fp/fp-ptrace.c

37

#define FPMR_NSCALE_MASK GENMASK(31, 24)

tools/testing/selftests/arm64/fp/fp-ptrace.c

38

#define FPMR_LSCALE_MASK GENMASK(22, 16)

tools/testing/selftests/arm64/fp/fp-ptrace.c

39

#define FPMR_OSC_MASK GENMASK(15, 15)

tools/testing/selftests/arm64/fp/fp-ptrace.c

40

#define FPMR_OSM_MASK GENMASK(14, 14)

tools/testing/selftests/bpf/xdp_hw_metadata.c

210

#define VLAN_PRIO_MASK GENMASK(15, 13) /* Priority Code Point */

tools/testing/selftests/bpf/xdp_hw_metadata.c

211

#define VLAN_DEI_MASK GENMASK(12, 12) /* Drop Eligible Indicator */

tools/testing/selftests/bpf/xdp_hw_metadata.c

212

#define VLAN_VID_MASK GENMASK(11, 0) /* VLAN Identifier */

tools/testing/selftests/kvm/arm64/external_aborts.c

287

*ptep &= ~GENMASK(47, 12);

tools/testing/selftests/kvm/arm64/hypercalls.c

18

#define FW_REG_ULIMIT_VAL(max_feat_bit) (GENMASK(max_feat_bit, 0))

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

52

mask |= GENMASK(n - 1, 0);

tools/testing/selftests/kvm/include/arm64/gic_v3.h

352

#define GICR_VSGIR_VPEID GENMASK(15, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

357

#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

95

#define GICD_TYPER2_VID GENMASK(4, 0)

tools/testing/selftests/kvm/include/arm64/processor.h

111

#define PTE_ATTRINDX_MASK GENMASK(4, 2)

tools/testing/selftests/kvm/include/arm64/processor.h

123

#define PTE_ADDR_MASK(page_shift) GENMASK(47, (page_shift))

tools/testing/selftests/kvm/include/arm64/processor.h

124

#define PTE_ADDR_51_48 GENMASK(15, 12)

tools/testing/selftests/kvm/include/arm64/processor.h

126

#define PTE_ADDR_MASK_LPA2(page_shift) GENMASK(49, (page_shift))

tools/testing/selftests/kvm/include/arm64/processor.h

127

#define PTE_ADDR_51_50_LPA2 GENMASK(9, 8)

tools/testing/selftests/kvm/include/x86/apic.h

31

#define GET_APIC_PRI(x) (((x) & GENMASK(7, 4)) >> 4)

tools/testing/selftests/kvm/include/x86/apic.h

32

#define SET_APIC_PRI(x, y) (((x) & ~GENMASK(7, 4)) | (y << 4))

tools/testing/selftests/kvm/include/x86/processor.h

729

return (gprs[reg] & GENMASK(hi, lo)) >> lo;

tools/testing/selftests/kvm/lib/arm64/gic.c

82

intid = irqstat & GENMASK(23, 0);

tools/testing/selftests/kvm/lib/arm64/processor.c

348

ttbr0_el1 = vm->mmu.pgd & GENMASK(47, vm->page_shift);

tools/testing/selftests/kvm/lib/arm64/processor.c

356

ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->mmu.pgd) << 2;

tools/testing/selftests/kvm/lib/arm64/processor.c

72

pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT;

tools/testing/selftests/kvm/lib/arm64/processor.c

77

pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT;

tools/testing/selftests/kvm/lib/x86/processor.c

1024

(&entry->eax)[property.reg] &= ~GENMASK(property.hi_bit, property.lo_bit);

tools/testing/selftests/kvm/lib/x86/processor.c

922

return ((&entry->eax)[reg] & GENMASK(hi, lo)) >> lo;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

341

unavailable_mask &= GENMASK(X86_PROPERTY_PMU_EVENTS_MASK.hi_bit,

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

102

return cr8 & GENMASK(3, 0);

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

174

return sregs->cr8 & GENMASK(3, 0);