GENERAL_PWRMGT
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
GENERAL_PWRMGT, STATIC_PM_EN, 1);
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
u32 tmp = RREG32(GENERAL_PWRMGT);
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
WREG32_SMC(GENERAL_PWRMGT, tmp);
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
WREG32_P(GENERAL_PWRMGT, 0,
WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
(RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT;
WREG32_P(GENERAL_PWRMGT, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK);
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN));
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);