GEN8_GT_IMR
reg = GEN8_GT_IMR(2);
pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
#define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \
MMIO_D(GEN8_GT_IMR(0));
MMIO_D(GEN8_GT_IMR(1));
MMIO_D(GEN8_GT_IMR(2));
MMIO_D(GEN8_GT_IMR(3));