drivers/gpu/drm/i915/gt/intel_engine_cs.c

139

{ .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },

drivers/gpu/drm/i915/gt/intel_engine_regs.h

38

#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

39

#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

40

#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))

drivers/gpu/drm/i915/gt/intel_rc6.c

464

(intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1055

intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1063

RING_PSMI_CTL(GEN6_BSD_RING_BASE),

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1076

intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),

drivers/gpu/drm/i915/gvt/handlers.c

2190

MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \

drivers/gpu/drm/i915/gvt/handlers.c

2816

MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1261

MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

55

MMIO_F(prefix(GEN6_BSD_RING_BASE), s); \