GEM_BFINS
dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,