GBE_REG_ADDR
val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi));
writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo));
writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
val = readl(GBE_REG_ADDR(gbe_dev, ss_regs, rgmii_status));
writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset));
v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset));
xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control));
writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control));
rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen);
rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen);
writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
GBE_REG_ADDR(slave, port_regs, rx_pri_map));
GBE_REG_ADDR(priv, host_port_regs, tx_pri_map));
writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs,
writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl));
writel(ts_en, GBE_REG_ADDR(slave, port_regs, ts_ctl));
writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype));
writel(ctl, GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2));
reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));
writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));
writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, control));
writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,