G1_REG_REF_PIC
vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));
{ G1_REG_REF_PIC(7), 22, 0x3ff },
{ G1_REG_REF_PIC(7), 12, 0x3ff },
{ G1_REG_REF_PIC(7), 2, 0x3ff },
vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0));
{ G1_REG_REF_PIC(2), 18, 0x3f },
{ G1_REG_REF_PIC(2), 12, 0x3f },
{ G1_REG_REF_PIC(2), 6, 0x3f },
{ G1_REG_REF_PIC(2), 0, 0x3f },
{ G1_REG_REF_PIC(0), 21, 0x7f },
{ G1_REG_REF_PIC(0), 14, 0x7f },
{ G1_REG_REF_PIC(0), 7, 0x7f },
{ G1_REG_REF_PIC(0), 0, 0x7f },
{ G1_REG_REF_PIC(1), 21, 0x7f },
{ G1_REG_REF_PIC(1), 14, 0x7f },
{ G1_REG_REF_PIC(1), 7, 0x7f },
{ G1_REG_REF_PIC(1), 0, 0x7f },
{ G1_REG_REF_PIC(3), 11, 0x7ff },
{ G1_REG_REF_PIC(3), 0, 0x7ff },
{ G1_REG_REF_PIC(3), 27, 0x1f },
{ G1_REG_REF_PIC(3), 22, 0x1f },
{ G1_REG_REF_PIC(4), 22, 0x3ff },
{ G1_REG_REF_PIC(4), 12, 0x3ff },
{ G1_REG_REF_PIC(4), 2, 0x3ff },
{ G1_REG_REF_PIC(5), 22, 0x3ff },
{ G1_REG_REF_PIC(5), 12, 0x3ff },
{ G1_REG_REF_PIC(5), 2, 0x3ff },
{ G1_REG_REF_PIC(6), 22, 0x3ff },
{ G1_REG_REF_PIC(6), 12, 0x3ff },
{ G1_REG_REF_PIC(6), 2, 0x3ff },