G1_REG_BD_REF_PIC
vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));
{ G1_REG_BD_REF_PIC(0), 22, 0x3ff },
{ G1_REG_BD_REF_PIC(0), 12, 0x3ff },
{ G1_REG_BD_REF_PIC(0), 2, 0x3ff },
{ G1_REG_BD_REF_PIC(1), 22, 0x3ff },
{ G1_REG_BD_REF_PIC(1), 12, 0x3ff },
{ G1_REG_BD_REF_PIC(1), 2, 0x3ff },
{ G1_REG_BD_REF_PIC(2), 22, 0x3ff },
{ G1_REG_BD_REF_PIC(2), 12, 0x3ff },
{ G1_REG_BD_REF_PIC(2), 2, 0x3ff },
{ G1_REG_BD_REF_PIC(3), 22, 0x3ff },
{ G1_REG_BD_REF_PIC(3), 12, 0x3ff },
reg.base = G1_REG_BD_REF_PIC(3);
{ G1_REG_BD_REF_PIC(4), 11, 0x7ff },
{ G1_REG_BD_REF_PIC(4), 0, 0x7ff },
{ G1_REG_BD_REF_PIC(4), 27, 0x1f },
{ G1_REG_BD_REF_PIC(4), 22, 0x1f },