GATE_TOP2
GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),