GATE_SCLK_FSYS
GATE_SCLK_FSYS,
GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),