GATE_PERI0
GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0),
GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1),
GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2),
GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3),
GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4),
GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5),
GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6),
GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7),
GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8),
GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9),
GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10),
GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13),
GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17),
GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23),
GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24),
GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27),
GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28),
GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29),
GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30),
GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),