drivers/gpu/drm/i915/display/i9xx_wm.c

1124

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1130

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);

drivers/gpu/drm/i915/display/i9xx_wm.c

1175

if (level <= G4X_WM_LEVEL_HPLL) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1193

if (level >= G4X_WM_LEVEL_HPLL &&

drivers/gpu/drm/i915/display/i9xx_wm.c

1194

wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))

drivers/gpu/drm/i915/display/i9xx_wm.c

1228

level = G4X_WM_LEVEL_HPLL;

drivers/gpu/drm/i915/display/i9xx_wm.c

1347

g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||

drivers/gpu/drm/i915/display/i9xx_wm.c

1349

g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&

drivers/gpu/drm/i915/display/i9xx_wm.c

3797

max_level = G4X_WM_LEVEL_HPLL;

drivers/gpu/drm/i915/display/i9xx_wm.c

3818

level = G4X_WM_LEVEL_HPLL;

drivers/gpu/drm/i915/display/i9xx_wm.c

921

display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;

drivers/gpu/drm/i915/display/i9xx_wm.c

923

display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;

drivers/gpu/drm/i915/display/i9xx_wm.c

960

case G4X_WM_LEVEL_HPLL: