G4X_WM_LEVEL_HPLL
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
if (level <= G4X_WM_LEVEL_HPLL) {
if (level >= G4X_WM_LEVEL_HPLL &&
wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
level = G4X_WM_LEVEL_HPLL;
g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
max_level = G4X_WM_LEVEL_HPLL;
level = G4X_WM_LEVEL_HPLL;
display->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
case G4X_WM_LEVEL_HPLL: