drivers/gpu/drm/i915/gvt/gvt.h

647

return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;

drivers/gpu/drm/i915/gvt/handlers.c

2257

F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2261

MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2263

MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2270

MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2271

MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2273

MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2274

MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2275

MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2277

MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2278

MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2279

MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2281

F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2282

MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2284

MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2286

MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2295

MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2296

MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2297

MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2457

MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2559

MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2570

MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2572

MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2574

MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2591

MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2592

MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2593

MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2594

MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2749

F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2750

MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2768

MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2771

MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2773

MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,