FZC_MAC
#define XMAC_PORT0_OFF (FZC_MAC + 0x000000)
#define XMAC_PORT1_OFF (FZC_MAC + 0x006000)
#define BMAC_PORT2_OFF (FZC_MAC + 0x00c000)
#define BMAC_PORT3_OFF (FZC_MAC + 0x010000)
#define XPCS_CONTROL1 (FZC_MAC + 0x00000UL)
#define XPCS_STATUS1 (FZC_MAC + 0x00008UL)
#define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL)
#define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL)
#define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL)
#define XPCS_CONTROL2 (FZC_MAC + 0x00028UL)
#define XPCS_STATUS2 (FZC_MAC + 0x00030UL)
#define XPCS_PKG_ID (FZC_MAC + 0x00038UL)
#define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
#define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL)
#define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL)
#define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL)
#define XPCS_MASK1 (FZC_MAC + 0x00060UL)
#define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL)
#define XPCS_TX_SM (FZC_MAC + 0x00070UL)
#define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL)
#define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL)
#define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL)
#define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL)
#define PCS_MII_CTL (FZC_MAC + 0x00000UL)
#define PCS_MII_STAT (FZC_MAC + 0x00008UL)
#define PCS_MII_ADV (FZC_MAC + 0x00010UL)
#define PCS_MII_PARTNER (FZC_MAC + 0x00018UL)
#define PCS_CONF (FZC_MAC + 0x00020UL)
#define PCS_STATE (FZC_MAC + 0x00028UL)
#define PCS_INTERRUPT (FZC_MAC + 0x00030UL)
#define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL)
#define PCS_PKT_CNT (FZC_MAC + 0x000c0UL)
#define MIF_BB_MDC (FZC_MAC + 0x16000UL)
#define MIF_BB_MDO (FZC_MAC + 0x16008UL)
#define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL)
#define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL)
#define MIF_CONFIG (FZC_MAC + 0x16020UL)
#define MIF_POLL_STATUS (FZC_MAC + 0x16028UL)
#define MIF_POLL_MASK (FZC_MAC + 0x16030UL)
#define MIF_SM (FZC_MAC + 0x16038UL)
#define MIF_STATUS (FZC_MAC + 0x16040UL)
#define MIF_MASK (FZC_MAC + 0x16048UL)
#define ENET_SERDES_RESET (FZC_MAC + 0x14000UL)
#define ENET_SERDES_CFG (FZC_MAC + 0x14008UL)
#define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL)
#define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL)
#define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL)
#define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL)
#define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL)
#define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL)
#define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL)
#define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL)
#define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL)