drivers/clocksource/timer-fsl-ftm.c

54

val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);

drivers/clocksource/timer-fsl-ftm.c

65

val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);

drivers/counter/ftm-quaddec.c

125

*cnt_mode = FIELD_GET(FTM_SC_PS_MASK, scflags);

drivers/counter/ftm-quaddec.c

138

FTM_FIELD_UPDATE(ftm, FTM_SC, FTM_SC_PS_MASK, cnt_mode);

drivers/pwm/pwm-fsl-ftm.c

273

regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,

drivers/rtc/rtc-fsl-ftm-alarm.c

32

#define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)

drivers/rtc/rtc-fsl-ftm-alarm.c

66

val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);

drivers/rtc/rtc-fsl-ftm-alarm.c

67

val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));

drivers/rtc/rtc-fsl-ftm-alarm.c

77

val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);