drivers/gpu/drm/gma500/cdv_intel_display.c

473

if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {

drivers/gpu/drm/gma500/cdv_intel_display.c

476

REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));

drivers/gpu/drm/gma500/cdv_intel_display.c

536

REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

drivers/gpu/drm/i915/display/i9xx_wm.c

171

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

172

intel_de_write(display, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

184

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

185

val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :

drivers/gpu/drm/i915/display/i9xx_wm.c

186

_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);

drivers/gpu/drm/i915/display/i9xx_wm.c

3773

wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

100

sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;