ALPHA_REG_BITWIDTH
&l, &a, ALPHA_REG_BITWIDTH);
rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
freq_hz = alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BITWIDTH);
clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false);
&l, &a, ALPHA_REG_BITWIDTH);
clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false);
clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH);
clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true);
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)