FRS
{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
#define FRT FRS
#define FRSp FRS + 1
{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},