FRAC_DIV_CFG_REG
writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG);
writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG);
FRAC_DIV_CFG_REG);
port->membase + FRAC_DIV_CFG_REG);
FRAC_DIV_CFG_REG);
frac_div = readl(port->membase + FRAC_DIV_CFG_REG);