ALT1
#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0