FM_A
outpw(FM_A(FM_MDREG1),FM_MINIT) ;
stu = inpw(FM_A(FM_ST1U)) ;
stl = inpw(FM_A(FM_ST1L)) ;
outpw(FM_A(FM_MDREG1),FM_MINIT) ;
outpw(FM_A(FM_IMSK2U),~(mac_imsk2u | mac_beacon_imsk2u)) ;
return (inpw(FM_A(FM_STMCHN))>>4) & 7;
tneg = (u_long)((long)inpw(FM_A(FM_TNEG))<<5) ;
return (u_long)((tneg + ((inpw(FM_A(FM_TMRS))>>10)&0x1f)) |
+ (u_short) inpw(FM_A(FM_FCNTR)) ;
+ (u_short) inpw(FM_A(FM_LCNTR)) ;
outpw(FM_A(FM_AFCMD),FM_IINV_CAM) ;
outpw(FM_A(FM_AFMASK2),0xffff) ;
outpw(FM_A(FM_AFMASK1),(u_short) ~((fu[0] << 8) + fu[1])) ;
outpw(FM_A(FM_AFMASK0),(u_short) ~((fu[2] << 8) + fu[3])) ;
outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
outpw(FM_A(FM_AFCOMP2), 0xc000) ;
outpw(FM_A(FM_AFCOMP1), 0x0000) ;
outpw(FM_A(FM_AFCOMP0), 0x0000) ;
outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
+ (u_short) inpw(FM_A(FM_ECNTR)) ;
outpw(FM_A(FM_AFMASK0),0xffff) ;
outpw(FM_A(FM_AFMASK1),0xffff) ;
outpw(FM_A(FM_AFMASK2),0xffff) ;
outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
outpw(FM_A(FM_AFCOMP2),
outpw(FM_A(FM_AFCOMP1),
outpw(FM_A(FM_AFCOMP0),
outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
outpw(FM_A(FM_CMDREG1),FM_ICL) ; /* force claim */
outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
p = (u_long)inpw(FM_A(FM_MDRU))<<16 ;
p += (u_long)inpw(FM_A(FM_MDRL)) ;
outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
outpw(FM_A(FM_CMDREG2),FM_IRSTQ) ; /* reset transmit queues */
outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */
outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */
outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */
outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */
outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ;
outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ;
outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ;
outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
outpw(FM_A(FM_RPXA1),rbc_ram_addr) ; /* a1-send pointer */
outpw(FM_A(FM_WPXA1),rbc_ram_addr) ;
outpw(FM_A(FM_SWPXA1),rbc_ram_addr) ;
outpw(FM_A(FM_EAA1),rbc_ram_addr) ;
outpw(FM_A(FM_TSYNC),(unsigned int) (((-sync_bw) >> 5) & 0xffff) ) ;
outpw(FM_A(FM_FCNTR),0) ;
outpw(FM_A(FM_LCNTR),0) ;
outpw(FM_A(FM_ECNTR),0) ;
outpw(FM_A(FM_SAID),my_said) ; /* set short address */
outpw(FM_A(FM_LAIL),(unsigned short)((smc->hw.fddi_home_addr.a[4]<<8) +
outpw(FM_A(FM_LAIC),(unsigned short)((smc->hw.fddi_home_addr.a[2]<<8) +
outpw(FM_A(FM_LAIM),(unsigned short)((smc->hw.fddi_home_addr.a[0]<<8) +
outpw(FM_A(FM_SAGP),my_sagp) ; /* set short group address */
outpw(FM_A(FM_LAGL),(unsigned short)((smc->hw.fp.group_addr.a[4]<<8) +
outpw(FM_A(FM_LAGC),(unsigned short)((smc->hw.fp.group_addr.a[2]<<8) +
outpw(FM_A(FM_LAGM),(unsigned short)((smc->hw.fp.group_addr.a[0]<<8) +
outpw(FM_A(FM_TREQ1),(unsigned short)(t_requ>>16)) ;
outpw(FM_A(FM_TREQ0),(unsigned short)t_requ) ;
outpw(FM_A(FM_CMDREG2),FM_ISTTB) ;
outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ;
outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ;
outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ;
while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\
outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ;
outpw(FM_A(FM_WPXSF),0) ;
outpw(FM_A(FM_RPXSF),0) ;
SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
outpw(FM_A(FM_CMDREG1),FM_ICLLR) ; /* clear receive lock */
outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
outpw(FM_A(FM_IMSK1U),(unsigned short)~mac_imsk1u);
outpw(FM_A(FM_IMSK1L),(unsigned short)~mac_imsk1l);
outpw(FM_A(FM_IMSK2U),(unsigned short)~mac_imsk2u);
outpw(FM_A(FM_IMSK2L),(unsigned short)~mac_imsk2l);
outpw(FM_A(FM_IMSK3U),(unsigned short)~mac_imsk3u);
outpw(FM_A(FM_IMSK3L),(unsigned short)~mac_imsk3l);
imask = ~(inpw(FM_A(FM_IMSK1U))) ;
while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\
outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMS)) ;
outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMA0)) ;
imask = ~(inpw(FM_A(FM_IMSK1U))) ;
outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMS)) ;
outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMA0)) ;
outpw(FM_A(FM_IMSK1U),MW) ;
outpw(FM_A(FM_IMSK1L),MW) ;
outpw(FM_A(FM_IMSK2U),MW) ;
outpw(FM_A(FM_IMSK2L),MW) ;
outpw(FM_A(FM_IMSK3U),MW) ;
outpw(FM_A(FM_IMSK3L),MW) ;
SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
outpw(FM_A(FM_CMDREG2),FM_IACTR) ;
outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ;
outpw(FM_A(FM_CMDREG2),FM_IACTR) ;/* abort current transmit activity */
SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
SETMASK(FM_A(FM_MDREG1),FM_MINIT,FM_MMODE) ;
SETMASK(FM_A(FM_MDREG1),FM_MONLINE | FM_SELRA | MDR1INIT |
outpw(FM_A(FM_MDREG1),FM_MINIT) ; /* FORMAC+ init mode */
outpw(FM_A(FM_MDREG1),FM_MMEMACT) ; /* FORMAC+ memory activ mode */
outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
outpw(FM_A(FM_FRMTHR),14<<12) ; /* switch on */
outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ;
outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ;
outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ;
outpw(FM_A(FM_TMAX),(u_short)t_max) ;
outpw(FM_A(FM_TVX), (u_short) (- US2BCLK(52))/255 & MB) ;
outpw(FM_A(FM_TVX),
outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
outpw(FM_A(FM_CMDREG1),FM_ICLLR); /* clear receive lock */
outpw(FM_A(FM_UNLCKDLY),(0xff|(0xff<<8))) ;
SETMASK(FM_A(FM_MDREG1),FM_SELRA,FM_SELRA) ;
#define MODR1 FM_A(FM_MDREG1) /* mode register 1 */
#define MODR2 FM_A(FM_MDREG2) /* mode register 2 */
#define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */
#define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */
#define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
#define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
#define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
outpw(FM_A(FM_MDRL),(unsigned int)(dd))
#define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))
#define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
#define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
#define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
#define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))
#define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
#define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
#define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
stu = inpw(FM_A(FM_ST1U)) ;
stl = inpw(FM_A(FM_ST1L)) ;
stu= inpw(FM_A(FM_ST2U)) ;
stl= inpw(FM_A(FM_ST2L)) ;
stu= inpw(FM_A(FM_ST3U)) ;
stl= inpw(FM_A(FM_ST3L)) ;