drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

537

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

538

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

539

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

540

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

542

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

543

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

549

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

551

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

552

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

553

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

555

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

556

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

562

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

563

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

564

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

565

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

566

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

568

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

569

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

109

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

118

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

124

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

134

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

156

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

163

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

168

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

177

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

204

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

209

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

214

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

274

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

284

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

306

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

311

REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

315

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

326

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

341

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

344

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

350

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

101

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

102

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

103

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

104

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

105

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

106

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

107

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

108

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

109

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

110

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

114

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

115

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

116

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

117

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

118

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

119

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

120

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

121

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

210

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

211

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

212

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

213

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

214

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

215

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

216

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

217

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

218

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

222

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

223

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

224

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

225

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

226

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

227

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

228

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

288

uint32_t FMT_BIT_DEPTH_CONTROL;

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

45

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

87

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

122

REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

54

REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

65

REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

37

SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

54

uint32_t FMT_BIT_DEPTH_CONTROL; \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

544

SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \

drivers/gpu/drm/radeon/cik.c

8802

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1345

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/r600.c

346

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);