FIFO
sun_pci_fd_out_byte(port, 0x08, FIFO);
result[i++] = inb(FIFO);
sun_pci_fd_out_byte(port, 0x07, FIFO);
sun_pci_fd_out_byte(port, drive & 0x03, FIFO);
#define TxErrMask (WND | TABRT | FIFO | LINK)
if (status & FIFO)
fifo = brcmf_skb_htod_tag_get_field(skb, FIFO);
brcmf_skb_htod_tag_set_field(p, FIFO, fifo);
outb(0xaa, FIFO(pb));
inb(FIFO(pb));
outb(0xaa, FIFO(pb));
outb(0xaa, FIFO(pb));
const unsigned long fifo = FIFO(port);
outb(0, FIFO(port));
outb(0, FIFO(port));
if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
(FIFO | TIMEOUT | RESET | SCAM_SEL));
else if (p_int & FIFO) {
WRW_HARPOON((p_port + hp_intstat), FIFO);
__USBHS_DFIFO_INIT(priv, fifo, channel, D##channel##FIFO)
NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
par->FIFO = par->REGS + (0x00800000 / 4);
volatile u32 __iomem *FIFO;
par->riva.FIFO =
LOAD_FIXED_STATE(nv4,FIFO);
chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
LOAD_FIXED_STATE(nv10,FIFO);
chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
LOAD_FIXED_STATE(Riva,FIFO);
(RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
(RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
(RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
(RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
(RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
(RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
volatile U032 __iomem *FIFO;