drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

120

FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

125

FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

129

SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET, mask_sh),\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

174

type FIFO_RESET;\

drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c

125

writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl);

drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c

126

writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl);

drivers/video/fbdev/sstfb.c

1171

sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);

drivers/video/fbdev/sstfb.c

1257

sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);

drivers/video/fbdev/sstfb.c

1267

sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);

drivers/video/fbdev/sstfb.c

527

sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);

drivers/video/fbdev/sstfb.c

611

sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);