drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

136

FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

167

FIFO_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

131

SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

176

type FIFO_ENABLE;\

sound/soc/ti/davinci-mcasp.c

282

mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);

sound/soc/ti/davinci-mcasp.c

283

mcasp_set_bits(mcasp, reg, FIFO_ENABLE);

sound/soc/ti/davinci-mcasp.c

326

mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);

sound/soc/ti/davinci-mcasp.c

327

mcasp_set_bits(mcasp, reg, FIFO_ENABLE);

sound/soc/ti/davinci-mcasp.c

399

mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);

sound/soc/ti/davinci-mcasp.c

430

mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);