drivers/gpib/fmh_gpib/fmh_gpib.c

1156

fifo_status = fifos_read(priv, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1212

fifos_write(priv, 0x0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1227

fifos_write(priv, 0x0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1335

fifos_write(e_priv, RX_FIFO_CLEAR | TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1342

fifo_status_bits = fifos_read(e_priv, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1501

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

1632

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

327

(fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) &

drivers/gpib/fmh_gpib/fmh_gpib.c

436

fifos_write(e_priv, TX_FIFO_DMA_REQUEST_ENABLE | TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

463

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

580

(fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) &

drivers/gpib/fmh_gpib/fmh_gpib.c

611

fifos_write(e_priv, TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

619

fifos_write(e_priv, TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

654

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

754

fifos_write(e_priv, RX_FIFO_DMA_REQUEST_ENABLE | RX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

781

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

800

while ((fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & RX_FIFO_EMPTY) == 0) {

drivers/gpib/fmh_gpib/fmh_gpib.c

931

fifos_write(e_priv, RX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

938

fifos_write(e_priv, RX_FIFO_HALF_FULL_INTERRUPT_ENABLE, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

956

fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);

drivers/gpib/fmh_gpib/fmh_gpib.c

959

while ((fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & RX_FIFO_EMPTY) == 0) {