FIELD_PREP_WM16
r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]);
r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]);
r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]);
r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]);
r1 = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]);
r2 = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1);
r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1);
*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 1) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 1) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 1) |
FIELD_PREP_WM16(DDRMON_CTRL_LP5_BANK_MODE_MASK,
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_TIMER_CNT_EN, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0) |
FIELD_PREP_WM16(DDRMON_CTRL_HARDWARE_EN, 0),
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 1),
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0),
FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0));
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0));
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1));
FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0));
FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0));
FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0));
FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf));
FIELD_PREP_WM16(RK3399_DSI1_ENABLE,
FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
FIELD_PREP_WM16(RK3228_HDMI_HPD_VSEL, 1) |
FIELD_PREP_WM16(RK3228_HDMI_SDA_VSEL, 1) |
FIELD_PREP_WM16(RK3228_HDMI_SCL_VSEL, 1));
FIELD_PREP_WM16(RK3228_HDMI_SDAIN_MSK, 1) |
FIELD_PREP_WM16(RK3228_HDMI_SCLIN_MSK, 1));
FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 1) |
FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 1));
FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |
FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0));
FIELD_PREP_WM16(RK3328_HDMI_HPD_SARADC, 0) |
FIELD_PREP_WM16(RK3328_HDMI_CEC_5V, 0) |
FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |
FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0) |
FIELD_PREP_WM16(RK3328_HDMI_HPD_5V, 0));
FIELD_PREP_WM16(RK3328_HDMI_SDA5V_GRF, 0) |
FIELD_PREP_WM16(RK3328_HDMI_SCL5V_GRF, 0) |
FIELD_PREP_WM16(RK3328_HDMI_HPD5V_GRF, 0) |
FIELD_PREP_WM16(RK3328_HDMI_CEC5V_GRF, 0));
FIELD_PREP_WM16(RK3328_HDMI_SDAIN_MSK, 1) |
FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1) |
FIELD_PREP_WM16(RK3328_HDMI_HPD_IOE, 0));
FIELD_PREP_WM16(RK3568_HDMI_SDAIN_MSK, 1) |
FIELD_PREP_WM16(RK3568_HDMI_SCLIN_MSK, 1));
val = (FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1) |
FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0));
val = (FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1) |
FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0));
val = (FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) |
FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0));
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1);
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1);
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1);
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1);
val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0);
val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0);
val = FIELD_PREP_WM16(RK3576_SCLIN_MASK, 1) |
FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) |
FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) |
FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1);
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
val = FIELD_PREP_WM16(RK3588_SCLIN_MASK, 1) |
FIELD_PREP_WM16(RK3588_SDAIN_MASK, 1) |
FIELD_PREP_WM16(RK3588_MODE_MASK, 1) |
FIELD_PREP_WM16(RK3588_I2S_SEL_MASK, 1);
val = FIELD_PREP_WM16(RK3588_HPD_HDMI0_IO_EN_MASK, 1) |
FIELD_PREP_WM16(RK3588_HPD_HDMI1_IO_EN_MASK, 1);
val = FIELD_PREP_WM16(RK3588_HDMI1_GRANT_SEL, 1);
val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1);
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
val = FIELD_PREP_WM16(RK3576_COLOR_DEPTH_MASK, RK3576_10BPC);
val = FIELD_PREP_WM16(RK3576_COLOR_DEPTH_MASK, RK3576_8BPC);
val = FIELD_PREP_WM16(RK3588_COLOR_DEPTH_MASK, RK3588_10BPC);
val = FIELD_PREP_WM16(RK3588_COLOR_DEPTH_MASK, RK3588_8BPC);
value = FIELD_PREP_WM16(RK3036_HDMI_PHSYNC, psync);
value |= FIELD_PREP_WM16(RK3036_HDMI_PVSYNC, psync);
#define PX30_LVDS_TIE_CLKS(val) FIELD_PREP_WM16(BIT(8), (val))
#define PX30_LVDS_INVERT_CLKS(val) FIELD_PREP_WM16(BIT(9), (val))
#define PX30_LVDS_INVERT_DCLK(val) FIELD_PREP_WM16(BIT(5), (val))
#define PX30_LVDS_FORMAT(val) FIELD_PREP_WM16(GENMASK(14, 13), (val))
#define PX30_LVDS_MODE_EN(val) FIELD_PREP_WM16(BIT(12), (val))
#define PX30_LVDS_MSBSEL(val) FIELD_PREP_WM16(BIT(11), (val))
#define PX30_LVDS_P2S_EN(val) FIELD_PREP_WM16(BIT(6), (val))
#define PX30_LVDS_VOP_SEL(val) FIELD_PREP_WM16(BIT(1), (val))
regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(1), 1));
FIELD_PREP_WM16(GENMASK(6, 5), val));
regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(4), 1));
FIELD_PREP_WM16(GENMASK(8, 7), val));
regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(0), 1));
regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(3), 1));
writel(FIELD_PREP_WM16(VDPU383_STA_INT_ALL, 0), rkvdec->link + VDPU383_LINK_STA_INT);
writel(FIELD_PREP_WM16(VDPU383_INT_EN_IRQ | VDPU383_INT_EN_LINE_IRQ, 0),
#define HIWORD_UPDATE(v, h, l) FIELD_PREP_WM16(GENMASK((h), (l)), (v))
FIELD_PREP_WM16(GENMASK(11, 1), raw_value));
FIELD_PREP_WM16(GENMASK(11, 1), raw_value));
FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
#define PCIE_CLIENT_SET_MODE(x) FIELD_PREP_WM16(PCIE_CLIENT_MODE_MASK, (x))
#define PCIE_CLIENT_LD_RQ_RST_GRT FIELD_PREP_WM16(BIT(3), 1)
#define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1)
#define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0)
val = FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_DONE, 1);
val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1);
val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) |
FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1);
val = FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0) |
FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0);
#define PCIE_CLKREQ_READY FIELD_PREP_WM16(BIT(0), 1)
#define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0)
#define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1)
#define PCIE_CLIENT_CONF_LANE_NUM(x) FIELD_PREP_WM16(0x0030, ENCODE_LANES(x))
(FIELD_PREP_WM16((mask) << (shift), (val)))
FIELD_PREP_WM16(PHY_LANE_IDLE_MASK,
FIELD_PREP_WM16(PHY_LANE_IDLE_MASK,
FIELD_PREP_WM16(PHY_LANE_IDLE_MASK,
FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, PHY_CFG_PLL_LOCK));
FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, PHY_CFG_PLL_LOCK));
FIELD_PREP_WM16(PHY_CFG_DATA_MASK, data) |
FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, addr));
FIELD_PREP_WM16(PHY_CFG_WR_MASK, PHY_CFG_WR_ENABLE));
FIELD_PREP_WM16(PHY_CFG_WR_MASK, PHY_CFG_WR_DISABLE));
#define S_CPHY_MODE FIELD_PREP_WM16(BIT(3), 1)
#define M_CPHY_MODE FIELD_PREP_WM16(BIT(0), 1)
val = FIELD_PREP_WM16(UOC_CON0_COMMON_ON_N, 1) |
FIELD_PREP_WM16(UOC_CON0_DISABLE, 1) |
FIELD_PREP_WM16(UOC_CON0_SIDDQ, 1);
val = FIELD_PREP_WM16(UOC_CON2_SOFT_CON_SEL, 1);
val = FIELD_PREP_WM16(UOC_CON3_UTMI_SUSPENDN, 0) |
FIELD_PREP_WM16(UOC_CON3_UTMI_OPMODE_MASK,
FIELD_PREP_WM16(UOC_CON3_UTMI_XCVRSEELCT_MASK,
FIELD_PREP_WM16(UOC_CON3_UTMI_TERMSEL_FULLSPEED, 1);
val = FIELD_PREP_WM16(RK3188_UOC0_CON0_BYPASSSEL, 1) |
FIELD_PREP_WM16(RK3188_UOC0_CON0_BYPASSDMEN, 1);
val = FIELD_PREP_WM16(RK3288_UOC0_CON3_BYPASSSEL, 1) |
FIELD_PREP_WM16(RK3288_UOC0_CON3_BYPASSDMEN, 1);
u32 val = FIELD_PREP_WM16(UOC_CON0_SIDDQ, siddq);