FIELD32
#define CSR6_BYTE4 FIELD32(0x000000ff)
#define CSR6_BYTE5 FIELD32(0x0000ff00)
#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR7_RXDONE FIELD32(0x00000040)
#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR8_RXDONE FIELD32(0x00000040)
#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
#define CSR11_CWMIN FIELD32(0x0000000f)
#define CSR11_CWMAX FIELD32(0x000000f0)
#define CSR11_SLOT_TIME FIELD32(0x00001f00)
#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
#define CSR11_SHORT_RETRY FIELD32(0xff000000)
#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
#define CSR14_TSF_COUNT FIELD32(0x00000001)
#define CSR14_TSF_SYNC FIELD32(0x00000006)
#define CSR14_TBCN FIELD32(0x00000008)
#define CSR14_TCFP FIELD32(0x00000010)
#define CSR14_TATIMW FIELD32(0x00000020)
#define CSR14_BEACON_GEN FIELD32(0x00000040)
#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
#define CSR15_CFP FIELD32(0x00000001)
#define CSR15_ATIMW FIELD32(0x00000002)
#define CSR15_BEACON_SENT FIELD32(0x00000004)
#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
#define CSR18_SIFS FIELD32(0x0000ffff)
#define CSR18_PIFS FIELD32(0xffff0000)
#define CSR19_DIFS FIELD32(0x0000ffff)
#define CSR19_EIFS FIELD32(0xffff0000)
#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
#define CSR20_AUTOWAKE FIELD32(0x01000000)
#define CSR21_RELOAD FIELD32(0x00000001)
#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
#define CSR21_TYPE_93C46 FIELD32(0x00000020)
#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
#define TXCSR0_KICK_TX FIELD32(0x00000001)
#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
#define TXCSR0_ABORT FIELD32(0x00000008)
#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
#define RXCSR0_DROP_CRC FIELD32(0x00000002)
#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
#define RXCSR0_DROP_TODS FIELD32(0x00000020)
#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
#define RXCSR0_PASS_CRC FIELD32(0x00000080)
#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
#define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
#define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
#define PCICSR_BURST_LENTH FIELD32(0x00000060)
#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
#define PWRCSR1_SET_STATE FIELD32(0x00000001)
#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
#define TIMECSR_US_COUNT FIELD32(0x000000ff)
#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
#define CSR0_REVISION FIELD32(0x0000ffff)
#define MACCSR1_KICK_RX FIELD32(0x00000001)
#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
#define MACCSR1_LOOPBACK FIELD32(0x00000060)
#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
#define BCNCSR_CHANGE FIELD32(0x00000001)
#define BCNCSR_DELTATIME FIELD32(0x0000001e)
#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
#define BCNCSR_MODE FIELD32(0x00006000)
#define BCNCSR_PLUS FIELD32(0x00008000)
#define BBPCSR_VALUE FIELD32(0x000000ff)
#define BBPCSR_REGNUM FIELD32(0x00007f00)
#define BBPCSR_BUSY FIELD32(0x00008000)
#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
#define RFCSR_VALUE FIELD32(0x00ffffff)
#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
#define RFCSR_IF_SELECT FIELD32(0x20000000)
#define RFCSR_PLL_LD FIELD32(0x40000000)
#define RFCSR_BUSY FIELD32(0x80000000)
#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
#define LEDCSR_LINK FIELD32(0x00010000)
#define LEDCSR_ACTIVITY FIELD32(0x00020000)
#define CSR1_SOFT_RESET FIELD32(0x00000001)
#define CSR1_BBP_RESET FIELD32(0x00000002)
#define GPIOCSR_VAL0 FIELD32(0x00000001)
#define GPIOCSR_VAL1 FIELD32(0x00000002)
#define GPIOCSR_VAL2 FIELD32(0x00000004)
#define GPIOCSR_VAL3 FIELD32(0x00000008)
#define GPIOCSR_VAL4 FIELD32(0x00000010)
#define GPIOCSR_VAL5 FIELD32(0x00000020)
#define CSR1_HOST_READY FIELD32(0x00000004)
#define GPIOCSR_VAL6 FIELD32(0x00000040)
#define GPIOCSR_VAL7 FIELD32(0x00000080)
#define GPIOCSR_DIR0 FIELD32(0x00000100)
#define GPIOCSR_DIR1 FIELD32(0x00000200)
#define GPIOCSR_DIR2 FIELD32(0x00000400)
#define GPIOCSR_DIR3 FIELD32(0x00000800)
#define GPIOCSR_DIR4 FIELD32(0x00001000)
#define GPIOCSR_DIR5 FIELD32(0x00002000)
#define GPIOCSR_DIR6 FIELD32(0x00004000)
#define GPIOCSR_DIR7 FIELD32(0x00008000)
#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
#define MACCSR2_DELAY FIELD32(0x000000ff)
#define ARCSR2_SIGNAL FIELD32(0x000000ff)
#define ARCSR2_SERVICE FIELD32(0x0000ff00)
#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
#define ARCSR2_LENGTH FIELD32(0xffff0000)
#define ARCSR3_SIGNAL FIELD32(0x000000ff)
#define ARCSR3_SERVICE FIELD32(0x0000ff00)
#define ARCSR3_LENGTH FIELD32(0xffff0000)
#define ARCSR4_SIGNAL FIELD32(0x000000ff)
#define ARCSR4_SERVICE FIELD32(0x0000ff00)
#define ARCSR4_LENGTH FIELD32(0xffff0000)
#define ARCSR5_SIGNAL FIELD32(0x000000ff)
#define ARCSR5_SERVICE FIELD32(0x0000ff00)
#define ARCSR5_LENGTH FIELD32(0xffff0000)
#define RF1_TUNER FIELD32(0x00020000)
#define RF3_TUNER FIELD32(0x00000100)
#define RF3_TXPOWER FIELD32(0x00003e00)
#define CSR3_BYTE0 FIELD32(0x000000ff)
#define CSR3_BYTE1 FIELD32(0x0000ff00)
#define CSR3_BYTE2 FIELD32(0x00ff0000)
#define CSR3_BYTE3 FIELD32(0xff000000)
#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_RESULT FIELD32(0x0000001c)
#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
#define TXD_W0_ACK FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
#define TXD_W0_RTS FIELD32(0x00000800)
#define TXD_W0_IFS FIELD32(0x00006000)
#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
#define TXD_W0_AGC FIELD32(0x00ff0000)
#define TXD_W0_R2 FIELD32(0xff000000)
#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
#define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
#define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
#define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
#define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
#define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
#define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
#define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
#define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
#define CSR4_BYTE4 FIELD32(0x000000ff)
#define TXD_W5_BBCR4 FIELD32(0x0000ffff)
#define TXD_W5_AGC_REG FIELD32(0x007f0000)
#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
#define TXD_W5_XXX_REG FIELD32(0x7f000000)
#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
#define CSR4_BYTE5 FIELD32(0x0000ff00)
#define TXD_W6_SK_BUFF FIELD32(0xffffffff)
#define TXD_W7_RESERVED FIELD32(0xffffffff)
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
#define RXD_W0_MULTICAST FIELD32(0x00000004)
#define RXD_W0_BROADCAST FIELD32(0x00000008)
#define RXD_W0_MY_BSS FIELD32(0x00000010)
#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
#define RXD_W2_BBR0 FIELD32(0x00ff0000)
#define RXD_W2_SIGNAL FIELD32(0xff000000)
#define RXD_W3_RSSI FIELD32(0x000000ff)
#define RXD_W3_BBR3 FIELD32(0x0000ff00)
#define RXD_W3_BBR4 FIELD32(0x00ff0000)
#define RXD_W3_BBR5 FIELD32(0xff000000)
#define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
#define RXD_W5_RESERVED FIELD32(0xffffffff)
#define RXD_W6_RESERVED FIELD32(0xffffffff)
#define RXD_W7_RESERVED FIELD32(0xffffffff)
#define CSR5_BYTE0 FIELD32(0x000000ff)
#define CSR5_BYTE1 FIELD32(0x0000ff00)
#define CSR5_BYTE2 FIELD32(0x00ff0000)
#define CSR5_BYTE3 FIELD32(0xff000000)
#define CSR5_BYTE0 FIELD32(0x000000ff)
#define CSR5_BYTE1 FIELD32(0x0000ff00)
#define CSR5_BYTE2 FIELD32(0x00ff0000)
#define CSR5_BYTE3 FIELD32(0xff000000)
#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_RESULT FIELD32(0x0000001c)
#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
#define TXD_W0_ACK FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
#define TXD_W0_OFDM FIELD32(0x00000800)
#define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
#define TXD_W0_IFS FIELD32(0x00006000)
#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
#define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
#define TXD_W2_AIFS FIELD32(0x000000c0)
#define TXD_W2_CWMIN FIELD32(0x00000f00)
#define TXD_W2_CWMAX FIELD32(0x0000f000)
#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
#define TXD_W4_IV FIELD32(0xffffffff)
#define CSR6_BYTE4 FIELD32(0x000000ff)
#define TXD_W5_EIV FIELD32(0xffffffff)
#define TXD_W6_KEY FIELD32(0xffffffff)
#define TXD_W7_KEY FIELD32(0xffffffff)
#define CSR6_BYTE5 FIELD32(0x0000ff00)
#define TXD_W8_KEY FIELD32(0xffffffff)
#define TXD_W9_KEY FIELD32(0xffffffff)
#define TXD_W10_RTS FIELD32(0x00000001)
#define TXD_W10_TX_RATE FIELD32(0x000000fe)
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
#define RXD_W0_MULTICAST FIELD32(0x00000004)
#define RXD_W0_BROADCAST FIELD32(0x00000008)
#define RXD_W0_MY_BSS FIELD32(0x00000010)
#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
#define RXD_W0_OFDM FIELD32(0x00000040)
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
#define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
#define RXD_W0_ICV_ERROR FIELD32(0x00000200)
#define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
#define RXD_W2_SIGNAL FIELD32(0x000000ff)
#define RXD_W2_RSSI FIELD32(0x0000ff00)
#define RXD_W2_TA FIELD32(0xffff0000)
#define RXD_W3_TA FIELD32(0xffffffff)
#define RXD_W4_IV FIELD32(0xffffffff)
#define RXD_W5_EIV FIELD32(0xffffffff)
#define RXD_W6_KEY FIELD32(0xffffffff)
#define RXD_W7_KEY FIELD32(0xffffffff)
#define RXD_W8_KEY FIELD32(0xffffffff)
#define RXD_W9_KEY FIELD32(0xffffffff)
#define RXD_W10_DROP FIELD32(0x00000001)
#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR7_RXDONE FIELD32(0x00000040)
#define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
#define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
#define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
#define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
#define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
#define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
#define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
#define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
#define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
#define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
#define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
#define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
#define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR8_RXDONE FIELD32(0x00000040)
#define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
#define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
#define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
#define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
#define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
#define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
#define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
#define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
#define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
#define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
#define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
#define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
#define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
#define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
#define SECCSR0_ONE_SHOT FIELD32(0x00000002)
#define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
#define CSR11_CWMIN FIELD32(0x0000000f)
#define CSR11_CWMAX FIELD32(0x000000f0)
#define CSR11_SLOT_TIME FIELD32(0x00001f00)
#define CSR11_CW_SELECT FIELD32(0x00002000)
#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
#define CSR11_SHORT_RETRY FIELD32(0xff000000)
#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
#define CSR14_TSF_COUNT FIELD32(0x00000001)
#define CSR14_TSF_SYNC FIELD32(0x00000006)
#define CSR14_TBCN FIELD32(0x00000008)
#define CSR14_TCFP FIELD32(0x00000010)
#define CSR14_TATIMW FIELD32(0x00000020)
#define CSR14_BEACON_GEN FIELD32(0x00000040)
#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
#define CSR15_CFP FIELD32(0x00000001)
#define CSR15_ATIMW FIELD32(0x00000002)
#define CSR15_BEACON_SENT FIELD32(0x00000004)
#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
#define CSR18_SIFS FIELD32(0x000001ff)
#define CSR18_PIFS FIELD32(0x001f0000)
#define CSR19_DIFS FIELD32(0x0000ffff)
#define CSR19_EIFS FIELD32(0xffff0000)
#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
#define CSR20_AUTOWAKE FIELD32(0x01000000)
#define CSR21_RELOAD FIELD32(0x00000001)
#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
#define CSR21_TYPE_93C46 FIELD32(0x00000020)
#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
#define TXCSR0_KICK_TX FIELD32(0x00000001)
#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
#define TXCSR0_ABORT FIELD32(0x00000008)
#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
#define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
#define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
#define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
#define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
#define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
#define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
#define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
#define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
#define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
#define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
#define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
#define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
#define RXCSR0_DROP_CRC FIELD32(0x00000002)
#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
#define RXCSR0_DROP_TODS FIELD32(0x00000020)
#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
#define RXCSR0_PASS_CRC FIELD32(0x00000080)
#define RXCSR0_PASS_PLCP FIELD32(0x00000100)
#define RXCSR0_DROP_MCAST FIELD32(0x00000200)
#define RXCSR0_DROP_BCAST FIELD32(0x00000400)
#define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
#define PCICSR_BURST_LENTH FIELD32(0x00000060)
#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
#define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
#define PCICSR_WRITE_INVALID FIELD32(0x00000200)
#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
#define CNT3_FALSE_CCA FIELD32(0x0000ffff)
#define PWRCSR1_SET_STATE FIELD32(0x00000001)
#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
#define TIMECSR_US_COUNT FIELD32(0x000000ff)
#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
#define MACCSR1_KICK_RX FIELD32(0x00000001)
#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
#define CSR0_REVISION FIELD32(0x0000ffff)
#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
#define MACCSR1_LOOPBACK FIELD32(0x00000060)
#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
#define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
#define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
#define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
#define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
#define BCNCSR_CHANGE FIELD32(0x00000001)
#define BCNCSR_DELTATIME FIELD32(0x0000001e)
#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
#define BCNCSR_MODE FIELD32(0x00006000)
#define BCNCSR_PLUS FIELD32(0x00008000)
#define BBPCSR_VALUE FIELD32(0x000000ff)
#define BBPCSR_REGNUM FIELD32(0x00007f00)
#define BBPCSR_BUSY FIELD32(0x00008000)
#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
#define RFCSR_VALUE FIELD32(0x00ffffff)
#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
#define RFCSR_IF_SELECT FIELD32(0x20000000)
#define RFCSR_PLL_LD FIELD32(0x40000000)
#define RFCSR_BUSY FIELD32(0x80000000)
#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
#define LEDCSR_LINK FIELD32(0x00010000)
#define LEDCSR_ACTIVITY FIELD32(0x00020000)
#define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
#define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
#define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
#define CSR1_SOFT_RESET FIELD32(0x00000001)
#define CSR1_BBP_RESET FIELD32(0x00000002)
#define CSR1_HOST_READY FIELD32(0x00000004)
#define GPIOCSR_VAL0 FIELD32(0x00000001)
#define GPIOCSR_VAL1 FIELD32(0x00000002)
#define GPIOCSR_VAL2 FIELD32(0x00000004)
#define GPIOCSR_VAL3 FIELD32(0x00000008)
#define GPIOCSR_VAL4 FIELD32(0x00000010)
#define GPIOCSR_VAL5 FIELD32(0x00000020)
#define GPIOCSR_VAL6 FIELD32(0x00000040)
#define GPIOCSR_VAL7 FIELD32(0x00000080)
#define GPIOCSR_DIR0 FIELD32(0x00000100)
#define GPIOCSR_DIR1 FIELD32(0x00000200)
#define GPIOCSR_DIR2 FIELD32(0x00000400)
#define GPIOCSR_DIR3 FIELD32(0x00000800)
#define GPIOCSR_DIR4 FIELD32(0x00001000)
#define GPIOCSR_DIR5 FIELD32(0x00002000)
#define GPIOCSR_DIR6 FIELD32(0x00004000)
#define GPIOCSR_DIR7 FIELD32(0x00008000)
#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
#define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
#define MACCSR2_DELAY FIELD32(0x000000ff)
#define ARCSR2_SIGNAL FIELD32(0x000000ff)
#define ARCSR2_SERVICE FIELD32(0x0000ff00)
#define ARCSR2_LENGTH FIELD32(0xffff0000)
#define ARCSR3_SIGNAL FIELD32(0x000000ff)
#define ARCSR3_SERVICE FIELD32(0x0000ff00)
#define ARCSR3_LENGTH FIELD32(0xffff0000)
#define ARCSR4_SIGNAL FIELD32(0x000000ff)
#define ARCSR4_SERVICE FIELD32(0x0000ff00)
#define ARCSR4_LENGTH FIELD32(0xffff0000)
#define ARCSR5_SIGNAL FIELD32(0x000000ff)
#define ARCSR5_SERVICE FIELD32(0x0000ff00)
#define ARCSR5_LENGTH FIELD32(0xffff0000)
#define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
#define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
#define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
#define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
#define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
#define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
#define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
#define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
#define CSR3_BYTE0 FIELD32(0x000000ff)
#define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
#define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
#define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
#define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
#define CSR3_BYTE1 FIELD32(0x0000ff00)
#define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
#define SECCSR1_ONE_SHOT FIELD32(0x00000002)
#define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
#define CSR3_BYTE2 FIELD32(0x00ff0000)
#define BBPCSR1_CCK FIELD32(0x00000003)
#define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
#define BBPCSR1_OFDM FIELD32(0x00030000)
#define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
#define CSR3_BYTE3 FIELD32(0xff000000)
#define CSR4_BYTE4 FIELD32(0x000000ff)
#define CSR4_BYTE5 FIELD32(0x0000ff00)
#define RF1_TUNER FIELD32(0x00020000)
#define RF3_TUNER FIELD32(0x00000100)
#define RF3_TXPOWER FIELD32(0x00003e00)
#define RF1_TUNER FIELD32(0x00020000)
#define RF3_TUNER FIELD32(0x00000100)
#define RF3_TXPOWER FIELD32(0x00003e00)
#define TXD_W0_PACKET_ID FIELD32(0x0000000f)
#define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
#define TXD_W0_ACK FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
#define TXD_W0_OFDM FIELD32(0x00000800)
#define TXD_W0_NEW_SEQ FIELD32(0x00001000)
#define TXD_W0_IFS FIELD32(0x00006000)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_CIPHER FIELD32(0x20000000)
#define TXD_W0_KEY_ID FIELD32(0xc0000000)
#define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
#define TXD_W1_AIFS FIELD32(0x000000c0)
#define TXD_W1_CWMIN FIELD32(0x00000f00)
#define TXD_W1_CWMAX FIELD32(0x0000f000)
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
#define TXD_W3_IV FIELD32(0xffffffff)
#define TXD_W4_EIV FIELD32(0xffffffff)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
#define RXD_W0_MULTICAST FIELD32(0x00000004)
#define RXD_W0_BROADCAST FIELD32(0x00000008)
#define RXD_W0_MY_BSS FIELD32(0x00000010)
#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
#define RXD_W0_OFDM FIELD32(0x00000040)
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
#define RXD_W0_CIPHER FIELD32(0x00000100)
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define RXD_W1_RSSI FIELD32(0x000000ff)
#define RXD_W1_SIGNAL FIELD32(0x0000ff00)
#define RXD_W2_IV FIELD32(0xffffffff)
#define RXD_W3_EIV FIELD32(0xffffffff)
#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
#define MAC_STATUS_CFG_BBP_RF_BUSY_TX FIELD32(0x00000001)
#define MAC_STATUS_CFG_BBP_RF_BUSY_RX FIELD32(0x00000002)
#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
#define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
#define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
#define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
#define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
#define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
#define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
#define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
#define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
#define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
#define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
#define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
#define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
#define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
#define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
#define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
#define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
#define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
#define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
#define TX_PWR_CFG_3_UNKNOWN1 FIELD32(0x000f0000)
#define TX_PWR_CFG_3_UNKNOWN2 FIELD32(0x00f00000)
#define TX_PWR_CFG_3_UNKNOWN3 FIELD32(0x0f000000)
#define TX_PWR_CFG_3_UNKNOWN4 FIELD32(0xf0000000)
#define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
#define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
#define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
#define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
#define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
#define TX_PWR_CFG_4_UNKNOWN5 FIELD32(0x0000000f)
#define TX_PWR_CFG_4_UNKNOWN6 FIELD32(0x000000f0)
#define TX_PWR_CFG_4_UNKNOWN7 FIELD32(0x00000f00)
#define TX_PWR_CFG_4_UNKNOWN8 FIELD32(0x0000f000)
#define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
#define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
#define TX_BAND_CFG_A FIELD32(0x00000002)
#define TX_BAND_CFG_BG FIELD32(0x00000004)
#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
#define E2PROM_CSR_TYPE FIELD32(0x00000030)
#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
#define AUX_OPT_BIT0 FIELD32(0x00000001)
#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
#define AUX_OPT_BIT1 FIELD32(0x00000002)
#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
#define AUX_OPT_BIT2 FIELD32(0x00000004)
#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
#define AUX_OPT_BIT3 FIELD32(0x00000008)
#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define AUX_OPT_BIT4 FIELD32(0x00000010)
#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define AUX_OPT_BIT5 FIELD32(0x00000020)
#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define AUX_OPT_BIT6 FIELD32(0x00000040)
#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define AUX_OPT_BIT7 FIELD32(0x00000080)
#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define AUX_OPT_BIT8 FIELD32(0x00000100)
#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define AUX_OPT_BIT9 FIELD32(0x00000200)
#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define AUX_OPT_BIT10 FIELD32(0x00000400)
#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define AUX_OPT_BIT11 FIELD32(0x00000800)
#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
#define AUX_OPT_BIT12 FIELD32(0x00001000)
#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
#define AUX_OPT_BIT13 FIELD32(0x00002000)
#define AUX_OPT_BIT14 FIELD32(0x00004000)
#define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
#define AUX_OPT_BIT15 FIELD32(0x00008000)
#define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
#define LDO25_LEVEL FIELD32(0x00030000)
#define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
#define LDO25_LARGEA FIELD32(0x00040000)
#define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
#define LDO25_FRC_ON FIELD32(0x00080000)
#define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
#define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
#define CMB_RSV FIELD32(0x00300000)
#define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
#define XTAL_RDY FIELD32(0x00400000)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
#define PLL_LD FIELD32(0x00800000)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
#define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
#define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
#define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
#define LDO_CORE_LEVEL FIELD32(0x0F000000)
#define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
#define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
#define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
#define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
#define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
#define LDO_BGSEL FIELD32(0x30000000)
#define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
#define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
#define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
#define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
#define LDO3_EN FIELD32(0x40000000)
#define LDO0_EN FIELD32(0x80000000)
#define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
#define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
#define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
#define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
#define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
#define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
#define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
#define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
#define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
#define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
#define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
#define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
#define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
#define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
#define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
#define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
#define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
#define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
#define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
#define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
#define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
#define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
#define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
#define TX_STA_FIFO_VALID FIELD32(0x00000001)
#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
#define TX_STA_FIFO_BW FIELD32(0x00800000)
#define TX_STA_FIFO_SGI FIELD32(0x01000000)
#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
#define OSC_REF_CYCLE FIELD32(0x00001fff)
#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
#define OSC_RSV FIELD32(0x0000e000)
#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
#define OSC_CAL_CNT FIELD32(0x0fff0000)
#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
#define OSC_CAL_ACK FIELD32(0x10000000)
#define OSC_CLK_32K_VLD FIELD32(0x20000000)
#define OSC_CAL_REQ FIELD32(0x40000000)
#define OSC_ROSC_EN FIELD32(0x80000000)
#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
#define COEX_CFG_ANT FIELD32(0xff000000)
#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
#define BT_COEX_CFG1 FIELD32(0xff000000)
#define BT_COEX_CFG0 FIELD32(0x00ff0000)
#define WL_COEX_CFG1 FIELD32(0x0000ff00)
#define WL_COEX_CFG0 FIELD32(0x000000ff)
#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
#define PLL_CONTROL FIELD32(0x00070000)
#define PLL_LPF_R1 FIELD32(0x00080000)
#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
#define PLL_LOCK_CTRL FIELD32(0x70000000)
#define PLL_VBGBK_EN FIELD32(0x80000000)
#define WLAN_EN FIELD32(0x00000001)
#define WLAN_CLK_EN FIELD32(0x00000002)
#define WLAN_RSV1 FIELD32(0x00000004)
#define WLAN_RESET FIELD32(0x00000008)
#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
#define FRC_WL_ANT_SET FIELD32(0x00000020)
#define INV_TR_SW0 FIELD32(0x00000040)
#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
#define RF3_TXPOWER_G FIELD32(0x00003e00)
#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
#define RF3_TXPOWER_A FIELD32(0x00003c00)
#define RF4_TXPOWER_G FIELD32(0x000007c0)
#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
#define RF4_TXPOWER_A FIELD32(0x00000780)
#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
#define RF4_HT40 FIELD32(0x00200000)
#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
#define TXWI_W0_FRAG FIELD32(0x00000001)
#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
#define TXWI_W0_CF_ACK FIELD32(0x00000004)
#define TXWI_W0_TS FIELD32(0x00000008)
#define TXWI_W0_AMPDU FIELD32(0x00000010)
#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
#define TXWI_W0_TX_OP FIELD32(0x00000300)
#define TXWI_W0_MCS FIELD32(0x007f0000)
#define TXWI_W0_BW FIELD32(0x00800000)
#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
#define TXWI_W0_STBC FIELD32(0x06000000)
#define TXWI_W0_IFS FIELD32(0x08000000)
#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
#define TXWI_W1_ACK FIELD32(0x00000001)
#define TXWI_W1_NSEQ FIELD32(0x00000002)
#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
#define TXWI_W1_PACKETID FIELD32(0xf0000000)
#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
#define TXWI_W2_IV FIELD32(0xffffffff)
#define TXWI_W3_EIV FIELD32(0xffffffff)
#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
#define RXWI_W0_BSSID FIELD32(0x00001c00)
#define RXWI_W0_UDF FIELD32(0x0000e000)
#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
#define RXWI_W0_TID FIELD32(0xf0000000)
#define RXWI_W1_FRAG FIELD32(0x0000000f)
#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
#define RXWI_W1_MCS FIELD32(0x007f0000)
#define RXWI_W1_BW FIELD32(0x00800000)
#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
#define RXWI_W1_STBC FIELD32(0x06000000)
#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
#define RXWI_W3_SNR0 FIELD32(0x000000ff)
#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
#define GPIO_CTRL_VAL0 FIELD32(0x00000001)
#define GPIO_CTRL_VAL1 FIELD32(0x00000002)
#define GPIO_CTRL_VAL2 FIELD32(0x00000004)
#define GPIO_CTRL_VAL3 FIELD32(0x00000008)
#define GPIO_CTRL_VAL4 FIELD32(0x00000010)
#define GPIO_CTRL_VAL5 FIELD32(0x00000020)
#define GPIO_CTRL_VAL6 FIELD32(0x00000040)
#define GPIO_CTRL_VAL7 FIELD32(0x00000080)
#define GPIO_CTRL_DIR0 FIELD32(0x00000100)
#define GPIO_CTRL_DIR1 FIELD32(0x00000200)
#define GPIO_CTRL_DIR2 FIELD32(0x00000400)
#define GPIO_CTRL_DIR3 FIELD32(0x00000800)
#define GPIO_CTRL_DIR4 FIELD32(0x00001000)
#define GPIO_CTRL_DIR5 FIELD32(0x00002000)
#define GPIO_CTRL_DIR6 FIELD32(0x00004000)
#define GPIO_CTRL_DIR7 FIELD32(0x00008000)
#define GPIO_CTRL_VAL8 FIELD32(0x00010000)
#define GPIO_CTRL_VAL9 FIELD32(0x00020000)
#define GPIO_CTRL_VAL10 FIELD32(0x00040000)
#define GPIO_CTRL_DIR8 FIELD32(0x01000000)
#define GPIO_CTRL_DIR9 FIELD32(0x02000000)
#define GPIO_CTRL_DIR10 FIELD32(0x04000000)
#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
#define EFUSE_CTRL_KICK FIELD32(0x40000000)
#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
#define LDO_CFG0_BGSEL FIELD32(0x03000000)
#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
#define GPIO_SWITCH_0 FIELD32(0x00000001)
#define GPIO_SWITCH_1 FIELD32(0x00000002)
#define GPIO_SWITCH_2 FIELD32(0x00000004)
#define GPIO_SWITCH_3 FIELD32(0x00000008)
#define GPIO_SWITCH_4 FIELD32(0x00000010)
#define GPIO_SWITCH_5 FIELD32(0x00000020)
#define GPIO_SWITCH_6 FIELD32(0x00000040)
#define GPIO_SWITCH_7 FIELD32(0x00000080)
#define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
#define MAC_CSR0_REVISION FIELD32(0x0000ffff)
#define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
#define LED_CFG_LED_POLAR FIELD32(0x40000000)
#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
#define RXD_W3_NULLDATA FIELD32(0x00000004)
#define RXD_W3_FRAG FIELD32(0x00000008)
#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
#define RXD_W3_MULTICAST FIELD32(0x00000020)
#define RXD_W3_BROADCAST FIELD32(0x00000040)
#define RXD_W3_MY_BSS FIELD32(0x00000080)
#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
#define RXD_W3_AMSDU FIELD32(0x00000800)
#define RXD_W3_HTC FIELD32(0x00001000)
#define RXD_W3_RSSI FIELD32(0x00002000)
#define RXD_W3_L2PAD FIELD32(0x00004000)
#define RXD_W3_AMPDU FIELD32(0x00008000)
#define RXD_W3_DECRYPTED FIELD32(0x00010000)
#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
#define TXD_W1_BURST FIELD32(0x00008000)
#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
#define TXD_W1_DMA_DONE FIELD32(0x80000000)
#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
#define TXD_W3_WIV FIELD32(0x01000000)
#define TXD_W3_QSEL FIELD32(0x06000000)
#define TXD_W3_TCO FIELD32(0x20000000)
#define TXD_W3_UCO FIELD32(0x40000000)
#define TXD_W3_ICO FIELD32(0x80000000)
#define RXD_W0_SDP0 FIELD32(0xffffffff)
#define RXD_W1_SDL1 FIELD32(0x00003fff)
#define RXD_W1_SDL0 FIELD32(0x3fff0000)
#define RXD_W1_LS0 FIELD32(0x40000000)
#define RXD_W1_DMA_DONE FIELD32(0x80000000)
#define RXD_W2_SDP1 FIELD32(0xffffffff)
#define RXD_W3_BA FIELD32(0x00000001)
#define RXD_W3_DATA FIELD32(0x00000002)
#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
#define TXINFO_W0_WIV FIELD32(0x01000000)
#define TXINFO_W0_QSEL FIELD32(0x06000000)
#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
#define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff)
#define RXD_W0_BA FIELD32(0x00000001)
#define RXD_W0_DATA FIELD32(0x00000002)
#define RXD_W0_NULLDATA FIELD32(0x00000004)
#define RXD_W0_FRAG FIELD32(0x00000008)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
#define RXD_W0_MULTICAST FIELD32(0x00000020)
#define RXD_W0_BROADCAST FIELD32(0x00000040)
#define RXD_W0_MY_BSS FIELD32(0x00000080)
#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
#define RXD_W0_AMSDU FIELD32(0x00000800)
#define RXD_W0_HTC FIELD32(0x00001000)
#define RXD_W0_RSSI FIELD32(0x00002000)
#define RXD_W0_L2PAD FIELD32(0x00004000)
#define RXD_W0_AMPDU FIELD32(0x00008000)
#define RXD_W0_DECRYPTED FIELD32(0x00010000)
#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
#define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
#define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
#define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
#define IO_CNTL_CSR_RF_PS FIELD32(0x00000004)
#define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
#define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
#define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
#define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
#define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
#define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
#define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
#define RF3_TXPOWER FIELD32(0x00003e00)
#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
#define TXD_W0_ACK FIELD32(0x00000008)
#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
#define TXD_W0_OFDM FIELD32(0x00000020)
#define TXD_W0_IFS FIELD32(0x00000040)
#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_BURST FIELD32(0x10000000)
#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
#define TXD_W1_AIFSN FIELD32(0x000000f0)
#define TXD_W1_CWMIN FIELD32(0x00000f00)
#define TXD_W1_CWMAX FIELD32(0x0000f000)
#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
#define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
#define TXD_W3_IV FIELD32(0xffffffff)
#define TXD_W4_EIV FIELD32(0xffffffff)
#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
#define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
#define TXD_W5_PID_TYPE FIELD32(0x0000e000)
#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
#define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
#define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
#define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
#define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
#define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
#define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
#define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_DROP FIELD32(0x00000002)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
#define RXD_W0_MULTICAST FIELD32(0x00000008)
#define RXD_W0_BROADCAST FIELD32(0x00000010)
#define RXD_W0_MY_BSS FIELD32(0x00000020)
#define RXD_W0_CRC_ERROR FIELD32(0x00000040)
#define RXD_W0_OFDM FIELD32(0x00000080)
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define RXD_W1_SIGNAL FIELD32(0x000000ff)
#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
#define RXD_W1_RSSI_LNA FIELD32(0x00006000)
#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
#define RXD_W2_IV FIELD32(0xffffffff)
#define RXD_W3_EIV FIELD32(0xffffffff)
#define RXD_W4_ICV FIELD32(0xffffffff)
#define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
#define RXD_W6_RESERVED FIELD32(0xffffffff)
#define RXD_W7_RESERVED FIELD32(0xffffffff)
#define RXD_W8_RESERVED FIELD32(0xffffffff)
#define RXD_W9_RESERVED FIELD32(0xffffffff)
#define RXD_W10_RESERVED FIELD32(0xffffffff)
#define RXD_W11_RESERVED FIELD32(0xffffffff)
#define RXD_W12_RESERVED FIELD32(0xffffffff)
#define RXD_W13_RESERVED FIELD32(0xffffffff)
#define RXD_W14_RESERVED FIELD32(0xffffffff)
#define RXD_W15_RESERVED FIELD32(0xffffffff)
#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
#define MAC_CSR0_REVISION FIELD32(0x0000000f)
#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
#define MAC_CSR8_SIFS FIELD32(0x000000ff)
#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
#define MAC_CSR8_EIFS FIELD32(0xffff0000)
#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
#define MAC_CSR13_VAL0 FIELD32(0x00000001)
#define MAC_CSR13_VAL1 FIELD32(0x00000002)
#define MAC_CSR13_VAL2 FIELD32(0x00000004)
#define MAC_CSR13_VAL3 FIELD32(0x00000008)
#define MAC_CSR13_VAL4 FIELD32(0x00000010)
#define MAC_CSR13_VAL5 FIELD32(0x00000020)
#define MAC_CSR13_DIR0 FIELD32(0x00000100)
#define MAC_CSR13_DIR1 FIELD32(0x00000200)
#define MAC_CSR13_DIR2 FIELD32(0x00000400)
#define MAC_CSR13_DIR3 FIELD32(0x00000800)
#define MAC_CSR13_DIR4 FIELD32(0x00001000)
#define MAC_CSR13_DIR5 FIELD32(0x00002000)
#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
#define MAC_CSR14_HW_LED FIELD32(0x00010000)
#define MAC_CSR14_SW_LED FIELD32(0x00020000)
#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
#define PHY_CSR3_VALUE FIELD32(0x000000ff)
#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
#define PHY_CSR3_BUSY FIELD32(0x00010000)
#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
#define PHY_CSR4_BUSY FIELD32(0x80000000)
#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
#define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_VALID FIELD32(0x00000001)
#define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
#define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
#define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
#define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
#define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
#define STA_CSR4_TXRATE FIELD32(0x000f0000)
#define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
#define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
#define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
#define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
#define QOS_CSR0_BYTE3 FIELD32(0xff000000)
#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
#define MCU_CNTL_CSR_READY FIELD32(0x00000004)
#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
#define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
#define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
#define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
#define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
#define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
#define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
#define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002)
#define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
#define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
#define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
#define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
#define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
#define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
#define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
#define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
#define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
#define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
#define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
#define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
#define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
#define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
#define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
#define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
#define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
#define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
#define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
#define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
#define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
#define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
#define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
#define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
#define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
#define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
#define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
#define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
#define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
#define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
#define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
#define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
#define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
#define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
#define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
#define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
#define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
#define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
#define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
#define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
#define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
#define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
#define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
#define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
#define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
#define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_DROP FIELD32(0x00000002)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
#define RXD_W0_MULTICAST FIELD32(0x00000008)
#define RXD_W0_BROADCAST FIELD32(0x00000010)
#define RXD_W0_MY_BSS FIELD32(0x00000020)
#define RXD_W0_CRC_ERROR FIELD32(0x00000040)
#define RXD_W0_OFDM FIELD32(0x00000080)
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define RXD_W1_SIGNAL FIELD32(0x000000ff)
#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
#define RXD_W1_RSSI_LNA FIELD32(0x00006000)
#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
#define RXD_W2_IV FIELD32(0xffffffff)
#define RXD_W3_EIV FIELD32(0xffffffff)
#define RXD_W4_ICV FIELD32(0xffffffff)
#define RXD_W5_RESERVED FIELD32(0xffffffff)
#define MAC_CSR0_REVISION FIELD32(0x0000000f)
#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
#define MAC_CSR8_SIFS FIELD32(0x000000ff)
#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
#define MAC_CSR8_EIFS FIELD32(0xffff0000)
#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
#define MAC_CSR13_VAL0 FIELD32(0x00000001)
#define MAC_CSR13_VAL1 FIELD32(0x00000002)
#define MAC_CSR13_VAL2 FIELD32(0x00000004)
#define MAC_CSR13_VAL3 FIELD32(0x00000008)
#define MAC_CSR13_VAL4 FIELD32(0x00000010)
#define MAC_CSR13_VAL5 FIELD32(0x00000020)
#define MAC_CSR13_VAL6 FIELD32(0x00000040)
#define MAC_CSR13_VAL7 FIELD32(0x00000080)
#define MAC_CSR13_DIR0 FIELD32(0x00000100)
#define MAC_CSR13_DIR1 FIELD32(0x00000200)
#define MAC_CSR13_DIR2 FIELD32(0x00000400)
#define MAC_CSR13_DIR3 FIELD32(0x00000800)
#define MAC_CSR13_DIR4 FIELD32(0x00001000)
#define MAC_CSR13_DIR5 FIELD32(0x00002000)
#define MAC_CSR13_DIR6 FIELD32(0x00004000)
#define MAC_CSR13_DIR7 FIELD32(0x00008000)
#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
#define MAC_CSR14_HW_LED FIELD32(0x00010000)
#define MAC_CSR14_SW_LED FIELD32(0x00020000)
#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
#define PHY_CSR1_RF_RPI FIELD32(0x00010000)
#define PHY_CSR3_VALUE FIELD32(0x000000ff)
#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
#define PHY_CSR3_BUSY FIELD32(0x00010000)
#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
#define PHY_CSR4_BUSY FIELD32(0x80000000)
#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
#define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
#define RF3_TXPOWER FIELD32(0x00003e00)
#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
#define TXD_W0_BURST FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
#define TXD_W0_ACK FIELD32(0x00000008)
#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
#define TXD_W0_OFDM FIELD32(0x00000020)
#define TXD_W0_IFS FIELD32(0x00000040)
#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_BURST2 FIELD32(0x10000000)
#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
#define TXD_W1_AIFSN FIELD32(0x000000f0)
#define TXD_W1_CWMIN FIELD32(0x00000f00)
#define TXD_W1_CWMAX FIELD32(0x0000f000)
#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
#define TXD_W3_IV FIELD32(0xffffffff)
#define TXD_W4_EIV FIELD32(0xffffffff)
#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
#define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)