drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

68

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

44

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

43

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

40

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

56

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

65

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

57

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

56

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

265

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 1,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

266

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

267

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

270

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

272

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

273

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 1);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

289

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

290

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

291

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

292

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

294

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

295

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

331

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT), trig_src_select,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

332

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT), TRIGGER_POLARITY_SELECT_LOGIC_ZERO,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

333

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL), rising_edge,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

334

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL), falling_edge,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

336

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

338

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

340

FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR), 1);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

49

CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

52

CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

55

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

561

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

562

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

563

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

564

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

565

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

566

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

574

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

575

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

576

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

577

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

578

FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

58

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

61

CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

64

CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

67

CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

70

CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

61

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

47

#define FN(reg_name, field) FD(reg_name##__##field)

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

1715

XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

1871

if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {

drivers/net/ethernet/cadence/macb_main.c

780

ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));

drivers/net/ethernet/cadence/macb_main.c

786

ctrl |= MACB_BIT(FD);

tools/lib/perf/evlist.c

573

fd = FD(evsel, cpu, thread);

tools/lib/perf/evsel.c

117

fd = FD(leader, cpu_map_idx, thread);

tools/lib/perf/evsel.c

164

evsel_fd = FD(evsel, idx, thread);

tools/lib/perf/evsel.c

198

int *fd = FD(evsel, cpu_map_idx, thread);

tools/lib/perf/evsel.c

245

int *fd = FD(evsel, idx, thread);

tools/lib/perf/evsel.c

274

int *fd = FD(evsel, idx, thread);

tools/lib/perf/evsel.c

297

int *fd = FD(evsel, cpu_map_idx, thread);

tools/lib/perf/evsel.c

338

int *fd = FD(evsel, cpu_map_idx, thread);

tools/lib/perf/evsel.c

404

int *fd = FD(evsel, cpu_map_idx, thread);

tools/lib/perf/evsel.c

431

int *fd = FD(evsel, cpu_map_idx, thread);

tools/lib/perf/evsel.c

74

int *fd = FD(evsel, idx, thread);

tools/perf/trace/beauty/futex_op.c

40

P_FUTEX_OP(FD); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break;

tools/perf/util/bpf-filter.c

300

int ret = ioctl(FD(evsel, x, y), PERF_EVENT_IOC_ID, &id);

tools/perf/util/bpf-filter.c

498

ret = ioctl(FD(evsel, x, y), PERF_EVENT_IOC_SET_BPF, fd);

tools/perf/util/bpf-filter.c

532

link = bpf_program__attach_perf_event_opts(prog, FD(evsel, x, y),

tools/perf/util/bpf_counter_cgroup.c

133

FD(cgrp_switch, i));

tools/perf/util/bpf_counter_cgroup.c

159

int fd = FD(evsel, j);

tools/perf/util/evsel.c

2048

if (FD(leader, cpu_map_idx, thread) < 0)

tools/perf/util/evsel.c

2051

if (readn(FD(leader, cpu_map_idx, thread), data, size) <= 0)

tools/perf/util/evsel.c

2103

if (FD(evsel, cpu_map_idx, thread) < 0)

tools/perf/util/evsel.c

2109

if (readn(FD(evsel, cpu_map_idx, thread), &count, nv * sizeof(u64)) <= 0)

tools/perf/util/evsel.c

2157

fd = FD(leader, cpu_map_idx, thread);

tools/perf/util/evsel.c

2171

FD(pos, cpu, thread) = FD(pos, cpu, thread + 1);

tools/perf/util/evsel.c

2863

FD(evsel, idx, thread) = fd;

tools/perf/util/evsel.c

2945

if (FD(evsel, idx, thread) >= 0)

tools/perf/util/evsel.c

2946

close(FD(evsel, idx, thread));

tools/perf/util/evsel.c

2947

FD(evsel, idx, thread) = -1;

tools/perf/util/evsel.c

4147

int fd = FD(evsel, cpu_map_idx, thread);

tools/perf/util/hwmon_pmu.c

782

FD(evsel, idx, thread) = fd;

tools/perf/util/hwmon_pmu.c

797

if (FD(evsel, idx, thread) >= 0)

tools/perf/util/hwmon_pmu.c

798

close(FD(evsel, idx, thread));

tools/perf/util/hwmon_pmu.c

799

FD(evsel, idx, thread) = -1;

tools/perf/util/hwmon_pmu.c

818

fd = FD(evsel, cpu_map_idx, thread);

tools/perf/util/tool_pmu.c

267

FD(evsel, idx, thread) = fd;

tools/perf/util/tool_pmu.c

297

if (FD(evsel, idx, thread) >= 0)

tools/perf/util/tool_pmu.c

298

close(FD(evsel, idx, thread));

tools/perf/util/tool_pmu.c

299

FD(evsel, idx, thread) = -1;

tools/perf/util/tool_pmu.c

524

int fd = FD(evsel, cpu_map_idx, thread);

tools/testing/selftests/bpf/prog_tests/fd_array.c

48

#define Close(FD) do { \

tools/testing/selftests/bpf/prog_tests/fd_array.c

49

if ((FD) >= 0) { \

tools/testing/selftests/bpf/prog_tests/fd_array.c

50

close(FD); \

tools/testing/selftests/bpf/prog_tests/fd_array.c

51

FD = -1; \