FCR
writel(0x07, UART1_REG(FCR));
writel(0x07, UART1_REG(FCR));
writel(0x00, UART1_REG(FCR));
ns87303_modify(config, FCR, 0, FCR_LDE);
outb(0, port + FCR); /* no fifo */
static_call(serial_out)(early_serial_base, FCR, 0); /* no fifo */
uart_config.fcr.value = __cpu_to_le32(FCR);
doc->rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS);
s[i] ^= cd->alpha_to[rs_modnn(cd, tmp + (FCR + i) * j)];
syn[i] = rs_modnn(cd, cd->index_of[s[i]] + (NN - FCR - i));
outb(0x01, FCR(iobase)); /* enable FIFOs */
outb(0, FCR(dev->base_addr)); /* disable FIFOs */
outb(0x01, FCR(iobase)); /* enable FIFOs */
outb(0, FCR(dev->base_addr)); /* disable FIFOs */
outb(0x00, FCR(dev->base_addr));
outb(0x01, FCR(iobase)); /* enable FIFOs */
writel(0x00, UART1_REG(FCR));
outb(port->FCR | UART_FCR_CLEAR_RCVR,
outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
u8 FCR; /* FIFO control register */
info->FCR = 0;
info->FCR |= UART_FCR_ENABLE_FIFO |
info->FCR |= UART_FCR_ENABLE_FIFO;
info->FCR |= UART_FCR_TRIGGER_1;
info->FCR |= UART_FCR_TRIGGER_4;
info->FCR |= UART_FCR_TRIGGER_8;
info->FCR |= UART_FCR_TRIGGER_14;
outb(info->FCR, info->ioaddr + UART_FCR);
outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
u32 fcr = rsci_serial_in(port, FCR);
rsci_serial_out(port, FCR, fcr);
ctrl = rsci_serial_in(port, FCR);
rsci_serial_out(port, FCR, ctrl);